Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	122036	1			T1	2		T2	1447		T3	490
all_pins[1]	122036	1			T1	2		T2	1447		T3	490
all_pins[2]	122036	1			T1	2		T2	1447		T3	490
all_pins[3]	122036	1			T1	2		T2	1447		T3	490
all_pins[4]	122036	1			T1	2		T2	1447		T3	490
all_pins[5]	122036	1			T1	2		T2	1447		T3	490
all_pins[6]	122036	1			T1	2		T2	1447		T3	490
all_pins[7]	122036	1			T1	2		T2	1447		T3	490
all_pins[8]	122036	1			T1	2		T2	1447		T3	490

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1048958	1			T1	18		T2	12560		T3	4316
values[0x1]	49366	1			T2	463		T3	94		T4	18
transitions[0x0=>0x1]	39181	1			T2	463		T3	75		T4	16
transitions[0x1=>0x0]	38987	1			T2	462		T3	75		T4	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97066	1			T1	2		T2	984		T3	455
all_pins[0]	values[0x1]	24970	1			T2	463		T3	35		T4	4
all_pins[0]	transitions[0x0=>0x1]	24324	1			T2	463		T3	35		T4	4
all_pins[0]	transitions[0x1=>0x0]	1151	1			T4	2		T8	33		T12	2
all_pins[1]	values[0x0]	120239	1			T1	2		T2	1447		T3	490
all_pins[1]	values[0x1]	1797	1			T4	2		T8	33		T12	2
all_pins[1]	transitions[0x0=>0x1]	1700	1			T4	2		T8	33		T12	2
all_pins[1]	transitions[0x1=>0x0]	2456	1			T3	16		T4	5		T5	3
all_pins[2]	values[0x0]	119483	1			T1	2		T2	1447		T3	474
all_pins[2]	values[0x1]	2553	1			T3	16		T4	5		T5	3
all_pins[2]	transitions[0x0=>0x1]	2491	1			T3	16		T4	5		T5	3
all_pins[2]	transitions[0x1=>0x0]	216	1			T190	2		T17	4		T18	2
all_pins[3]	values[0x0]	121758	1			T1	2		T2	1447		T3	490
all_pins[3]	values[0x1]	278	1			T12	1		T14	1		T190	3
all_pins[3]	transitions[0x0=>0x1]	245	1			T12	1		T14	1		T190	3
all_pins[3]	transitions[0x1=>0x0]	383	1			T23	1		T18	14		T21	7
all_pins[4]	values[0x0]	121620	1			T1	2		T2	1447		T3	490
all_pins[4]	values[0x1]	416	1			T23	1		T18	14		T21	7
all_pins[4]	transitions[0x0=>0x1]	353	1			T23	1		T18	14		T21	7
all_pins[4]	transitions[0x1=>0x0]	178	1			T19	2		T35	3		T132	2
all_pins[5]	values[0x0]	121795	1			T1	2		T2	1447		T3	490
all_pins[5]	values[0x1]	241	1			T19	2		T96	1		T35	3
all_pins[5]	transitions[0x0=>0x1]	186	1			T19	2		T96	1		T35	3
all_pins[5]	transitions[0x1=>0x0]	803	1			T6	1		T7	3		T9	2
all_pins[6]	values[0x0]	121178	1			T1	2		T2	1447		T3	490
all_pins[6]	values[0x1]	858	1			T6	1		T7	3		T9	2
all_pins[6]	transitions[0x0=>0x1]	812	1			T6	1		T7	3		T9	2
all_pins[6]	transitions[0x1=>0x0]	298	1			T147	1		T17	3		T19	3
all_pins[7]	values[0x0]	121692	1			T1	2		T2	1447		T3	490
all_pins[7]	values[0x1]	344	1			T147	1		T17	3		T19	3
all_pins[7]	transitions[0x0=>0x1]	178	1			T147	1		T17	2		T52	9
all_pins[7]	transitions[0x1=>0x0]	17743	1			T3	43		T4	7		T5	2
all_pins[8]	values[0x0]	104127	1			T1	2		T2	1447		T3	447
all_pins[8]	values[0x1]	17909	1			T3	43		T4	7		T5	2
all_pins[8]	transitions[0x0=>0x1]	8892	1			T3	24		T4	5		T5	1
all_pins[8]	transitions[0x1=>0x0]	15759	1			T2	462		T3	16		T4	1