Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8818084	1			T2	241477		T3	72811		T4	11510
all_levels[1]	2210614	1			T2	3763		T3	1776		T4	111
all_levels[2]	567604	1			T2	3564		T3	1774		T4	108
all_levels[3]	236098	1			T2	1601		T3	1773		T4	96
all_levels[4]	839326	1			T2	1594		T3	1762		T4	114
all_levels[5]	337262	1			T2	1602		T3	1765		T4	109
all_levels[6]	301031	1			T2	1585		T3	1776		T4	112
all_levels[7]	248823	1			T2	1595		T3	1776		T4	108
all_levels[8]	341085	1			T2	1603		T3	1777		T4	95
all_levels[9]	289872	1			T2	1599		T3	1769		T4	105
all_levels[10]	272929	1			T2	1557		T3	2157		T4	96
all_levels[11]	346092	1			T2	1334		T3	1331		T4	99
all_levels[12]	389743	1			T2	1329		T3	1333		T4	109
all_levels[13]	348405	1			T2	1334		T3	1337		T4	103
all_levels[14]	226268	1			T2	1322		T3	1340		T4	113
all_levels[15]	344551	1			T2	1334		T3	1340		T4	95
all_levels[16]	253253	1			T2	1334		T3	1339		T4	106
all_levels[17]	487287	1			T2	1334		T3	1338		T4	98
all_levels[18]	559205	1			T2	1332		T3	1336		T4	117
all_levels[19]	303315	1			T2	1334		T3	1339		T4	105
all_levels[20]	494939	1			T2	1335		T3	1337		T4	106
all_levels[21]	218674	1			T2	1334		T3	1338		T4	124
all_levels[22]	274487	1			T2	1328		T3	1336		T4	104
all_levels[23]	251757	1			T2	1332		T3	1320		T4	96
all_levels[24]	409889	1			T2	1334		T3	1343		T4	101
all_levels[25]	200384	1			T2	1332		T3	1331		T4	121
all_levels[26]	309374	1			T2	1324		T3	1336		T4	106
all_levels[27]	215658	1			T2	1324		T3	18574		T4	109
all_levels[28]	248463	1			T2	1325		T3	1342		T4	89
all_levels[29]	229532	1			T2	1334		T3	1342		T4	102
all_levels[30]	382691	1			T2	1333		T3	1328		T4	113
all_levels[31]	573325	1			T2	1636		T3	6237		T4	2844
all_levels[32]	12405756	1			T2	207065		T3	39763		T4	71735

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33931293

1

T2

496863

T3

180876

T4

89258

auto[1]

4483

1

T4

1

T6

6

T7

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8815458	1			T2	241477		T3	72811		T4	11510
all_levels[0]	auto[1]	2626	1			T6	3		T9	10		T42	4
all_levels[1]	auto[0]	2210295	1			T2	3763		T3	1776		T4	111
all_levels[1]	auto[1]	319	1			T9	2		T42	1		T12	1
all_levels[2]	auto[0]	567561	1			T2	3564		T3	1774		T4	108
all_levels[2]	auto[1]	43	1			T45	1		T47	1		T130	1
all_levels[3]	auto[0]	235985	1			T2	1601		T3	1773		T4	96
all_levels[3]	auto[1]	113	1			T44	1		T151	2		T18	3
all_levels[4]	auto[0]	839282	1			T2	1594		T3	1762		T4	114
all_levels[4]	auto[1]	44	1			T23	10		T316	1		T157	2
all_levels[5]	auto[0]	337226	1			T2	1602		T3	1765		T4	109
all_levels[5]	auto[1]	36	1			T140	1		T151	1		T194	1
all_levels[6]	auto[0]	301000	1			T2	1585		T3	1776		T4	112
all_levels[6]	auto[1]	31	1			T34	2		T165	2		T23	1
all_levels[7]	auto[0]	248712	1			T2	1595		T3	1776		T4	108
all_levels[7]	auto[1]	111	1			T9	1		T256	1		T289	1
all_levels[8]	auto[0]	341065	1			T2	1603		T3	1777		T4	95
all_levels[8]	auto[1]	20	1			T36	1		T203	1		T317	1
all_levels[9]	auto[0]	289833	1			T2	1599		T3	1769		T4	105
all_levels[9]	auto[1]	39	1			T272	1		T23	1		T193	1
all_levels[10]	auto[0]	272905	1			T2	1557		T3	2157		T4	96
all_levels[10]	auto[1]	24	1			T192	1		T35	1		T279	1
all_levels[11]	auto[0]	346040	1			T2	1334		T3	1331		T4	99
all_levels[11]	auto[1]	52	1			T45	1		T232	1		T193	2
all_levels[12]	auto[0]	389721	1			T2	1329		T3	1333		T4	109
all_levels[12]	auto[1]	22	1			T128	1		T281	1		T301	1
all_levels[13]	auto[0]	348387	1			T2	1334		T3	1337		T4	103
all_levels[13]	auto[1]	18	1			T118	2		T77	2		T318	2
all_levels[14]	auto[0]	226240	1			T2	1322		T3	1340		T4	113
all_levels[14]	auto[1]	28	1			T142	1		T131	1		T168	1
all_levels[15]	auto[0]	344451	1			T2	1334		T3	1340		T4	95
all_levels[15]	auto[1]	100	1			T134	3		T61	7		T319	1
all_levels[16]	auto[0]	253225	1			T2	1334		T3	1339		T4	106
all_levels[16]	auto[1]	28	1			T192	2		T188	2		T60	1
all_levels[17]	auto[0]	487269	1			T2	1334		T3	1338		T4	98
all_levels[17]	auto[1]	18	1			T157	1		T116	1		T320	1
all_levels[18]	auto[0]	559178	1			T2	1332		T3	1336		T4	117
all_levels[18]	auto[1]	27	1			T129	1		T140	1		T161	1
all_levels[19]	auto[0]	303293	1			T2	1334		T3	1339		T4	105
all_levels[19]	auto[1]	22	1			T6	3		T55	1		T295	3
all_levels[20]	auto[0]	494920	1			T2	1335		T3	1337		T4	106
all_levels[20]	auto[1]	19	1			T274	2		T196	3		T321	1
all_levels[21]	auto[0]	218648	1			T2	1334		T3	1338		T4	124
all_levels[21]	auto[1]	26	1			T23	1		T59	1		T40	2
all_levels[22]	auto[0]	274470	1			T2	1328		T3	1336		T4	104
all_levels[22]	auto[1]	17	1			T142	1		T260	1		T322	3
all_levels[23]	auto[0]	251739	1			T2	1332		T3	1320		T4	96
all_levels[23]	auto[1]	18	1			T272	1		T35	1		T274	1
all_levels[24]	auto[0]	409877	1			T2	1334		T3	1343		T4	101
all_levels[24]	auto[1]	12	1			T9	1		T12	1		T190	1
all_levels[25]	auto[0]	200364	1			T2	1332		T3	1331		T4	121
all_levels[25]	auto[1]	20	1			T56	1		T323	1		T159	1
all_levels[26]	auto[0]	309358	1			T2	1324		T3	1336		T4	106
all_levels[26]	auto[1]	16	1			T23	1		T193	1		T133	1
all_levels[27]	auto[0]	215641	1			T2	1324		T3	18574		T4	109
all_levels[27]	auto[1]	17	1			T42	1		T324	1		T203	1
all_levels[28]	auto[0]	248437	1			T2	1325		T3	1342		T4	89
all_levels[28]	auto[1]	26	1			T9	1		T125	1		T188	1
all_levels[29]	auto[0]	229518	1			T2	1334		T3	1342		T4	102
all_levels[29]	auto[1]	14	1			T17	1		T168	2		T303	1
all_levels[30]	auto[0]	382654	1			T2	1333		T3	1328		T4	113
all_levels[30]	auto[1]	37	1			T151	1		T205	1		T35	19
all_levels[31]	auto[0]	573304	1			T2	1636		T3	6237		T4	2844
all_levels[31]	auto[1]	21	1			T316	3		T216	1		T279	1
all_levels[32]	auto[0]	12405237	1			T2	207065		T3	39763		T4	71734
all_levels[32]	auto[1]	519	1			T4	1		T7	1		T9	3