Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	764	1			T17	4		T35	8		T39	4
all_values[1]	764	1			T17	4		T35	8		T39	4
all_values[2]	764	1			T17	4		T35	8		T39	4
all_values[3]	764	1			T17	4		T35	8		T39	4
all_values[4]	764	1			T17	4		T35	8		T39	4
all_values[5]	764	1			T17	4		T35	8		T39	4
all_values[6]	764	1			T17	4		T35	8		T39	4
all_values[7]	764	1			T17	4		T35	8		T39	4
all_values[8]	764	1			T17	4		T35	8		T39	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3730

1

T17

18

T35

49

T39

16

auto[1]

3146

1

T17

18

T35

23

T39

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2236

1

T17

12

T35

24

T39

12

auto[1]

4640

1

T17

24

T35

48

T39

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4084

1

T17

22

T35

44

T39

23

auto[1]

2792

1

T17

14

T35

28

T39

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	266	1			T17	2		T35	6		T39	1
all_values[0]	auto[0]	auto[1]	auto[1]	185	1			T17	2		T35	1		T39	2
all_values[0]	auto[1]	auto[0]	auto[1]	171	1			T35	1		T134	2		T116	1
all_values[0]	auto[1]	auto[1]	auto[1]	142	1			T39	1		T95	1		T134	3
all_values[1]	auto[0]	auto[0]	auto[0]	233	1			T35	2		T39	1		T95	2
all_values[1]	auto[0]	auto[1]	auto[0]	207	1			T17	1		T35	2		T39	1
all_values[1]	auto[1]	auto[0]	auto[1]	163	1			T17	2		T35	4		T95	2
all_values[1]	auto[1]	auto[1]	auto[1]	161	1			T17	1		T39	2		T134	1
all_values[2]	auto[0]	auto[0]	auto[0]	171	1			T35	4		T95	1		T134	2
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T35	1		T39	1		T95	1
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T17	4		T35	2		T39	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T39	1		T134	2		T116	1
all_values[2]	auto[1]	auto[0]	auto[1]	174	1			T95	2		T134	2		T116	1
all_values[2]	auto[1]	auto[1]	auto[1]	123	1			T35	1		T39	1		T134	2
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T17	1		T39	1		T95	1
all_values[3]	auto[0]	auto[0]	auto[1]	90	1			T35	2		T39	1		T117	2
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T35	1		T134	4		T118	2
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T17	1		T35	1		T95	1
all_values[3]	auto[1]	auto[0]	auto[1]	178	1			T17	1		T35	3		T39	2
all_values[3]	auto[1]	auto[1]	auto[1]	134	1			T17	1		T35	1		T95	1
all_values[4]	auto[0]	auto[0]	auto[0]	179	1			T17	1		T35	3		T134	1
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T17	1		T134	2		T116	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T35	3		T95	1		T134	3
all_values[4]	auto[0]	auto[1]	auto[1]	60	1			T39	2		T95	1		T134	1
all_values[4]	auto[1]	auto[0]	auto[1]	174	1			T17	2		T35	2		T134	4
all_values[4]	auto[1]	auto[1]	auto[1]	131	1			T39	2		T95	2		T134	3
all_values[5]	auto[0]	auto[0]	auto[0]	145	1			T17	2		T35	1		T39	2
all_values[5]	auto[0]	auto[0]	auto[1]	82	1			T61	3		T78	2		T135	1
all_values[5]	auto[0]	auto[1]	auto[0]	132	1			T17	1		T35	1		T39	1
all_values[5]	auto[0]	auto[1]	auto[1]	85	1			T35	1		T95	1		T134	2
all_values[5]	auto[1]	auto[0]	auto[1]	182	1			T35	4		T39	1		T134	4
all_values[5]	auto[1]	auto[1]	auto[1]	138	1			T17	1		T35	1		T95	1
all_values[6]	auto[0]	auto[0]	auto[0]	151	1			T35	2		T39	1		T134	4
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T17	1		T134	2		T117	2
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T17	1		T39	3		T134	3
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T95	1		T134	2		T116	1
all_values[6]	auto[1]	auto[0]	auto[1]	170	1			T17	1		T35	4		T95	2
all_values[6]	auto[1]	auto[1]	auto[1]	133	1			T17	1		T35	2		T95	1
all_values[7]	auto[0]	auto[0]	auto[0]	151	1			T17	1		T35	2		T95	1
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T35	1		T39	1		T134	2
all_values[7]	auto[0]	auto[1]	auto[0]	158	1			T35	1		T39	1		T95	2
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T17	1		T35	1		T134	1
all_values[7]	auto[1]	auto[0]	auto[1]	172	1			T17	1		T35	2		T39	1
all_values[7]	auto[1]	auto[1]	auto[1]	136	1			T17	1		T35	1		T39	1
all_values[8]	auto[0]	auto[0]	auto[1]	245	1			T17	1		T35	5		T39	2
all_values[8]	auto[0]	auto[1]	auto[1]	209	1			T17	1		T35	1		T95	3
all_values[8]	auto[1]	auto[0]	auto[1]	163	1			T17	1		T39	1		T134	3
all_values[8]	auto[1]	auto[1]	auto[1]	147	1			T17	1		T35	2		T39	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal