Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1314
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T101 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2484224972 Jul 07 04:19:12 PM PDT 24 Jul 07 04:19:13 PM PDT 24 274359187 ps
T1256 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2490381675 Jul 07 04:21:09 PM PDT 24 Jul 07 04:21:10 PM PDT 24 31186547 ps
T1257 /workspace/coverage/cover_reg_top/26.uart_intr_test.4219191861 Jul 07 04:18:41 PM PDT 24 Jul 07 04:18:42 PM PDT 24 48353616 ps
T104 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3545524542 Jul 07 04:21:38 PM PDT 24 Jul 07 04:21:39 PM PDT 24 41174509 ps
T82 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3236061229 Jul 07 04:18:12 PM PDT 24 Jul 07 04:18:13 PM PDT 24 51578011 ps
T1258 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1662022153 Jul 07 04:21:25 PM PDT 24 Jul 07 04:21:27 PM PDT 24 66107946 ps
T1259 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1975986949 Jul 07 04:22:13 PM PDT 24 Jul 07 04:22:16 PM PDT 24 209284990 ps
T1260 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3350128545 Jul 07 04:17:46 PM PDT 24 Jul 07 04:17:47 PM PDT 24 15936318 ps
T1261 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.176270647 Jul 07 04:17:35 PM PDT 24 Jul 07 04:17:38 PM PDT 24 127265832 ps
T1262 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1124964880 Jul 07 04:22:53 PM PDT 24 Jul 07 04:22:55 PM PDT 24 171471661 ps
T1263 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.287291066 Jul 07 04:21:15 PM PDT 24 Jul 07 04:21:16 PM PDT 24 73064474 ps
T1264 /workspace/coverage/cover_reg_top/17.uart_intr_test.1014890777 Jul 07 04:18:14 PM PDT 24 Jul 07 04:18:15 PM PDT 24 29242102 ps
T1265 /workspace/coverage/cover_reg_top/10.uart_intr_test.3042809164 Jul 07 04:17:35 PM PDT 24 Jul 07 04:17:36 PM PDT 24 40090881 ps
T1266 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.828635441 Jul 07 04:17:33 PM PDT 24 Jul 07 04:17:34 PM PDT 24 23825409 ps
T1267 /workspace/coverage/cover_reg_top/43.uart_intr_test.3662826637 Jul 07 04:19:26 PM PDT 24 Jul 07 04:19:27 PM PDT 24 124956593 ps
T1268 /workspace/coverage/cover_reg_top/4.uart_intr_test.1671920902 Jul 07 04:18:24 PM PDT 24 Jul 07 04:18:25 PM PDT 24 23591196 ps
T1269 /workspace/coverage/cover_reg_top/2.uart_intr_test.491181679 Jul 07 04:21:21 PM PDT 24 Jul 07 04:21:22 PM PDT 24 149560601 ps
T1270 /workspace/coverage/cover_reg_top/7.uart_intr_test.491189197 Jul 07 04:21:25 PM PDT 24 Jul 07 04:21:27 PM PDT 24 27399677 ps
T1271 /workspace/coverage/cover_reg_top/9.uart_intr_test.851098118 Jul 07 04:22:19 PM PDT 24 Jul 07 04:22:19 PM PDT 24 33322347 ps
T1272 /workspace/coverage/cover_reg_top/44.uart_intr_test.3221115643 Jul 07 04:22:19 PM PDT 24 Jul 07 04:22:20 PM PDT 24 26001957 ps
T1273 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.341996095 Jul 07 04:23:02 PM PDT 24 Jul 07 04:23:03 PM PDT 24 24441798 ps
T1274 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2195132962 Jul 07 04:17:17 PM PDT 24 Jul 07 04:17:18 PM PDT 24 33485798 ps
T1275 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3899849425 Jul 07 04:19:02 PM PDT 24 Jul 07 04:19:03 PM PDT 24 39193901 ps
T1276 /workspace/coverage/cover_reg_top/18.uart_intr_test.3511224237 Jul 07 04:21:11 PM PDT 24 Jul 07 04:21:13 PM PDT 24 17378663 ps
T1277 /workspace/coverage/cover_reg_top/21.uart_intr_test.2849074098 Jul 07 04:18:20 PM PDT 24 Jul 07 04:18:21 PM PDT 24 36326475 ps
T1278 /workspace/coverage/cover_reg_top/39.uart_intr_test.1976797830 Jul 07 04:18:45 PM PDT 24 Jul 07 04:18:46 PM PDT 24 13709327 ps
T1279 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1861372711 Jul 07 04:18:20 PM PDT 24 Jul 07 04:18:21 PM PDT 24 49472548 ps
T1280 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2961038174 Jul 07 04:17:22 PM PDT 24 Jul 07 04:17:23 PM PDT 24 17609724 ps
T1281 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.255889616 Jul 07 04:19:15 PM PDT 24 Jul 07 04:19:16 PM PDT 24 56949337 ps
T1282 /workspace/coverage/cover_reg_top/19.uart_tl_errors.443483276 Jul 07 04:18:20 PM PDT 24 Jul 07 04:18:22 PM PDT 24 130310192 ps
T1283 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2987844348 Jul 07 04:19:16 PM PDT 24 Jul 07 04:19:17 PM PDT 24 52640702 ps
T1284 /workspace/coverage/cover_reg_top/11.uart_tl_errors.634847391 Jul 07 04:21:28 PM PDT 24 Jul 07 04:21:30 PM PDT 24 25188362 ps
T1285 /workspace/coverage/cover_reg_top/28.uart_intr_test.1793630789 Jul 07 04:19:34 PM PDT 24 Jul 07 04:19:34 PM PDT 24 42568874 ps
T1286 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2227486420 Jul 07 04:18:59 PM PDT 24 Jul 07 04:19:00 PM PDT 24 87519997 ps
T1287 /workspace/coverage/cover_reg_top/15.uart_intr_test.3604975200 Jul 07 04:19:45 PM PDT 24 Jul 07 04:19:46 PM PDT 24 36835883 ps
T1288 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2036999766 Jul 07 04:18:25 PM PDT 24 Jul 07 04:18:26 PM PDT 24 21585312 ps
T1289 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3425779050 Jul 07 04:19:45 PM PDT 24 Jul 07 04:19:47 PM PDT 24 282883138 ps
T1290 /workspace/coverage/cover_reg_top/31.uart_intr_test.154518451 Jul 07 04:21:22 PM PDT 24 Jul 07 04:21:23 PM PDT 24 87884677 ps
T1291 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2436621399 Jul 07 04:17:27 PM PDT 24 Jul 07 04:17:28 PM PDT 24 110365994 ps
T1292 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3579748090 Jul 07 04:22:56 PM PDT 24 Jul 07 04:22:58 PM PDT 24 87520313 ps
T1293 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.211646729 Jul 07 04:17:40 PM PDT 24 Jul 07 04:17:43 PM PDT 24 57288387 ps
T1294 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2341914790 Jul 07 04:18:15 PM PDT 24 Jul 07 04:18:16 PM PDT 24 152250881 ps
T1295 /workspace/coverage/cover_reg_top/41.uart_intr_test.3725766660 Jul 07 04:20:02 PM PDT 24 Jul 07 04:20:02 PM PDT 24 42719371 ps
T1296 /workspace/coverage/cover_reg_top/47.uart_intr_test.2490294992 Jul 07 04:22:12 PM PDT 24 Jul 07 04:22:13 PM PDT 24 23433404 ps
T1297 /workspace/coverage/cover_reg_top/22.uart_intr_test.942659151 Jul 07 04:21:15 PM PDT 24 Jul 07 04:21:16 PM PDT 24 29925744 ps
T1298 /workspace/coverage/cover_reg_top/20.uart_intr_test.613558624 Jul 07 04:21:32 PM PDT 24 Jul 07 04:21:33 PM PDT 24 13362285 ps
T1299 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1190086909 Jul 07 04:18:42 PM PDT 24 Jul 07 04:18:43 PM PDT 24 115645129 ps
T1300 /workspace/coverage/cover_reg_top/32.uart_intr_test.400219480 Jul 07 04:18:34 PM PDT 24 Jul 07 04:18:35 PM PDT 24 23308533 ps
T1301 /workspace/coverage/cover_reg_top/11.uart_csr_rw.361164763 Jul 07 04:20:55 PM PDT 24 Jul 07 04:20:56 PM PDT 24 20457632 ps
T1302 /workspace/coverage/cover_reg_top/49.uart_intr_test.2177437390 Jul 07 04:21:11 PM PDT 24 Jul 07 04:21:13 PM PDT 24 16504270 ps
T1303 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1362958663 Jul 07 04:18:23 PM PDT 24 Jul 07 04:18:24 PM PDT 24 19857240 ps
T1304 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1181185227 Jul 07 04:21:59 PM PDT 24 Jul 07 04:22:00 PM PDT 24 21992110 ps
T1305 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1681734337 Jul 07 04:22:24 PM PDT 24 Jul 07 04:22:26 PM PDT 24 46381635 ps
T1306 /workspace/coverage/cover_reg_top/46.uart_intr_test.3036631556 Jul 07 04:22:19 PM PDT 24 Jul 07 04:22:20 PM PDT 24 12436620 ps
T1307 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2321692402 Jul 07 04:19:11 PM PDT 24 Jul 07 04:19:12 PM PDT 24 16961624 ps
T83 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.49869117 Jul 07 04:18:17 PM PDT 24 Jul 07 04:18:18 PM PDT 24 64778851 ps
T84 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2072668094 Jul 07 04:18:05 PM PDT 24 Jul 07 04:18:05 PM PDT 24 62936477 ps
T1308 /workspace/coverage/cover_reg_top/0.uart_tl_errors.14964552 Jul 07 04:17:24 PM PDT 24 Jul 07 04:17:25 PM PDT 24 47393695 ps
T1309 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4104112778 Jul 07 04:18:24 PM PDT 24 Jul 07 04:18:25 PM PDT 24 296400642 ps
T1310 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.548781271 Jul 07 04:19:45 PM PDT 24 Jul 07 04:19:46 PM PDT 24 134297172 ps
T1311 /workspace/coverage/cover_reg_top/30.uart_intr_test.1644565720 Jul 07 04:22:14 PM PDT 24 Jul 07 04:22:15 PM PDT 24 13071966 ps
T1312 /workspace/coverage/cover_reg_top/18.uart_csr_rw.320414968 Jul 07 04:18:20 PM PDT 24 Jul 07 04:18:21 PM PDT 24 17762467 ps
T1313 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2252718028 Jul 07 04:18:33 PM PDT 24 Jul 07 04:18:35 PM PDT 24 32822767 ps
T1314 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3457943602 Jul 07 04:21:31 PM PDT 24 Jul 07 04:21:32 PM PDT 24 55616931 ps

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.937115061
Short name T9
Test name
Test status
Simulation time 254066885868 ps
CPU time 1954.86 seconds
Started Jul 07 05:16:33 PM PDT 24
Finished Jul 07 05:49:09 PM PDT 24
Peak memory 233052 kb
Host smart-50b6c5d7-0735-4455-8038-fe7e20fe834b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937115061 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.937115061
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3791375863
Short name T35
Test name
Test status
Simulation time 493224286303 ps
CPU time 1267.47 seconds
Started Jul 07 05:12:53 PM PDT 24
Finished Jul 07 05:34:01 PM PDT 24
Peak memory 224740 kb
Host smart-70d8bf52-ced8-4acf-b842-6a7a3d21bc6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791375863 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3791375863
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.417520929
Short name T4
Test name
Test status
Simulation time 547608862489 ps
CPU time 918.54 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:29:07 PM PDT 24
Peak memory 199936 kb
Host smart-604e50c1-ae5d-4533-bf16-8cdd8530a5c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417520929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.417520929
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2398895628
Short name T23
Test name
Test status
Simulation time 210145657600 ps
CPU time 1026.78 seconds
Started Jul 07 05:14:13 PM PDT 24
Finished Jul 07 05:31:20 PM PDT 24
Peak memory 216396 kb
Host smart-d6c592a5-448c-4677-96ee-b1f317e4f3ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398895628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2398895628
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3941582701
Short name T116
Test name
Test status
Simulation time 196788908911 ps
CPU time 768.74 seconds
Started Jul 07 05:16:48 PM PDT 24
Finished Jul 07 05:29:37 PM PDT 24
Peak memory 216548 kb
Host smart-230f27fe-f680-4cb6-bc99-a0569d9f1a0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941582701 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3941582701
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.857795460
Short name T40
Test name
Test status
Simulation time 189136204987 ps
CPU time 1857.85 seconds
Started Jul 07 05:12:53 PM PDT 24
Finished Jul 07 05:43:52 PM PDT 24
Peak memory 233068 kb
Host smart-8c94b6c7-acf9-47fb-a4c6-8cea8bc2550c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857795460 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.857795460
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1983785737
Short name T269
Test name
Test status
Simulation time 119765964531 ps
CPU time 1132.59 seconds
Started Jul 07 05:15:56 PM PDT 24
Finished Jul 07 05:34:50 PM PDT 24
Peak memory 199964 kb
Host smart-eb864731-3f16-45ee-b164-d4150e5342e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983785737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1983785737
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_alert_test.2684359956
Short name T27
Test name
Test status
Simulation time 35064134 ps
CPU time 0.53 seconds
Started Jul 07 05:15:26 PM PDT 24
Finished Jul 07 05:15:27 PM PDT 24
Peak memory 195292 kb
Host smart-d005b4d0-fa0e-443e-90eb-be251bc61dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684359956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2684359956
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1309915046
Short name T107
Test name
Test status
Simulation time 461861847 ps
CPU time 0.88 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:12:37 PM PDT 24
Peak memory 218220 kb
Host smart-71807d43-cfa8-48fa-9a6f-7deaaee6a603
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309915046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1309915046
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1053517370
Short name T255
Test name
Test status
Simulation time 95911709656 ps
CPU time 126.8 seconds
Started Jul 07 05:16:32 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 199964 kb
Host smart-bd2b9940-da8e-4aa9-9270-bf458dfa1097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053517370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1053517370
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.1778249139
Short name T279
Test name
Test status
Simulation time 278284341503 ps
CPU time 610.96 seconds
Started Jul 07 05:13:13 PM PDT 24
Finished Jul 07 05:23:24 PM PDT 24
Peak memory 200012 kb
Host smart-dc5d478f-a4a7-42e5-ba7a-81c1ab9262d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778249139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1778249139
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all.1155529171
Short name T161
Test name
Test status
Simulation time 280256480210 ps
CPU time 157.8 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:15:42 PM PDT 24
Peak memory 207892 kb
Host smart-7a94a5d9-07d3-462e-98b4-3dc3a301ca21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155529171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1155529171
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1087539169
Short name T63
Test name
Test status
Simulation time 412650410615 ps
CPU time 1057.88 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:30:35 PM PDT 24
Peak memory 217412 kb
Host smart-697cecf6-49ce-4950-908f-cf6c4fc85f0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087539169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1087539169
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2687652222
Short name T202
Test name
Test status
Simulation time 245972342880 ps
CPU time 26.35 seconds
Started Jul 07 05:17:30 PM PDT 24
Finished Jul 07 05:17:57 PM PDT 24
Peak memory 199984 kb
Host smart-fd28a507-5bd5-4e20-b370-d65b4ef84f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687652222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2687652222
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.2127771768
Short name T158
Test name
Test status
Simulation time 165196360590 ps
CPU time 418.39 seconds
Started Jul 07 05:14:01 PM PDT 24
Finished Jul 07 05:21:00 PM PDT 24
Peak memory 199912 kb
Host smart-1e894bfd-a19a-4c68-ab9f-0b011f1eff03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127771768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2127771768
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2655809837
Short name T103
Test name
Test status
Simulation time 170450750 ps
CPU time 1.29 seconds
Started Jul 07 04:21:39 PM PDT 24
Finished Jul 07 04:21:41 PM PDT 24
Peak memory 199852 kb
Host smart-0edd3631-26c5-472f-82e0-3785fb8e17f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655809837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2655809837
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2504365628
Short name T39
Test name
Test status
Simulation time 56585893259 ps
CPU time 580.86 seconds
Started Jul 07 05:13:30 PM PDT 24
Finished Jul 07 05:23:11 PM PDT 24
Peak memory 224872 kb
Host smart-062d2c23-50e2-4843-9d7d-ed055cd65461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504365628 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2504365628
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.4263560361
Short name T80
Test name
Test status
Simulation time 11253299 ps
CPU time 0.61 seconds
Started Jul 07 04:18:17 PM PDT 24
Finished Jul 07 04:18:18 PM PDT 24
Peak memory 196060 kb
Host smart-f2389688-b28a-4ee0-ab84-c5c237f384e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263560361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4263560361
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2774826807
Short name T13
Test name
Test status
Simulation time 120336213699 ps
CPU time 43.8 seconds
Started Jul 07 05:13:07 PM PDT 24
Finished Jul 07 05:13:51 PM PDT 24
Peak memory 199928 kb
Host smart-da82d786-7420-48f7-8add-9d996dadc6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774826807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2774826807
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2817457379
Short name T52
Test name
Test status
Simulation time 267019406903 ps
CPU time 62.63 seconds
Started Jul 07 05:14:23 PM PDT 24
Finished Jul 07 05:15:26 PM PDT 24
Peak memory 199316 kb
Host smart-ff99d455-ca27-4c40-a168-c4acc0364070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817457379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2817457379
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_stress_all.901368677
Short name T263
Test name
Test status
Simulation time 114846101470 ps
CPU time 204.12 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:16:01 PM PDT 24
Peak memory 199924 kb
Host smart-a2735e97-fb4f-4725-8f4b-b582937d6ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901368677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.901368677
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2060167581
Short name T152
Test name
Test status
Simulation time 130280591023 ps
CPU time 53.21 seconds
Started Jul 07 05:17:58 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 199980 kb
Host smart-9ba252e1-daf1-4347-9328-404f8b4e29ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060167581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2060167581
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1030423189
Short name T17
Test name
Test status
Simulation time 68049540722 ps
CPU time 718.69 seconds
Started Jul 07 05:15:34 PM PDT 24
Finished Jul 07 05:27:33 PM PDT 24
Peak memory 220852 kb
Host smart-ec5c0af3-0c61-496e-827a-eb67999b585a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030423189 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1030423189
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.3879760241
Short name T78
Test name
Test status
Simulation time 380334213234 ps
CPU time 1326.84 seconds
Started Jul 07 05:13:24 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 199856 kb
Host smart-577fab04-d4fb-48e1-b5f6-2a7fafe2eba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879760241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3879760241
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all.2722797322
Short name T421
Test name
Test status
Simulation time 576097059014 ps
CPU time 183.61 seconds
Started Jul 07 05:12:49 PM PDT 24
Finished Jul 07 05:15:54 PM PDT 24
Peak memory 208444 kb
Host smart-48fb42a9-b6a7-4392-a498-01f584030c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722797322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2722797322
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.4201971610
Short name T251
Test name
Test status
Simulation time 246906530318 ps
CPU time 1389.75 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:35:49 PM PDT 24
Peak memory 224300 kb
Host smart-d9e993d7-385a-46b3-9b67-af119a229b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201971610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.4201971610
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2484224972
Short name T101
Test name
Test status
Simulation time 274359187 ps
CPU time 1.31 seconds
Started Jul 07 04:19:12 PM PDT 24
Finished Jul 07 04:19:13 PM PDT 24
Peak memory 200072 kb
Host smart-72e9c33c-8998-4d94-a069-917b1044b816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484224972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2484224972
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1212698057
Short name T8
Test name
Test status
Simulation time 173678307002 ps
CPU time 128.87 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:15:15 PM PDT 24
Peak memory 199948 kb
Host smart-c6efecca-dd5e-40c2-a254-436a971d67d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212698057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1212698057
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.50932893
Short name T130
Test name
Test status
Simulation time 173484740788 ps
CPU time 60.54 seconds
Started Jul 07 05:18:11 PM PDT 24
Finished Jul 07 05:19:13 PM PDT 24
Peak memory 199944 kb
Host smart-90f42813-11a8-41af-953f-603a72d9acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50932893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.50932893
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2796158220
Short name T119
Test name
Test status
Simulation time 87239683743 ps
CPU time 640.69 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:23:47 PM PDT 24
Peak memory 216436 kb
Host smart-63752199-4daf-4c0a-95ac-6a997fbcc609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796158220 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2796158220
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.633647144
Short name T59
Test name
Test status
Simulation time 348273633460 ps
CPU time 527.81 seconds
Started Jul 07 05:16:13 PM PDT 24
Finished Jul 07 05:25:01 PM PDT 24
Peak memory 199744 kb
Host smart-b88539dc-58f7-4b70-8b98-30c55a0dd840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633647144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.633647144
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.346531416
Short name T168
Test name
Test status
Simulation time 81378731842 ps
CPU time 35.92 seconds
Started Jul 07 05:17:00 PM PDT 24
Finished Jul 07 05:17:36 PM PDT 24
Peak memory 200008 kb
Host smart-475b787d-5862-4c42-a5e3-5358f619549a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346531416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.346531416
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2626045387
Short name T257
Test name
Test status
Simulation time 283083350374 ps
CPU time 59.87 seconds
Started Jul 07 05:13:14 PM PDT 24
Finished Jul 07 05:14:14 PM PDT 24
Peak memory 199904 kb
Host smart-f394ef66-86c1-48f2-b561-3e5b75a1882f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626045387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2626045387
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3079997248
Short name T546
Test name
Test status
Simulation time 394578190413 ps
CPU time 1122.69 seconds
Started Jul 07 05:16:04 PM PDT 24
Finished Jul 07 05:34:47 PM PDT 24
Peak memory 225756 kb
Host smart-53ff0420-bf53-4621-8aa5-d1069feb1fc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079997248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3079997248
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.480335711
Short name T252
Test name
Test status
Simulation time 31442628598 ps
CPU time 52.13 seconds
Started Jul 07 05:12:54 PM PDT 24
Finished Jul 07 05:13:46 PM PDT 24
Peak memory 199976 kb
Host smart-ad4fe512-e19e-4e33-a4a7-008c4d1dd1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480335711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.480335711
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2353238044
Short name T179
Test name
Test status
Simulation time 27367585079 ps
CPU time 45.02 seconds
Started Jul 07 05:17:12 PM PDT 24
Finished Jul 07 05:17:57 PM PDT 24
Peak memory 200280 kb
Host smart-d6ef0bd2-dcee-45ff-a02b-4d632c06e94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353238044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2353238044
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4083357654
Short name T232
Test name
Test status
Simulation time 35308703212 ps
CPU time 36.58 seconds
Started Jul 07 05:17:55 PM PDT 24
Finished Jul 07 05:18:31 PM PDT 24
Peak memory 199876 kb
Host smart-a8d6b13a-9c41-4166-b050-26535e265d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083357654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4083357654
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3911520763
Short name T20
Test name
Test status
Simulation time 183689628081 ps
CPU time 215.34 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:16:34 PM PDT 24
Peak memory 199984 kb
Host smart-a1881f08-93ef-4208-8eb4-509c9c65f739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911520763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3911520763
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1981158579
Short name T170
Test name
Test status
Simulation time 61292189031 ps
CPU time 34.94 seconds
Started Jul 07 05:17:13 PM PDT 24
Finished Jul 07 05:17:48 PM PDT 24
Peak memory 199920 kb
Host smart-ee1b6342-a6e2-4aa5-9e1c-1cf663ffc2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981158579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1981158579
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2676034
Short name T281
Test name
Test status
Simulation time 75643508787 ps
CPU time 80.05 seconds
Started Jul 07 05:18:04 PM PDT 24
Finished Jul 07 05:19:25 PM PDT 24
Peak memory 199908 kb
Host smart-bbfdafe3-ab55-4922-85ad-ffc78ac4371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2676034
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.920879890
Short name T193
Test name
Test status
Simulation time 204705850460 ps
CPU time 193.3 seconds
Started Jul 07 05:18:11 PM PDT 24
Finished Jul 07 05:21:25 PM PDT 24
Peak memory 199916 kb
Host smart-ef36a988-8d0f-4dbd-a4e3-f8c905bceaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920879890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.920879890
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2379995881
Short name T183
Test name
Test status
Simulation time 440658370722 ps
CPU time 1534.76 seconds
Started Jul 07 05:16:24 PM PDT 24
Finished Jul 07 05:41:59 PM PDT 24
Peak memory 224684 kb
Host smart-194c4b8e-b95a-4b19-9344-a690b59a8228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379995881 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2379995881
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3400128325
Short name T231
Test name
Test status
Simulation time 32093796320 ps
CPU time 16.75 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:12:54 PM PDT 24
Peak memory 199908 kb
Host smart-0beba81f-87d7-401f-b268-437a076ffb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400128325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3400128325
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1772440111
Short name T196
Test name
Test status
Simulation time 13127668684 ps
CPU time 24.36 seconds
Started Jul 07 05:16:59 PM PDT 24
Finished Jul 07 05:17:23 PM PDT 24
Peak memory 199988 kb
Host smart-0c363435-531b-436d-b5fc-a6d2f746a082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772440111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1772440111
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2819219931
Short name T77
Test name
Test status
Simulation time 42138635309 ps
CPU time 82.79 seconds
Started Jul 07 05:17:21 PM PDT 24
Finished Jul 07 05:18:44 PM PDT 24
Peak memory 199924 kb
Host smart-0d66b7d4-2bb1-4a8d-bf86-04ba67059dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819219931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2819219931
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2016206411
Short name T223
Test name
Test status
Simulation time 35821076917 ps
CPU time 54.44 seconds
Started Jul 07 05:17:44 PM PDT 24
Finished Jul 07 05:18:39 PM PDT 24
Peak memory 199920 kb
Host smart-f71b26b1-4cb3-4487-9e4a-b795fa6d41b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016206411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2016206411
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.435917901
Short name T188
Test name
Test status
Simulation time 206045449510 ps
CPU time 66.63 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:14:54 PM PDT 24
Peak memory 199868 kb
Host smart-d268b76b-6664-41ea-b53d-c253aa356d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435917901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.435917901
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2551665429
Short name T240
Test name
Test status
Simulation time 38783394718 ps
CPU time 28.85 seconds
Started Jul 07 05:18:03 PM PDT 24
Finished Jul 07 05:18:32 PM PDT 24
Peak memory 199940 kb
Host smart-52204f53-3d4c-49ba-b566-e0c15ddbc804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551665429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2551665429
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.706298527
Short name T209
Test name
Test status
Simulation time 71882483418 ps
CPU time 45.81 seconds
Started Jul 07 05:14:10 PM PDT 24
Finished Jul 07 05:14:56 PM PDT 24
Peak memory 199892 kb
Host smart-e8fae5d4-5c59-4078-befa-ebbf8adb8974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706298527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.706298527
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3416071478
Short name T157
Test name
Test status
Simulation time 21377876863 ps
CPU time 57.05 seconds
Started Jul 07 05:12:48 PM PDT 24
Finished Jul 07 05:13:46 PM PDT 24
Peak memory 199804 kb
Host smart-8e4ccf63-b261-41a2-90b6-4e46b5e09b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416071478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3416071478
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3987535689
Short name T212
Test name
Test status
Simulation time 240648540710 ps
CPU time 48.52 seconds
Started Jul 07 05:17:09 PM PDT 24
Finished Jul 07 05:17:58 PM PDT 24
Peak memory 199988 kb
Host smart-5be67008-61f1-4166-93f2-a13eb31c833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987535689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3987535689
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.4146414695
Short name T125
Test name
Test status
Simulation time 99308217402 ps
CPU time 43.42 seconds
Started Jul 07 05:17:14 PM PDT 24
Finished Jul 07 05:17:57 PM PDT 24
Peak memory 199852 kb
Host smart-a0166514-b85e-4e2b-b9b4-3a05771ae57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146414695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.4146414695
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2063814995
Short name T166
Test name
Test status
Simulation time 86926745925 ps
CPU time 101.66 seconds
Started Jul 07 05:17:11 PM PDT 24
Finished Jul 07 05:18:53 PM PDT 24
Peak memory 199852 kb
Host smart-2d0e56d3-dd4d-4c2c-b1a4-bb4d7f5a6371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063814995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2063814995
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2997672168
Short name T246
Test name
Test status
Simulation time 14018551166 ps
CPU time 32.32 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:13:38 PM PDT 24
Peak memory 200000 kb
Host smart-f21cfe06-3424-4be1-8b6a-d1ad6a935730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997672168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2997672168
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1869518697
Short name T237
Test name
Test status
Simulation time 134807828578 ps
CPU time 69.81 seconds
Started Jul 07 05:17:17 PM PDT 24
Finished Jul 07 05:18:27 PM PDT 24
Peak memory 199996 kb
Host smart-a8d5df0b-52e0-4d94-8f1c-920f190d8bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869518697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1869518697
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.68823437
Short name T481
Test name
Test status
Simulation time 168780555269 ps
CPU time 196.38 seconds
Started Jul 07 05:17:24 PM PDT 24
Finished Jul 07 05:20:40 PM PDT 24
Peak memory 199956 kb
Host smart-94f42dc6-855a-40cd-a493-fbd60680d151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68823437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.68823437
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2523654611
Short name T129
Test name
Test status
Simulation time 19678998873 ps
CPU time 24.67 seconds
Started Jul 07 05:17:35 PM PDT 24
Finished Jul 07 05:18:00 PM PDT 24
Peak memory 199780 kb
Host smart-c689a7fe-308f-4831-a5ca-0f9bcd8dbc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523654611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2523654611
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.816014873
Short name T201
Test name
Test status
Simulation time 8693675850 ps
CPU time 9.92 seconds
Started Jul 07 05:17:38 PM PDT 24
Finished Jul 07 05:17:48 PM PDT 24
Peak memory 199852 kb
Host smart-1b1550ac-565e-4087-b1bc-860955ee71f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816014873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.816014873
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1132554522
Short name T249
Test name
Test status
Simulation time 16943650799 ps
CPU time 10.47 seconds
Started Jul 07 05:17:41 PM PDT 24
Finished Jul 07 05:17:51 PM PDT 24
Peak memory 199912 kb
Host smart-b789bdc8-ac70-4f6e-9257-aa174e9bf075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132554522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1132554522
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3441288527
Short name T221
Test name
Test status
Simulation time 89143445624 ps
CPU time 14.59 seconds
Started Jul 07 05:17:53 PM PDT 24
Finished Jul 07 05:18:08 PM PDT 24
Peak memory 199688 kb
Host smart-5ed30b0d-ae1d-4c27-a010-bd0cf526ace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441288527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3441288527
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2495503046
Short name T245
Test name
Test status
Simulation time 150059677456 ps
CPU time 23.58 seconds
Started Jul 07 05:18:11 PM PDT 24
Finished Jul 07 05:18:35 PM PDT 24
Peak memory 200000 kb
Host smart-f2cf4133-1d8a-4681-ad3a-c3fd46cf6025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495503046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2495503046
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2464019828
Short name T72
Test name
Test status
Simulation time 136942181937 ps
CPU time 116.87 seconds
Started Jul 07 05:18:19 PM PDT 24
Finished Jul 07 05:20:16 PM PDT 24
Peak memory 199976 kb
Host smart-6cac1ce4-54f6-45ab-b739-6301a9b675dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464019828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2464019828
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.4149459511
Short name T230
Test name
Test status
Simulation time 99345294464 ps
CPU time 176.67 seconds
Started Jul 07 05:14:23 PM PDT 24
Finished Jul 07 05:17:20 PM PDT 24
Peak memory 199860 kb
Host smart-3ad5dd09-c552-497e-b44b-0763a8433b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149459511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4149459511
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2086401456
Short name T243
Test name
Test status
Simulation time 203443951855 ps
CPU time 29.01 seconds
Started Jul 07 05:18:22 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 199976 kb
Host smart-5234bf29-81da-4b09-9ea5-6ce244d7c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086401456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2086401456
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.4042529965
Short name T242
Test name
Test status
Simulation time 179770651315 ps
CPU time 917.83 seconds
Started Jul 07 05:16:23 PM PDT 24
Finished Jul 07 05:31:41 PM PDT 24
Peak memory 225100 kb
Host smart-66fa53be-1c1a-472a-ad97-015a3b023dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042529965 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.4042529965
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2637840147
Short name T250
Test name
Test status
Simulation time 171022970847 ps
CPU time 104.97 seconds
Started Jul 07 05:16:36 PM PDT 24
Finished Jul 07 05:18:21 PM PDT 24
Peak memory 199928 kb
Host smart-76fe358f-2927-4fa6-95f6-c601133226e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637840147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2637840147
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1715116697
Short name T235
Test name
Test status
Simulation time 36317788281 ps
CPU time 57.45 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:14:01 PM PDT 24
Peak memory 199488 kb
Host smart-d3deeb4b-2dcb-44a3-be0a-7e999821f671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715116697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1715116697
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2195132962
Short name T1274
Test name
Test status
Simulation time 33485798 ps
CPU time 0.67 seconds
Started Jul 07 04:17:17 PM PDT 24
Finished Jul 07 04:17:18 PM PDT 24
Peak memory 196120 kb
Host smart-49cc33f9-82af-4aa1-883b-878fba89628d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195132962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2195132962
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.176270647
Short name T1261
Test name
Test status
Simulation time 127265832 ps
CPU time 1.6 seconds
Started Jul 07 04:17:35 PM PDT 24
Finished Jul 07 04:17:38 PM PDT 24
Peak memory 197016 kb
Host smart-59f66ee4-af44-4f91-810a-56287ea7200c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176270647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.176270647
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1686191369
Short name T1208
Test name
Test status
Simulation time 20224094 ps
CPU time 0.58 seconds
Started Jul 07 04:17:47 PM PDT 24
Finished Jul 07 04:17:48 PM PDT 24
Peak memory 195960 kb
Host smart-f7448286-3169-4ff9-bb72-b16d3fba3bc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686191369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1686191369
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2502750958
Short name T1204
Test name
Test status
Simulation time 37019258 ps
CPU time 1.46 seconds
Started Jul 07 04:16:34 PM PDT 24
Finished Jul 07 04:16:36 PM PDT 24
Peak memory 200612 kb
Host smart-d1af280c-25dc-41af-a540-0ee7fad20719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502750958 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2502750958
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3086007407
Short name T1253
Test name
Test status
Simulation time 88759634 ps
CPU time 0.63 seconds
Started Jul 07 04:17:32 PM PDT 24
Finished Jul 07 04:17:33 PM PDT 24
Peak memory 194424 kb
Host smart-e29b0305-6356-460d-9245-a26849bc2ed4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086007407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3086007407
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2573846914
Short name T1177
Test name
Test status
Simulation time 34891212 ps
CPU time 0.57 seconds
Started Jul 07 04:17:34 PM PDT 24
Finished Jul 07 04:17:34 PM PDT 24
Peak memory 195116 kb
Host smart-758c8455-fe8c-4e79-a0ce-a832edd6248c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573846914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2573846914
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3350128545
Short name T1260
Test name
Test status
Simulation time 15936318 ps
CPU time 0.7 seconds
Started Jul 07 04:17:46 PM PDT 24
Finished Jul 07 04:17:47 PM PDT 24
Peak memory 198016 kb
Host smart-cc780fa8-4fce-412c-b3e5-bca1eb3bea2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350128545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3350128545
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.14964552
Short name T1308
Test name
Test status
Simulation time 47393695 ps
CPU time 0.91 seconds
Started Jul 07 04:17:24 PM PDT 24
Finished Jul 07 04:17:25 PM PDT 24
Peak memory 200756 kb
Host smart-54d7c218-f59d-41d9-8947-6c6ccb4bfad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14964552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.14964552
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2759017479
Short name T97
Test name
Test status
Simulation time 58246954 ps
CPU time 1.01 seconds
Started Jul 07 04:17:35 PM PDT 24
Finished Jul 07 04:17:37 PM PDT 24
Peak memory 197860 kb
Host smart-b41077fb-c81c-4dc9-b41e-76e4159abf30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759017479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2759017479
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3899849425
Short name T1275
Test name
Test status
Simulation time 39193901 ps
CPU time 0.66 seconds
Started Jul 07 04:19:02 PM PDT 24
Finished Jul 07 04:19:03 PM PDT 24
Peak memory 195556 kb
Host smart-c5ac301c-6d09-48ee-9d54-24b2001b61e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899849425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3899849425
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.211646729
Short name T1293
Test name
Test status
Simulation time 57288387 ps
CPU time 2.23 seconds
Started Jul 07 04:17:40 PM PDT 24
Finished Jul 07 04:17:43 PM PDT 24
Peak memory 198700 kb
Host smart-df823edc-3f44-47c1-b84f-b1ff7b19edf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211646729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.211646729
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2321692402
Short name T1307
Test name
Test status
Simulation time 16961624 ps
CPU time 0.59 seconds
Started Jul 07 04:19:11 PM PDT 24
Finished Jul 07 04:19:12 PM PDT 24
Peak memory 196120 kb
Host smart-56eddf88-f39b-4a44-8270-e0f91e2af8bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321692402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2321692402
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2091690854
Short name T1200
Test name
Test status
Simulation time 23500963 ps
CPU time 1.04 seconds
Started Jul 07 04:18:26 PM PDT 24
Finished Jul 07 04:18:27 PM PDT 24
Peak memory 200376 kb
Host smart-27a8085e-7a7a-438e-a1d1-103620e5a712
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091690854 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2091690854
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1861372711
Short name T1279
Test name
Test status
Simulation time 49472548 ps
CPU time 0.59 seconds
Started Jul 07 04:18:20 PM PDT 24
Finished Jul 07 04:18:21 PM PDT 24
Peak memory 196324 kb
Host smart-141d2c3d-b9b5-4a0e-8558-06e3921331a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861372711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1861372711
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1873846142
Short name T1221
Test name
Test status
Simulation time 17131237 ps
CPU time 0.54 seconds
Started Jul 07 04:18:00 PM PDT 24
Finished Jul 07 04:18:01 PM PDT 24
Peak memory 195104 kb
Host smart-66cfb887-a6df-4c22-a3c2-6dce6bcdc456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873846142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1873846142
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.250521389
Short name T1227
Test name
Test status
Simulation time 64369831 ps
CPU time 0.6 seconds
Started Jul 07 04:17:19 PM PDT 24
Finished Jul 07 04:17:20 PM PDT 24
Peak memory 195968 kb
Host smart-de626d16-319f-4fa8-8458-17ae259fabe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250521389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.250521389
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1032953211
Short name T1254
Test name
Test status
Simulation time 1229883041 ps
CPU time 2.14 seconds
Started Jul 07 04:17:32 PM PDT 24
Finished Jul 07 04:17:35 PM PDT 24
Peak memory 198912 kb
Host smart-a3770622-6080-4813-a2d3-116fcab5f9c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032953211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1032953211
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1978866860
Short name T137
Test name
Test status
Simulation time 70376683 ps
CPU time 0.94 seconds
Started Jul 07 04:17:32 PM PDT 24
Finished Jul 07 04:17:33 PM PDT 24
Peak memory 197900 kb
Host smart-da0d7425-330d-4c6a-9c21-1285d240ec9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978866860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1978866860
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2693681991
Short name T1228
Test name
Test status
Simulation time 65617164 ps
CPU time 0.66 seconds
Started Jul 07 04:18:57 PM PDT 24
Finished Jul 07 04:18:57 PM PDT 24
Peak memory 198936 kb
Host smart-4792e3dd-1e80-46eb-a37d-9ba245dbbe4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693681991 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2693681991
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1095488033
Short name T1244
Test name
Test status
Simulation time 52358168 ps
CPU time 0.64 seconds
Started Jul 07 04:17:22 PM PDT 24
Finished Jul 07 04:17:22 PM PDT 24
Peak memory 196212 kb
Host smart-45a60f81-adac-43e3-b984-7031a6c1529e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095488033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1095488033
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3042809164
Short name T1265
Test name
Test status
Simulation time 40090881 ps
CPU time 0.56 seconds
Started Jul 07 04:17:35 PM PDT 24
Finished Jul 07 04:17:36 PM PDT 24
Peak memory 195076 kb
Host smart-1fe95959-8cff-49a3-ba49-dea80e4bccdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042809164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3042809164
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1181185227
Short name T1304
Test name
Test status
Simulation time 21992110 ps
CPU time 0.67 seconds
Started Jul 07 04:21:59 PM PDT 24
Finished Jul 07 04:22:00 PM PDT 24
Peak memory 195092 kb
Host smart-8c36bcb3-cfd7-4a94-b371-fc70d93a2df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181185227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1181185227
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1975986949
Short name T1259
Test name
Test status
Simulation time 209284990 ps
CPU time 2.14 seconds
Started Jul 07 04:22:13 PM PDT 24
Finished Jul 07 04:22:16 PM PDT 24
Peak memory 200384 kb
Host smart-56852ccb-55c5-4f92-b8c7-2a002c9c479c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975986949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1975986949
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1253225629
Short name T98
Test name
Test status
Simulation time 202892668 ps
CPU time 1.04 seconds
Started Jul 07 04:21:58 PM PDT 24
Finished Jul 07 04:22:00 PM PDT 24
Peak memory 198528 kb
Host smart-5a7f799d-f436-43a5-9158-89c75744d46f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253225629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1253225629
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.260716976
Short name T1234
Test name
Test status
Simulation time 77115752 ps
CPU time 0.81 seconds
Started Jul 07 04:20:55 PM PDT 24
Finished Jul 07 04:20:56 PM PDT 24
Peak memory 200232 kb
Host smart-8f7c09f5-92b9-48ea-bec4-23b35cb2eb43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260716976 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.260716976
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.361164763
Short name T1301
Test name
Test status
Simulation time 20457632 ps
CPU time 0.63 seconds
Started Jul 07 04:20:55 PM PDT 24
Finished Jul 07 04:20:56 PM PDT 24
Peak memory 196100 kb
Host smart-fe770e4d-b4c4-4acc-8675-75466582df3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361164763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.361164763
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2038589002
Short name T1201
Test name
Test status
Simulation time 46718513 ps
CPU time 0.57 seconds
Started Jul 07 04:19:27 PM PDT 24
Finished Jul 07 04:19:28 PM PDT 24
Peak memory 195044 kb
Host smart-fe61df6b-122d-4947-9c24-68a9446fa705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038589002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2038589002
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1165809423
Short name T1215
Test name
Test status
Simulation time 16815309 ps
CPU time 0.66 seconds
Started Jul 07 04:19:07 PM PDT 24
Finished Jul 07 04:19:08 PM PDT 24
Peak memory 196780 kb
Host smart-4f7910f3-7af7-445e-a5f2-343b04f458b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165809423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1165809423
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.634847391
Short name T1284
Test name
Test status
Simulation time 25188362 ps
CPU time 1.27 seconds
Started Jul 07 04:21:28 PM PDT 24
Finished Jul 07 04:21:30 PM PDT 24
Peak memory 199468 kb
Host smart-aac4c611-b741-4a54-bd43-e0cc99883a57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634847391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.634847391
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3545524542
Short name T104
Test name
Test status
Simulation time 41174509 ps
CPU time 0.93 seconds
Started Jul 07 04:21:38 PM PDT 24
Finished Jul 07 04:21:39 PM PDT 24
Peak memory 199496 kb
Host smart-d6abcd89-4f67-4bb3-939f-bdf61304b8b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545524542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3545524542
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3376186279
Short name T1239
Test name
Test status
Simulation time 30766382 ps
CPU time 0.86 seconds
Started Jul 07 04:21:11 PM PDT 24
Finished Jul 07 04:21:13 PM PDT 24
Peak memory 199248 kb
Host smart-6bbd4ed4-df2a-4ec2-b86e-ee74c1a982e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376186279 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3376186279
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3269683719
Short name T93
Test name
Test status
Simulation time 27363466 ps
CPU time 0.68 seconds
Started Jul 07 04:20:48 PM PDT 24
Finished Jul 07 04:20:49 PM PDT 24
Peak memory 196128 kb
Host smart-d99ed2cb-07ea-4584-9a87-8c6886f15ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269683719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3269683719
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.4124775300
Short name T1243
Test name
Test status
Simulation time 16043131 ps
CPU time 0.62 seconds
Started Jul 07 04:22:24 PM PDT 24
Finished Jul 07 04:22:25 PM PDT 24
Peak memory 193452 kb
Host smart-62ccd018-b7f8-4885-9ffb-6073b1ee33ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124775300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4124775300
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1362958663
Short name T1303
Test name
Test status
Simulation time 19857240 ps
CPU time 0.73 seconds
Started Jul 07 04:18:23 PM PDT 24
Finished Jul 07 04:18:24 PM PDT 24
Peak memory 197756 kb
Host smart-959704d1-81b3-4f0a-8003-6bd403d90781
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362958663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1362958663
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1681734337
Short name T1305
Test name
Test status
Simulation time 46381635 ps
CPU time 1.4 seconds
Started Jul 07 04:22:24 PM PDT 24
Finished Jul 07 04:22:26 PM PDT 24
Peak memory 199260 kb
Host smart-64eb96aa-6223-4acc-bc1a-96b3f5d6b7ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681734337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1681734337
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2436621399
Short name T1291
Test name
Test status
Simulation time 110365994 ps
CPU time 0.91 seconds
Started Jul 07 04:17:27 PM PDT 24
Finished Jul 07 04:17:28 PM PDT 24
Peak memory 199572 kb
Host smart-b9d4d927-89be-49f9-b7d7-0cfc3b54d664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436621399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2436621399
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1700893601
Short name T1192
Test name
Test status
Simulation time 17926195 ps
CPU time 0.7 seconds
Started Jul 07 04:19:23 PM PDT 24
Finished Jul 07 04:19:24 PM PDT 24
Peak memory 199020 kb
Host smart-c45fb628-dbef-42ba-8b8f-a05b1291bc0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700893601 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1700893601
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3898632593
Short name T90
Test name
Test status
Simulation time 15325141 ps
CPU time 0.57 seconds
Started Jul 07 04:18:45 PM PDT 24
Finished Jul 07 04:18:46 PM PDT 24
Peak memory 195916 kb
Host smart-28818d97-d007-43a7-97d3-e8e38e3e7615
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898632593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3898632593
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1558156886
Short name T1194
Test name
Test status
Simulation time 16045979 ps
CPU time 0.63 seconds
Started Jul 07 04:18:57 PM PDT 24
Finished Jul 07 04:18:58 PM PDT 24
Peak memory 195108 kb
Host smart-49f50ee6-ff42-41b8-8469-f5ebda213786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558156886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1558156886
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2341914790
Short name T1294
Test name
Test status
Simulation time 152250881 ps
CPU time 0.77 seconds
Started Jul 07 04:18:15 PM PDT 24
Finished Jul 07 04:18:16 PM PDT 24
Peak memory 197832 kb
Host smart-1e6a86be-569b-4b44-8d5a-07b37f35427f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341914790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2341914790
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.425097019
Short name T1212
Test name
Test status
Simulation time 92775375 ps
CPU time 1.26 seconds
Started Jul 07 04:22:09 PM PDT 24
Finished Jul 07 04:22:11 PM PDT 24
Peak memory 199208 kb
Host smart-620d3a96-6b08-40bc-bc49-c349ca175f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425097019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.425097019
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.410215308
Short name T99
Test name
Test status
Simulation time 170419723 ps
CPU time 0.94 seconds
Started Jul 07 04:18:17 PM PDT 24
Finished Jul 07 04:18:18 PM PDT 24
Peak memory 199656 kb
Host smart-5f71328d-24b1-4884-9645-be2e4c65131c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410215308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.410215308
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3438943804
Short name T1213
Test name
Test status
Simulation time 19860684 ps
CPU time 1.08 seconds
Started Jul 07 04:20:59 PM PDT 24
Finished Jul 07 04:21:00 PM PDT 24
Peak memory 200880 kb
Host smart-709d5f43-80b6-4d83-9748-b9d60b85667d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438943804 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3438943804
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2843223987
Short name T1211
Test name
Test status
Simulation time 25849906 ps
CPU time 0.61 seconds
Started Jul 07 04:22:21 PM PDT 24
Finished Jul 07 04:22:23 PM PDT 24
Peak memory 194044 kb
Host smart-0b3dfee9-f6aa-408d-add7-5160b1da4a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843223987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2843223987
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3603627200
Short name T94
Test name
Test status
Simulation time 67290795 ps
CPU time 0.64 seconds
Started Jul 07 04:18:45 PM PDT 24
Finished Jul 07 04:18:46 PM PDT 24
Peak memory 194896 kb
Host smart-12225519-2d7e-4203-82c2-60e2496bc076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603627200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3603627200
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2227486420
Short name T1286
Test name
Test status
Simulation time 87519997 ps
CPU time 1.28 seconds
Started Jul 07 04:18:59 PM PDT 24
Finished Jul 07 04:19:00 PM PDT 24
Peak memory 201092 kb
Host smart-8f116c24-e63c-4985-9a94-cf8f3a0c8bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227486420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2227486420
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2473744671
Short name T1250
Test name
Test status
Simulation time 399225643 ps
CPU time 1.44 seconds
Started Jul 07 04:18:20 PM PDT 24
Finished Jul 07 04:18:22 PM PDT 24
Peak memory 200256 kb
Host smart-d717dbb8-d3b3-49eb-b75c-aeee67460380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473744671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2473744671
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.341996095
Short name T1273
Test name
Test status
Simulation time 24441798 ps
CPU time 1 seconds
Started Jul 07 04:23:02 PM PDT 24
Finished Jul 07 04:23:03 PM PDT 24
Peak memory 199548 kb
Host smart-fc949a09-a0f0-49c0-8a38-a8d30b9f96ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341996095 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.341996095
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2124540637
Short name T1235
Test name
Test status
Simulation time 54507046 ps
CPU time 0.63 seconds
Started Jul 07 04:19:07 PM PDT 24
Finished Jul 07 04:19:08 PM PDT 24
Peak memory 196468 kb
Host smart-19fd363e-5f93-4a5b-b31d-8b04c1bf2cbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124540637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2124540637
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3604975200
Short name T1287
Test name
Test status
Simulation time 36835883 ps
CPU time 0.55 seconds
Started Jul 07 04:19:45 PM PDT 24
Finished Jul 07 04:19:46 PM PDT 24
Peak memory 195044 kb
Host smart-f7f047bc-2e6e-496d-9b97-46fa7a09dc99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604975200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3604975200
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3554302101
Short name T92
Test name
Test status
Simulation time 36397629 ps
CPU time 0.77 seconds
Started Jul 07 04:21:25 PM PDT 24
Finished Jul 07 04:21:26 PM PDT 24
Peak memory 198416 kb
Host smart-050802fe-4bc0-449a-93ad-c1c5fd305e19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554302101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3554302101
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2890306822
Short name T1206
Test name
Test status
Simulation time 365393163 ps
CPU time 1.9 seconds
Started Jul 07 04:19:10 PM PDT 24
Finished Jul 07 04:19:12 PM PDT 24
Peak memory 200776 kb
Host smart-a1811885-2c7b-4d35-b4b8-bd7817dce109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890306822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2890306822
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2087548737
Short name T100
Test name
Test status
Simulation time 237432941 ps
CPU time 0.99 seconds
Started Jul 07 04:21:25 PM PDT 24
Finished Jul 07 04:21:26 PM PDT 24
Peak memory 199636 kb
Host smart-560eab68-29f8-48ef-a356-9f558c820f02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087548737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2087548737
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3834874213
Short name T1241
Test name
Test status
Simulation time 143438551 ps
CPU time 1.2 seconds
Started Jul 07 04:18:18 PM PDT 24
Finished Jul 07 04:18:19 PM PDT 24
Peak memory 200760 kb
Host smart-c6884cf4-16c4-4b53-be47-3322641bfe8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834874213 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3834874213
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2770156181
Short name T1184
Test name
Test status
Simulation time 42419404 ps
CPU time 0.58 seconds
Started Jul 07 04:18:15 PM PDT 24
Finished Jul 07 04:18:15 PM PDT 24
Peak memory 196044 kb
Host smart-c3ec7fa5-4bca-4c63-a896-2eb05bcc3024
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770156181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2770156181
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.140509743
Short name T1182
Test name
Test status
Simulation time 14143425 ps
CPU time 0.6 seconds
Started Jul 07 04:18:57 PM PDT 24
Finished Jul 07 04:18:58 PM PDT 24
Peak memory 195048 kb
Host smart-971dbf3b-9c1a-449d-ade0-576b0fe32163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140509743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.140509743
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.790405845
Short name T91
Test name
Test status
Simulation time 35208247 ps
CPU time 0.61 seconds
Started Jul 07 04:23:05 PM PDT 24
Finished Jul 07 04:23:06 PM PDT 24
Peak memory 195984 kb
Host smart-a2923a5a-adc1-4f9b-b2a0-8a4d942d32c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790405845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.790405845
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.490461146
Short name T1197
Test name
Test status
Simulation time 73465946 ps
CPU time 1.88 seconds
Started Jul 07 04:19:41 PM PDT 24
Finished Jul 07 04:19:43 PM PDT 24
Peak memory 201088 kb
Host smart-67ba71a4-0241-4342-9527-d8a3f0cb46a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490461146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.490461146
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2621137431
Short name T1216
Test name
Test status
Simulation time 138982574 ps
CPU time 0.89 seconds
Started Jul 07 04:18:24 PM PDT 24
Finished Jul 07 04:18:25 PM PDT 24
Peak memory 199640 kb
Host smart-408bbfa1-02d5-441f-b5c7-a0a155f67f69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621137431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2621137431
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.287291066
Short name T1263
Test name
Test status
Simulation time 73064474 ps
CPU time 0.7 seconds
Started Jul 07 04:21:15 PM PDT 24
Finished Jul 07 04:21:16 PM PDT 24
Peak memory 197296 kb
Host smart-fbab6226-a863-409f-be2d-d8251f4a9b4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287291066 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.287291066
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3457943602
Short name T1314
Test name
Test status
Simulation time 55616931 ps
CPU time 0.63 seconds
Started Jul 07 04:21:31 PM PDT 24
Finished Jul 07 04:21:32 PM PDT 24
Peak memory 195164 kb
Host smart-53f0b252-00d0-4ed3-9d79-a4318b58c86d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457943602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3457943602
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1014890777
Short name T1264
Test name
Test status
Simulation time 29242102 ps
CPU time 0.58 seconds
Started Jul 07 04:18:14 PM PDT 24
Finished Jul 07 04:18:15 PM PDT 24
Peak memory 195384 kb
Host smart-e2774741-0002-44e9-aa36-25b597beac84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014890777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1014890777
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3562104371
Short name T1246
Test name
Test status
Simulation time 18231205 ps
CPU time 0.65 seconds
Started Jul 07 04:20:46 PM PDT 24
Finished Jul 07 04:20:47 PM PDT 24
Peak memory 196128 kb
Host smart-f26efb5f-184e-47c5-afed-faa460b5bf9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562104371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3562104371
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3463380396
Short name T1188
Test name
Test status
Simulation time 112317170 ps
CPU time 1.59 seconds
Started Jul 07 04:22:13 PM PDT 24
Finished Jul 07 04:22:15 PM PDT 24
Peak memory 200632 kb
Host smart-a016312c-922a-4e87-8191-2a728d88214b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463380396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3463380396
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1124964880
Short name T1262
Test name
Test status
Simulation time 171471661 ps
CPU time 1.3 seconds
Started Jul 07 04:22:53 PM PDT 24
Finished Jul 07 04:22:55 PM PDT 24
Peak memory 199176 kb
Host smart-d5eaf1c8-1190-4794-8da9-18b720a57974
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124964880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1124964880
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3579748090
Short name T1292
Test name
Test status
Simulation time 87520313 ps
CPU time 1.16 seconds
Started Jul 07 04:22:56 PM PDT 24
Finished Jul 07 04:22:58 PM PDT 24
Peak memory 200640 kb
Host smart-b02ea066-b606-4d95-9bc5-29f0d2e20191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579748090 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3579748090
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.320414968
Short name T1312
Test name
Test status
Simulation time 17762467 ps
CPU time 0.65 seconds
Started Jul 07 04:18:20 PM PDT 24
Finished Jul 07 04:18:21 PM PDT 24
Peak memory 196832 kb
Host smart-d64bc65b-c3bb-4da0-958e-7f1c2e95e606
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320414968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.320414968
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3511224237
Short name T1276
Test name
Test status
Simulation time 17378663 ps
CPU time 0.61 seconds
Started Jul 07 04:21:11 PM PDT 24
Finished Jul 07 04:21:13 PM PDT 24
Peak memory 193924 kb
Host smart-b0cee88c-eef9-414a-a6b4-ab57b06cf505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511224237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3511224237
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2036999766
Short name T1288
Test name
Test status
Simulation time 21585312 ps
CPU time 0.63 seconds
Started Jul 07 04:18:25 PM PDT 24
Finished Jul 07 04:18:26 PM PDT 24
Peak memory 196252 kb
Host smart-f80d4b78-e0f2-4329-9921-222496f86c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036999766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2036999766
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2431893479
Short name T1199
Test name
Test status
Simulation time 125111996 ps
CPU time 1.44 seconds
Started Jul 07 04:18:22 PM PDT 24
Finished Jul 07 04:18:24 PM PDT 24
Peak memory 200780 kb
Host smart-c5933e06-e694-4a80-a986-ab6452bb452b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431893479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2431893479
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3712929316
Short name T138
Test name
Test status
Simulation time 85888880 ps
CPU time 1.41 seconds
Started Jul 07 04:22:10 PM PDT 24
Finished Jul 07 04:22:12 PM PDT 24
Peak memory 199000 kb
Host smart-26051d64-255f-4197-b3c1-1b647d474476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712929316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3712929316
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2320566871
Short name T1191
Test name
Test status
Simulation time 57475149 ps
CPU time 0.7 seconds
Started Jul 07 04:19:42 PM PDT 24
Finished Jul 07 04:19:43 PM PDT 24
Peak memory 198696 kb
Host smart-e3f13e16-b8fc-4da7-85e5-12f2caeba4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320566871 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2320566871
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2430127329
Short name T1242
Test name
Test status
Simulation time 17985614 ps
CPU time 0.61 seconds
Started Jul 07 04:21:28 PM PDT 24
Finished Jul 07 04:21:30 PM PDT 24
Peak memory 194780 kb
Host smart-cef5fd3d-a92a-41e8-b1f5-cdc973dd89be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430127329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2430127329
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1045634820
Short name T1178
Test name
Test status
Simulation time 44169554 ps
CPU time 0.55 seconds
Started Jul 07 04:22:54 PM PDT 24
Finished Jul 07 04:22:54 PM PDT 24
Peak memory 194644 kb
Host smart-2b4b0d3c-ab2b-49eb-a0d8-0990b20e65ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045634820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1045634820
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1977542745
Short name T1232
Test name
Test status
Simulation time 46477944 ps
CPU time 0.64 seconds
Started Jul 07 04:18:19 PM PDT 24
Finished Jul 07 04:18:19 PM PDT 24
Peak memory 196212 kb
Host smart-e1b564e8-60f3-4a04-a9d8-51b5a4af5579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977542745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1977542745
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.443483276
Short name T1282
Test name
Test status
Simulation time 130310192 ps
CPU time 1.8 seconds
Started Jul 07 04:18:20 PM PDT 24
Finished Jul 07 04:18:22 PM PDT 24
Peak memory 201104 kb
Host smart-cf30fd6d-2746-40df-a2bf-d8bedf59cff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443483276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.443483276
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3787510990
Short name T136
Test name
Test status
Simulation time 516774974 ps
CPU time 1.27 seconds
Started Jul 07 04:21:23 PM PDT 24
Finished Jul 07 04:21:25 PM PDT 24
Peak memory 199976 kb
Host smart-2cc2da7d-4234-4561-bc9e-6bc2175c6fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787510990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3787510990
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.49869117
Short name T83
Test name
Test status
Simulation time 64778851 ps
CPU time 0.78 seconds
Started Jul 07 04:18:17 PM PDT 24
Finished Jul 07 04:18:18 PM PDT 24
Peak memory 196880 kb
Host smart-3e15a1d6-4ce0-4253-95a8-c414440b5805
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49869117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.49869117
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3963633110
Short name T1185
Test name
Test status
Simulation time 74246989 ps
CPU time 1.34 seconds
Started Jul 07 04:17:29 PM PDT 24
Finished Jul 07 04:17:30 PM PDT 24
Peak memory 198712 kb
Host smart-41b513cb-544c-4eb7-9590-e21f02abb44b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963633110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3963633110
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.828635441
Short name T1266
Test name
Test status
Simulation time 23825409 ps
CPU time 0.62 seconds
Started Jul 07 04:17:33 PM PDT 24
Finished Jul 07 04:17:34 PM PDT 24
Peak memory 196144 kb
Host smart-27128dc8-938f-422e-8c3d-af1affaedca8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828635441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.828635441
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.215747702
Short name T1223
Test name
Test status
Simulation time 15838455 ps
CPU time 0.68 seconds
Started Jul 07 04:18:12 PM PDT 24
Finished Jul 07 04:18:13 PM PDT 24
Peak memory 198476 kb
Host smart-1f0d2dff-b235-4540-a940-cdf5da058f3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215747702 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.215747702
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2072668094
Short name T84
Test name
Test status
Simulation time 62936477 ps
CPU time 0.61 seconds
Started Jul 07 04:18:05 PM PDT 24
Finished Jul 07 04:18:05 PM PDT 24
Peak memory 196200 kb
Host smart-196d85e7-f60f-4df8-8c32-f404193fd184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072668094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2072668094
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.491181679
Short name T1269
Test name
Test status
Simulation time 149560601 ps
CPU time 0.57 seconds
Started Jul 07 04:21:21 PM PDT 24
Finished Jul 07 04:21:22 PM PDT 24
Peak memory 194960 kb
Host smart-f0eeb2c5-d125-4d42-a0b4-3d998bc5aed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491181679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.491181679
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.255889616
Short name T1281
Test name
Test status
Simulation time 56949337 ps
CPU time 0.64 seconds
Started Jul 07 04:19:15 PM PDT 24
Finished Jul 07 04:19:16 PM PDT 24
Peak memory 196204 kb
Host smart-d747d254-af71-4f57-b56a-200c9b1daca2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255889616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.255889616
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2224141802
Short name T1202
Test name
Test status
Simulation time 1933539471 ps
CPU time 2.34 seconds
Started Jul 07 04:18:24 PM PDT 24
Finished Jul 07 04:18:26 PM PDT 24
Peak memory 200600 kb
Host smart-c64d9c94-e223-4609-9cb3-dcbecd046e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224141802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2224141802
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4104112778
Short name T1309
Test name
Test status
Simulation time 296400642 ps
CPU time 1.21 seconds
Started Jul 07 04:18:24 PM PDT 24
Finished Jul 07 04:18:25 PM PDT 24
Peak memory 199736 kb
Host smart-7a7aea12-a490-4194-81a8-54d9f57e7aba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104112778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4104112778
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.613558624
Short name T1298
Test name
Test status
Simulation time 13362285 ps
CPU time 0.56 seconds
Started Jul 07 04:21:32 PM PDT 24
Finished Jul 07 04:21:33 PM PDT 24
Peak memory 194812 kb
Host smart-1de0ee1f-3f60-4e9b-88dc-a1de40aaea63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613558624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.613558624
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2849074098
Short name T1277
Test name
Test status
Simulation time 36326475 ps
CPU time 0.63 seconds
Started Jul 07 04:18:20 PM PDT 24
Finished Jul 07 04:18:21 PM PDT 24
Peak memory 195440 kb
Host smart-7af5fd03-cf7a-43f1-a4d7-83979d8016ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849074098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2849074098
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.942659151
Short name T1297
Test name
Test status
Simulation time 29925744 ps
CPU time 0.6 seconds
Started Jul 07 04:21:15 PM PDT 24
Finished Jul 07 04:21:16 PM PDT 24
Peak memory 193832 kb
Host smart-20f3dc62-eedd-4784-a7a4-abf1dd9ad039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942659151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.942659151
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1460930848
Short name T1245
Test name
Test status
Simulation time 40416962 ps
CPU time 0.55 seconds
Started Jul 07 04:18:24 PM PDT 24
Finished Jul 07 04:18:25 PM PDT 24
Peak memory 195016 kb
Host smart-b1aa180a-b960-4d97-aa90-14df37688583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460930848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1460930848
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1876654741
Short name T1240
Test name
Test status
Simulation time 35044098 ps
CPU time 0.55 seconds
Started Jul 07 04:22:18 PM PDT 24
Finished Jul 07 04:22:19 PM PDT 24
Peak memory 194976 kb
Host smart-f527cf50-c3f4-43e9-b948-2860768d8959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876654741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1876654741
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.197760235
Short name T1195
Test name
Test status
Simulation time 30714325 ps
CPU time 0.61 seconds
Started Jul 07 04:19:34 PM PDT 24
Finished Jul 07 04:19:35 PM PDT 24
Peak memory 194896 kb
Host smart-4aecddf3-8612-41f1-895b-71373b8e0551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197760235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.197760235
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4219191861
Short name T1257
Test name
Test status
Simulation time 48353616 ps
CPU time 0.58 seconds
Started Jul 07 04:18:41 PM PDT 24
Finished Jul 07 04:18:42 PM PDT 24
Peak memory 194880 kb
Host smart-8e8176ac-c638-4814-9819-4b14f5d7319e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219191861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4219191861
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3019647706
Short name T1214
Test name
Test status
Simulation time 43967710 ps
CPU time 0.62 seconds
Started Jul 07 04:21:56 PM PDT 24
Finished Jul 07 04:21:57 PM PDT 24
Peak memory 194124 kb
Host smart-3c83988e-fe45-484c-967a-92dd3fe1bee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019647706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3019647706
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1793630789
Short name T1285
Test name
Test status
Simulation time 42568874 ps
CPU time 0.56 seconds
Started Jul 07 04:19:34 PM PDT 24
Finished Jul 07 04:19:34 PM PDT 24
Peak memory 194900 kb
Host smart-b83a3a27-3aca-488b-b8a3-b5616ed243ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793630789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1793630789
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3749899488
Short name T1226
Test name
Test status
Simulation time 245485385 ps
CPU time 0.6 seconds
Started Jul 07 04:18:27 PM PDT 24
Finished Jul 07 04:18:28 PM PDT 24
Peak memory 194912 kb
Host smart-2371e529-630e-4181-b5f5-2b9962a8e597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749899488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3749899488
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2987844348
Short name T1283
Test name
Test status
Simulation time 52640702 ps
CPU time 0.74 seconds
Started Jul 07 04:19:16 PM PDT 24
Finished Jul 07 04:19:17 PM PDT 24
Peak memory 196936 kb
Host smart-c9be8922-0c62-40b7-ae0c-302a942bed07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987844348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2987844348
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2271666378
Short name T1247
Test name
Test status
Simulation time 336480162 ps
CPU time 2.28 seconds
Started Jul 07 04:21:10 PM PDT 24
Finished Jul 07 04:21:13 PM PDT 24
Peak memory 197360 kb
Host smart-de1595af-5ca2-4074-8f47-363390265810
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271666378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2271666378
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2961038174
Short name T1280
Test name
Test status
Simulation time 17609724 ps
CPU time 0.59 seconds
Started Jul 07 04:17:22 PM PDT 24
Finished Jul 07 04:17:23 PM PDT 24
Peak memory 196056 kb
Host smart-9969e5f0-1ab1-4948-a849-97064057f767
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961038174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2961038174
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4227923223
Short name T1181
Test name
Test status
Simulation time 47871336 ps
CPU time 1.21 seconds
Started Jul 07 04:21:09 PM PDT 24
Finished Jul 07 04:21:11 PM PDT 24
Peak memory 200024 kb
Host smart-c1b835c0-100e-4763-a8dd-8bf400b452ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227923223 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4227923223
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2100511539
Short name T1238
Test name
Test status
Simulation time 25435863 ps
CPU time 0.64 seconds
Started Jul 07 04:21:06 PM PDT 24
Finished Jul 07 04:21:07 PM PDT 24
Peak memory 195232 kb
Host smart-0a821cd2-8bea-4a36-bcee-5b0f4dabc262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100511539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2100511539
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1103806464
Short name T1222
Test name
Test status
Simulation time 117457326 ps
CPU time 0.64 seconds
Started Jul 07 04:19:47 PM PDT 24
Finished Jul 07 04:19:48 PM PDT 24
Peak memory 195016 kb
Host smart-dc073dda-ae90-47a8-93e7-677651af82d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103806464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1103806464
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2490381675
Short name T1256
Test name
Test status
Simulation time 31186547 ps
CPU time 0.74 seconds
Started Jul 07 04:21:09 PM PDT 24
Finished Jul 07 04:21:10 PM PDT 24
Peak memory 197684 kb
Host smart-af66a471-3591-4a92-b68e-332a2a42ab7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490381675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2490381675
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3425779050
Short name T1289
Test name
Test status
Simulation time 282883138 ps
CPU time 1.54 seconds
Started Jul 07 04:19:45 PM PDT 24
Finished Jul 07 04:19:47 PM PDT 24
Peak memory 201088 kb
Host smart-7660098c-6722-4f6b-af65-ee964d62dfe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425779050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3425779050
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1922852189
Short name T102
Test name
Test status
Simulation time 302875237 ps
CPU time 1.36 seconds
Started Jul 07 04:20:44 PM PDT 24
Finished Jul 07 04:20:45 PM PDT 24
Peak memory 199920 kb
Host smart-db8e0d0b-415f-4054-b5da-8b28770306d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922852189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1922852189
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1644565720
Short name T1311
Test name
Test status
Simulation time 13071966 ps
CPU time 0.55 seconds
Started Jul 07 04:22:14 PM PDT 24
Finished Jul 07 04:22:15 PM PDT 24
Peak memory 194900 kb
Host smart-93b1dbdf-4e14-4946-b29b-c1c00d1f1631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644565720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1644565720
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.154518451
Short name T1290
Test name
Test status
Simulation time 87884677 ps
CPU time 0.54 seconds
Started Jul 07 04:21:22 PM PDT 24
Finished Jul 07 04:21:23 PM PDT 24
Peak memory 194908 kb
Host smart-d7fd0ac1-e9a5-4145-82e0-695897dc1071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154518451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.154518451
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.400219480
Short name T1300
Test name
Test status
Simulation time 23308533 ps
CPU time 0.6 seconds
Started Jul 07 04:18:34 PM PDT 24
Finished Jul 07 04:18:35 PM PDT 24
Peak memory 195108 kb
Host smart-c4bbf4ce-9dc4-4ffb-a9ae-3bbcf22504c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400219480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.400219480
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3856142841
Short name T1189
Test name
Test status
Simulation time 50350396 ps
CPU time 0.57 seconds
Started Jul 07 04:21:29 PM PDT 24
Finished Jul 07 04:21:30 PM PDT 24
Peak memory 194944 kb
Host smart-aa237306-5582-4322-9c2c-5d0339b771f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856142841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3856142841
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1942862055
Short name T1179
Test name
Test status
Simulation time 41887258 ps
CPU time 0.6 seconds
Started Jul 07 04:18:40 PM PDT 24
Finished Jul 07 04:18:41 PM PDT 24
Peak memory 194940 kb
Host smart-362c4365-3e32-4b02-8dbc-5550505bbf56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942862055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1942862055
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1383905391
Short name T1229
Test name
Test status
Simulation time 15426962 ps
CPU time 0.58 seconds
Started Jul 07 04:18:40 PM PDT 24
Finished Jul 07 04:18:41 PM PDT 24
Peak memory 194956 kb
Host smart-e2b6844b-7254-4e96-b402-6c1888b8b5b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383905391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1383905391
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2124663292
Short name T1180
Test name
Test status
Simulation time 13837088 ps
CPU time 0.61 seconds
Started Jul 07 04:19:32 PM PDT 24
Finished Jul 07 04:19:33 PM PDT 24
Peak memory 195028 kb
Host smart-f93fa3f7-2149-4ed8-8775-26c73f042d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124663292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2124663292
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.807736745
Short name T1187
Test name
Test status
Simulation time 138156200 ps
CPU time 0.58 seconds
Started Jul 07 04:21:10 PM PDT 24
Finished Jul 07 04:21:11 PM PDT 24
Peak memory 194200 kb
Host smart-8dfe09fc-0096-47f4-992e-4432db8c7a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807736745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.807736745
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4090748661
Short name T1251
Test name
Test status
Simulation time 71989435 ps
CPU time 0.6 seconds
Started Jul 07 04:22:09 PM PDT 24
Finished Jul 07 04:22:10 PM PDT 24
Peak memory 193408 kb
Host smart-bc7f6d03-98d7-40a9-badf-c09155eaaa21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090748661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4090748661
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1976797830
Short name T1278
Test name
Test status
Simulation time 13709327 ps
CPU time 0.55 seconds
Started Jul 07 04:18:45 PM PDT 24
Finished Jul 07 04:18:46 PM PDT 24
Peak memory 194896 kb
Host smart-c8954bb2-4b1e-469f-8640-95fcd209e2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976797830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1976797830
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3236061229
Short name T82
Test name
Test status
Simulation time 51578011 ps
CPU time 0.8 seconds
Started Jul 07 04:18:12 PM PDT 24
Finished Jul 07 04:18:13 PM PDT 24
Peak memory 197500 kb
Host smart-c3ae41dc-7b7a-4cd2-b4b8-8f2d5209f3c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236061229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3236061229
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3905923719
Short name T1255
Test name
Test status
Simulation time 872663663 ps
CPU time 2.45 seconds
Started Jul 07 04:21:23 PM PDT 24
Finished Jul 07 04:21:25 PM PDT 24
Peak memory 198508 kb
Host smart-fed90b8a-a1db-4c7e-96f1-c238ed4d5697
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905923719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3905923719
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.931911035
Short name T1219
Test name
Test status
Simulation time 15176614 ps
CPU time 0.64 seconds
Started Jul 07 04:19:01 PM PDT 24
Finished Jul 07 04:19:02 PM PDT 24
Peak memory 196056 kb
Host smart-b7483824-7529-4bf1-b8e8-51687ed820c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931911035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.931911035
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4191758997
Short name T1224
Test name
Test status
Simulation time 195588723 ps
CPU time 0.81 seconds
Started Jul 07 04:21:22 PM PDT 24
Finished Jul 07 04:21:23 PM PDT 24
Peak memory 199048 kb
Host smart-8adb8055-fe1b-47a2-b79e-773f7ab04fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191758997 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4191758997
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2374055962
Short name T1217
Test name
Test status
Simulation time 13550047 ps
CPU time 0.6 seconds
Started Jul 07 04:17:27 PM PDT 24
Finished Jul 07 04:17:28 PM PDT 24
Peak memory 196040 kb
Host smart-79387885-3bde-442d-9e76-c757b9108672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374055962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2374055962
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1671920902
Short name T1268
Test name
Test status
Simulation time 23591196 ps
CPU time 0.57 seconds
Started Jul 07 04:18:24 PM PDT 24
Finished Jul 07 04:18:25 PM PDT 24
Peak memory 195088 kb
Host smart-fc0d9611-5a9f-41b2-9a63-9e7a51126f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671920902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1671920902
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.522873460
Short name T1236
Test name
Test status
Simulation time 99652260 ps
CPU time 0.71 seconds
Started Jul 07 04:21:22 PM PDT 24
Finished Jul 07 04:21:24 PM PDT 24
Peak memory 197748 kb
Host smart-f8005342-7738-45ca-b486-4e67a21db1db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522873460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.522873460
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2514854316
Short name T1220
Test name
Test status
Simulation time 348220768 ps
CPU time 1.91 seconds
Started Jul 07 04:21:10 PM PDT 24
Finished Jul 07 04:21:12 PM PDT 24
Peak memory 200332 kb
Host smart-0edd8047-353b-4f66-98c0-56841defd6cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514854316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2514854316
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2975811659
Short name T1193
Test name
Test status
Simulation time 68377276 ps
CPU time 0.61 seconds
Started Jul 07 04:18:40 PM PDT 24
Finished Jul 07 04:18:41 PM PDT 24
Peak memory 195016 kb
Host smart-e0f1335c-478e-417e-8d3b-98709dc5269c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975811659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2975811659
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3725766660
Short name T1295
Test name
Test status
Simulation time 42719371 ps
CPU time 0.58 seconds
Started Jul 07 04:20:02 PM PDT 24
Finished Jul 07 04:20:02 PM PDT 24
Peak memory 195112 kb
Host smart-ee45e38d-8ae9-4cb3-aafb-7e7d6fbdd211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725766660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3725766660
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4031765138
Short name T1186
Test name
Test status
Simulation time 103688798 ps
CPU time 0.58 seconds
Started Jul 07 04:19:08 PM PDT 24
Finished Jul 07 04:19:09 PM PDT 24
Peak memory 195376 kb
Host smart-82d2028d-c5e8-4be2-aa6c-03a1d5004c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031765138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4031765138
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3662826637
Short name T1267
Test name
Test status
Simulation time 124956593 ps
CPU time 0.63 seconds
Started Jul 07 04:19:26 PM PDT 24
Finished Jul 07 04:19:27 PM PDT 24
Peak memory 195376 kb
Host smart-ab30f974-c38e-4e42-abad-c3f17bf9443f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662826637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3662826637
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3221115643
Short name T1272
Test name
Test status
Simulation time 26001957 ps
CPU time 0.6 seconds
Started Jul 07 04:22:19 PM PDT 24
Finished Jul 07 04:22:20 PM PDT 24
Peak memory 193916 kb
Host smart-e574cc5f-5d21-43db-b1c8-361dfc1e582e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221115643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3221115643
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.471621885
Short name T1237
Test name
Test status
Simulation time 15220297 ps
CPU time 0.6 seconds
Started Jul 07 04:19:15 PM PDT 24
Finished Jul 07 04:19:16 PM PDT 24
Peak memory 194956 kb
Host smart-22f5e92e-326f-4f51-b40c-3ebf2a5cea20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471621885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.471621885
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3036631556
Short name T1306
Test name
Test status
Simulation time 12436620 ps
CPU time 0.54 seconds
Started Jul 07 04:22:19 PM PDT 24
Finished Jul 07 04:22:20 PM PDT 24
Peak memory 194172 kb
Host smart-fb9e54fd-c8e6-46a0-b99f-415de408f68a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036631556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3036631556
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2490294992
Short name T1296
Test name
Test status
Simulation time 23433404 ps
CPU time 0.54 seconds
Started Jul 07 04:22:12 PM PDT 24
Finished Jul 07 04:22:13 PM PDT 24
Peak memory 194784 kb
Host smart-7ceee41e-0c28-4997-b23f-1fb115d3ee72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490294992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2490294992
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1365432369
Short name T1233
Test name
Test status
Simulation time 35210048 ps
CPU time 0.6 seconds
Started Jul 07 04:20:01 PM PDT 24
Finished Jul 07 04:20:02 PM PDT 24
Peak memory 195048 kb
Host smart-eb22b65d-91fb-4d42-afd8-ae61aeec0bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365432369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1365432369
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2177437390
Short name T1302
Test name
Test status
Simulation time 16504270 ps
CPU time 0.6 seconds
Started Jul 07 04:21:11 PM PDT 24
Finished Jul 07 04:21:13 PM PDT 24
Peak memory 194072 kb
Host smart-1d019a73-40f1-4ea0-a14d-2dc9b4b43c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177437390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2177437390
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4140472642
Short name T1230
Test name
Test status
Simulation time 78037230 ps
CPU time 1.17 seconds
Started Jul 07 04:21:09 PM PDT 24
Finished Jul 07 04:21:10 PM PDT 24
Peak memory 200212 kb
Host smart-ccb93437-2c36-404a-b534-0241573da774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140472642 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.4140472642
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2911085684
Short name T86
Test name
Test status
Simulation time 12744265 ps
CPU time 0.63 seconds
Started Jul 07 04:21:17 PM PDT 24
Finished Jul 07 04:21:18 PM PDT 24
Peak memory 195648 kb
Host smart-28dc9a37-d22c-4e44-910a-c761b5114e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911085684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2911085684
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2486340160
Short name T1205
Test name
Test status
Simulation time 11101115 ps
CPU time 0.56 seconds
Started Jul 07 04:17:16 PM PDT 24
Finished Jul 07 04:17:17 PM PDT 24
Peak memory 194936 kb
Host smart-cfe136a7-914b-4495-a863-853559dd677f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486340160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2486340160
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2984940654
Short name T1249
Test name
Test status
Simulation time 33384122 ps
CPU time 0.74 seconds
Started Jul 07 04:21:22 PM PDT 24
Finished Jul 07 04:21:23 PM PDT 24
Peak memory 198420 kb
Host smart-9d8c7038-fc0b-4b64-b2b7-ead26e702390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984940654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2984940654
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.627090585
Short name T1231
Test name
Test status
Simulation time 82430715 ps
CPU time 1.68 seconds
Started Jul 07 04:17:18 PM PDT 24
Finished Jul 07 04:17:20 PM PDT 24
Peak memory 201104 kb
Host smart-f3f0de66-78b7-4d6e-882f-4f2f0af585d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627090585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.627090585
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3635458660
Short name T105
Test name
Test status
Simulation time 318071918 ps
CPU time 1.11 seconds
Started Jul 07 04:21:22 PM PDT 24
Finished Jul 07 04:21:24 PM PDT 24
Peak memory 199524 kb
Host smart-111f50be-b565-45af-8faf-b685452323d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635458660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3635458660
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.969590188
Short name T1218
Test name
Test status
Simulation time 49015448 ps
CPU time 0.66 seconds
Started Jul 07 04:21:57 PM PDT 24
Finished Jul 07 04:21:58 PM PDT 24
Peak memory 196936 kb
Host smart-f027ce30-ff7a-4ea3-a0c2-e4f61132aab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969590188 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.969590188
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1747807339
Short name T1252
Test name
Test status
Simulation time 17427854 ps
CPU time 0.67 seconds
Started Jul 07 04:19:28 PM PDT 24
Finished Jul 07 04:19:29 PM PDT 24
Peak memory 196340 kb
Host smart-4af95c79-e364-45b4-a8c5-9c0e465dcd29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747807339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1747807339
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1267046432
Short name T1203
Test name
Test status
Simulation time 35146765 ps
CPU time 0.6 seconds
Started Jul 07 04:17:27 PM PDT 24
Finished Jul 07 04:17:28 PM PDT 24
Peak memory 195448 kb
Host smart-8277dc42-7189-4d39-b4a0-149409a168d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267046432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1267046432
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.763898172
Short name T88
Test name
Test status
Simulation time 130707480 ps
CPU time 0.69 seconds
Started Jul 07 04:21:58 PM PDT 24
Finished Jul 07 04:21:59 PM PDT 24
Peak memory 197376 kb
Host smart-796aba51-97ad-457a-8a1a-f4f56b29eb5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763898172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.763898172
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1190086909
Short name T1299
Test name
Test status
Simulation time 115645129 ps
CPU time 1.27 seconds
Started Jul 07 04:18:42 PM PDT 24
Finished Jul 07 04:18:43 PM PDT 24
Peak memory 201044 kb
Host smart-121cb131-bae3-481f-8ab0-55c0665731c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190086909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1190086909
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.548781271
Short name T1310
Test name
Test status
Simulation time 134297172 ps
CPU time 0.96 seconds
Started Jul 07 04:19:45 PM PDT 24
Finished Jul 07 04:19:46 PM PDT 24
Peak memory 199656 kb
Host smart-687cea0c-504a-4953-b7c6-bf20074bd390
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548781271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.548781271
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2252718028
Short name T1313
Test name
Test status
Simulation time 32822767 ps
CPU time 0.93 seconds
Started Jul 07 04:18:33 PM PDT 24
Finished Jul 07 04:18:35 PM PDT 24
Peak memory 200556 kb
Host smart-b237ed26-8e3f-4f4f-a76e-bf6d51fb78d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252718028 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2252718028
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1469697697
Short name T1196
Test name
Test status
Simulation time 13945335 ps
CPU time 0.56 seconds
Started Jul 07 04:17:17 PM PDT 24
Finished Jul 07 04:17:18 PM PDT 24
Peak memory 196028 kb
Host smart-e4982a48-7943-46a9-86de-471d5bad4495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469697697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1469697697
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.491189197
Short name T1270
Test name
Test status
Simulation time 27399677 ps
CPU time 0.56 seconds
Started Jul 07 04:21:25 PM PDT 24
Finished Jul 07 04:21:27 PM PDT 24
Peak memory 193244 kb
Host smart-3e476e05-357b-408e-bd0a-fbd41e2971be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491189197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.491189197
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2777626512
Short name T1225
Test name
Test status
Simulation time 55680016 ps
CPU time 0.81 seconds
Started Jul 07 04:21:22 PM PDT 24
Finished Jul 07 04:21:24 PM PDT 24
Peak memory 196256 kb
Host smart-ce155c8e-2190-4046-adfb-8d194e753c1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777626512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2777626512
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2027743979
Short name T1183
Test name
Test status
Simulation time 223180813 ps
CPU time 1.2 seconds
Started Jul 07 04:19:49 PM PDT 24
Finished Jul 07 04:19:50 PM PDT 24
Peak memory 200664 kb
Host smart-22401fb5-7f93-4ea1-980b-a9cc9192375e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027743979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2027743979
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1662022153
Short name T1258
Test name
Test status
Simulation time 66107946 ps
CPU time 0.97 seconds
Started Jul 07 04:21:25 PM PDT 24
Finished Jul 07 04:21:27 PM PDT 24
Peak memory 197844 kb
Host smart-c79427ee-aa29-4fba-8b46-c59eac39ebf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662022153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1662022153
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1921524004
Short name T1207
Test name
Test status
Simulation time 63661153 ps
CPU time 0.85 seconds
Started Jul 07 04:20:48 PM PDT 24
Finished Jul 07 04:20:49 PM PDT 24
Peak memory 200832 kb
Host smart-e86e6578-9ccb-48e6-9222-6ddbf479fe3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921524004 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1921524004
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.92992644
Short name T1190
Test name
Test status
Simulation time 23498079 ps
CPU time 0.61 seconds
Started Jul 07 04:22:35 PM PDT 24
Finished Jul 07 04:22:36 PM PDT 24
Peak memory 195936 kb
Host smart-1c0978b4-d593-4058-9af7-557fe3d5458c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92992644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.92992644
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2079997073
Short name T1210
Test name
Test status
Simulation time 50686950 ps
CPU time 0.6 seconds
Started Jul 07 04:21:52 PM PDT 24
Finished Jul 07 04:21:54 PM PDT 24
Peak memory 194096 kb
Host smart-5a703fc8-7376-4c10-89df-d7c0f4ab5515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079997073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2079997073
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3618164271
Short name T87
Test name
Test status
Simulation time 41243221 ps
CPU time 0.67 seconds
Started Jul 07 04:19:09 PM PDT 24
Finished Jul 07 04:19:10 PM PDT 24
Peak memory 196552 kb
Host smart-7034ece5-ce3d-459c-a922-3d7cfc72d9d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618164271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3618164271
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2255800843
Short name T1209
Test name
Test status
Simulation time 24063578 ps
CPU time 1.14 seconds
Started Jul 07 04:21:23 PM PDT 24
Finished Jul 07 04:21:24 PM PDT 24
Peak memory 200332 kb
Host smart-64dafd20-3380-459a-9443-5155d4cc5361
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255800843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2255800843
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.637691419
Short name T1198
Test name
Test status
Simulation time 83585480 ps
CPU time 0.75 seconds
Started Jul 07 04:21:24 PM PDT 24
Finished Jul 07 04:21:25 PM PDT 24
Peak memory 197604 kb
Host smart-addff0b2-3e4c-4629-a684-9770de316094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637691419 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.637691419
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3644514958
Short name T81
Test name
Test status
Simulation time 25915419 ps
CPU time 0.58 seconds
Started Jul 07 04:22:01 PM PDT 24
Finished Jul 07 04:22:02 PM PDT 24
Peak memory 195460 kb
Host smart-9a2b18b5-cf13-4004-b235-3d4c2f9091bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644514958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3644514958
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.851098118
Short name T1271
Test name
Test status
Simulation time 33322347 ps
CPU time 0.57 seconds
Started Jul 07 04:22:19 PM PDT 24
Finished Jul 07 04:22:19 PM PDT 24
Peak memory 194956 kb
Host smart-3abb7449-2c27-4615-ac1d-f4f53d39c8f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851098118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.851098118
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3663843670
Short name T89
Test name
Test status
Simulation time 30813396 ps
CPU time 0.69 seconds
Started Jul 07 04:17:26 PM PDT 24
Finished Jul 07 04:17:27 PM PDT 24
Peak memory 196460 kb
Host smart-ec31bfa9-ab35-4b26-8d1c-5b8128cce3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663843670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3663843670
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2967139024
Short name T1248
Test name
Test status
Simulation time 239242511 ps
CPU time 2.51 seconds
Started Jul 07 04:22:01 PM PDT 24
Finished Jul 07 04:22:04 PM PDT 24
Peak memory 199704 kb
Host smart-3a1a0a33-00a7-4118-b393-f3405a1b8d02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967139024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2967139024
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2576405770
Short name T139
Test name
Test status
Simulation time 83018460 ps
CPU time 1.19 seconds
Started Jul 07 04:22:23 PM PDT 24
Finished Jul 07 04:22:24 PM PDT 24
Peak memory 199700 kb
Host smart-3296e1aa-4f7c-4866-b662-a9329aa766c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576405770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2576405770
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2061979441
Short name T54
Test name
Test status
Simulation time 15609876 ps
CPU time 0.6 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:12:40 PM PDT 24
Peak memory 195572 kb
Host smart-fbb13b4e-ef44-461a-86e6-9dfc6e0d6716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061979441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2061979441
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3775213540
Short name T989
Test name
Test status
Simulation time 131329368575 ps
CPU time 55.93 seconds
Started Jul 07 05:12:33 PM PDT 24
Finished Jul 07 05:13:30 PM PDT 24
Peak memory 199956 kb
Host smart-0f7697de-3b39-45b4-88d3-eedea7392f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775213540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3775213540
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3046374141
Short name T770
Test name
Test status
Simulation time 17573069873 ps
CPU time 14.95 seconds
Started Jul 07 05:12:34 PM PDT 24
Finished Jul 07 05:12:49 PM PDT 24
Peak memory 199984 kb
Host smart-6e81ef11-a4ae-416b-a8e1-7e41f5e44361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046374141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3046374141
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.311166840
Short name T992
Test name
Test status
Simulation time 29790574649 ps
CPU time 65.69 seconds
Started Jul 07 05:12:35 PM PDT 24
Finished Jul 07 05:13:41 PM PDT 24
Peak memory 198788 kb
Host smart-cc158ab4-52d7-4157-843a-c875cbaeb2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311166840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.311166840
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2735328027
Short name T764
Test name
Test status
Simulation time 20684864385 ps
CPU time 18.93 seconds
Started Jul 07 05:12:34 PM PDT 24
Finished Jul 07 05:12:54 PM PDT 24
Peak memory 199500 kb
Host smart-b874bd38-e750-4f50-a8a3-c452da1b94da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735328027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2735328027
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.62675009
Short name T796
Test name
Test status
Simulation time 70221890624 ps
CPU time 282.02 seconds
Started Jul 07 05:12:41 PM PDT 24
Finished Jul 07 05:17:24 PM PDT 24
Peak memory 199880 kb
Host smart-5cefa778-3ff3-421c-96f1-36a0282f5a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62675009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.62675009
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4172359665
Short name T426
Test name
Test status
Simulation time 6715943812 ps
CPU time 14.34 seconds
Started Jul 07 05:12:34 PM PDT 24
Finished Jul 07 05:12:49 PM PDT 24
Peak memory 200008 kb
Host smart-335c5fe2-f20d-40ab-8a44-a660f9a864c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172359665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4172359665
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1540062917
Short name T834
Test name
Test status
Simulation time 47561966835 ps
CPU time 75.83 seconds
Started Jul 07 05:12:33 PM PDT 24
Finished Jul 07 05:13:49 PM PDT 24
Peak memory 199364 kb
Host smart-c4295cc8-404c-4406-880f-1442ef55e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540062917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1540062917
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.864349089
Short name T1165
Test name
Test status
Simulation time 11294962610 ps
CPU time 585.6 seconds
Started Jul 07 05:12:32 PM PDT 24
Finished Jul 07 05:22:18 PM PDT 24
Peak memory 200272 kb
Host smart-3babf5fd-68f6-44ef-978d-259cc613edfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864349089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.864349089
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3947996469
Short name T415
Test name
Test status
Simulation time 4957431988 ps
CPU time 11.65 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:12:48 PM PDT 24
Peak memory 198200 kb
Host smart-c4610db4-81de-442f-8cc8-93c4cb570fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947996469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3947996469
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.4081894332
Short name T1070
Test name
Test status
Simulation time 20077949080 ps
CPU time 17.39 seconds
Started Jul 07 05:12:35 PM PDT 24
Finished Jul 07 05:12:53 PM PDT 24
Peak memory 198796 kb
Host smart-d405cef4-1317-4fab-b22a-bce963ec1a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081894332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.4081894332
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2747239221
Short name T1137
Test name
Test status
Simulation time 810767953 ps
CPU time 2.1 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:12:38 PM PDT 24
Peak memory 195700 kb
Host smart-4056bee7-6944-4389-a9ae-29e6888596cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747239221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2747239221
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.2352216751
Short name T339
Test name
Test status
Simulation time 5968646386 ps
CPU time 17.26 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:12:57 PM PDT 24
Peak memory 199424 kb
Host smart-ac76cd16-a1ed-4bfd-9267-c0c3ee64386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352216751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2352216751
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2067946146
Short name T895
Test name
Test status
Simulation time 146283308189 ps
CPU time 1676.89 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 231420 kb
Host smart-f7ed2a84-1472-4552-a6d1-b4209aac298c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067946146 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2067946146
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3980978945
Short name T1000
Test name
Test status
Simulation time 1312332208 ps
CPU time 3.03 seconds
Started Jul 07 05:12:35 PM PDT 24
Finished Jul 07 05:12:38 PM PDT 24
Peak memory 198328 kb
Host smart-994a0bff-c9b8-4d7e-943f-5d19e86fe3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980978945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3980978945
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1847187259
Short name T1151
Test name
Test status
Simulation time 4301835291 ps
CPU time 6.53 seconds
Started Jul 07 05:12:37 PM PDT 24
Finished Jul 07 05:12:44 PM PDT 24
Peak memory 196968 kb
Host smart-5fe4d9ab-60ab-4a3a-9f44-4e2791fc445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847187259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1847187259
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1723513482
Short name T912
Test name
Test status
Simulation time 39286478 ps
CPU time 0.58 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:12:37 PM PDT 24
Peak memory 195288 kb
Host smart-a1ed69eb-92d7-495a-b654-a3daa786ceaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723513482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1723513482
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3504307739
Short name T596
Test name
Test status
Simulation time 39285458200 ps
CPU time 66.54 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:13:43 PM PDT 24
Peak memory 199988 kb
Host smart-4dcb3f6e-de40-4655-af41-da7564f410bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504307739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3504307739
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3933475041
Short name T831
Test name
Test status
Simulation time 23037237923 ps
CPU time 44.02 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:13:24 PM PDT 24
Peak memory 199972 kb
Host smart-fa9dcc08-999d-4743-999c-d5b4a82bc7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933475041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3933475041
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.3544893890
Short name T649
Test name
Test status
Simulation time 31276569832 ps
CPU time 30.31 seconds
Started Jul 07 05:12:38 PM PDT 24
Finished Jul 07 05:13:09 PM PDT 24
Peak memory 199848 kb
Host smart-cecec20a-f823-4caa-9035-5b48b48ab5a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544893890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3544893890
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1576854665
Short name T1160
Test name
Test status
Simulation time 103064919879 ps
CPU time 91.68 seconds
Started Jul 07 05:12:38 PM PDT 24
Finished Jul 07 05:14:10 PM PDT 24
Peak memory 199920 kb
Host smart-97d14888-f222-44a9-8dae-e46bb91c31ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576854665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1576854665
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.890615258
Short name T1079
Test name
Test status
Simulation time 7193968324 ps
CPU time 18.35 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:12:58 PM PDT 24
Peak memory 197340 kb
Host smart-78a52a2b-3a4a-4115-905e-54bc0fe08a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890615258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.890615258
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2097096520
Short name T306
Test name
Test status
Simulation time 76585983423 ps
CPU time 58.84 seconds
Started Jul 07 05:12:37 PM PDT 24
Finished Jul 07 05:13:36 PM PDT 24
Peak memory 199800 kb
Host smart-0877fc90-438d-409b-a5d0-01b7a2cc36a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097096520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2097096520
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2371377005
Short name T700
Test name
Test status
Simulation time 15301355514 ps
CPU time 178.14 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:15:35 PM PDT 24
Peak memory 199868 kb
Host smart-46f854f9-9b4d-4542-8b76-8f79717b614d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371377005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2371377005
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2419091643
Short name T842
Test name
Test status
Simulation time 4177628559 ps
CPU time 12.14 seconds
Started Jul 07 05:12:37 PM PDT 24
Finished Jul 07 05:12:50 PM PDT 24
Peak memory 197960 kb
Host smart-b09da6db-5641-44ed-aeaf-ba1d627fcddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419091643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2419091643
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2836818941
Short name T655
Test name
Test status
Simulation time 65353060309 ps
CPU time 51.01 seconds
Started Jul 07 05:12:38 PM PDT 24
Finished Jul 07 05:13:29 PM PDT 24
Peak memory 200216 kb
Host smart-7f8b9e9c-c9e9-4a7e-b1b4-105a0f1e0072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836818941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2836818941
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4243959844
Short name T398
Test name
Test status
Simulation time 3245865351 ps
CPU time 5.13 seconds
Started Jul 07 05:12:41 PM PDT 24
Finished Jul 07 05:12:47 PM PDT 24
Peak memory 195976 kb
Host smart-a9610799-482a-4ce5-a8f1-14bf2b919334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243959844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4243959844
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3221195633
Short name T31
Test name
Test status
Simulation time 245227937 ps
CPU time 0.86 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:12:40 PM PDT 24
Peak memory 218244 kb
Host smart-50ca33d5-332d-4b27-aa78-7c2f259e4a3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221195633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3221195633
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2346412317
Short name T291
Test name
Test status
Simulation time 6071903597 ps
CPU time 19.68 seconds
Started Jul 07 05:12:37 PM PDT 24
Finished Jul 07 05:12:57 PM PDT 24
Peak memory 199808 kb
Host smart-be50ebbe-5397-4c41-866b-660b4204aa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346412317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2346412317
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2531819451
Short name T592
Test name
Test status
Simulation time 104268182777 ps
CPU time 688.37 seconds
Started Jul 07 05:12:37 PM PDT 24
Finished Jul 07 05:24:06 PM PDT 24
Peak memory 199960 kb
Host smart-3e6e9c31-2a95-4a78-9918-33be9e6b7cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531819451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2531819451
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.111055240
Short name T939
Test name
Test status
Simulation time 873841719 ps
CPU time 2.45 seconds
Started Jul 07 05:12:37 PM PDT 24
Finished Jul 07 05:12:40 PM PDT 24
Peak memory 199804 kb
Host smart-715a1d5d-1d09-46c4-b2ad-ac31f60b66a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111055240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.111055240
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.303470856
Short name T383
Test name
Test status
Simulation time 21119798900 ps
CPU time 10.05 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:12:50 PM PDT 24
Peak memory 199904 kb
Host smart-708275be-c2b3-4358-a300-e0b5796eb045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303470856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.303470856
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3011756217
Short name T325
Test name
Test status
Simulation time 32271486 ps
CPU time 0.54 seconds
Started Jul 07 05:13:08 PM PDT 24
Finished Jul 07 05:13:09 PM PDT 24
Peak memory 195200 kb
Host smart-4544ba2a-7d5f-45b1-b396-ab42f263699b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011756217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3011756217
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2799201052
Short name T164
Test name
Test status
Simulation time 114892789272 ps
CPU time 101.58 seconds
Started Jul 07 05:13:00 PM PDT 24
Finished Jul 07 05:14:42 PM PDT 24
Peak memory 199976 kb
Host smart-1e3db383-8a38-4106-a0cd-f7a52eea388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799201052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2799201052
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2523870783
Short name T1019
Test name
Test status
Simulation time 122176433750 ps
CPU time 167.43 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:15:46 PM PDT 24
Peak memory 199756 kb
Host smart-2b9dbd54-1315-497e-8c0a-5e65ddfbe1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523870783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2523870783
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.234135056
Short name T1140
Test name
Test status
Simulation time 144856292894 ps
CPU time 52.93 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:13:57 PM PDT 24
Peak memory 199824 kb
Host smart-d86e3a2b-b823-4ed6-921f-c646dade3f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234135056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.234135056
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.253094274
Short name T794
Test name
Test status
Simulation time 35646070127 ps
CPU time 14.07 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:13:14 PM PDT 24
Peak memory 198992 kb
Host smart-c318cfcf-f855-4fbc-accc-0588936f475f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253094274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.253094274
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.601538904
Short name T480
Test name
Test status
Simulation time 130824389465 ps
CPU time 940.09 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:28:47 PM PDT 24
Peak memory 199912 kb
Host smart-740ac581-45ad-42ee-aecd-b507fa081441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601538904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.601538904
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2342218086
Short name T1021
Test name
Test status
Simulation time 4136852587 ps
CPU time 2.19 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:13:03 PM PDT 24
Peak memory 199716 kb
Host smart-77473978-57fa-4895-bf57-4811e5c98c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342218086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2342218086
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3770126490
Short name T1108
Test name
Test status
Simulation time 47547692178 ps
CPU time 12.85 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:13:13 PM PDT 24
Peak memory 200140 kb
Host smart-b1d10cb5-050e-40b5-a003-9e2baec1fa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770126490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3770126490
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.974283805
Short name T446
Test name
Test status
Simulation time 9507067219 ps
CPU time 400.86 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:19:46 PM PDT 24
Peak memory 199880 kb
Host smart-817f2892-8f63-43a3-910b-d2a0f7ac8f3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974283805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.974283805
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2677172134
Short name T871
Test name
Test status
Simulation time 4117799242 ps
CPU time 10.01 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:17 PM PDT 24
Peak memory 197744 kb
Host smart-fd7d85f8-d671-455f-8d93-e3ffa70473fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677172134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2677172134
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3192850755
Short name T1089
Test name
Test status
Simulation time 71238634455 ps
CPU time 24.9 seconds
Started Jul 07 05:13:04 PM PDT 24
Finished Jul 07 05:13:29 PM PDT 24
Peak memory 199888 kb
Host smart-136349c2-058b-47f5-86d5-b920c4719dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192850755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3192850755
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3450315073
Short name T709
Test name
Test status
Simulation time 854716268 ps
CPU time 0.97 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:07 PM PDT 24
Peak memory 195332 kb
Host smart-e73823d4-5201-404a-9c1d-74a4ede4aafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450315073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3450315073
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4075617998
Short name T998
Test name
Test status
Simulation time 484765101 ps
CPU time 1.17 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:13:00 PM PDT 24
Peak memory 199432 kb
Host smart-996ddbc0-d6c3-4ac0-bfce-28e7ac7770af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075617998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4075617998
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1578655155
Short name T940
Test name
Test status
Simulation time 1035268489 ps
CPU time 3.38 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:13:03 PM PDT 24
Peak memory 199908 kb
Host smart-92be5ce7-12c0-47db-8107-a2a8d63e8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578655155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1578655155
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3390117079
Short name T320
Test name
Test status
Simulation time 275036142979 ps
CPU time 85.05 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:14:23 PM PDT 24
Peak memory 200256 kb
Host smart-1b539582-9ed3-4bc7-a6bb-a23bced41410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390117079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3390117079
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1481085771
Short name T184
Test name
Test status
Simulation time 181250800577 ps
CPU time 59.79 seconds
Started Jul 07 05:16:54 PM PDT 24
Finished Jul 07 05:17:54 PM PDT 24
Peak memory 199900 kb
Host smart-31d312e6-4d8c-45d7-ab7a-6a2768e4e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481085771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1481085771
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.902457732
Short name T736
Test name
Test status
Simulation time 133928906506 ps
CPU time 229.14 seconds
Started Jul 07 05:16:52 PM PDT 24
Finished Jul 07 05:20:41 PM PDT 24
Peak memory 199920 kb
Host smart-c60c1c23-e54e-4e4e-8be6-2ccf4ffd9afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902457732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.902457732
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4030619758
Short name T253
Test name
Test status
Simulation time 128323581474 ps
CPU time 47.9 seconds
Started Jul 07 05:16:53 PM PDT 24
Finished Jul 07 05:17:41 PM PDT 24
Peak memory 199932 kb
Host smart-7a498d29-4d57-4ee4-95e1-a85346ebb53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030619758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4030619758
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3857365743
Short name T994
Test name
Test status
Simulation time 29709121068 ps
CPU time 54.36 seconds
Started Jul 07 05:16:51 PM PDT 24
Finished Jul 07 05:17:46 PM PDT 24
Peak memory 199984 kb
Host smart-5c43ec8c-9344-49a4-906e-09d8e431da0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857365743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3857365743
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.218313264
Short name T599
Test name
Test status
Simulation time 81721894360 ps
CPU time 64.23 seconds
Started Jul 07 05:16:57 PM PDT 24
Finished Jul 07 05:18:02 PM PDT 24
Peak memory 199944 kb
Host smart-d0c80c75-ae8e-49b1-a8aa-8edf3a6e2fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218313264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.218313264
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.535632648
Short name T301
Test name
Test status
Simulation time 103191275917 ps
CPU time 33.4 seconds
Started Jul 07 05:16:55 PM PDT 24
Finished Jul 07 05:17:29 PM PDT 24
Peak memory 199900 kb
Host smart-981b8dc1-f92a-4e7b-8e75-8ba6ec830936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535632648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.535632648
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2293748078
Short name T127
Test name
Test status
Simulation time 8050455068 ps
CPU time 12.35 seconds
Started Jul 07 05:16:55 PM PDT 24
Finished Jul 07 05:17:07 PM PDT 24
Peak memory 199952 kb
Host smart-a83daa70-892c-4663-8335-93f61e3eefca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293748078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2293748078
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3069331394
Short name T622
Test name
Test status
Simulation time 32846834021 ps
CPU time 17.08 seconds
Started Jul 07 05:16:55 PM PDT 24
Finished Jul 07 05:17:13 PM PDT 24
Peak memory 199920 kb
Host smart-5683ed2e-8524-4172-8e60-2af1b42c733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069331394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3069331394
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3544547738
Short name T620
Test name
Test status
Simulation time 9173854114 ps
CPU time 13.93 seconds
Started Jul 07 05:16:57 PM PDT 24
Finished Jul 07 05:17:11 PM PDT 24
Peak memory 199460 kb
Host smart-33270c1c-779b-4122-af04-25492f55d7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544547738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3544547738
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1876312198
Short name T336
Test name
Test status
Simulation time 30732100572 ps
CPU time 10.31 seconds
Started Jul 07 05:16:57 PM PDT 24
Finished Jul 07 05:17:08 PM PDT 24
Peak memory 198336 kb
Host smart-7ec5d394-8916-44f4-b0c4-5db84f10713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876312198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1876312198
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3599279031
Short name T787
Test name
Test status
Simulation time 39150329 ps
CPU time 0.54 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:12:58 PM PDT 24
Peak memory 195216 kb
Host smart-f31ee0f2-000e-40ce-87c6-ecacfed0e397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599279031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3599279031
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2601635257
Short name T456
Test name
Test status
Simulation time 66880166096 ps
CPU time 29.82 seconds
Started Jul 07 05:13:04 PM PDT 24
Finished Jul 07 05:13:34 PM PDT 24
Peak memory 199932 kb
Host smart-39ebf0bd-ddc1-493d-bd50-bf869dec7b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601635257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2601635257
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.468140668
Short name T847
Test name
Test status
Simulation time 49389192446 ps
CPU time 33.97 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:41 PM PDT 24
Peak memory 199784 kb
Host smart-6ea7c9bb-0b8d-4afd-ae17-4ed37bbc3aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468140668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.468140668
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2746654535
Short name T1025
Test name
Test status
Simulation time 40952960017 ps
CPU time 15.69 seconds
Started Jul 07 05:13:00 PM PDT 24
Finished Jul 07 05:13:17 PM PDT 24
Peak memory 199888 kb
Host smart-17991bbe-76d9-4ad1-ac2b-fb00bd023d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746654535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2746654535
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1301984242
Short name T1086
Test name
Test status
Simulation time 27428672329 ps
CPU time 24.12 seconds
Started Jul 07 05:13:08 PM PDT 24
Finished Jul 07 05:13:33 PM PDT 24
Peak memory 198292 kb
Host smart-483fe45c-61e5-49b9-a616-3eb1035e92f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301984242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1301984242
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3933798278
Short name T408
Test name
Test status
Simulation time 142674369067 ps
CPU time 400.88 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:19:41 PM PDT 24
Peak memory 199948 kb
Host smart-e58699be-17c8-4e84-aa61-6273a0e6f624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933798278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3933798278
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.460608657
Short name T312
Test name
Test status
Simulation time 6269914015 ps
CPU time 13 seconds
Started Jul 07 05:13:00 PM PDT 24
Finished Jul 07 05:13:14 PM PDT 24
Peak memory 199416 kb
Host smart-5d2834dd-a4e4-46ad-88b9-de8cf6cf1d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460608657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.460608657
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.181229268
Short name T337
Test name
Test status
Simulation time 17834846009 ps
CPU time 21.46 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:28 PM PDT 24
Peak memory 197736 kb
Host smart-a725ba3b-b4be-41f8-979b-3d097d26bdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181229268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.181229268
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.227994931
Short name T567
Test name
Test status
Simulation time 15546134347 ps
CPU time 371.02 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:19:18 PM PDT 24
Peak memory 199888 kb
Host smart-8b600b54-1793-4695-9754-daab8f3c6e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227994931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.227994931
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2214458429
Short name T484
Test name
Test status
Simulation time 3305457188 ps
CPU time 6.83 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:13:05 PM PDT 24
Peak memory 199140 kb
Host smart-55c95681-4227-46e5-8ab4-ded72b8918d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214458429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2214458429
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2859670581
Short name T548
Test name
Test status
Simulation time 68143932265 ps
CPU time 134.85 seconds
Started Jul 07 05:13:04 PM PDT 24
Finished Jul 07 05:15:19 PM PDT 24
Peak memory 199920 kb
Host smart-e3a4bc20-3894-4c39-b922-5f7c633ad0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859670581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2859670581
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3822471594
Short name T996
Test name
Test status
Simulation time 2161152914 ps
CPU time 3.6 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:10 PM PDT 24
Peak memory 195380 kb
Host smart-b984b3d2-148b-4c6f-9821-6de1d6ab5d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822471594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3822471594
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3400585360
Short name T359
Test name
Test status
Simulation time 5374292074 ps
CPU time 7.16 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:14 PM PDT 24
Peak memory 199868 kb
Host smart-b253e93f-f8a0-4a9d-a7f7-aaa653fea4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400585360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3400585360
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.4135759474
Short name T935
Test name
Test status
Simulation time 149382863852 ps
CPU time 97.28 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:14:43 PM PDT 24
Peak memory 199928 kb
Host smart-d3c89881-aa63-4348-9cbe-6692c720f756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135759474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.4135759474
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3512885566
Short name T75
Test name
Test status
Simulation time 20052784463 ps
CPU time 214.83 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:16:34 PM PDT 24
Peak memory 216464 kb
Host smart-3f2c803a-0d98-4908-9336-0a69a3f55e89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512885566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3512885566
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.4097018556
Short name T341
Test name
Test status
Simulation time 1209853664 ps
CPU time 2 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:13:08 PM PDT 24
Peak memory 199260 kb
Host smart-5c105d2d-1684-447e-bff3-776944b1ca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097018556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4097018556
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4183236697
Short name T772
Test name
Test status
Simulation time 13803765668 ps
CPU time 23.66 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:13:23 PM PDT 24
Peak memory 199912 kb
Host smart-f92e7c3c-77a2-4e22-b032-d8b8a3f5a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183236697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4183236697
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.970896821
Short name T165
Test name
Test status
Simulation time 11620831535 ps
CPU time 21.45 seconds
Started Jul 07 05:16:57 PM PDT 24
Finished Jul 07 05:17:18 PM PDT 24
Peak memory 199972 kb
Host smart-1acc09b4-9e3e-4fcd-af53-a60af1711dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970896821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.970896821
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1496898740
Short name T792
Test name
Test status
Simulation time 145411760854 ps
CPU time 245.13 seconds
Started Jul 07 05:16:57 PM PDT 24
Finished Jul 07 05:21:03 PM PDT 24
Peak memory 199940 kb
Host smart-ac189558-cb7f-4880-a309-42f2a1bd6db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496898740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1496898740
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3327345289
Short name T34
Test name
Test status
Simulation time 35941788164 ps
CPU time 15.28 seconds
Started Jul 07 05:16:57 PM PDT 24
Finished Jul 07 05:17:13 PM PDT 24
Peak memory 199884 kb
Host smart-034deae2-1007-4147-b211-72ad89c89c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327345289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3327345289
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.625721363
Short name T6
Test name
Test status
Simulation time 14655642561 ps
CPU time 10.56 seconds
Started Jul 07 05:17:04 PM PDT 24
Finished Jul 07 05:17:15 PM PDT 24
Peak memory 200016 kb
Host smart-d362da14-2a93-4189-b9a8-e7648d7825d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625721363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.625721363
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2593345801
Short name T115
Test name
Test status
Simulation time 6908129267 ps
CPU time 13.22 seconds
Started Jul 07 05:17:00 PM PDT 24
Finished Jul 07 05:17:13 PM PDT 24
Peak memory 199792 kb
Host smart-c491764a-b97c-450a-b750-587d3a5d8cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593345801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2593345801
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2111720122
Short name T1126
Test name
Test status
Simulation time 120936631788 ps
CPU time 181 seconds
Started Jul 07 05:17:05 PM PDT 24
Finished Jul 07 05:20:07 PM PDT 24
Peak memory 199912 kb
Host smart-9f506b8c-1962-4f51-8753-2fba89c83251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111720122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2111720122
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2481105029
Short name T569
Test name
Test status
Simulation time 113956118753 ps
CPU time 59.9 seconds
Started Jul 07 05:17:02 PM PDT 24
Finished Jul 07 05:18:02 PM PDT 24
Peak memory 199852 kb
Host smart-ed8705d1-ffc4-434d-91b7-7a8ce71844bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481105029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2481105029
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1024504135
Short name T757
Test name
Test status
Simulation time 30656998670 ps
CPU time 31.55 seconds
Started Jul 07 05:17:05 PM PDT 24
Finished Jul 07 05:17:37 PM PDT 24
Peak memory 199944 kb
Host smart-05afabca-36aa-4af9-a0a3-794ef1efc25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024504135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1024504135
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3604512040
Short name T856
Test name
Test status
Simulation time 20570547 ps
CPU time 0.56 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:07 PM PDT 24
Peak memory 195556 kb
Host smart-a0113280-a9da-4caa-8f35-d0aa029788ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604512040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3604512040
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.483280449
Short name T46
Test name
Test status
Simulation time 71269441990 ps
CPU time 35.65 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:13:38 PM PDT 24
Peak memory 199980 kb
Host smart-32ea1854-efdc-459c-86c8-3ce214c4a4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483280449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.483280449
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2703097296
Short name T331
Test name
Test status
Simulation time 114849870359 ps
CPU time 127.76 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:15:12 PM PDT 24
Peak memory 199876 kb
Host smart-a72c3e1a-5d08-4090-ad39-67807bf98d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703097296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2703097296
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1662517129
Short name T167
Test name
Test status
Simulation time 59231058680 ps
CPU time 82.39 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:14:28 PM PDT 24
Peak memory 199956 kb
Host smart-9682dfc6-627e-4516-8f28-a7325d7eebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662517129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1662517129
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1700733301
Short name T96
Test name
Test status
Simulation time 39230949230 ps
CPU time 14.15 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:13:18 PM PDT 24
Peak memory 199712 kb
Host smart-c3b8f232-164c-4c2d-afec-d65c16cc5c29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700733301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1700733301
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1269974194
Short name T1167
Test name
Test status
Simulation time 56711973230 ps
CPU time 314.75 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:18:17 PM PDT 24
Peak memory 199924 kb
Host smart-a253e042-626a-437a-b353-229c92bf7f73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269974194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1269974194
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.755076802
Short name T1123
Test name
Test status
Simulation time 6394864909 ps
CPU time 11.21 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:13:15 PM PDT 24
Peak memory 197456 kb
Host smart-3c537678-bcab-494b-9d7d-cb750c1078e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755076802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.755076802
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.461562898
Short name T1117
Test name
Test status
Simulation time 53438310964 ps
CPU time 93.98 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:14:38 PM PDT 24
Peak memory 199960 kb
Host smart-d763cb27-64e1-4259-addb-7a8ad85da77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461562898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.461562898
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1976405709
Short name T972
Test name
Test status
Simulation time 4623609622 ps
CPU time 177.36 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:15:59 PM PDT 24
Peak memory 199908 kb
Host smart-1b2bce17-1dcb-4abe-a679-942987d6b9cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976405709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1976405709
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2982249565
Short name T10
Test name
Test status
Simulation time 6717696154 ps
CPU time 67.27 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:14:12 PM PDT 24
Peak memory 199484 kb
Host smart-b6709479-79e5-4e7c-9bb0-4ec85c7493cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982249565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2982249565
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.722223424
Short name T284
Test name
Test status
Simulation time 16443363658 ps
CPU time 31.57 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:13:34 PM PDT 24
Peak memory 199844 kb
Host smart-151f8ce6-4c46-489e-9428-67805c9587ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722223424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.722223424
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3320525329
Short name T824
Test name
Test status
Simulation time 3549376794 ps
CPU time 6.07 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:13:08 PM PDT 24
Peak memory 196212 kb
Host smart-3a5849f1-5cc0-4300-807d-80e7ef0c3ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320525329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3320525329
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3803143911
Short name T974
Test name
Test status
Simulation time 680911694 ps
CPU time 2.13 seconds
Started Jul 07 05:13:04 PM PDT 24
Finished Jul 07 05:13:07 PM PDT 24
Peak memory 199908 kb
Host smart-90c9c6e4-8c9b-4bec-a6cd-4d2cb569cc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803143911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3803143911
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3089013077
Short name T204
Test name
Test status
Simulation time 526235334834 ps
CPU time 417.75 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:19:59 PM PDT 24
Peak memory 199856 kb
Host smart-76730c29-81c6-4db4-8ee6-78d6ede61a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089013077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3089013077
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.157597208
Short name T133
Test name
Test status
Simulation time 826618724293 ps
CPU time 745.67 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:25:29 PM PDT 24
Peak memory 224872 kb
Host smart-261d5c81-1707-4dac-bed2-a7f392f5285b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157597208 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.157597208
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3646115037
Short name T1
Test name
Test status
Simulation time 6577265798 ps
CPU time 18.67 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:25 PM PDT 24
Peak memory 199744 kb
Host smart-61c21bca-c7ff-4384-b5f0-efcc67c20633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646115037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3646115037
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1395985558
Short name T1090
Test name
Test status
Simulation time 70814119217 ps
CPU time 32.56 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:13:35 PM PDT 24
Peak memory 199924 kb
Host smart-c1ab3bca-f46c-43b2-80b0-38ca0ff80e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395985558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1395985558
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.502330099
Short name T58
Test name
Test status
Simulation time 7221719240 ps
CPU time 11.69 seconds
Started Jul 07 05:17:04 PM PDT 24
Finished Jul 07 05:17:16 PM PDT 24
Peak memory 199896 kb
Host smart-52e51fe5-c1e0-411a-a4c2-e2b9762287ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502330099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.502330099
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1529397742
Short name T447
Test name
Test status
Simulation time 49135628097 ps
CPU time 42.07 seconds
Started Jul 07 05:17:05 PM PDT 24
Finished Jul 07 05:17:47 PM PDT 24
Peak memory 199896 kb
Host smart-a170d57a-046d-460b-8131-c970941ab46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529397742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1529397742
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1042558982
Short name T482
Test name
Test status
Simulation time 39380536216 ps
CPU time 45.24 seconds
Started Jul 07 05:17:05 PM PDT 24
Finished Jul 07 05:17:51 PM PDT 24
Peak memory 199856 kb
Host smart-760dd785-dc1f-4ba7-a2e6-e54fd80ff20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042558982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1042558982
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1723903266
Short name T1056
Test name
Test status
Simulation time 36824130225 ps
CPU time 59.75 seconds
Started Jul 07 05:17:04 PM PDT 24
Finished Jul 07 05:18:04 PM PDT 24
Peak memory 199844 kb
Host smart-3267619b-fe99-4ddb-baea-a3554af59a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723903266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1723903266
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3768733288
Short name T1133
Test name
Test status
Simulation time 72482080395 ps
CPU time 98 seconds
Started Jul 07 05:17:05 PM PDT 24
Finished Jul 07 05:18:44 PM PDT 24
Peak memory 199920 kb
Host smart-f36aecb4-a16f-4620-81c3-b1100eb27316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768733288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3768733288
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.240007944
Short name T229
Test name
Test status
Simulation time 88714898417 ps
CPU time 41.72 seconds
Started Jul 07 05:17:08 PM PDT 24
Finished Jul 07 05:17:49 PM PDT 24
Peak memory 199912 kb
Host smart-f3544b3e-5e97-4144-957f-74d923dba471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240007944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.240007944
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.4233002118
Short name T539
Test name
Test status
Simulation time 141176229657 ps
CPU time 193.29 seconds
Started Jul 07 05:17:12 PM PDT 24
Finished Jul 07 05:20:26 PM PDT 24
Peak memory 199972 kb
Host smart-9f798a85-f4e8-40a1-a9f3-6592c1832b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233002118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.4233002118
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3702490520
Short name T225
Test name
Test status
Simulation time 11101293465 ps
CPU time 16.03 seconds
Started Jul 07 05:17:08 PM PDT 24
Finished Jul 07 05:17:24 PM PDT 24
Peak memory 199932 kb
Host smart-65f0efdc-60d3-4e7e-aad4-1437037890b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702490520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3702490520
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1034642521
Short name T73
Test name
Test status
Simulation time 29875031 ps
CPU time 0.53 seconds
Started Jul 07 05:13:04 PM PDT 24
Finished Jul 07 05:13:05 PM PDT 24
Peak memory 195220 kb
Host smart-8b7cf220-f4f5-4335-9dbd-241d6dfffaa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034642521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1034642521
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.269101284
Short name T1095
Test name
Test status
Simulation time 33855826220 ps
CPU time 32.75 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:13:38 PM PDT 24
Peak memory 199960 kb
Host smart-08beecd8-e784-48b3-a6c0-19feb479a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269101284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.269101284
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3831774650
Short name T372
Test name
Test status
Simulation time 121948640529 ps
CPU time 248.35 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:17:11 PM PDT 24
Peak memory 199844 kb
Host smart-41bf47c7-36ca-4789-9d46-8b500cf44c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831774650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3831774650
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.67732945
Short name T1109
Test name
Test status
Simulation time 10567962001 ps
CPU time 21.52 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:28 PM PDT 24
Peak memory 199832 kb
Host smart-4a099fe4-9095-4fdd-a417-049fa0a12a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67732945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.67732945
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.465117038
Short name T315
Test name
Test status
Simulation time 54003475105 ps
CPU time 19.02 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:13:22 PM PDT 24
Peak memory 199564 kb
Host smart-36d4e344-9cd4-439f-95df-85f7b79d7415
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465117038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.465117038
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1932238327
Short name T744
Test name
Test status
Simulation time 103243210640 ps
CPU time 1094.33 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:31:21 PM PDT 24
Peak memory 200156 kb
Host smart-92761636-ff0c-4cb6-a9b9-7e4b7ae094c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932238327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1932238327
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1414566832
Short name T405
Test name
Test status
Simulation time 9976950733 ps
CPU time 17.82 seconds
Started Jul 07 05:13:07 PM PDT 24
Finished Jul 07 05:13:25 PM PDT 24
Peak memory 198912 kb
Host smart-69ff1989-2f1b-40ff-a758-95b50f6d84c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414566832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1414566832
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1070746412
Short name T724
Test name
Test status
Simulation time 9905770051 ps
CPU time 16.8 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:13:22 PM PDT 24
Peak memory 197832 kb
Host smart-9de10394-f3d0-4a38-b0c5-d22f09442836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070746412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1070746412
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.360443291
Short name T1120
Test name
Test status
Simulation time 15652589628 ps
CPU time 892.14 seconds
Started Jul 07 05:13:09 PM PDT 24
Finished Jul 07 05:28:01 PM PDT 24
Peak memory 199956 kb
Host smart-f327a73e-255f-4658-a77c-b043394e5ebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360443291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.360443291
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1643918009
Short name T843
Test name
Test status
Simulation time 1932661577 ps
CPU time 3.69 seconds
Started Jul 07 05:13:06 PM PDT 24
Finished Jul 07 05:13:11 PM PDT 24
Peak memory 198168 kb
Host smart-5b538a2c-077c-4234-8345-a5572ba8b90d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643918009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1643918009
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2025162239
Short name T469
Test name
Test status
Simulation time 82939704709 ps
CPU time 135.45 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:15:19 PM PDT 24
Peak memory 199916 kb
Host smart-f95efb76-4b56-4852-9843-2040659eb8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025162239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2025162239
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2119324455
Short name T1092
Test name
Test status
Simulation time 40781111448 ps
CPU time 55.21 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:13:59 PM PDT 24
Peak memory 196752 kb
Host smart-12ceccd4-945e-4dbf-a5e2-e8678765e0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119324455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2119324455
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3707093839
Short name T926
Test name
Test status
Simulation time 463862506 ps
CPU time 2.26 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:13:05 PM PDT 24
Peak memory 198712 kb
Host smart-4e42f677-8458-4e6e-8e87-d79b978881f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707093839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3707093839
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.100373946
Short name T1107
Test name
Test status
Simulation time 568147520290 ps
CPU time 1683.47 seconds
Started Jul 07 05:13:10 PM PDT 24
Finished Jul 07 05:41:14 PM PDT 24
Peak memory 199948 kb
Host smart-1b73c361-7db7-437f-a4e3-93f27be4c49d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100373946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.100373946
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1040485521
Short name T1136
Test name
Test status
Simulation time 589683770535 ps
CPU time 1725.41 seconds
Started Jul 07 05:13:05 PM PDT 24
Finished Jul 07 05:41:51 PM PDT 24
Peak memory 230092 kb
Host smart-bcebdced-993f-4451-bcf2-4595534828f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040485521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1040485521
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.745707924
Short name T568
Test name
Test status
Simulation time 348756180 ps
CPU time 1.49 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:13:03 PM PDT 24
Peak memory 197780 kb
Host smart-4a2046e0-8644-46f4-80d6-1d22f8eadd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745707924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.745707924
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3415204164
Short name T505
Test name
Test status
Simulation time 3122104517 ps
CPU time 7.42 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:13:09 PM PDT 24
Peak memory 199924 kb
Host smart-33df28f7-3b84-4dd4-be3a-e60462db5e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415204164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3415204164
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1113578803
Short name T572
Test name
Test status
Simulation time 21565659543 ps
CPU time 17.8 seconds
Started Jul 07 05:17:08 PM PDT 24
Finished Jul 07 05:17:26 PM PDT 24
Peak memory 199880 kb
Host smart-c29c850e-f46e-4867-8090-748f667d1427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113578803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1113578803
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2209162142
Short name T454
Test name
Test status
Simulation time 133089776074 ps
CPU time 217 seconds
Started Jul 07 05:17:07 PM PDT 24
Finished Jul 07 05:20:44 PM PDT 24
Peak memory 200196 kb
Host smart-f9f78887-4f37-4e1a-a0c6-8948123248ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209162142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2209162142
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1596678871
Short name T444
Test name
Test status
Simulation time 9640616553 ps
CPU time 9.48 seconds
Started Jul 07 05:17:12 PM PDT 24
Finished Jul 07 05:17:22 PM PDT 24
Peak memory 199904 kb
Host smart-e7ab7e74-1867-4f59-90c8-cbe6849c948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596678871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1596678871
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2649610147
Short name T207
Test name
Test status
Simulation time 33869479316 ps
CPU time 49.86 seconds
Started Jul 07 05:17:13 PM PDT 24
Finished Jul 07 05:18:03 PM PDT 24
Peak memory 199872 kb
Host smart-f9c9b73a-5aca-4a7a-83b9-4baf236bd037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649610147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2649610147
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4172003223
Short name T663
Test name
Test status
Simulation time 13154336888 ps
CPU time 12.84 seconds
Started Jul 07 05:17:14 PM PDT 24
Finished Jul 07 05:17:27 PM PDT 24
Peak memory 199888 kb
Host smart-f0604d87-7303-457c-bcfc-a408d0505530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172003223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4172003223
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4028992537
Short name T739
Test name
Test status
Simulation time 15269977804 ps
CPU time 23.55 seconds
Started Jul 07 05:17:12 PM PDT 24
Finished Jul 07 05:17:36 PM PDT 24
Peak memory 199980 kb
Host smart-7c396586-ff6f-461d-b561-5bbb9f762790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028992537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4028992537
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.4076990867
Short name T215
Test name
Test status
Simulation time 15979189356 ps
CPU time 22.58 seconds
Started Jul 07 05:17:14 PM PDT 24
Finished Jul 07 05:17:37 PM PDT 24
Peak memory 199924 kb
Host smart-427f1332-3e76-446d-88d7-5dad3cafa21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076990867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.4076990867
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3047416342
Short name T393
Test name
Test status
Simulation time 42308614 ps
CPU time 0.58 seconds
Started Jul 07 05:13:09 PM PDT 24
Finished Jul 07 05:13:10 PM PDT 24
Peak memory 195292 kb
Host smart-e0e7b086-205a-4ee5-a8a8-16b96a3da0f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047416342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3047416342
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_intr.4217750147
Short name T21
Test name
Test status
Simulation time 13539106309 ps
CPU time 13.12 seconds
Started Jul 07 05:13:08 PM PDT 24
Finished Jul 07 05:13:21 PM PDT 24
Peak memory 197480 kb
Host smart-f3f274c2-8d18-4d51-87e2-347b454d92cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217750147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4217750147
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2377945375
Short name T938
Test name
Test status
Simulation time 146099673862 ps
CPU time 1433.06 seconds
Started Jul 07 05:13:10 PM PDT 24
Finished Jul 07 05:37:03 PM PDT 24
Peak memory 199828 kb
Host smart-b4d66a50-9582-4174-9f10-427bb5614143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377945375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2377945375
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.313924340
Short name T626
Test name
Test status
Simulation time 6194438513 ps
CPU time 3.78 seconds
Started Jul 07 05:13:09 PM PDT 24
Finished Jul 07 05:13:13 PM PDT 24
Peak memory 198332 kb
Host smart-dfe637a5-abc6-41eb-b310-bae9a915358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313924340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.313924340
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3161836809
Short name T694
Test name
Test status
Simulation time 27661226397 ps
CPU time 42.25 seconds
Started Jul 07 05:13:08 PM PDT 24
Finished Jul 07 05:13:50 PM PDT 24
Peak memory 199532 kb
Host smart-2a4c29bd-cd6b-4bba-bd08-d5be664c943f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161836809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3161836809
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2421217393
Short name T400
Test name
Test status
Simulation time 4365190491 ps
CPU time 235.8 seconds
Started Jul 07 05:13:10 PM PDT 24
Finished Jul 07 05:17:06 PM PDT 24
Peak memory 199948 kb
Host smart-0dbc5792-c746-4e6d-85a5-9cef03e4eadf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421217393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2421217393
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1367571976
Short name T1063
Test name
Test status
Simulation time 3624734772 ps
CPU time 28.88 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:13:33 PM PDT 24
Peak memory 198932 kb
Host smart-038a9062-b3b0-4bca-a0be-8fc4a0d95e7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367571976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1367571976
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2620914843
Short name T438
Test name
Test status
Simulation time 24612385229 ps
CPU time 34.84 seconds
Started Jul 07 05:13:11 PM PDT 24
Finished Jul 07 05:13:46 PM PDT 24
Peak memory 199948 kb
Host smart-4880cb5d-3db8-41da-a3d0-6a388762a45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620914843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2620914843
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4287616606
Short name T648
Test name
Test status
Simulation time 602783855 ps
CPU time 1.55 seconds
Started Jul 07 05:13:08 PM PDT 24
Finished Jul 07 05:13:10 PM PDT 24
Peak memory 195420 kb
Host smart-7b61fee9-359e-49a6-8ef4-d469919f6dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287616606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4287616606
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3273737789
Short name T420
Test name
Test status
Simulation time 5722060066 ps
CPU time 7.44 seconds
Started Jul 07 05:13:07 PM PDT 24
Finished Jul 07 05:13:15 PM PDT 24
Peak memory 199900 kb
Host smart-96ba552f-2678-47ba-978b-0c9bfa46e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273737789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3273737789
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3749941491
Short name T123
Test name
Test status
Simulation time 46576119287 ps
CPU time 73 seconds
Started Jul 07 05:13:10 PM PDT 24
Finished Jul 07 05:14:23 PM PDT 24
Peak memory 199896 kb
Host smart-70909a7b-ccf4-4192-ba89-25490df5dc3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749941491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3749941491
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2092790103
Short name T66
Test name
Test status
Simulation time 208885933806 ps
CPU time 1283.22 seconds
Started Jul 07 05:13:07 PM PDT 24
Finished Jul 07 05:34:31 PM PDT 24
Peak memory 224860 kb
Host smart-9e7c2dcb-5f9f-477f-b750-396c886f2ebc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092790103 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2092790103
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1301030331
Short name T368
Test name
Test status
Simulation time 7009682300 ps
CPU time 12.61 seconds
Started Jul 07 05:13:10 PM PDT 24
Finished Jul 07 05:13:23 PM PDT 24
Peak memory 199708 kb
Host smart-2f0dc344-f757-419a-abc9-0033d86f5a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301030331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1301030331
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.826717264
Short name T418
Test name
Test status
Simulation time 47602450549 ps
CPU time 90.12 seconds
Started Jul 07 05:13:07 PM PDT 24
Finished Jul 07 05:14:37 PM PDT 24
Peak memory 199856 kb
Host smart-f1eec5fa-59b4-4d48-bd8d-18b8282c65a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826717264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.826717264
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1257003076
Short name T913
Test name
Test status
Simulation time 14394333905 ps
CPU time 14.23 seconds
Started Jul 07 05:17:18 PM PDT 24
Finished Jul 07 05:17:32 PM PDT 24
Peak memory 199724 kb
Host smart-df48505b-e1d3-44d8-a1c8-48470e1bf0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257003076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1257003076
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.872999351
Short name T683
Test name
Test status
Simulation time 10122976026 ps
CPU time 8.32 seconds
Started Jul 07 05:17:17 PM PDT 24
Finished Jul 07 05:17:25 PM PDT 24
Peak memory 198408 kb
Host smart-e38e029a-fc57-4e56-8b24-de7d9de164b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872999351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.872999351
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.445587159
Short name T508
Test name
Test status
Simulation time 115298112496 ps
CPU time 150.54 seconds
Started Jul 07 05:17:19 PM PDT 24
Finished Jul 07 05:19:50 PM PDT 24
Peak memory 199848 kb
Host smart-c4ca2f05-0b54-4d54-87be-827667c71d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445587159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.445587159
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3912438456
Short name T214
Test name
Test status
Simulation time 46884160398 ps
CPU time 38.17 seconds
Started Jul 07 05:17:17 PM PDT 24
Finished Jul 07 05:17:55 PM PDT 24
Peak memory 199916 kb
Host smart-f1353951-1424-4dc3-a3cb-a400de3778e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912438456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3912438456
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.445405834
Short name T1169
Test name
Test status
Simulation time 114110035478 ps
CPU time 147.96 seconds
Started Jul 07 05:17:19 PM PDT 24
Finished Jul 07 05:19:47 PM PDT 24
Peak memory 199852 kb
Host smart-87ac61a6-a0ae-4ab5-806f-db0f989a2929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445405834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.445405834
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1123636827
Short name T611
Test name
Test status
Simulation time 77521498890 ps
CPU time 9.9 seconds
Started Jul 07 05:17:17 PM PDT 24
Finished Jul 07 05:17:27 PM PDT 24
Peak memory 199964 kb
Host smart-48d2502b-3fba-4158-a1c0-b4edb21076ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123636827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1123636827
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3073995896
Short name T45
Test name
Test status
Simulation time 148594700428 ps
CPU time 32.22 seconds
Started Jul 07 05:17:19 PM PDT 24
Finished Jul 07 05:17:51 PM PDT 24
Peak memory 199896 kb
Host smart-4d72e5f5-7f28-4047-bb93-20d021f0d32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073995896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3073995896
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2252455757
Short name T226
Test name
Test status
Simulation time 104989597215 ps
CPU time 147.61 seconds
Started Jul 07 05:17:18 PM PDT 24
Finished Jul 07 05:19:46 PM PDT 24
Peak memory 199936 kb
Host smart-afc17701-3efe-4a3d-8a13-5ce00c70a04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252455757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2252455757
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.654906861
Short name T984
Test name
Test status
Simulation time 35115369688 ps
CPU time 64.82 seconds
Started Jul 07 05:17:16 PM PDT 24
Finished Jul 07 05:18:21 PM PDT 24
Peak memory 199900 kb
Host smart-43f37a9c-89f5-4c93-b2e9-f92cd082f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654906861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.654906861
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1758911822
Short name T833
Test name
Test status
Simulation time 25067813 ps
CPU time 0.55 seconds
Started Jul 07 05:13:15 PM PDT 24
Finished Jul 07 05:13:15 PM PDT 24
Peak memory 194948 kb
Host smart-6bc52df3-599b-4516-b1db-d6df50c6d6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758911822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1758911822
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1201091836
Short name T692
Test name
Test status
Simulation time 33219780147 ps
CPU time 35.04 seconds
Started Jul 07 05:13:10 PM PDT 24
Finished Jul 07 05:13:45 PM PDT 24
Peak memory 199944 kb
Host smart-91f02b68-79ad-4c97-b9d0-2334de47305a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201091836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1201091836
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1217438944
Short name T173
Test name
Test status
Simulation time 59106898654 ps
CPU time 95.6 seconds
Started Jul 07 05:13:12 PM PDT 24
Finished Jul 07 05:14:48 PM PDT 24
Peak memory 199952 kb
Host smart-506faca4-613a-4514-aa9b-5da66de69ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217438944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1217438944
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.612213421
Short name T628
Test name
Test status
Simulation time 41123956468 ps
CPU time 15.49 seconds
Started Jul 07 05:13:09 PM PDT 24
Finished Jul 07 05:13:24 PM PDT 24
Peak memory 199932 kb
Host smart-cb49a6e1-a3db-4d28-8b8e-359f5797f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612213421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.612213421
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3959194913
Short name T696
Test name
Test status
Simulation time 286598631569 ps
CPU time 230.11 seconds
Started Jul 07 05:13:14 PM PDT 24
Finished Jul 07 05:17:05 PM PDT 24
Peak memory 199300 kb
Host smart-dcd142fe-e0f9-4c07-bb13-d71e9a1e7406
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959194913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3959194913
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3108591830
Short name T643
Test name
Test status
Simulation time 153154333377 ps
CPU time 135.21 seconds
Started Jul 07 05:13:13 PM PDT 24
Finished Jul 07 05:15:28 PM PDT 24
Peak memory 199968 kb
Host smart-83c9521c-a8e6-4a3a-9c2a-8b1c6c42352e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108591830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3108591830
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3263054457
Short name T326
Test name
Test status
Simulation time 747145267 ps
CPU time 0.95 seconds
Started Jul 07 05:13:14 PM PDT 24
Finished Jul 07 05:13:15 PM PDT 24
Peak memory 195956 kb
Host smart-591b8d4b-724b-42fa-b1a9-7e763a1b116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263054457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3263054457
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2436146041
Short name T691
Test name
Test status
Simulation time 79239793693 ps
CPU time 38.77 seconds
Started Jul 07 05:13:14 PM PDT 24
Finished Jul 07 05:13:53 PM PDT 24
Peak memory 200160 kb
Host smart-a74fb79f-8f2c-4961-a98d-36427fb46da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436146041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2436146041
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.4036989707
Short name T47
Test name
Test status
Simulation time 18404905229 ps
CPU time 984.26 seconds
Started Jul 07 05:13:16 PM PDT 24
Finished Jul 07 05:29:41 PM PDT 24
Peak memory 199880 kb
Host smart-28826a92-3cd7-42d8-86ba-b9fb27a03c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036989707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4036989707
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2197105690
Short name T890
Test name
Test status
Simulation time 5740583090 ps
CPU time 46.53 seconds
Started Jul 07 05:13:13 PM PDT 24
Finished Jul 07 05:14:00 PM PDT 24
Peak memory 199968 kb
Host smart-da84c9d4-7d94-413d-b503-41df47e11c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197105690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2197105690
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1737806375
Short name T1125
Test name
Test status
Simulation time 3606923745 ps
CPU time 3.19 seconds
Started Jul 07 05:13:14 PM PDT 24
Finished Jul 07 05:13:17 PM PDT 24
Peak memory 195952 kb
Host smart-9c8fa202-de4c-460d-b3db-f46cdf1aa48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737806375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1737806375
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1023853317
Short name T689
Test name
Test status
Simulation time 501894950 ps
CPU time 1.37 seconds
Started Jul 07 05:13:09 PM PDT 24
Finished Jul 07 05:13:11 PM PDT 24
Peak memory 199948 kb
Host smart-5e4cc284-a61c-4fd2-986b-cf28f837748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023853317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1023853317
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.428282223
Short name T565
Test name
Test status
Simulation time 201464891751 ps
CPU time 1337.88 seconds
Started Jul 07 05:13:17 PM PDT 24
Finished Jul 07 05:35:35 PM PDT 24
Peak memory 224720 kb
Host smart-4b125979-714f-4377-a1e2-af5f64728305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428282223 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.428282223
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.4219744798
Short name T1142
Test name
Test status
Simulation time 1927264659 ps
CPU time 1.9 seconds
Started Jul 07 05:13:16 PM PDT 24
Finished Jul 07 05:13:18 PM PDT 24
Peak memory 199092 kb
Host smart-4d491a7e-34d4-4880-9924-e51b6e33547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219744798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.4219744798
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3335937101
Short name T276
Test name
Test status
Simulation time 35966246256 ps
CPU time 59.32 seconds
Started Jul 07 05:13:09 PM PDT 24
Finished Jul 07 05:14:09 PM PDT 24
Peak memory 199900 kb
Host smart-dfb98f18-1063-4a8c-86e1-1060b7fad112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335937101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3335937101
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2189640722
Short name T195
Test name
Test status
Simulation time 14992082693 ps
CPU time 21.1 seconds
Started Jul 07 05:17:23 PM PDT 24
Finished Jul 07 05:17:44 PM PDT 24
Peak memory 199976 kb
Host smart-5d69621b-9211-4a62-abfa-8d164951a7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189640722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2189640722
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2066206176
Short name T767
Test name
Test status
Simulation time 220546708710 ps
CPU time 78.32 seconds
Started Jul 07 05:17:24 PM PDT 24
Finished Jul 07 05:18:42 PM PDT 24
Peak memory 199956 kb
Host smart-0e3939a6-96b8-454b-aef8-7338c7004630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066206176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2066206176
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2159830823
Short name T346
Test name
Test status
Simulation time 55344484581 ps
CPU time 22.69 seconds
Started Jul 07 05:17:24 PM PDT 24
Finished Jul 07 05:17:47 PM PDT 24
Peak memory 199940 kb
Host smart-84cfc67b-4bf8-4297-a98c-73d5a2884ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159830823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2159830823
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1907480178
Short name T1118
Test name
Test status
Simulation time 35458190956 ps
CPU time 17.31 seconds
Started Jul 07 05:17:19 PM PDT 24
Finished Jul 07 05:17:36 PM PDT 24
Peak memory 199848 kb
Host smart-0c4fea52-ccd4-4214-8e0c-348fd7d860e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907480178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1907480178
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3756167796
Short name T1127
Test name
Test status
Simulation time 168154386794 ps
CPU time 23.95 seconds
Started Jul 07 05:17:22 PM PDT 24
Finished Jul 07 05:17:46 PM PDT 24
Peak memory 199832 kb
Host smart-7c5c9bbe-5e59-4e44-8d7a-3be5ae915588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756167796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3756167796
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.556722734
Short name T185
Test name
Test status
Simulation time 108909065142 ps
CPU time 206.18 seconds
Started Jul 07 05:17:20 PM PDT 24
Finished Jul 07 05:20:47 PM PDT 24
Peak memory 199924 kb
Host smart-8e0a4437-f8ea-45b8-8e75-c21606f59819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556722734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.556722734
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3471332809
Short name T641
Test name
Test status
Simulation time 25782931161 ps
CPU time 18.62 seconds
Started Jul 07 05:17:21 PM PDT 24
Finished Jul 07 05:17:40 PM PDT 24
Peak memory 199108 kb
Host smart-b9079fbe-3428-4301-a648-8f37fb9a8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471332809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3471332809
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2126556637
Short name T162
Test name
Test status
Simulation time 151421678731 ps
CPU time 21.56 seconds
Started Jul 07 05:17:24 PM PDT 24
Finished Jul 07 05:17:46 PM PDT 24
Peak memory 199928 kb
Host smart-fc82fd3f-a219-4ed5-bfa0-6440454f5f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126556637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2126556637
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3508361056
Short name T1122
Test name
Test status
Simulation time 12852683 ps
CPU time 0.58 seconds
Started Jul 07 05:13:24 PM PDT 24
Finished Jul 07 05:13:24 PM PDT 24
Peak memory 195584 kb
Host smart-7c31da8d-8c58-428e-9ba9-1079d79a0a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508361056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3508361056
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2976684885
Short name T266
Test name
Test status
Simulation time 82312691754 ps
CPU time 40.88 seconds
Started Jul 07 05:13:19 PM PDT 24
Finished Jul 07 05:14:00 PM PDT 24
Peak memory 199968 kb
Host smart-4feea7ba-c2e3-478b-a52d-0406daa81286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976684885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2976684885
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.4215292938
Short name T175
Test name
Test status
Simulation time 93347910745 ps
CPU time 74.35 seconds
Started Jul 07 05:13:17 PM PDT 24
Finished Jul 07 05:14:32 PM PDT 24
Peak memory 199916 kb
Host smart-1ffb618d-4f59-4a26-b806-ce2b807bb941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215292938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4215292938
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3076711162
Short name T1098
Test name
Test status
Simulation time 162511661472 ps
CPU time 107.16 seconds
Started Jul 07 05:13:20 PM PDT 24
Finished Jul 07 05:15:07 PM PDT 24
Peak memory 199884 kb
Host smart-91aebf00-7de9-45cf-a0d3-699f728a8277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076711162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3076711162
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.206609363
Short name T1048
Test name
Test status
Simulation time 12699071926 ps
CPU time 13.27 seconds
Started Jul 07 05:13:17 PM PDT 24
Finished Jul 07 05:13:31 PM PDT 24
Peak memory 199900 kb
Host smart-640f49d2-60af-4f6d-bbab-7c1f49a4e180
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206609363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.206609363
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1103750098
Short name T635
Test name
Test status
Simulation time 69210960098 ps
CPU time 505.53 seconds
Started Jul 07 05:13:24 PM PDT 24
Finished Jul 07 05:21:49 PM PDT 24
Peak memory 199868 kb
Host smart-6ae89701-fec8-4e04-9f1e-6b7a4cb60a7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103750098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1103750098
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1574903345
Short name T428
Test name
Test status
Simulation time 1454805977 ps
CPU time 2.61 seconds
Started Jul 07 05:13:18 PM PDT 24
Finished Jul 07 05:13:21 PM PDT 24
Peak memory 198336 kb
Host smart-e4a7bb7b-f671-46b1-8fb9-5153a1f111ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574903345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1574903345
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1933079784
Short name T1060
Test name
Test status
Simulation time 47220730371 ps
CPU time 133.64 seconds
Started Jul 07 05:13:17 PM PDT 24
Finished Jul 07 05:15:30 PM PDT 24
Peak memory 198820 kb
Host smart-05a241c1-d8a9-4732-8814-befa00c40a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933079784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1933079784
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.4194895650
Short name T290
Test name
Test status
Simulation time 19459037145 ps
CPU time 1115.74 seconds
Started Jul 07 05:13:17 PM PDT 24
Finished Jul 07 05:31:53 PM PDT 24
Peak memory 199864 kb
Host smart-7eae0bfb-53e0-49eb-a907-35be34396309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194895650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4194895650
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2063261273
Short name T388
Test name
Test status
Simulation time 1675399078 ps
CPU time 3.01 seconds
Started Jul 07 05:13:17 PM PDT 24
Finished Jul 07 05:13:21 PM PDT 24
Peak memory 198660 kb
Host smart-ac6f3df0-7395-4dd0-9423-b14a32fc7723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063261273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2063261273
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.529422634
Short name T910
Test name
Test status
Simulation time 73926926189 ps
CPU time 104.8 seconds
Started Jul 07 05:13:20 PM PDT 24
Finished Jul 07 05:15:05 PM PDT 24
Peak memory 199908 kb
Host smart-9d62e966-b8b9-4cbb-a95a-dd7536742f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529422634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.529422634
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2930593562
Short name T1171
Test name
Test status
Simulation time 40470319935 ps
CPU time 15.66 seconds
Started Jul 07 05:13:17 PM PDT 24
Finished Jul 07 05:13:33 PM PDT 24
Peak memory 196700 kb
Host smart-3e61c5c2-13d3-4a16-a7c5-937091988e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930593562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2930593562
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3437229676
Short name T969
Test name
Test status
Simulation time 88725936 ps
CPU time 0.92 seconds
Started Jul 07 05:13:13 PM PDT 24
Finished Jul 07 05:13:14 PM PDT 24
Peak memory 197936 kb
Host smart-b38c195a-476c-4bbb-84a7-2d1d6f38e0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437229676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3437229676
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.145815828
Short name T1080
Test name
Test status
Simulation time 167485380152 ps
CPU time 260.58 seconds
Started Jul 07 05:13:21 PM PDT 24
Finished Jul 07 05:17:41 PM PDT 24
Peak memory 199960 kb
Host smart-7d59ce5f-6ee0-4f48-a5c3-c9f1a1b5ce63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145815828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.145815828
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.948775926
Short name T85
Test name
Test status
Simulation time 66158781295 ps
CPU time 455.71 seconds
Started Jul 07 05:13:24 PM PDT 24
Finished Jul 07 05:21:00 PM PDT 24
Peak memory 216680 kb
Host smart-9e4a9923-3d1e-4dc5-a44f-7dbce2265c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948775926 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.948775926
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3046170708
Short name T982
Test name
Test status
Simulation time 672578598 ps
CPU time 5.33 seconds
Started Jul 07 05:13:20 PM PDT 24
Finished Jul 07 05:13:26 PM PDT 24
Peak memory 199200 kb
Host smart-05bb2199-5ccc-4d70-8390-9cd5aef2b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046170708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3046170708
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2399406210
Short name T270
Test name
Test status
Simulation time 85778205809 ps
CPU time 70.83 seconds
Started Jul 07 05:13:19 PM PDT 24
Finished Jul 07 05:14:30 PM PDT 24
Peak memory 199912 kb
Host smart-441c4bef-7657-495f-a126-13624463d8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399406210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2399406210
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1327582981
Short name T698
Test name
Test status
Simulation time 218769418846 ps
CPU time 31.72 seconds
Started Jul 07 05:17:25 PM PDT 24
Finished Jul 07 05:17:57 PM PDT 24
Peak memory 199972 kb
Host smart-803d8620-5698-42eb-bdd1-0c03a7219274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327582981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1327582981
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3510454017
Short name T254
Test name
Test status
Simulation time 173063477421 ps
CPU time 273.75 seconds
Started Jul 07 05:17:25 PM PDT 24
Finished Jul 07 05:21:59 PM PDT 24
Peak memory 199980 kb
Host smart-e7ae3198-1486-47d7-819f-39d070220524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510454017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3510454017
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.859164549
Short name T322
Test name
Test status
Simulation time 41439947653 ps
CPU time 13.67 seconds
Started Jul 07 05:17:23 PM PDT 24
Finished Jul 07 05:17:37 PM PDT 24
Peak memory 199940 kb
Host smart-ffd9b6a7-b9c5-4165-bbfa-b326e29c9ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859164549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.859164549
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.501546909
Short name T673
Test name
Test status
Simulation time 2190929785 ps
CPU time 3.5 seconds
Started Jul 07 05:17:26 PM PDT 24
Finished Jul 07 05:17:30 PM PDT 24
Peak memory 199136 kb
Host smart-55c652c7-e006-4ba8-936b-91ccc0411bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501546909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.501546909
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2385405278
Short name T128
Test name
Test status
Simulation time 35978363020 ps
CPU time 23.37 seconds
Started Jul 07 05:17:27 PM PDT 24
Finished Jul 07 05:17:50 PM PDT 24
Peak memory 199952 kb
Host smart-84aa1240-2e9c-45a1-b528-45463ddfc8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385405278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2385405278
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.919935783
Short name T669
Test name
Test status
Simulation time 126090008986 ps
CPU time 197.23 seconds
Started Jul 07 05:17:32 PM PDT 24
Finished Jul 07 05:20:49 PM PDT 24
Peak memory 199900 kb
Host smart-1438fe4d-9d39-40d9-b2d4-128b429a63c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919935783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.919935783
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.906033317
Short name T1007
Test name
Test status
Simulation time 48550621054 ps
CPU time 67.19 seconds
Started Jul 07 05:17:32 PM PDT 24
Finished Jul 07 05:18:39 PM PDT 24
Peak memory 199960 kb
Host smart-bf8c0212-e4c6-4cc7-b13b-127e245c6c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906033317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.906033317
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.474938200
Short name T717
Test name
Test status
Simulation time 20936498846 ps
CPU time 22.85 seconds
Started Jul 07 05:17:31 PM PDT 24
Finished Jul 07 05:17:54 PM PDT 24
Peak memory 199840 kb
Host smart-850b1255-4884-41fd-bfbf-13f9dbbc365e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474938200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.474938200
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1623989129
Short name T1104
Test name
Test status
Simulation time 15046241579 ps
CPU time 26.83 seconds
Started Jul 07 05:17:29 PM PDT 24
Finished Jul 07 05:17:56 PM PDT 24
Peak memory 199884 kb
Host smart-683c7a4f-59a0-4233-8223-f1b5dde71b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623989129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1623989129
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.315064985
Short name T841
Test name
Test status
Simulation time 28806280 ps
CPU time 0.56 seconds
Started Jul 07 05:13:27 PM PDT 24
Finished Jul 07 05:13:28 PM PDT 24
Peak memory 195292 kb
Host smart-de8c537b-3476-4937-ae1a-5c45e6b2a2d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315064985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.315064985
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.4101903873
Short name T1116
Test name
Test status
Simulation time 32184004943 ps
CPU time 12.88 seconds
Started Jul 07 05:13:21 PM PDT 24
Finished Jul 07 05:13:35 PM PDT 24
Peak memory 199960 kb
Host smart-40e48a7c-3803-45bb-ba5a-e8c3df424db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101903873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.4101903873
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.664743238
Short name T462
Test name
Test status
Simulation time 29537785394 ps
CPU time 12.01 seconds
Started Jul 07 05:13:22 PM PDT 24
Finished Jul 07 05:13:35 PM PDT 24
Peak memory 199912 kb
Host smart-9896d984-6a1f-4d66-b0c2-099318c4bc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664743238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.664743238
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2654118967
Short name T761
Test name
Test status
Simulation time 17334200222 ps
CPU time 13.56 seconds
Started Jul 07 05:13:22 PM PDT 24
Finished Jul 07 05:13:36 PM PDT 24
Peak memory 199844 kb
Host smart-f1a20c4f-692a-4e3b-a29b-17254f5e523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654118967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2654118967
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.149806062
Short name T1023
Test name
Test status
Simulation time 48259385859 ps
CPU time 44.34 seconds
Started Jul 07 05:13:21 PM PDT 24
Finished Jul 07 05:14:06 PM PDT 24
Peak memory 199940 kb
Host smart-dc5b12d9-3f53-4998-94df-ca2720691532
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149806062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.149806062
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3497674231
Short name T603
Test name
Test status
Simulation time 109840789336 ps
CPU time 315.08 seconds
Started Jul 07 05:13:25 PM PDT 24
Finished Jul 07 05:18:41 PM PDT 24
Peak memory 200176 kb
Host smart-53297d1a-6404-47f7-9fe0-71ffa46b9d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497674231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3497674231
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.437481791
Short name T937
Test name
Test status
Simulation time 5713458544 ps
CPU time 9.18 seconds
Started Jul 07 05:13:27 PM PDT 24
Finished Jul 07 05:13:37 PM PDT 24
Peak memory 198896 kb
Host smart-9b8d00f9-6def-4450-95b0-d168668128ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437481791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.437481791
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1411869450
Short name T407
Test name
Test status
Simulation time 27791764918 ps
CPU time 12.25 seconds
Started Jul 07 05:13:24 PM PDT 24
Finished Jul 07 05:13:36 PM PDT 24
Peak memory 200416 kb
Host smart-f9772817-4f26-4d20-8e2c-50d9e31cce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411869450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1411869450
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4026273608
Short name T3
Test name
Test status
Simulation time 23614461924 ps
CPU time 268.44 seconds
Started Jul 07 05:13:25 PM PDT 24
Finished Jul 07 05:17:53 PM PDT 24
Peak memory 200008 kb
Host smart-ed6340f5-cc0b-4062-b7d2-6e8d89b7a481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026273608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4026273608
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1988498046
Short name T396
Test name
Test status
Simulation time 4832556768 ps
CPU time 23.99 seconds
Started Jul 07 05:13:23 PM PDT 24
Finished Jul 07 05:13:47 PM PDT 24
Peak memory 199092 kb
Host smart-7849ae58-f956-4e69-85a5-bd7fda89e95d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988498046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1988498046
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3883794095
Short name T349
Test name
Test status
Simulation time 161801101523 ps
CPU time 408.17 seconds
Started Jul 07 05:13:24 PM PDT 24
Finished Jul 07 05:20:13 PM PDT 24
Peak memory 199880 kb
Host smart-5069e232-325e-41d1-8370-623ba2125c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883794095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3883794095
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2477574923
Short name T1106
Test name
Test status
Simulation time 61345793595 ps
CPU time 90.09 seconds
Started Jul 07 05:13:29 PM PDT 24
Finished Jul 07 05:14:59 PM PDT 24
Peak memory 196196 kb
Host smart-2309b1ee-8084-4585-a1b6-dbad6212ea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477574923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2477574923
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.864183196
Short name T802
Test name
Test status
Simulation time 707636395 ps
CPU time 1.47 seconds
Started Jul 07 05:13:21 PM PDT 24
Finished Jul 07 05:13:23 PM PDT 24
Peak memory 198296 kb
Host smart-cf977dd6-bdaf-4c4a-beda-888724b0cf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864183196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.864183196
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3012368630
Short name T930
Test name
Test status
Simulation time 45465014386 ps
CPU time 748.14 seconds
Started Jul 07 05:13:26 PM PDT 24
Finished Jul 07 05:25:54 PM PDT 24
Peak memory 216924 kb
Host smart-654a0e43-840c-489d-b14d-4bed6a95db0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012368630 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3012368630
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1683157578
Short name T502
Test name
Test status
Simulation time 794765014 ps
CPU time 2.59 seconds
Started Jul 07 05:13:27 PM PDT 24
Finished Jul 07 05:13:30 PM PDT 24
Peak memory 199212 kb
Host smart-498ad447-48f3-44f6-99a7-5e2cac2013dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683157578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1683157578
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1910455879
Short name T711
Test name
Test status
Simulation time 73103157372 ps
CPU time 56.56 seconds
Started Jul 07 05:13:21 PM PDT 24
Finished Jul 07 05:14:18 PM PDT 24
Peak memory 200012 kb
Host smart-1ac06aa9-eed6-49cf-8d56-560850aa1fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910455879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1910455879
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3834247550
Short name T1040
Test name
Test status
Simulation time 26559274301 ps
CPU time 50.92 seconds
Started Jul 07 05:17:32 PM PDT 24
Finished Jul 07 05:18:23 PM PDT 24
Peak memory 199844 kb
Host smart-99694b27-8d2b-476c-b62e-a75837b80765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834247550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3834247550
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3213743277
Short name T933
Test name
Test status
Simulation time 88107759251 ps
CPU time 173.24 seconds
Started Jul 07 05:17:35 PM PDT 24
Finished Jul 07 05:20:28 PM PDT 24
Peak memory 199896 kb
Host smart-2d1ff98f-468f-4a02-bf4a-53ae7877e0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213743277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3213743277
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2002026577
Short name T227
Test name
Test status
Simulation time 21668412105 ps
CPU time 19.25 seconds
Started Jul 07 05:17:33 PM PDT 24
Finished Jul 07 05:17:52 PM PDT 24
Peak memory 199988 kb
Host smart-7b9d82eb-917e-455b-8145-0391b68b8c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002026577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2002026577
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.4221840795
Short name T845
Test name
Test status
Simulation time 130118030573 ps
CPU time 51.98 seconds
Started Jul 07 05:17:30 PM PDT 24
Finished Jul 07 05:18:22 PM PDT 24
Peak memory 199784 kb
Host smart-5620dd76-9c0b-4691-848f-23fe6f83ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221840795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.4221840795
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3905480243
Short name T186
Test name
Test status
Simulation time 133736624740 ps
CPU time 211.37 seconds
Started Jul 07 05:17:34 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 199976 kb
Host smart-7449162e-8d9d-4e98-9856-b01073dfc985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905480243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3905480243
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.638921747
Short name T142
Test name
Test status
Simulation time 29757799805 ps
CPU time 39.62 seconds
Started Jul 07 05:17:36 PM PDT 24
Finished Jul 07 05:18:16 PM PDT 24
Peak memory 199920 kb
Host smart-68f7e0c0-8069-4b73-99f0-cd8f0099cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638921747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.638921747
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2786642992
Short name T293
Test name
Test status
Simulation time 54727063123 ps
CPU time 20.21 seconds
Started Jul 07 05:17:31 PM PDT 24
Finished Jul 07 05:17:51 PM PDT 24
Peak memory 199876 kb
Host smart-0817357e-df01-4939-8433-2e9e9b829598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786642992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2786642992
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.318406796
Short name T56
Test name
Test status
Simulation time 53194867130 ps
CPU time 48.18 seconds
Started Jul 07 05:17:37 PM PDT 24
Finished Jul 07 05:18:26 PM PDT 24
Peak memory 199980 kb
Host smart-bf799de2-e450-4efd-ac38-03c787717054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318406796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.318406796
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.850157804
Short name T574
Test name
Test status
Simulation time 33373307319 ps
CPU time 47.94 seconds
Started Jul 07 05:17:33 PM PDT 24
Finished Jul 07 05:18:21 PM PDT 24
Peak memory 199776 kb
Host smart-a8184a7b-272d-4a52-acac-e776d9cc89b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850157804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.850157804
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2162474340
Short name T57
Test name
Test status
Simulation time 53454247 ps
CPU time 0.55 seconds
Started Jul 07 05:13:33 PM PDT 24
Finished Jul 07 05:13:34 PM PDT 24
Peak memory 195268 kb
Host smart-e3ccc21c-d7bb-4697-aca3-a546def39819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162474340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2162474340
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.4118745539
Short name T658
Test name
Test status
Simulation time 11510949307 ps
CPU time 8.56 seconds
Started Jul 07 05:13:28 PM PDT 24
Finished Jul 07 05:13:37 PM PDT 24
Peak memory 199940 kb
Host smart-1628c3dd-2c26-416a-8949-20adddb68f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118745539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.4118745539
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3538648456
Short name T815
Test name
Test status
Simulation time 112366058720 ps
CPU time 181.52 seconds
Started Jul 07 05:13:24 PM PDT 24
Finished Jul 07 05:16:26 PM PDT 24
Peak memory 199840 kb
Host smart-62a5de2c-0199-4fb8-9fa9-f7c41b668b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538648456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3538648456
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2871645565
Short name T163
Test name
Test status
Simulation time 31369248139 ps
CPU time 15.04 seconds
Started Jul 07 05:13:25 PM PDT 24
Finished Jul 07 05:13:41 PM PDT 24
Peak memory 199944 kb
Host smart-bd8b8029-a062-42de-960f-c29c9e9daa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871645565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2871645565
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.312028817
Short name T705
Test name
Test status
Simulation time 21849345396 ps
CPU time 9.94 seconds
Started Jul 07 05:13:27 PM PDT 24
Finished Jul 07 05:13:37 PM PDT 24
Peak memory 199316 kb
Host smart-b163c475-1b19-4045-a7b0-56e78ef42f78
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312028817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.312028817
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.242119252
Short name T584
Test name
Test status
Simulation time 158929322936 ps
CPU time 498.1 seconds
Started Jul 07 05:13:30 PM PDT 24
Finished Jul 07 05:21:48 PM PDT 24
Peak memory 199968 kb
Host smart-fb12fe3c-eead-4f3c-9d3e-02aec8af4c95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242119252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.242119252
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.4028452618
Short name T755
Test name
Test status
Simulation time 9884064945 ps
CPU time 13.32 seconds
Started Jul 07 05:13:31 PM PDT 24
Finished Jul 07 05:13:44 PM PDT 24
Peak memory 199956 kb
Host smart-49f63a46-6a16-4c26-9712-e6a6949dc953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028452618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.4028452618
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1998543463
Short name T1119
Test name
Test status
Simulation time 169733853975 ps
CPU time 53.71 seconds
Started Jul 07 05:13:27 PM PDT 24
Finished Jul 07 05:14:21 PM PDT 24
Peak memory 208180 kb
Host smart-daaed76c-9878-4101-8e73-678758793c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998543463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1998543463
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3838543352
Short name T526
Test name
Test status
Simulation time 18365691120 ps
CPU time 228.07 seconds
Started Jul 07 05:13:30 PM PDT 24
Finished Jul 07 05:17:18 PM PDT 24
Peak memory 199804 kb
Host smart-6b7f7f63-50d8-40d1-b9b8-82797b734d75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838543352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3838543352
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3073738012
Short name T850
Test name
Test status
Simulation time 3257194196 ps
CPU time 21.68 seconds
Started Jul 07 05:13:25 PM PDT 24
Finished Jul 07 05:13:47 PM PDT 24
Peak memory 197852 kb
Host smart-a60f9105-917c-4c24-b789-baf375ec1d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073738012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3073738012
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.198486153
Short name T53
Test name
Test status
Simulation time 130315384625 ps
CPU time 253.69 seconds
Started Jul 07 05:13:31 PM PDT 24
Finished Jul 07 05:17:45 PM PDT 24
Peak memory 199884 kb
Host smart-386eada7-73b2-4afe-93c8-086b37f91ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198486153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.198486153
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1508031371
Short name T863
Test name
Test status
Simulation time 37406005361 ps
CPU time 24.91 seconds
Started Jul 07 05:13:32 PM PDT 24
Finished Jul 07 05:13:57 PM PDT 24
Peak memory 196408 kb
Host smart-e1208a63-c585-4a74-a620-6781a8ff8462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508031371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1508031371
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2309724073
Short name T1148
Test name
Test status
Simulation time 501343455 ps
CPU time 2.82 seconds
Started Jul 07 05:13:25 PM PDT 24
Finished Jul 07 05:13:28 PM PDT 24
Peak memory 199032 kb
Host smart-40eeee85-75e1-4051-aa2d-0b3dba09a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309724073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2309724073
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.919112466
Short name T720
Test name
Test status
Simulation time 241273497130 ps
CPU time 600.5 seconds
Started Jul 07 05:13:30 PM PDT 24
Finished Jul 07 05:23:31 PM PDT 24
Peak memory 199880 kb
Host smart-aa8ee311-de7e-4ffc-973d-0b5603e3ca30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919112466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.919112466
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.105490832
Short name T11
Test name
Test status
Simulation time 2021770169 ps
CPU time 1.58 seconds
Started Jul 07 05:13:31 PM PDT 24
Finished Jul 07 05:13:33 PM PDT 24
Peak memory 198336 kb
Host smart-834622d7-1ca7-4c06-b6d6-998a75b0b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105490832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.105490832
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1759882960
Short name T562
Test name
Test status
Simulation time 59558144132 ps
CPU time 44.23 seconds
Started Jul 07 05:13:25 PM PDT 24
Finished Jul 07 05:14:09 PM PDT 24
Peak memory 199872 kb
Host smart-3fc99888-9acb-402e-81b6-09c3ae3fbc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759882960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1759882960
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.709789818
Short name T785
Test name
Test status
Simulation time 438565947475 ps
CPU time 51.37 seconds
Started Jul 07 05:17:38 PM PDT 24
Finished Jul 07 05:18:29 PM PDT 24
Peak memory 199920 kb
Host smart-47f5ae3e-c98a-4dd4-ae1b-153ae719fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709789818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.709789818
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.543748962
Short name T272
Test name
Test status
Simulation time 67975337658 ps
CPU time 105.34 seconds
Started Jul 07 05:17:32 PM PDT 24
Finished Jul 07 05:19:17 PM PDT 24
Peak memory 200172 kb
Host smart-baffba4e-5501-4540-ae25-ddea08cbcf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543748962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.543748962
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.606448872
Short name T477
Test name
Test status
Simulation time 5556114287 ps
CPU time 5.05 seconds
Started Jul 07 05:17:39 PM PDT 24
Finished Jul 07 05:17:44 PM PDT 24
Peak memory 198876 kb
Host smart-9b72b5e2-9d1a-4dd4-8fd4-88a96f6091e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606448872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.606448872
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3728799807
Short name T932
Test name
Test status
Simulation time 144760320084 ps
CPU time 170.68 seconds
Started Jul 07 05:17:40 PM PDT 24
Finished Jul 07 05:20:30 PM PDT 24
Peak memory 199908 kb
Host smart-0e1afb5a-f554-44c1-a437-ef75eb258ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728799807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3728799807
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1141596986
Short name T228
Test name
Test status
Simulation time 39357485692 ps
CPU time 8.5 seconds
Started Jul 07 05:17:41 PM PDT 24
Finished Jul 07 05:17:49 PM PDT 24
Peak memory 199912 kb
Host smart-8e6b60a2-df9b-47c7-b1a4-4895a8ef8bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141596986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1141596986
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.288450628
Short name T682
Test name
Test status
Simulation time 184523797598 ps
CPU time 43.03 seconds
Started Jul 07 05:17:38 PM PDT 24
Finished Jul 07 05:18:21 PM PDT 24
Peak memory 199900 kb
Host smart-7d481416-d7df-4b1c-88c4-9e837850e71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288450628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.288450628
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1207966345
Short name T928
Test name
Test status
Simulation time 18554257667 ps
CPU time 29.02 seconds
Started Jul 07 05:17:38 PM PDT 24
Finished Jul 07 05:18:07 PM PDT 24
Peak memory 199828 kb
Host smart-ff104655-95a8-47ed-986a-ceb3033677a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207966345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1207966345
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.257209879
Short name T538
Test name
Test status
Simulation time 128755066690 ps
CPU time 378.55 seconds
Started Jul 07 05:17:40 PM PDT 24
Finished Jul 07 05:23:59 PM PDT 24
Peak memory 199912 kb
Host smart-03e0df57-7c35-4f0b-8db6-e86427d256b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257209879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.257209879
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1798042721
Short name T714
Test name
Test status
Simulation time 14599996 ps
CPU time 0.56 seconds
Started Jul 07 05:13:34 PM PDT 24
Finished Jul 07 05:13:35 PM PDT 24
Peak memory 195432 kb
Host smart-9b3afb26-472b-4465-aa75-e65177774faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798042721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1798042721
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.943741878
Short name T784
Test name
Test status
Simulation time 23458366828 ps
CPU time 17.73 seconds
Started Jul 07 05:13:34 PM PDT 24
Finished Jul 07 05:13:52 PM PDT 24
Peak memory 199992 kb
Host smart-3f5e1560-85c2-404f-b30e-0df8af9534a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943741878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.943741878
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2078126258
Short name T768
Test name
Test status
Simulation time 21301433276 ps
CPU time 10.2 seconds
Started Jul 07 05:13:34 PM PDT 24
Finished Jul 07 05:13:45 PM PDT 24
Peak memory 199260 kb
Host smart-1bff064d-7acc-40e1-bcd8-1eaceeb060d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078126258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2078126258
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.530065339
Short name T570
Test name
Test status
Simulation time 40849935541 ps
CPU time 30.36 seconds
Started Jul 07 05:13:33 PM PDT 24
Finished Jul 07 05:14:04 PM PDT 24
Peak memory 199808 kb
Host smart-00efbcb9-3710-4b4d-b62d-8307b4a80aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530065339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.530065339
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.70411193
Short name T132
Test name
Test status
Simulation time 42989302921 ps
CPU time 17.49 seconds
Started Jul 07 05:13:35 PM PDT 24
Finished Jul 07 05:13:53 PM PDT 24
Peak memory 199912 kb
Host smart-09accbd8-fa61-4753-8989-a1bf6ad93a76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70411193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.70411193
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2012891038
Short name T292
Test name
Test status
Simulation time 117975571475 ps
CPU time 285.89 seconds
Started Jul 07 05:13:33 PM PDT 24
Finished Jul 07 05:18:19 PM PDT 24
Peak memory 199888 kb
Host smart-0072b95a-38f5-4582-8d6e-aa14f987123f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012891038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2012891038
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3752863038
Short name T467
Test name
Test status
Simulation time 2465543648 ps
CPU time 3.57 seconds
Started Jul 07 05:13:34 PM PDT 24
Finished Jul 07 05:13:38 PM PDT 24
Peak memory 198668 kb
Host smart-1aaf990a-bef1-4793-bc65-cd0b8e5eb228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752863038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3752863038
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.692352365
Short name T820
Test name
Test status
Simulation time 68293617159 ps
CPU time 96.06 seconds
Started Jul 07 05:13:36 PM PDT 24
Finished Jul 07 05:15:13 PM PDT 24
Peak memory 199512 kb
Host smart-856ddeb1-c753-4bc0-b850-8461915dbd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692352365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.692352365
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2991111117
Short name T869
Test name
Test status
Simulation time 15446071971 ps
CPU time 177.83 seconds
Started Jul 07 05:13:34 PM PDT 24
Finished Jul 07 05:16:32 PM PDT 24
Peak memory 199824 kb
Host smart-f4e17c80-4066-4ecb-870c-140f38aff6ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991111117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2991111117
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.973134828
Short name T924
Test name
Test status
Simulation time 2426575505 ps
CPU time 6.77 seconds
Started Jul 07 05:13:34 PM PDT 24
Finished Jul 07 05:13:41 PM PDT 24
Peak memory 198988 kb
Host smart-a158da0f-3dd5-4173-a65f-f24f0d7a8dec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973134828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.973134828
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2032950024
Short name T741
Test name
Test status
Simulation time 71397257937 ps
CPU time 36.47 seconds
Started Jul 07 05:13:35 PM PDT 24
Finished Jul 07 05:14:12 PM PDT 24
Peak memory 199912 kb
Host smart-c53b7258-a891-4279-9c79-f6a42088053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032950024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2032950024
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.467951540
Short name T893
Test name
Test status
Simulation time 86076223573 ps
CPU time 139.05 seconds
Started Jul 07 05:13:36 PM PDT 24
Finished Jul 07 05:15:56 PM PDT 24
Peak memory 195928 kb
Host smart-08bd2a24-6fd3-4dd7-8de8-57d02a9a1b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467951540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.467951540
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.676123487
Short name T544
Test name
Test status
Simulation time 105422182 ps
CPU time 0.83 seconds
Started Jul 07 05:13:33 PM PDT 24
Finished Jul 07 05:13:34 PM PDT 24
Peak memory 196848 kb
Host smart-7bff84ee-c9d6-45b0-a2ab-9f263d9a17d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676123487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.676123487
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.214226764
Short name T557
Test name
Test status
Simulation time 389148992899 ps
CPU time 97.42 seconds
Started Jul 07 05:13:32 PM PDT 24
Finished Jul 07 05:15:10 PM PDT 24
Peak memory 199968 kb
Host smart-609ce1bd-0b71-4e22-ad24-51eb2542863a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214226764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.214226764
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1637723692
Short name T25
Test name
Test status
Simulation time 61553719980 ps
CPU time 334.51 seconds
Started Jul 07 05:13:35 PM PDT 24
Finished Jul 07 05:19:10 PM PDT 24
Peak memory 214020 kb
Host smart-d1ffa729-d29f-4a49-b2d0-b6f274566682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637723692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1637723692
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.598135673
Short name T294
Test name
Test status
Simulation time 8826350140 ps
CPU time 13.25 seconds
Started Jul 07 05:13:34 PM PDT 24
Finished Jul 07 05:13:47 PM PDT 24
Peak memory 199992 kb
Host smart-53ae0f16-76b2-4021-bb52-3f38cc630b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598135673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.598135673
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1662326811
Short name T578
Test name
Test status
Simulation time 74344381898 ps
CPU time 29.99 seconds
Started Jul 07 05:13:32 PM PDT 24
Finished Jul 07 05:14:02 PM PDT 24
Peak memory 199960 kb
Host smart-c46d82a5-8d1a-4957-91fd-6a8183c09ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662326811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1662326811
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2940215566
Short name T534
Test name
Test status
Simulation time 54994615613 ps
CPU time 85.32 seconds
Started Jul 07 05:17:37 PM PDT 24
Finished Jul 07 05:19:03 PM PDT 24
Peak memory 199924 kb
Host smart-57cd73cc-53d5-4fbd-b071-fecf6d4822a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940215566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2940215566
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3635764903
Short name T789
Test name
Test status
Simulation time 315487980413 ps
CPU time 29 seconds
Started Jul 07 05:17:46 PM PDT 24
Finished Jul 07 05:18:15 PM PDT 24
Peak memory 199908 kb
Host smart-8df70dfc-a799-4776-b8a2-afa3fd2b5d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635764903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3635764903
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1032951744
Short name T189
Test name
Test status
Simulation time 264815500819 ps
CPU time 84.05 seconds
Started Jul 07 05:17:46 PM PDT 24
Finished Jul 07 05:19:11 PM PDT 24
Peak memory 199932 kb
Host smart-cb2219d5-c89a-4298-81fb-08bd8f1f37a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032951744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1032951744
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3334317070
Short name T1002
Test name
Test status
Simulation time 17007215267 ps
CPU time 33.28 seconds
Started Jul 07 05:17:45 PM PDT 24
Finished Jul 07 05:18:19 PM PDT 24
Peak memory 200024 kb
Host smart-3f68e26f-8e3c-420d-9061-5c109b54439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334317070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3334317070
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.4248676478
Short name T239
Test name
Test status
Simulation time 42866647742 ps
CPU time 18.26 seconds
Started Jul 07 05:17:42 PM PDT 24
Finished Jul 07 05:18:00 PM PDT 24
Peak memory 199984 kb
Host smart-f0d4df6b-c126-45c7-934c-771928341270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248676478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.4248676478
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2897474826
Short name T233
Test name
Test status
Simulation time 36927172186 ps
CPU time 53.47 seconds
Started Jul 07 05:17:41 PM PDT 24
Finished Jul 07 05:18:35 PM PDT 24
Peak memory 199888 kb
Host smart-a1aea1ba-045d-469a-9b2c-20481f055e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897474826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2897474826
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4158538145
Short name T967
Test name
Test status
Simulation time 234799448766 ps
CPU time 104.71 seconds
Started Jul 07 05:17:43 PM PDT 24
Finished Jul 07 05:19:28 PM PDT 24
Peak memory 199984 kb
Host smart-50d5c9ac-7c74-4f6b-9f48-75cacc374c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158538145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4158538145
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3408915163
Short name T344
Test name
Test status
Simulation time 20275487556 ps
CPU time 30.96 seconds
Started Jul 07 05:17:41 PM PDT 24
Finished Jul 07 05:18:12 PM PDT 24
Peak memory 199956 kb
Host smart-00d62d68-df47-4ade-9855-c3dac066cbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408915163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3408915163
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.36631052
Short name T525
Test name
Test status
Simulation time 23114960978 ps
CPU time 10.24 seconds
Started Jul 07 05:17:46 PM PDT 24
Finished Jul 07 05:17:57 PM PDT 24
Peak memory 199884 kb
Host smart-7e298310-2e4a-406d-9f53-5299ea96a3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36631052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.36631052
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1326522151
Short name T455
Test name
Test status
Simulation time 21923725885 ps
CPU time 33.35 seconds
Started Jul 07 05:17:40 PM PDT 24
Finished Jul 07 05:18:14 PM PDT 24
Peak memory 199948 kb
Host smart-4aaff037-ba31-49ee-890c-a1aadfc9aa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326522151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1326522151
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2132805277
Short name T550
Test name
Test status
Simulation time 18907638 ps
CPU time 0.56 seconds
Started Jul 07 05:12:43 PM PDT 24
Finished Jul 07 05:12:44 PM PDT 24
Peak memory 194540 kb
Host smart-5adb90ab-a48d-498d-baf0-b6b1ba024dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132805277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2132805277
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3114898394
Short name T308
Test name
Test status
Simulation time 61199881888 ps
CPU time 44.76 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:13:25 PM PDT 24
Peak memory 199884 kb
Host smart-8e6d2431-8aca-4251-bdc9-258143152cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114898394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3114898394
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1861526114
Short name T1114
Test name
Test status
Simulation time 7595558367 ps
CPU time 11.83 seconds
Started Jul 07 05:12:38 PM PDT 24
Finished Jul 07 05:12:50 PM PDT 24
Peak memory 199940 kb
Host smart-93f7c9b9-aa63-4cd9-8bae-32eb0efa1ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861526114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1861526114
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.259441549
Short name T746
Test name
Test status
Simulation time 10569682259 ps
CPU time 28.44 seconds
Started Jul 07 05:12:36 PM PDT 24
Finished Jul 07 05:13:06 PM PDT 24
Peak memory 199864 kb
Host smart-54934169-4151-4266-bbdc-41689b4cb1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259441549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.259441549
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.822247748
Short name T551
Test name
Test status
Simulation time 7501695347 ps
CPU time 10.46 seconds
Started Jul 07 05:12:42 PM PDT 24
Finished Jul 07 05:12:53 PM PDT 24
Peak memory 199528 kb
Host smart-1bda913a-0142-4e8a-8d3c-d2df082383e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822247748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.822247748
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3029812473
Short name T1046
Test name
Test status
Simulation time 144552013359 ps
CPU time 450.03 seconds
Started Jul 07 05:12:39 PM PDT 24
Finished Jul 07 05:20:09 PM PDT 24
Peak memory 199880 kb
Host smart-29600e8c-f6e0-4dfa-ab56-6f5355bade8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029812473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3029812473
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1958881281
Short name T838
Test name
Test status
Simulation time 7722688476 ps
CPU time 5.68 seconds
Started Jul 07 05:12:44 PM PDT 24
Finished Jul 07 05:12:51 PM PDT 24
Peak memory 199696 kb
Host smart-d4387205-5168-4ea5-b27e-3939d038c9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958881281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1958881281
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.705341538
Short name T44
Test name
Test status
Simulation time 91949802752 ps
CPU time 186.13 seconds
Started Jul 07 05:12:43 PM PDT 24
Finished Jul 07 05:15:50 PM PDT 24
Peak memory 208208 kb
Host smart-6545912a-1282-437e-be4a-4032a747bfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705341538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.705341538
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3549402324
Short name T986
Test name
Test status
Simulation time 10405605160 ps
CPU time 301.94 seconds
Started Jul 07 05:12:45 PM PDT 24
Finished Jul 07 05:17:48 PM PDT 24
Peak memory 199956 kb
Host smart-73f42fc9-68a8-432e-8092-abfb3f59d8e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549402324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3549402324
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.416123764
Short name T718
Test name
Test status
Simulation time 2760233151 ps
CPU time 17.89 seconds
Started Jul 07 05:12:41 PM PDT 24
Finished Jul 07 05:12:59 PM PDT 24
Peak memory 198296 kb
Host smart-4cac37c9-f558-4663-97f5-bb9ec292301c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416123764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.416123764
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4213653112
Short name T365
Test name
Test status
Simulation time 93665555089 ps
CPU time 45.71 seconds
Started Jul 07 05:12:41 PM PDT 24
Finished Jul 07 05:13:27 PM PDT 24
Peak memory 199936 kb
Host smart-0e182440-8cf3-4e83-be91-4c6d84ff74dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213653112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4213653112
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1639336636
Short name T771
Test name
Test status
Simulation time 2508489542 ps
CPU time 3.15 seconds
Started Jul 07 05:12:45 PM PDT 24
Finished Jul 07 05:12:49 PM PDT 24
Peak memory 195840 kb
Host smart-76fd1c6e-2406-4dd9-91cc-90a75fb26d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639336636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1639336636
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3928477026
Short name T32
Test name
Test status
Simulation time 70833075 ps
CPU time 0.82 seconds
Started Jul 07 05:12:44 PM PDT 24
Finished Jul 07 05:12:46 PM PDT 24
Peak memory 218252 kb
Host smart-fbafb8ca-a607-4268-b8bd-62d612276a72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928477026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3928477026
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.813677376
Short name T979
Test name
Test status
Simulation time 804219071 ps
CPU time 2.91 seconds
Started Jul 07 05:12:37 PM PDT 24
Finished Jul 07 05:12:41 PM PDT 24
Peak memory 198216 kb
Host smart-a66b1987-d3e4-4156-84f5-a8893d139346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813677376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.813677376
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1696444229
Short name T921
Test name
Test status
Simulation time 25230631484 ps
CPU time 217.78 seconds
Started Jul 07 05:12:45 PM PDT 24
Finished Jul 07 05:16:23 PM PDT 24
Peak memory 208208 kb
Host smart-356a52a3-2bcf-4b69-bd8d-594e573214dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696444229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1696444229
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1671056395
Short name T1139
Test name
Test status
Simulation time 799023564 ps
CPU time 2.53 seconds
Started Jul 07 05:12:41 PM PDT 24
Finished Jul 07 05:12:43 PM PDT 24
Peak memory 199664 kb
Host smart-21eeac84-88d5-4e64-ac7d-747381754ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671056395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1671056395
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2379873516
Short name T873
Test name
Test status
Simulation time 46206778549 ps
CPU time 18.69 seconds
Started Jul 07 05:12:38 PM PDT 24
Finished Jul 07 05:12:57 PM PDT 24
Peak memory 200256 kb
Host smart-c689b3f6-6f3b-4f64-a8cb-92d8e0b4e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379873516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2379873516
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2792988089
Short name T594
Test name
Test status
Simulation time 16183757 ps
CPU time 0.57 seconds
Started Jul 07 05:13:39 PM PDT 24
Finished Jul 07 05:13:40 PM PDT 24
Peak memory 195268 kb
Host smart-b8fabed8-591a-46fd-bde7-d656ff04c32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792988089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2792988089
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.4237016739
Short name T1011
Test name
Test status
Simulation time 143675030569 ps
CPU time 40.42 seconds
Started Jul 07 05:13:37 PM PDT 24
Finished Jul 07 05:14:17 PM PDT 24
Peak memory 199916 kb
Host smart-8ecdfa49-b3c3-4f00-a4fc-0fee19a866d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237016739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4237016739
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1676480656
Short name T813
Test name
Test status
Simulation time 94358213753 ps
CPU time 81.67 seconds
Started Jul 07 05:13:36 PM PDT 24
Finished Jul 07 05:14:58 PM PDT 24
Peak memory 199976 kb
Host smart-21fab206-91d5-41f5-b7ad-efa13322f5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676480656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1676480656
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1603715261
Short name T840
Test name
Test status
Simulation time 112387459153 ps
CPU time 33.66 seconds
Started Jul 07 05:13:37 PM PDT 24
Finished Jul 07 05:14:11 PM PDT 24
Peak memory 200000 kb
Host smart-1f5ee94b-a8f0-4088-a664-c17febfa22af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603715261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1603715261
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3096825119
Short name T881
Test name
Test status
Simulation time 33696372933 ps
CPU time 52.58 seconds
Started Jul 07 05:13:40 PM PDT 24
Finished Jul 07 05:14:33 PM PDT 24
Peak memory 199912 kb
Host smart-f1fc6186-7089-43e6-bf02-18f2919ad6ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096825119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3096825119
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1244779906
Short name T849
Test name
Test status
Simulation time 80543999007 ps
CPU time 165.4 seconds
Started Jul 07 05:13:39 PM PDT 24
Finished Jul 07 05:16:25 PM PDT 24
Peak memory 199868 kb
Host smart-9a9e6e64-2b4a-4074-9c32-32324193f3af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244779906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1244779906
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2327051013
Short name T1078
Test name
Test status
Simulation time 5232038320 ps
CPU time 11.59 seconds
Started Jul 07 05:13:38 PM PDT 24
Finished Jul 07 05:13:50 PM PDT 24
Peak memory 199336 kb
Host smart-d872bcd5-0ffb-4895-a29d-7c819c4b0792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327051013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2327051013
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.240079648
Short name T1157
Test name
Test status
Simulation time 90362167980 ps
CPU time 24.51 seconds
Started Jul 07 05:13:38 PM PDT 24
Finished Jul 07 05:14:03 PM PDT 24
Peak memory 199620 kb
Host smart-d3b8190f-3b69-47c5-b8b1-fc5995ad6b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240079648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.240079648
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2519510355
Short name T1121
Test name
Test status
Simulation time 14422493778 ps
CPU time 444.43 seconds
Started Jul 07 05:13:40 PM PDT 24
Finished Jul 07 05:21:04 PM PDT 24
Peak memory 199992 kb
Host smart-c8fe8dd8-16c2-4a7e-bd88-f8b088f1734d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519510355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2519510355
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.235017599
Short name T1061
Test name
Test status
Simulation time 1481412915 ps
CPU time 6.03 seconds
Started Jul 07 05:13:48 PM PDT 24
Finished Jul 07 05:13:55 PM PDT 24
Peak memory 197944 kb
Host smart-c8c1d28b-a538-40dc-a7b6-f13a66e0556a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235017599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.235017599
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.40523161
Short name T1161
Test name
Test status
Simulation time 84183546226 ps
CPU time 121.25 seconds
Started Jul 07 05:13:40 PM PDT 24
Finished Jul 07 05:15:42 PM PDT 24
Peak memory 199988 kb
Host smart-d8138eb7-7ce4-498b-9232-89fd210b5b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40523161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.40523161
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3506356599
Short name T26
Test name
Test status
Simulation time 2150938891 ps
CPU time 2.15 seconds
Started Jul 07 05:13:37 PM PDT 24
Finished Jul 07 05:13:39 PM PDT 24
Peak memory 195476 kb
Host smart-d49e1721-d342-4cc8-980c-1595bd5bdf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506356599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3506356599
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1837095048
Short name T695
Test name
Test status
Simulation time 5768803354 ps
CPU time 7.72 seconds
Started Jul 07 05:13:36 PM PDT 24
Finished Jul 07 05:13:44 PM PDT 24
Peak memory 199908 kb
Host smart-ea443519-25d5-43f6-a59a-795a4ca7ebd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837095048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1837095048
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1784974245
Short name T903
Test name
Test status
Simulation time 174656545239 ps
CPU time 305.84 seconds
Started Jul 07 05:13:50 PM PDT 24
Finished Jul 07 05:18:56 PM PDT 24
Peak memory 208188 kb
Host smart-a98c80a9-6f39-4db0-bdb6-fbb0b096d0d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784974245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1784974245
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1620726404
Short name T65
Test name
Test status
Simulation time 19243884266 ps
CPU time 177.88 seconds
Started Jul 07 05:13:40 PM PDT 24
Finished Jul 07 05:16:38 PM PDT 24
Peak memory 215764 kb
Host smart-c3d56269-0d1b-403e-9731-ef4b8b9369e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620726404 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1620726404
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.4062902076
Short name T348
Test name
Test status
Simulation time 2409019643 ps
CPU time 1.93 seconds
Started Jul 07 05:13:48 PM PDT 24
Finished Jul 07 05:13:51 PM PDT 24
Peak memory 199716 kb
Host smart-bd5f1e93-79cc-4a8e-b81c-960d5c62b392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062902076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.4062902076
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3104660790
Short name T751
Test name
Test status
Simulation time 127836128766 ps
CPU time 24.72 seconds
Started Jul 07 05:13:36 PM PDT 24
Finished Jul 07 05:14:01 PM PDT 24
Peak memory 200256 kb
Host smart-3b199af7-e8c3-4ac6-9cb1-0b9880b74c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104660790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3104660790
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3452693821
Short name T14
Test name
Test status
Simulation time 141218945489 ps
CPU time 58.11 seconds
Started Jul 07 05:17:43 PM PDT 24
Finished Jul 07 05:18:41 PM PDT 24
Peak memory 199844 kb
Host smart-a19a95a6-74cb-4bfd-9158-8ae921735bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452693821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3452693821
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3908841209
Short name T762
Test name
Test status
Simulation time 147782328396 ps
CPU time 28.44 seconds
Started Jul 07 05:17:44 PM PDT 24
Finished Jul 07 05:18:13 PM PDT 24
Peak memory 199408 kb
Host smart-4eb57c68-ad92-4e0a-8ddd-2ed19f78c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908841209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3908841209
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.805211829
Short name T512
Test name
Test status
Simulation time 25451105474 ps
CPU time 21.3 seconds
Started Jul 07 05:17:46 PM PDT 24
Finished Jul 07 05:18:07 PM PDT 24
Peak memory 199936 kb
Host smart-8b61f827-1a6b-4700-8de2-f61f6f0d4fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805211829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.805211829
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2470028499
Short name T715
Test name
Test status
Simulation time 25342694014 ps
CPU time 10.37 seconds
Started Jul 07 05:17:46 PM PDT 24
Finished Jul 07 05:17:57 PM PDT 24
Peak memory 199716 kb
Host smart-47c501f7-5532-4f5e-8c1f-f296452ddf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470028499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2470028499
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2340127140
Short name T795
Test name
Test status
Simulation time 21247513359 ps
CPU time 32.89 seconds
Started Jul 07 05:17:44 PM PDT 24
Finished Jul 07 05:18:17 PM PDT 24
Peak memory 199980 kb
Host smart-d8712160-5cc3-473f-b92d-0e712bdcfa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340127140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2340127140
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1638501294
Short name T490
Test name
Test status
Simulation time 37178333661 ps
CPU time 29.17 seconds
Started Jul 07 05:17:43 PM PDT 24
Finished Jul 07 05:18:13 PM PDT 24
Peak memory 199868 kb
Host smart-9d35ce27-483d-46f1-89d1-d413f55d9251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638501294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1638501294
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3855592730
Short name T299
Test name
Test status
Simulation time 66516377394 ps
CPU time 111.96 seconds
Started Jul 07 05:17:50 PM PDT 24
Finished Jul 07 05:19:42 PM PDT 24
Peak memory 199952 kb
Host smart-72cd1eac-4705-4257-a0b0-179f22da34dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855592730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3855592730
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1562091775
Short name T1076
Test name
Test status
Simulation time 127757039949 ps
CPU time 27.59 seconds
Started Jul 07 05:17:45 PM PDT 24
Finished Jul 07 05:18:13 PM PDT 24
Peak memory 199948 kb
Host smart-366ee24e-d8a5-4b10-8f81-d3c01e683934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562091775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1562091775
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2815029067
Short name T633
Test name
Test status
Simulation time 29416567140 ps
CPU time 46.21 seconds
Started Jul 07 05:17:46 PM PDT 24
Finished Jul 07 05:18:33 PM PDT 24
Peak memory 199888 kb
Host smart-96e568fc-f683-4e3a-8fa7-ca44ea345864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815029067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2815029067
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.821979729
Short name T366
Test name
Test status
Simulation time 27247153 ps
CPU time 0.56 seconds
Started Jul 07 05:13:43 PM PDT 24
Finished Jul 07 05:13:44 PM PDT 24
Peak memory 195300 kb
Host smart-a84780a4-de79-467f-8f40-464b09aa7957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821979729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.821979729
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2613658302
Short name T363
Test name
Test status
Simulation time 197866837612 ps
CPU time 24.31 seconds
Started Jul 07 05:13:41 PM PDT 24
Finished Jul 07 05:14:06 PM PDT 24
Peak memory 199868 kb
Host smart-fde5a70c-8789-49ed-84de-a75af78366f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613658302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2613658302
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2530095808
Short name T271
Test name
Test status
Simulation time 9565516647 ps
CPU time 14.31 seconds
Started Jul 07 05:13:41 PM PDT 24
Finished Jul 07 05:13:55 PM PDT 24
Peak memory 199404 kb
Host smart-44a76c27-9595-4b34-967a-9bc6fa5d23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530095808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2530095808
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3926711052
Short name T194
Test name
Test status
Simulation time 59330385987 ps
CPU time 29.42 seconds
Started Jul 07 05:13:44 PM PDT 24
Finished Jul 07 05:14:14 PM PDT 24
Peak memory 199936 kb
Host smart-1575a26a-3af0-4787-a51d-a8315a8ad8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926711052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3926711052
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1211641971
Short name T411
Test name
Test status
Simulation time 40621459417 ps
CPU time 81.97 seconds
Started Jul 07 05:13:43 PM PDT 24
Finished Jul 07 05:15:06 PM PDT 24
Peak memory 199888 kb
Host smart-5a6a1430-e59a-4142-be3d-7886cf6e537b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211641971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1211641971
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2321252543
Short name T280
Test name
Test status
Simulation time 142178294315 ps
CPU time 1019.5 seconds
Started Jul 07 05:13:44 PM PDT 24
Finished Jul 07 05:30:44 PM PDT 24
Peak memory 199788 kb
Host smart-abe77c2a-e64c-4642-9ade-de1c25f1963a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321252543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2321252543
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1008858230
Short name T674
Test name
Test status
Simulation time 11804356602 ps
CPU time 5.69 seconds
Started Jul 07 05:13:42 PM PDT 24
Finished Jul 07 05:13:48 PM PDT 24
Peak memory 199656 kb
Host smart-8315d1b3-6ade-4e4b-9890-0a8f2f3abcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008858230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1008858230
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3176840800
Short name T864
Test name
Test status
Simulation time 97652794852 ps
CPU time 51.7 seconds
Started Jul 07 05:13:43 PM PDT 24
Finished Jul 07 05:14:35 PM PDT 24
Peak memory 208304 kb
Host smart-9d851a25-e328-4a9a-b5f8-0aa0e9ea994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176840800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3176840800
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.608786282
Short name T1017
Test name
Test status
Simulation time 9629043099 ps
CPU time 455.92 seconds
Started Jul 07 05:13:42 PM PDT 24
Finished Jul 07 05:21:19 PM PDT 24
Peak memory 199904 kb
Host smart-fae8adcf-f68f-41bf-8003-eadd6b46d869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=608786282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.608786282
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2502319188
Short name T433
Test name
Test status
Simulation time 5905009812 ps
CPU time 16.8 seconds
Started Jul 07 05:13:41 PM PDT 24
Finished Jul 07 05:13:58 PM PDT 24
Peak memory 198136 kb
Host smart-1d98e2c6-35ae-4181-8488-30a1a2d33f8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2502319188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2502319188
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1033362856
Short name T1034
Test name
Test status
Simulation time 56881879857 ps
CPU time 134.63 seconds
Started Jul 07 05:13:49 PM PDT 24
Finished Jul 07 05:16:04 PM PDT 24
Peak memory 199812 kb
Host smart-04a60970-5979-46c5-950a-b3b9caaf5f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033362856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1033362856
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.599882040
Short name T997
Test name
Test status
Simulation time 5736564294 ps
CPU time 1.92 seconds
Started Jul 07 05:13:46 PM PDT 24
Finished Jul 07 05:13:49 PM PDT 24
Peak memory 196216 kb
Host smart-b68556db-4376-4fb5-84e7-99911903b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599882040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.599882040
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1662107680
Short name T419
Test name
Test status
Simulation time 978694468 ps
CPU time 1.51 seconds
Started Jul 07 05:13:38 PM PDT 24
Finished Jul 07 05:13:40 PM PDT 24
Peak memory 198696 kb
Host smart-94b96bfa-5c48-422c-8e47-d61c5301d601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662107680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1662107680
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3454110429
Short name T818
Test name
Test status
Simulation time 210989684621 ps
CPU time 927.05 seconds
Started Jul 07 05:13:48 PM PDT 24
Finished Jul 07 05:29:16 PM PDT 24
Peak memory 199784 kb
Host smart-cc479b9b-dc89-4031-a86f-36e1a85dae1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454110429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3454110429
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2061204516
Short name T529
Test name
Test status
Simulation time 21903412228 ps
CPU time 265.33 seconds
Started Jul 07 05:13:43 PM PDT 24
Finished Jul 07 05:18:08 PM PDT 24
Peak memory 215980 kb
Host smart-aa01e4e5-7d00-4a43-adef-6e4435b80b41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061204516 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2061204516
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1977398513
Short name T973
Test name
Test status
Simulation time 1097980809 ps
CPU time 4.15 seconds
Started Jul 07 05:13:49 PM PDT 24
Finished Jul 07 05:13:54 PM PDT 24
Peak memory 198100 kb
Host smart-e94e9767-1fff-4851-96a8-ec6dccf2e9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977398513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1977398513
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2324565722
Short name T487
Test name
Test status
Simulation time 26275037312 ps
CPU time 23.63 seconds
Started Jul 07 05:13:43 PM PDT 24
Finished Jul 07 05:14:06 PM PDT 24
Peak memory 199848 kb
Host smart-77e45257-39be-40ed-8b52-6b8e0fe08b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324565722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2324565722
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3226462593
Short name T604
Test name
Test status
Simulation time 72545366573 ps
CPU time 156.35 seconds
Started Jul 07 05:17:48 PM PDT 24
Finished Jul 07 05:20:25 PM PDT 24
Peak memory 199944 kb
Host smart-644952a6-178e-4992-ba9a-1880839286d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226462593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3226462593
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1346590172
Short name T154
Test name
Test status
Simulation time 25521497047 ps
CPU time 42.31 seconds
Started Jul 07 05:17:52 PM PDT 24
Finished Jul 07 05:18:35 PM PDT 24
Peak memory 199884 kb
Host smart-df565442-1951-4605-9f05-b14be54e8280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346590172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1346590172
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3886887013
Short name T593
Test name
Test status
Simulation time 7497550680 ps
CPU time 11.56 seconds
Started Jul 07 05:17:48 PM PDT 24
Finished Jul 07 05:18:00 PM PDT 24
Peak memory 199980 kb
Host smart-565c6c5f-0322-4d74-9893-d86a2164b38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886887013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3886887013
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3130044176
Short name T754
Test name
Test status
Simulation time 107700123829 ps
CPU time 46.46 seconds
Started Jul 07 05:17:48 PM PDT 24
Finished Jul 07 05:18:35 PM PDT 24
Peak memory 199768 kb
Host smart-260ded0e-0e62-49ad-840e-f8a42aafea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130044176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3130044176
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4246572429
Short name T900
Test name
Test status
Simulation time 15698570667 ps
CPU time 23.22 seconds
Started Jul 07 05:17:48 PM PDT 24
Finished Jul 07 05:18:12 PM PDT 24
Peak memory 199960 kb
Host smart-7ecec25d-7eb4-42c4-862e-5da1ef0b3d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246572429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4246572429
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2043503693
Short name T199
Test name
Test status
Simulation time 19400957860 ps
CPU time 37.23 seconds
Started Jul 07 05:17:46 PM PDT 24
Finished Jul 07 05:18:23 PM PDT 24
Peak memory 199916 kb
Host smart-26c4c609-4412-4ab0-a016-e9255b655f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043503693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2043503693
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1738136921
Short name T909
Test name
Test status
Simulation time 7002355475 ps
CPU time 11.23 seconds
Started Jul 07 05:17:47 PM PDT 24
Finished Jul 07 05:17:58 PM PDT 24
Peak memory 199920 kb
Host smart-a70f976f-ff8e-4a13-a70f-403e7b7917de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738136921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1738136921
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.817932299
Short name T745
Test name
Test status
Simulation time 36780190456 ps
CPU time 67.71 seconds
Started Jul 07 05:17:49 PM PDT 24
Finished Jul 07 05:18:57 PM PDT 24
Peak memory 199980 kb
Host smart-b374364f-c449-4167-b92d-ca77a83e0986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817932299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.817932299
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2370033036
Short name T527
Test name
Test status
Simulation time 34180192871 ps
CPU time 63.86 seconds
Started Jul 07 05:17:49 PM PDT 24
Finished Jul 07 05:18:54 PM PDT 24
Peak memory 199968 kb
Host smart-51c35976-4468-4d46-9f5b-dd1de0c6736d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370033036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2370033036
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2401233239
Short name T960
Test name
Test status
Simulation time 134435727552 ps
CPU time 52.63 seconds
Started Jul 07 05:17:52 PM PDT 24
Finished Jul 07 05:18:45 PM PDT 24
Peak memory 199860 kb
Host smart-c9f4bc43-e6e2-407a-bac5-6c6ae0641af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401233239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2401233239
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3724953895
Short name T985
Test name
Test status
Simulation time 21688115 ps
CPU time 0.54 seconds
Started Jul 07 05:13:46 PM PDT 24
Finished Jul 07 05:13:47 PM PDT 24
Peak memory 195508 kb
Host smart-3b9df4f7-c684-49d2-8a44-307d93a4fa02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724953895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3724953895
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1102914103
Short name T1156
Test name
Test status
Simulation time 108759477522 ps
CPU time 56.88 seconds
Started Jul 07 05:13:48 PM PDT 24
Finished Jul 07 05:14:45 PM PDT 24
Peak memory 199928 kb
Host smart-00e5969f-760d-43b2-b22b-6c8cf914f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102914103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1102914103
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.297132062
Short name T513
Test name
Test status
Simulation time 94018729019 ps
CPU time 220.64 seconds
Started Jul 07 05:13:49 PM PDT 24
Finished Jul 07 05:17:30 PM PDT 24
Peak memory 199908 kb
Host smart-39cb4a7b-609c-406e-94a6-66200f84debb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297132062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.297132062
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.3880982149
Short name T861
Test name
Test status
Simulation time 355277426942 ps
CPU time 67.67 seconds
Started Jul 07 05:13:48 PM PDT 24
Finished Jul 07 05:14:56 PM PDT 24
Peak memory 197992 kb
Host smart-115e04f5-787e-4c68-aab9-8d3131bce541
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880982149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3880982149
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.676813066
Short name T431
Test name
Test status
Simulation time 64365361980 ps
CPU time 361.37 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:19:49 PM PDT 24
Peak memory 199964 kb
Host smart-488ebb2d-7cc1-4ea4-85cf-2041f3ff0cd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676813066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.676813066
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3223430616
Short name T327
Test name
Test status
Simulation time 57446226 ps
CPU time 0.69 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:13:49 PM PDT 24
Peak memory 195816 kb
Host smart-1fecff67-fc59-452c-9006-e3e25df18d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223430616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3223430616
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3290301246
Short name T55
Test name
Test status
Simulation time 236818831210 ps
CPU time 86.12 seconds
Started Jul 07 05:13:49 PM PDT 24
Finished Jul 07 05:15:16 PM PDT 24
Peak memory 208192 kb
Host smart-36890714-981e-47fe-887f-ce3c66ad493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290301246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3290301246
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.906897127
Short name T880
Test name
Test status
Simulation time 12729463609 ps
CPU time 296.8 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:18:45 PM PDT 24
Peak memory 199668 kb
Host smart-df854519-709c-4bb6-a595-d69f03f4ae13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906897127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.906897127
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.874763145
Short name T542
Test name
Test status
Simulation time 2417507208 ps
CPU time 4.54 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:13:52 PM PDT 24
Peak memory 199160 kb
Host smart-37235791-30bf-4b32-8c58-94fb817a7ec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874763145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.874763145
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.181741160
Short name T605
Test name
Test status
Simulation time 143447219921 ps
CPU time 38.61 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:14:25 PM PDT 24
Peak memory 199684 kb
Host smart-4ddd43ab-b873-461c-b4d0-97a626dbfb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181741160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.181741160
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2574331516
Short name T371
Test name
Test status
Simulation time 2816568597 ps
CPU time 1.37 seconds
Started Jul 07 05:13:50 PM PDT 24
Finished Jul 07 05:13:51 PM PDT 24
Peak memory 195888 kb
Host smart-9043ac33-f783-4429-8e90-29297015d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574331516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2574331516
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3772114819
Short name T498
Test name
Test status
Simulation time 6089265863 ps
CPU time 5.73 seconds
Started Jul 07 05:13:49 PM PDT 24
Finished Jul 07 05:13:55 PM PDT 24
Peak memory 199792 kb
Host smart-8742dfe8-c7e8-44ad-b64d-5e5f734bbc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772114819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3772114819
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.498854246
Short name T516
Test name
Test status
Simulation time 20790536279 ps
CPU time 448.21 seconds
Started Jul 07 05:13:46 PM PDT 24
Finished Jul 07 05:21:15 PM PDT 24
Peak memory 212848 kb
Host smart-57703849-bbbb-4c39-a5ad-a8b56ab39d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498854246 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.498854246
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4270306649
Short name T364
Test name
Test status
Simulation time 1962308444 ps
CPU time 2.24 seconds
Started Jul 07 05:13:50 PM PDT 24
Finished Jul 07 05:13:53 PM PDT 24
Peak memory 198752 kb
Host smart-d85eb915-4147-49e8-8b78-7f621f2bf36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270306649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4270306649
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2061437273
Short name T262
Test name
Test status
Simulation time 67841845363 ps
CPU time 197.17 seconds
Started Jul 07 05:13:51 PM PDT 24
Finished Jul 07 05:17:09 PM PDT 24
Peak memory 199820 kb
Host smart-4da4f9b8-34cd-44a3-8ece-0b67881a7bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061437273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2061437273
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2916847967
Short name T1093
Test name
Test status
Simulation time 9904271104 ps
CPU time 19.18 seconds
Started Jul 07 05:17:49 PM PDT 24
Finished Jul 07 05:18:08 PM PDT 24
Peak memory 199740 kb
Host smart-6795e606-03cd-4451-aba6-5c15e5db61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916847967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2916847967
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3364894453
Short name T238
Test name
Test status
Simulation time 21686182490 ps
CPU time 16.6 seconds
Started Jul 07 05:17:51 PM PDT 24
Finished Jul 07 05:18:08 PM PDT 24
Peak memory 199872 kb
Host smart-bfc2297d-e8cb-4548-a5ec-5e8451e3b651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364894453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3364894453
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3717766341
Short name T404
Test name
Test status
Simulation time 127260671429 ps
CPU time 17.14 seconds
Started Jul 07 05:17:52 PM PDT 24
Finished Jul 07 05:18:10 PM PDT 24
Peak memory 199972 kb
Host smart-05fb916f-f68a-42ed-bee2-808dba76f92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717766341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3717766341
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2531460006
Short name T466
Test name
Test status
Simulation time 108013448439 ps
CPU time 194.76 seconds
Started Jul 07 05:17:53 PM PDT 24
Finished Jul 07 05:21:08 PM PDT 24
Peak memory 199960 kb
Host smart-538c7180-62c5-47c5-96bc-9a8346aec374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531460006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2531460006
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3100776057
Short name T384
Test name
Test status
Simulation time 84237182201 ps
CPU time 31.14 seconds
Started Jul 07 05:17:53 PM PDT 24
Finished Jul 07 05:18:25 PM PDT 24
Peak memory 198884 kb
Host smart-e57fdee1-d5e4-4809-bd1a-3e70f1f3cf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100776057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3100776057
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.313771996
Short name T391
Test name
Test status
Simulation time 109888647135 ps
CPU time 20.95 seconds
Started Jul 07 05:17:51 PM PDT 24
Finished Jul 07 05:18:12 PM PDT 24
Peak memory 199848 kb
Host smart-e579eb33-4122-4970-8500-b5b7dadda737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313771996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.313771996
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.375761012
Short name T634
Test name
Test status
Simulation time 183084798717 ps
CPU time 76.28 seconds
Started Jul 07 05:17:49 PM PDT 24
Finished Jul 07 05:19:06 PM PDT 24
Peak memory 200008 kb
Host smart-2eb47109-41a7-46b8-859d-e4c1ba47d151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375761012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.375761012
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3194541455
Short name T906
Test name
Test status
Simulation time 34561963690 ps
CPU time 52.58 seconds
Started Jul 07 05:17:52 PM PDT 24
Finished Jul 07 05:18:45 PM PDT 24
Peak memory 199916 kb
Host smart-6de5ed33-6550-4c57-bd4f-9b399a9efbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194541455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3194541455
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3988425586
Short name T855
Test name
Test status
Simulation time 30864380971 ps
CPU time 21.58 seconds
Started Jul 07 05:17:51 PM PDT 24
Finished Jul 07 05:18:13 PM PDT 24
Peak memory 199896 kb
Host smart-6942f12f-4bf2-4737-bd00-19ab4dce20ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988425586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3988425586
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1147474083
Short name T345
Test name
Test status
Simulation time 25012880 ps
CPU time 0.58 seconds
Started Jul 07 05:13:51 PM PDT 24
Finished Jul 07 05:13:52 PM PDT 24
Peak memory 194948 kb
Host smart-f938fc0d-6cca-44f9-8f08-b193bf917f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147474083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1147474083
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.985112212
Short name T1071
Test name
Test status
Simulation time 161690648482 ps
CPU time 62.3 seconds
Started Jul 07 05:13:51 PM PDT 24
Finished Jul 07 05:14:54 PM PDT 24
Peak memory 199924 kb
Host smart-a5c708fa-001d-4f61-9329-527470db7367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985112212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.985112212
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2980755555
Short name T897
Test name
Test status
Simulation time 27720701885 ps
CPU time 11.35 seconds
Started Jul 07 05:13:51 PM PDT 24
Finished Jul 07 05:14:03 PM PDT 24
Peak memory 199328 kb
Host smart-7e2765d1-3700-43c5-bead-2b8910da6ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980755555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2980755555
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2565913389
Short name T1154
Test name
Test status
Simulation time 43764699273 ps
CPU time 37.45 seconds
Started Jul 07 05:13:54 PM PDT 24
Finished Jul 07 05:14:32 PM PDT 24
Peak memory 199932 kb
Host smart-bd05e5b4-cc34-4b2e-9a17-5bcc3b08653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565913389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2565913389
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4162706314
Short name T1174
Test name
Test status
Simulation time 72131386880 ps
CPU time 102.47 seconds
Started Jul 07 05:13:54 PM PDT 24
Finished Jul 07 05:15:37 PM PDT 24
Peak memory 199896 kb
Host smart-3d5f15dc-bcd2-4844-8949-2bfb5a01220d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162706314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4162706314
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.146523858
Short name T499
Test name
Test status
Simulation time 91935701553 ps
CPU time 185.16 seconds
Started Jul 07 05:13:58 PM PDT 24
Finished Jul 07 05:17:04 PM PDT 24
Peak memory 199732 kb
Host smart-e4c788f3-7a5c-4d51-895d-2c0ae3583e52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146523858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.146523858
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3651760676
Short name T329
Test name
Test status
Simulation time 9646649593 ps
CPU time 8.05 seconds
Started Jul 07 05:13:52 PM PDT 24
Finished Jul 07 05:14:01 PM PDT 24
Peak memory 199564 kb
Host smart-7339ce21-5714-4c25-a9f0-b56b31e4f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651760676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3651760676
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1462826132
Short name T866
Test name
Test status
Simulation time 63933804963 ps
CPU time 108.76 seconds
Started Jul 07 05:13:53 PM PDT 24
Finished Jul 07 05:15:42 PM PDT 24
Peak memory 200056 kb
Host smart-a6dd2e20-f3e1-465a-883e-9d08c0e11e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462826132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1462826132
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.4260470400
Short name T434
Test name
Test status
Simulation time 11126995095 ps
CPU time 636.07 seconds
Started Jul 07 05:13:50 PM PDT 24
Finished Jul 07 05:24:28 PM PDT 24
Peak memory 199896 kb
Host smart-d86178ee-c40d-4808-9183-381dd72c2268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260470400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4260470400
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.620605533
Short name T1173
Test name
Test status
Simulation time 4501174124 ps
CPU time 9.19 seconds
Started Jul 07 05:13:52 PM PDT 24
Finished Jul 07 05:14:01 PM PDT 24
Peak memory 199164 kb
Host smart-1f8490cd-2ef5-4ca5-a72a-bdbe00222b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620605533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.620605533
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3691240834
Short name T524
Test name
Test status
Simulation time 172059418738 ps
CPU time 22.03 seconds
Started Jul 07 05:13:52 PM PDT 24
Finished Jul 07 05:14:14 PM PDT 24
Peak memory 199752 kb
Host smart-ff26dc56-88d5-4bc8-956c-36058828bb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691240834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3691240834
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1846465178
Short name T704
Test name
Test status
Simulation time 45166748623 ps
CPU time 63.24 seconds
Started Jul 07 05:13:52 PM PDT 24
Finished Jul 07 05:14:55 PM PDT 24
Peak memory 195732 kb
Host smart-74aa34f2-05f9-491d-b79c-f57d0ed42394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846465178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1846465178
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.816055636
Short name T378
Test name
Test status
Simulation time 651917208 ps
CPU time 2.64 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:13:50 PM PDT 24
Peak memory 198696 kb
Host smart-1d20896c-1e2f-4704-9e71-b59a4f6ffae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816055636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.816055636
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3898213298
Short name T814
Test name
Test status
Simulation time 127372597134 ps
CPU time 103.85 seconds
Started Jul 07 05:13:53 PM PDT 24
Finished Jul 07 05:15:37 PM PDT 24
Peak memory 199864 kb
Host smart-33397dd5-76bc-4dcb-8413-d975fcf1e4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898213298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3898213298
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.4122235321
Short name T894
Test name
Test status
Simulation time 90712530089 ps
CPU time 1172.22 seconds
Started Jul 07 05:13:51 PM PDT 24
Finished Jul 07 05:33:24 PM PDT 24
Peak memory 224836 kb
Host smart-884ae382-ee67-412b-bd7f-bc0f244aa5be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122235321 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4122235321
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.274389675
Short name T748
Test name
Test status
Simulation time 1031721538 ps
CPU time 1.52 seconds
Started Jul 07 05:13:58 PM PDT 24
Finished Jul 07 05:14:01 PM PDT 24
Peak memory 198524 kb
Host smart-945f5a6a-f072-4517-b22d-8f45da3a3254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274389675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.274389675
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1554521625
Short name T590
Test name
Test status
Simulation time 57992902203 ps
CPU time 109.92 seconds
Started Jul 07 05:13:47 PM PDT 24
Finished Jul 07 05:15:38 PM PDT 24
Peak memory 199916 kb
Host smart-14124057-2edc-4781-82fd-1e3570e04be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554521625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1554521625
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1810698299
Short name T965
Test name
Test status
Simulation time 24741318765 ps
CPU time 44.16 seconds
Started Jul 07 05:17:50 PM PDT 24
Finished Jul 07 05:18:35 PM PDT 24
Peak memory 199792 kb
Host smart-4e3c4e2a-41a7-4b91-8ea3-ea6330d87173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810698299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1810698299
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.109684298
Short name T417
Test name
Test status
Simulation time 118695916942 ps
CPU time 297.6 seconds
Started Jul 07 05:17:52 PM PDT 24
Finished Jul 07 05:22:50 PM PDT 24
Peak memory 199840 kb
Host smart-97665abc-70f7-4d8a-9cf6-fb357eec9134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109684298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.109684298
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2303789500
Short name T1087
Test name
Test status
Simulation time 33253365081 ps
CPU time 57.75 seconds
Started Jul 07 05:17:53 PM PDT 24
Finished Jul 07 05:18:52 PM PDT 24
Peak memory 199912 kb
Host smart-5bcd1abf-bfda-4c75-a9ea-29834aed7270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303789500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2303789500
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2271181479
Short name T858
Test name
Test status
Simulation time 29675161174 ps
CPU time 12.49 seconds
Started Jul 07 05:17:57 PM PDT 24
Finished Jul 07 05:18:10 PM PDT 24
Peak memory 199940 kb
Host smart-fd6ddf97-3a91-41e5-a5d5-8eeb0c38699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271181479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2271181479
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1700611126
Short name T999
Test name
Test status
Simulation time 28195379421 ps
CPU time 42.72 seconds
Started Jul 07 05:17:56 PM PDT 24
Finished Jul 07 05:18:39 PM PDT 24
Peak memory 199920 kb
Host smart-41b396e0-23fe-438e-8226-0d142f13f51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700611126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1700611126
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3548896944
Short name T520
Test name
Test status
Simulation time 130770736321 ps
CPU time 67 seconds
Started Jul 07 05:17:56 PM PDT 24
Finished Jul 07 05:19:03 PM PDT 24
Peak memory 199900 kb
Host smart-adbb4160-f599-4ed5-88ac-60c6ba1ef5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548896944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3548896944
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3825074211
Short name T347
Test name
Test status
Simulation time 114519186425 ps
CPU time 40.13 seconds
Started Jul 07 05:17:57 PM PDT 24
Finished Jul 07 05:18:37 PM PDT 24
Peak memory 199856 kb
Host smart-43d5fb0e-9ffc-4596-b96e-cb55d97afd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825074211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3825074211
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4146869764
Short name T911
Test name
Test status
Simulation time 41390769585 ps
CPU time 34.9 seconds
Started Jul 07 05:17:55 PM PDT 24
Finished Jul 07 05:18:30 PM PDT 24
Peak memory 199880 kb
Host smart-535ec8e6-0f67-4cfe-addd-4b92f9fd117e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146869764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4146869764
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3412713607
Short name T42
Test name
Test status
Simulation time 30692422704 ps
CPU time 13.44 seconds
Started Jul 07 05:17:56 PM PDT 24
Finished Jul 07 05:18:10 PM PDT 24
Peak memory 199864 kb
Host smart-dedc5654-2bb2-4d97-aaa1-e830ccb68410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412713607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3412713607
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1510836762
Short name T474
Test name
Test status
Simulation time 54773745 ps
CPU time 0.59 seconds
Started Jul 07 05:14:03 PM PDT 24
Finished Jul 07 05:14:04 PM PDT 24
Peak memory 195348 kb
Host smart-5c002345-071f-4a1d-a0ff-d45d5f9ed299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510836762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1510836762
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3926119298
Short name T126
Test name
Test status
Simulation time 172908726672 ps
CPU time 234.22 seconds
Started Jul 07 05:14:00 PM PDT 24
Finished Jul 07 05:17:55 PM PDT 24
Peak memory 199928 kb
Host smart-74d7fd2f-7ebf-4be0-bb5f-3660d938a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926119298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3926119298
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3009501458
Short name T776
Test name
Test status
Simulation time 27510315533 ps
CPU time 15.2 seconds
Started Jul 07 05:13:58 PM PDT 24
Finished Jul 07 05:14:14 PM PDT 24
Peak memory 199840 kb
Host smart-4be89aa0-8a8c-464f-ab91-893c3cad5bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009501458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3009501458
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3534246780
Short name T244
Test name
Test status
Simulation time 81874118670 ps
CPU time 31.76 seconds
Started Jul 07 05:13:57 PM PDT 24
Finished Jul 07 05:14:30 PM PDT 24
Peak memory 199740 kb
Host smart-6e13d583-57ef-4b9e-94ef-d349010a69d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534246780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3534246780
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3578716985
Short name T256
Test name
Test status
Simulation time 23729902061 ps
CPU time 24.81 seconds
Started Jul 07 05:13:59 PM PDT 24
Finished Jul 07 05:14:24 PM PDT 24
Peak memory 199736 kb
Host smart-b2b23779-c521-4ec8-a258-fa621fb6b4a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578716985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3578716985
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1110795117
Short name T1097
Test name
Test status
Simulation time 80922869175 ps
CPU time 302.1 seconds
Started Jul 07 05:13:59 PM PDT 24
Finished Jul 07 05:19:02 PM PDT 24
Peak memory 199912 kb
Host smart-84e4fdc1-c116-453b-a935-7f24af7a9056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110795117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1110795117
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1120349312
Short name T870
Test name
Test status
Simulation time 3739905550 ps
CPU time 2.58 seconds
Started Jul 07 05:13:56 PM PDT 24
Finished Jul 07 05:13:59 PM PDT 24
Peak memory 196236 kb
Host smart-a2174d66-c26e-47d4-b175-bbfa26ca291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120349312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1120349312
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.292560267
Short name T1049
Test name
Test status
Simulation time 155696032471 ps
CPU time 78.1 seconds
Started Jul 07 05:14:00 PM PDT 24
Finished Jul 07 05:15:18 PM PDT 24
Peak memory 200124 kb
Host smart-85321d13-bb68-4f46-98df-43c9036269b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292560267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.292560267
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2062111361
Short name T478
Test name
Test status
Simulation time 12506556715 ps
CPU time 194.15 seconds
Started Jul 07 05:14:01 PM PDT 24
Finished Jul 07 05:17:16 PM PDT 24
Peak memory 199936 kb
Host smart-c8eba28f-187a-43ba-b899-3954c5ef5661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2062111361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2062111361
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3564487024
Short name T15
Test name
Test status
Simulation time 7138754898 ps
CPU time 55.5 seconds
Started Jul 07 05:13:58 PM PDT 24
Finished Jul 07 05:14:54 PM PDT 24
Peak memory 198824 kb
Host smart-4bb269b4-5fa2-490c-904a-407c640fdc12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564487024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3564487024
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2166600266
Short name T608
Test name
Test status
Simulation time 43602411099 ps
CPU time 17 seconds
Started Jul 07 05:13:56 PM PDT 24
Finished Jul 07 05:14:14 PM PDT 24
Peak memory 199636 kb
Host smart-478392ee-2bce-461b-9b60-e809acd99b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166600266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2166600266
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.527093521
Short name T443
Test name
Test status
Simulation time 3407410120 ps
CPU time 5.81 seconds
Started Jul 07 05:14:01 PM PDT 24
Finished Jul 07 05:14:07 PM PDT 24
Peak memory 195752 kb
Host smart-8f7afb6b-85ee-46ac-bcb4-4d4b54860488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527093521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.527093521
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3061144790
Short name T662
Test name
Test status
Simulation time 428352530 ps
CPU time 2.23 seconds
Started Jul 07 05:14:01 PM PDT 24
Finished Jul 07 05:14:03 PM PDT 24
Peak memory 198872 kb
Host smart-51ca136f-e32d-463f-850f-9fec48e53330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061144790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3061144790
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.96764983
Short name T561
Test name
Test status
Simulation time 259928103692 ps
CPU time 1009.74 seconds
Started Jul 07 05:14:02 PM PDT 24
Finished Jul 07 05:30:52 PM PDT 24
Peak memory 224836 kb
Host smart-827ba550-01eb-4e63-a27f-b7b27c89050e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96764983 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.96764983
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1134549084
Short name T953
Test name
Test status
Simulation time 1696274373 ps
CPU time 2.78 seconds
Started Jul 07 05:13:59 PM PDT 24
Finished Jul 07 05:14:02 PM PDT 24
Peak memory 198288 kb
Host smart-bc5a3463-31a3-4cb9-b72c-c20af91ebe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134549084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1134549084
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1953425015
Short name T806
Test name
Test status
Simulation time 93562322002 ps
CPU time 144.61 seconds
Started Jul 07 05:13:59 PM PDT 24
Finished Jul 07 05:16:24 PM PDT 24
Peak memory 199892 kb
Host smart-33290f53-4d72-40ec-9147-e0fc5217f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953425015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1953425015
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.624517647
Short name T706
Test name
Test status
Simulation time 88686920266 ps
CPU time 51.08 seconds
Started Jul 07 05:17:58 PM PDT 24
Finished Jul 07 05:18:49 PM PDT 24
Peak memory 199908 kb
Host smart-2031c545-dde6-4b1e-bfe3-a64d1e9834cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624517647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.624517647
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1927961131
Short name T1057
Test name
Test status
Simulation time 220498977375 ps
CPU time 42.72 seconds
Started Jul 07 05:18:02 PM PDT 24
Finished Jul 07 05:18:45 PM PDT 24
Peak memory 199900 kb
Host smart-567f27ec-cc73-4882-aac3-b5bfe5b443bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927961131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1927961131
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.803231997
Short name T589
Test name
Test status
Simulation time 82201945293 ps
CPU time 134.69 seconds
Started Jul 07 05:17:58 PM PDT 24
Finished Jul 07 05:20:13 PM PDT 24
Peak memory 199904 kb
Host smart-8604b29c-ce96-4422-b1e5-c40e13252008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803231997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.803231997
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.778497567
Short name T151
Test name
Test status
Simulation time 168609609097 ps
CPU time 121.57 seconds
Started Jul 07 05:18:03 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 199904 kb
Host smart-0bae0b04-ef5f-4a05-b56f-7a00943d38b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778497567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.778497567
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.4167884572
Short name T860
Test name
Test status
Simulation time 17127809093 ps
CPU time 28.46 seconds
Started Jul 07 05:17:59 PM PDT 24
Finished Jul 07 05:18:27 PM PDT 24
Peak memory 199924 kb
Host smart-93373646-f0ff-4d35-935c-ab3efa6d672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167884572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4167884572
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1884332119
Short name T295
Test name
Test status
Simulation time 75176367616 ps
CPU time 62.19 seconds
Started Jul 07 05:18:01 PM PDT 24
Finished Jul 07 05:19:03 PM PDT 24
Peak memory 199808 kb
Host smart-78011afd-0080-4274-abeb-f11540711c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884332119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1884332119
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.873233348
Short name T217
Test name
Test status
Simulation time 138452440751 ps
CPU time 189.72 seconds
Started Jul 07 05:18:07 PM PDT 24
Finished Jul 07 05:21:16 PM PDT 24
Peak memory 199832 kb
Host smart-959b46e5-7ab3-45f6-9b29-d4681e2b8000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873233348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.873233348
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2781869997
Short name T342
Test name
Test status
Simulation time 35199339 ps
CPU time 0.63 seconds
Started Jul 07 05:14:06 PM PDT 24
Finished Jul 07 05:14:07 PM PDT 24
Peak memory 195572 kb
Host smart-9c7f30ea-7d80-401d-ba7b-bc74108c9136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781869997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2781869997
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3929242365
Short name T143
Test name
Test status
Simulation time 156034446868 ps
CPU time 122.68 seconds
Started Jul 07 05:14:02 PM PDT 24
Finished Jul 07 05:16:05 PM PDT 24
Peak memory 199844 kb
Host smart-294087b9-19f7-4622-931a-0a079970d059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929242365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3929242365
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1025392792
Short name T677
Test name
Test status
Simulation time 169545297803 ps
CPU time 29.88 seconds
Started Jul 07 05:14:00 PM PDT 24
Finished Jul 07 05:14:31 PM PDT 24
Peak memory 199484 kb
Host smart-6f304c7e-83f3-450e-84e6-96dc1f4f8224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025392792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1025392792
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.61660198
Short name T632
Test name
Test status
Simulation time 142344293681 ps
CPU time 28.72 seconds
Started Jul 07 05:14:00 PM PDT 24
Finished Jul 07 05:14:30 PM PDT 24
Peak memory 199948 kb
Host smart-381b9583-e7e7-4c46-9c42-929d473d0b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61660198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.61660198
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.644664086
Short name T819
Test name
Test status
Simulation time 100448000357 ps
CPU time 100.77 seconds
Started Jul 07 05:14:01 PM PDT 24
Finished Jul 07 05:15:42 PM PDT 24
Peak memory 199800 kb
Host smart-7cee0e01-8c76-44a5-b57f-ed6dd46eebc2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644664086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.644664086
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.990802693
Short name T453
Test name
Test status
Simulation time 308968896329 ps
CPU time 448.32 seconds
Started Jul 07 05:14:06 PM PDT 24
Finished Jul 07 05:21:34 PM PDT 24
Peak memory 199960 kb
Host smart-d07ce019-0424-4949-8fe5-4eaa17d2f94e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990802693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.990802693
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.59024904
Short name T956
Test name
Test status
Simulation time 6788236993 ps
CPU time 15.4 seconds
Started Jul 07 05:14:05 PM PDT 24
Finished Jul 07 05:14:20 PM PDT 24
Peak memory 199912 kb
Host smart-302759d2-991e-4ba9-8707-6d0792c8774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59024904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.59024904
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1107862229
Short name T564
Test name
Test status
Simulation time 102751419128 ps
CPU time 199.52 seconds
Started Jul 07 05:13:59 PM PDT 24
Finished Jul 07 05:17:20 PM PDT 24
Peak memory 199272 kb
Host smart-e12cd681-d708-418a-bee6-13513c905d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107862229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1107862229
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1357146147
Short name T1022
Test name
Test status
Simulation time 8946042461 ps
CPU time 70.58 seconds
Started Jul 07 05:14:03 PM PDT 24
Finished Jul 07 05:15:14 PM PDT 24
Peak memory 199836 kb
Host smart-6600083e-abdd-440e-b6ce-588674313d6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357146147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1357146147
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3522086967
Short name T361
Test name
Test status
Simulation time 3190097633 ps
CPU time 22.67 seconds
Started Jul 07 05:13:59 PM PDT 24
Finished Jul 07 05:14:23 PM PDT 24
Peak memory 198408 kb
Host smart-9fd324e0-e21b-4dac-af53-96b05af82103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522086967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3522086967
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3030399998
Short name T763
Test name
Test status
Simulation time 43696736950 ps
CPU time 15.58 seconds
Started Jul 07 05:14:02 PM PDT 24
Finished Jul 07 05:14:18 PM PDT 24
Peak memory 199924 kb
Host smart-6d8aa6a0-1bf6-4a12-a036-9a01fefe9e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030399998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3030399998
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2960805442
Short name T586
Test name
Test status
Simulation time 2574720716 ps
CPU time 4.54 seconds
Started Jul 07 05:13:59 PM PDT 24
Finished Jul 07 05:14:05 PM PDT 24
Peak memory 196420 kb
Host smart-4b96cd5f-c36f-43c4-bcb5-b677348575d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960805442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2960805442
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1008818658
Short name T278
Test name
Test status
Simulation time 531404692 ps
CPU time 2.24 seconds
Started Jul 07 05:13:59 PM PDT 24
Finished Jul 07 05:14:02 PM PDT 24
Peak memory 199680 kb
Host smart-d27f0a0d-5dbc-492f-bbdb-127821b8fb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008818658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1008818658
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1034287210
Short name T666
Test name
Test status
Simulation time 391549348716 ps
CPU time 326.37 seconds
Started Jul 07 05:14:05 PM PDT 24
Finished Jul 07 05:19:32 PM PDT 24
Peak memory 199952 kb
Host smart-f236ea31-8af7-480e-8e20-947b04c5ffec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034287210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1034287210
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2542652807
Short name T917
Test name
Test status
Simulation time 38494217887 ps
CPU time 184.89 seconds
Started Jul 07 05:14:04 PM PDT 24
Finished Jul 07 05:17:09 PM PDT 24
Peak memory 216412 kb
Host smart-dd6c4354-0ab4-4846-aeb7-0e70e8803c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542652807 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2542652807
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2640667215
Short name T1145
Test name
Test status
Simulation time 587849172 ps
CPU time 2.08 seconds
Started Jul 07 05:14:02 PM PDT 24
Finished Jul 07 05:14:04 PM PDT 24
Peak memory 198768 kb
Host smart-597344c6-f7a7-4c38-8530-bf6c80a46399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640667215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2640667215
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.4015385650
Short name T651
Test name
Test status
Simulation time 105040630723 ps
CPU time 22.29 seconds
Started Jul 07 05:14:02 PM PDT 24
Finished Jul 07 05:14:25 PM PDT 24
Peak memory 199876 kb
Host smart-8ec2f3d8-f37c-43a8-b53f-dfef8474014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015385650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4015385650
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4000405536
Short name T324
Test name
Test status
Simulation time 45340211353 ps
CPU time 16.36 seconds
Started Jul 07 05:18:07 PM PDT 24
Finished Jul 07 05:18:23 PM PDT 24
Peak memory 199508 kb
Host smart-0d005328-bdf2-4c38-8295-63358ff2143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000405536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4000405536
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.721828719
Short name T610
Test name
Test status
Simulation time 200166478376 ps
CPU time 82.98 seconds
Started Jul 07 05:18:09 PM PDT 24
Finished Jul 07 05:19:33 PM PDT 24
Peak memory 199996 kb
Host smart-366c4822-2817-4156-a52f-91ecda0897e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721828719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.721828719
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.743350824
Short name T241
Test name
Test status
Simulation time 26217725632 ps
CPU time 48.06 seconds
Started Jul 07 05:18:12 PM PDT 24
Finished Jul 07 05:19:00 PM PDT 24
Peak memory 199980 kb
Host smart-ef9358e5-df05-4e7b-ab34-914332511765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743350824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.743350824
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1765643100
Short name T699
Test name
Test status
Simulation time 57253171937 ps
CPU time 22.57 seconds
Started Jul 07 05:18:08 PM PDT 24
Finished Jul 07 05:18:31 PM PDT 24
Peak memory 199608 kb
Host smart-3d421bba-a3be-4d74-9013-a7c7dc455c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765643100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1765643100
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2587530701
Short name T205
Test name
Test status
Simulation time 21950122873 ps
CPU time 14.83 seconds
Started Jul 07 05:18:11 PM PDT 24
Finished Jul 07 05:18:26 PM PDT 24
Peak memory 198848 kb
Host smart-791237d6-5b31-472c-b7a9-2a5f55f3eeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587530701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2587530701
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2888944028
Short name T874
Test name
Test status
Simulation time 35225141678 ps
CPU time 77.57 seconds
Started Jul 07 05:18:11 PM PDT 24
Finished Jul 07 05:19:30 PM PDT 24
Peak memory 199928 kb
Host smart-23509ad8-f73c-40c5-b625-422fb1ebd190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888944028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2888944028
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3143910399
Short name T980
Test name
Test status
Simulation time 33024254398 ps
CPU time 20.12 seconds
Started Jul 07 05:18:10 PM PDT 24
Finished Jul 07 05:18:30 PM PDT 24
Peak memory 199888 kb
Host smart-24568a4f-f7a0-452d-82b9-80fb0f2a01b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143910399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3143910399
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2791254662
Short name T867
Test name
Test status
Simulation time 184878569963 ps
CPU time 145.66 seconds
Started Jul 07 05:18:08 PM PDT 24
Finished Jul 07 05:20:34 PM PDT 24
Peak memory 199908 kb
Host smart-32cebe78-040d-41fc-a2c7-bdc0e71d0de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791254662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2791254662
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1548347658
Short name T636
Test name
Test status
Simulation time 11708791 ps
CPU time 0.56 seconds
Started Jul 07 05:14:10 PM PDT 24
Finished Jul 07 05:14:11 PM PDT 24
Peak memory 195204 kb
Host smart-37e9a785-10ad-4d55-85ff-a7e4566a213f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548347658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1548347658
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3909741559
Short name T1012
Test name
Test status
Simulation time 35914463815 ps
CPU time 49.68 seconds
Started Jul 07 05:14:03 PM PDT 24
Finished Jul 07 05:14:54 PM PDT 24
Peak memory 199880 kb
Host smart-91e4038c-a443-4ae6-adc6-7a7758908524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909741559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3909741559
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3024075838
Short name T812
Test name
Test status
Simulation time 96025807193 ps
CPU time 113.76 seconds
Started Jul 07 05:14:03 PM PDT 24
Finished Jul 07 05:15:57 PM PDT 24
Peak memory 199916 kb
Host smart-759fadbe-3178-48bd-b829-ce857580060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024075838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3024075838
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3154429624
Short name T479
Test name
Test status
Simulation time 12341875116 ps
CPU time 18.75 seconds
Started Jul 07 05:14:04 PM PDT 24
Finished Jul 07 05:14:23 PM PDT 24
Peak memory 199904 kb
Host smart-8f89ebef-1960-43fc-b7c9-75da18c7b699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154429624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3154429624
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.987218659
Short name T563
Test name
Test status
Simulation time 21893599839 ps
CPU time 37.24 seconds
Started Jul 07 05:14:07 PM PDT 24
Finished Jul 07 05:14:45 PM PDT 24
Peak memory 199900 kb
Host smart-f9749106-610e-46c9-932d-cde419fe4f01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987218659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.987218659
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2057132271
Short name T422
Test name
Test status
Simulation time 96738848814 ps
CPU time 114.99 seconds
Started Jul 07 05:14:10 PM PDT 24
Finished Jul 07 05:16:06 PM PDT 24
Peak memory 199984 kb
Host smart-e743c378-3428-40f7-9a06-73bb6576a731
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057132271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2057132271
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3290078203
Short name T638
Test name
Test status
Simulation time 279807902 ps
CPU time 0.79 seconds
Started Jul 07 05:14:08 PM PDT 24
Finished Jul 07 05:14:09 PM PDT 24
Peak memory 195544 kb
Host smart-9362e5eb-6d51-4088-91a6-22390ccbb2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290078203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3290078203
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.4063997626
Short name T492
Test name
Test status
Simulation time 83116266729 ps
CPU time 40.83 seconds
Started Jul 07 05:14:08 PM PDT 24
Finished Jul 07 05:14:49 PM PDT 24
Peak memory 200280 kb
Host smart-189c3fe2-21bc-4ce3-9d8f-11a32cbbd85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063997626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4063997626
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.538023292
Short name T328
Test name
Test status
Simulation time 6370660749 ps
CPU time 105.71 seconds
Started Jul 07 05:14:09 PM PDT 24
Finished Jul 07 05:15:55 PM PDT 24
Peak memory 199908 kb
Host smart-6d795eed-a564-43ec-a588-8e60138f2079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538023292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.538023292
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1245651660
Short name T964
Test name
Test status
Simulation time 2120009570 ps
CPU time 1.92 seconds
Started Jul 07 05:14:07 PM PDT 24
Finished Jul 07 05:14:09 PM PDT 24
Peak memory 198076 kb
Host smart-11c85978-4629-4f7c-b664-58299b5cc401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245651660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1245651660
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2843865118
Short name T891
Test name
Test status
Simulation time 40655580077 ps
CPU time 75.63 seconds
Started Jul 07 05:14:05 PM PDT 24
Finished Jul 07 05:15:21 PM PDT 24
Peak memory 199940 kb
Host smart-1f9d5794-ee42-4bf5-abbb-e22282eb1a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843865118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2843865118
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2507825311
Short name T379
Test name
Test status
Simulation time 4917511918 ps
CPU time 4.47 seconds
Started Jul 07 05:14:09 PM PDT 24
Finished Jul 07 05:14:13 PM PDT 24
Peak memory 196072 kb
Host smart-14ee630b-3dce-4cc2-a3a1-063cd0205e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507825311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2507825311
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2803952982
Short name T836
Test name
Test status
Simulation time 5802866478 ps
CPU time 10.15 seconds
Started Jul 07 05:14:03 PM PDT 24
Finished Jul 07 05:14:13 PM PDT 24
Peak memory 199956 kb
Host smart-6d851b25-98cf-49ca-952d-4121fa369d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803952982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2803952982
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.36404458
Short name T1004
Test name
Test status
Simulation time 708662493398 ps
CPU time 464.11 seconds
Started Jul 07 05:14:11 PM PDT 24
Finished Jul 07 05:21:56 PM PDT 24
Peak memory 199804 kb
Host smart-beb736be-07b0-4c51-97a9-8fff99b069a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36404458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.36404458
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2252582231
Short name T1094
Test name
Test status
Simulation time 22153372689 ps
CPU time 419.53 seconds
Started Jul 07 05:14:09 PM PDT 24
Finished Jul 07 05:21:09 PM PDT 24
Peak memory 215712 kb
Host smart-2cd70e67-c536-48cb-8c9c-deb28cabaf2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252582231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2252582231
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4019074838
Short name T265
Test name
Test status
Simulation time 1272398536 ps
CPU time 2.81 seconds
Started Jul 07 05:14:08 PM PDT 24
Finished Jul 07 05:14:11 PM PDT 24
Peak memory 199424 kb
Host smart-24744131-4241-46cd-99b4-768bfc200aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019074838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4019074838
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2408024506
Short name T781
Test name
Test status
Simulation time 33239992368 ps
CPU time 57.42 seconds
Started Jul 07 05:14:06 PM PDT 24
Finished Jul 07 05:15:04 PM PDT 24
Peak memory 199880 kb
Host smart-90d7c224-41f5-4ea8-b55f-e14900323ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408024506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2408024506
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3213623080
Short name T614
Test name
Test status
Simulation time 58880442794 ps
CPU time 86.34 seconds
Started Jul 07 05:18:11 PM PDT 24
Finished Jul 07 05:19:38 PM PDT 24
Peak memory 199980 kb
Host smart-d005025e-a4be-4c5e-a81d-0c4dee7024ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213623080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3213623080
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3687541122
Short name T619
Test name
Test status
Simulation time 29910947791 ps
CPU time 40.02 seconds
Started Jul 07 05:18:13 PM PDT 24
Finished Jul 07 05:18:54 PM PDT 24
Peak memory 199976 kb
Host smart-b2fd8942-926e-46f8-8817-26d82e29dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687541122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3687541122
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.4283205155
Short name T859
Test name
Test status
Simulation time 72989051482 ps
CPU time 28.34 seconds
Started Jul 07 05:18:12 PM PDT 24
Finished Jul 07 05:18:41 PM PDT 24
Peak memory 199936 kb
Host smart-367a48b2-5fe9-4716-a76e-a645dd197b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283205155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4283205155
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1437264663
Short name T612
Test name
Test status
Simulation time 128190218494 ps
CPU time 444.09 seconds
Started Jul 07 05:18:13 PM PDT 24
Finished Jul 07 05:25:37 PM PDT 24
Peak memory 199984 kb
Host smart-ed06856f-f30f-4ac5-a90e-477341bcdfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437264663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1437264663
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2712971171
Short name T1101
Test name
Test status
Simulation time 38002530272 ps
CPU time 15.04 seconds
Started Jul 07 05:18:13 PM PDT 24
Finished Jul 07 05:18:28 PM PDT 24
Peak memory 199648 kb
Host smart-11dfcfb9-4b32-4029-8053-1d556e99f956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712971171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2712971171
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1474211691
Short name T51
Test name
Test status
Simulation time 188311978769 ps
CPU time 165.39 seconds
Started Jul 07 05:18:16 PM PDT 24
Finished Jul 07 05:21:02 PM PDT 24
Peak memory 199876 kb
Host smart-883f940d-c096-4788-85c1-da9d3a51d3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474211691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1474211691
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3800423434
Short name T506
Test name
Test status
Simulation time 65369048063 ps
CPU time 124.38 seconds
Started Jul 07 05:18:13 PM PDT 24
Finished Jul 07 05:20:18 PM PDT 24
Peak memory 199824 kb
Host smart-8cfc9fad-09df-4573-beaf-a06730cd0b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800423434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3800423434
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2146431529
Short name T473
Test name
Test status
Simulation time 58087823861 ps
CPU time 29.28 seconds
Started Jul 07 05:18:11 PM PDT 24
Finished Jul 07 05:18:41 PM PDT 24
Peak memory 199864 kb
Host smart-234a273e-6330-40ad-8114-f599549024fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146431529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2146431529
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2489888066
Short name T248
Test name
Test status
Simulation time 116544402312 ps
CPU time 36.46 seconds
Started Jul 07 05:18:19 PM PDT 24
Finished Jul 07 05:18:56 PM PDT 24
Peak memory 199920 kb
Host smart-e4692f38-7610-4b6b-bc3f-72f779dfbed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489888066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2489888066
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.489796590
Short name T892
Test name
Test status
Simulation time 155325434 ps
CPU time 0.54 seconds
Started Jul 07 05:14:13 PM PDT 24
Finished Jul 07 05:14:14 PM PDT 24
Peak memory 195292 kb
Host smart-4181b60d-f745-493f-ac12-1599e1b005c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489796590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.489796590
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1407632118
Short name T319
Test name
Test status
Simulation time 31359159952 ps
CPU time 22.75 seconds
Started Jul 07 05:14:10 PM PDT 24
Finished Jul 07 05:14:33 PM PDT 24
Peak memory 199940 kb
Host smart-455b5c03-42fc-42dc-b837-2616beecf658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407632118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1407632118
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2493590811
Short name T1113
Test name
Test status
Simulation time 83838360970 ps
CPU time 66.05 seconds
Started Jul 07 05:14:15 PM PDT 24
Finished Jul 07 05:15:21 PM PDT 24
Peak memory 199748 kb
Host smart-208ef1ba-fff2-4a04-9d56-bbf1e16ba163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493590811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2493590811
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.4796615
Short name T18
Test name
Test status
Simulation time 23210226406 ps
CPU time 35.98 seconds
Started Jul 07 05:14:15 PM PDT 24
Finished Jul 07 05:14:51 PM PDT 24
Peak memory 199740 kb
Host smart-9f3963f5-7396-46f5-8079-a39252ac3bd7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4796615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4796615
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1779286239
Short name T653
Test name
Test status
Simulation time 222321140780 ps
CPU time 156.98 seconds
Started Jul 07 05:14:11 PM PDT 24
Finished Jul 07 05:16:48 PM PDT 24
Peak memory 199980 kb
Host smart-29d0f21f-1ed7-4c4c-ab7b-c20926798a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779286239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1779286239
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.172813787
Short name T122
Test name
Test status
Simulation time 8206488949 ps
CPU time 13.95 seconds
Started Jul 07 05:14:12 PM PDT 24
Finished Jul 07 05:14:26 PM PDT 24
Peak memory 199812 kb
Host smart-ccbac100-5ac5-4e6f-9c49-40b39130810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172813787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.172813787
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1907919437
Short name T377
Test name
Test status
Simulation time 65407177354 ps
CPU time 33.55 seconds
Started Jul 07 05:14:13 PM PDT 24
Finished Jul 07 05:14:47 PM PDT 24
Peak memory 200168 kb
Host smart-ea9bc421-80ee-4150-b1ea-fa5e4be6a4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907919437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1907919437
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.110878402
Short name T1045
Test name
Test status
Simulation time 26190641890 ps
CPU time 188.31 seconds
Started Jul 07 05:14:11 PM PDT 24
Finished Jul 07 05:17:19 PM PDT 24
Peak memory 199888 kb
Host smart-eebe3614-4b1f-4756-afe8-2ea4722f8784
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110878402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.110878402
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1235954481
Short name T667
Test name
Test status
Simulation time 1486864273 ps
CPU time 3.04 seconds
Started Jul 07 05:14:14 PM PDT 24
Finished Jul 07 05:14:17 PM PDT 24
Peak memory 198040 kb
Host smart-fc183575-b456-4cc2-8781-70a11b253d41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235954481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1235954481
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1917508676
Short name T697
Test name
Test status
Simulation time 132712832542 ps
CPU time 182.57 seconds
Started Jul 07 05:14:15 PM PDT 24
Finished Jul 07 05:17:18 PM PDT 24
Peak memory 199832 kb
Host smart-569a4d18-d22b-42a5-81e6-832bbf48c8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917508676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1917508676
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1274009178
Short name T609
Test name
Test status
Simulation time 48468867172 ps
CPU time 17.71 seconds
Started Jul 07 05:14:09 PM PDT 24
Finished Jul 07 05:14:27 PM PDT 24
Peak memory 196392 kb
Host smart-8d263d52-9505-4134-9dac-5789ea92de47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274009178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1274009178
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.125148734
Short name T844
Test name
Test status
Simulation time 802760365 ps
CPU time 0.99 seconds
Started Jul 07 05:14:07 PM PDT 24
Finished Jul 07 05:14:09 PM PDT 24
Peak memory 198712 kb
Host smart-9fbf0eef-eec0-4237-83f5-a5e0595aca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125148734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.125148734
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.499261400
Short name T1052
Test name
Test status
Simulation time 56005919683 ps
CPU time 296.18 seconds
Started Jul 07 05:14:15 PM PDT 24
Finished Jul 07 05:19:11 PM PDT 24
Peak memory 199680 kb
Host smart-887069d2-318f-47de-b826-6f290f2ed154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499261400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.499261400
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2017902444
Short name T1020
Test name
Test status
Simulation time 1596934255 ps
CPU time 1.63 seconds
Started Jul 07 05:14:10 PM PDT 24
Finished Jul 07 05:14:12 PM PDT 24
Peak memory 198580 kb
Host smart-ff8921c6-406d-4eb5-9283-05d38dc94510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017902444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2017902444
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2822422907
Short name T708
Test name
Test status
Simulation time 84551821535 ps
CPU time 10.48 seconds
Started Jul 07 05:14:07 PM PDT 24
Finished Jul 07 05:14:18 PM PDT 24
Peak memory 199436 kb
Host smart-bb9fa508-24da-46e5-8061-9a523c081feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822422907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2822422907
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1868703568
Short name T274
Test name
Test status
Simulation time 123414866673 ps
CPU time 65.76 seconds
Started Jul 07 05:18:18 PM PDT 24
Finished Jul 07 05:19:24 PM PDT 24
Peak memory 199992 kb
Host smart-407e9ca5-20b7-4b4d-86c0-2b4247356bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868703568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1868703568
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.329829338
Short name T688
Test name
Test status
Simulation time 56533854893 ps
CPU time 22.62 seconds
Started Jul 07 05:18:17 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 199604 kb
Host smart-8a9ec91d-02cb-4a51-9636-bc85f817eed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329829338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.329829338
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4109757028
Short name T191
Test name
Test status
Simulation time 106076674219 ps
CPU time 30.31 seconds
Started Jul 07 05:18:22 PM PDT 24
Finished Jul 07 05:18:53 PM PDT 24
Peak memory 199724 kb
Host smart-4862fb6a-accb-403e-bb78-a84daf7e0e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109757028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4109757028
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1879661211
Short name T323
Test name
Test status
Simulation time 13316613072 ps
CPU time 17.61 seconds
Started Jul 07 05:18:15 PM PDT 24
Finished Jul 07 05:18:33 PM PDT 24
Peak memory 199888 kb
Host smart-7a56abae-b9d5-4599-8735-c0c729eec21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879661211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1879661211
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3344429554
Short name T1150
Test name
Test status
Simulation time 31134933193 ps
CPU time 31.13 seconds
Started Jul 07 05:18:18 PM PDT 24
Finished Jul 07 05:18:50 PM PDT 24
Peak memory 199932 kb
Host smart-fd69656a-9ebc-4e6a-b283-edb9252479cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344429554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3344429554
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2860442202
Short name T316
Test name
Test status
Simulation time 49574808211 ps
CPU time 21.58 seconds
Started Jul 07 05:18:21 PM PDT 24
Finished Jul 07 05:18:42 PM PDT 24
Peak memory 199956 kb
Host smart-b0f364b4-4bca-46df-9e76-949a7f0632d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860442202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2860442202
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2626183785
Short name T287
Test name
Test status
Simulation time 140377465300 ps
CPU time 134.94 seconds
Started Jul 07 05:18:21 PM PDT 24
Finished Jul 07 05:20:36 PM PDT 24
Peak memory 199992 kb
Host smart-3f365202-a95d-4588-aed0-d4e89d8fc700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626183785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2626183785
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.4128644400
Short name T630
Test name
Test status
Simulation time 13718279363 ps
CPU time 22.66 seconds
Started Jul 07 05:18:24 PM PDT 24
Finished Jul 07 05:18:47 PM PDT 24
Peak memory 199896 kb
Host smart-58d6b409-3d13-4d25-b6c1-3b6715e11466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128644400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.4128644400
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3118977984
Short name T747
Test name
Test status
Simulation time 18191726 ps
CPU time 0.56 seconds
Started Jul 07 05:14:19 PM PDT 24
Finished Jul 07 05:14:20 PM PDT 24
Peak memory 195292 kb
Host smart-f5723a9f-8dae-4938-9cd0-1d7ad9a341d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118977984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3118977984
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4085793208
Short name T875
Test name
Test status
Simulation time 151939687838 ps
CPU time 137.99 seconds
Started Jul 07 05:14:12 PM PDT 24
Finished Jul 07 05:16:31 PM PDT 24
Peak memory 199892 kb
Host smart-065b704a-09c5-4183-bc1e-baa932edf2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085793208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4085793208
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3803455012
Short name T629
Test name
Test status
Simulation time 13431291960 ps
CPU time 31.73 seconds
Started Jul 07 05:14:15 PM PDT 24
Finished Jul 07 05:14:47 PM PDT 24
Peak memory 199940 kb
Host smart-e72c7aa9-266a-48cf-8d91-9072c1829b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803455012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3803455012
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3173842674
Short name T234
Test name
Test status
Simulation time 20048707699 ps
CPU time 9.98 seconds
Started Jul 07 05:14:18 PM PDT 24
Finished Jul 07 05:14:28 PM PDT 24
Peak memory 199976 kb
Host smart-a86d60fd-07e0-44ac-90d5-605b19e7ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173842674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3173842674
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3545501790
Short name T1075
Test name
Test status
Simulation time 175424180613 ps
CPU time 274.35 seconds
Started Jul 07 05:14:19 PM PDT 24
Finished Jul 07 05:18:54 PM PDT 24
Peak memory 199968 kb
Host smart-eac7ea9a-e4a6-4ab5-9315-46cd5b126fb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545501790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3545501790
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.754761367
Short name T571
Test name
Test status
Simulation time 10293249398 ps
CPU time 58.6 seconds
Started Jul 07 05:14:16 PM PDT 24
Finished Jul 07 05:15:14 PM PDT 24
Peak memory 199912 kb
Host smart-67a65a5e-da97-40b6-af24-5fab8f64f1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754761367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.754761367
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2325965149
Short name T887
Test name
Test status
Simulation time 7896597921 ps
CPU time 13.06 seconds
Started Jul 07 05:14:16 PM PDT 24
Finished Jul 07 05:14:29 PM PDT 24
Peak memory 197392 kb
Host smart-f0064369-3ea6-4981-a8c4-b4af44e0b446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325965149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2325965149
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2151927894
Short name T646
Test name
Test status
Simulation time 16269963864 ps
CPU time 425.04 seconds
Started Jul 07 05:14:18 PM PDT 24
Finished Jul 07 05:21:23 PM PDT 24
Peak memory 199884 kb
Host smart-3ad8a815-49f2-4b99-ae93-768ef46661b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151927894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2151927894
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2170566652
Short name T1081
Test name
Test status
Simulation time 3940183554 ps
CPU time 7.51 seconds
Started Jul 07 05:14:15 PM PDT 24
Finished Jul 07 05:14:22 PM PDT 24
Peak memory 198172 kb
Host smart-c8957377-e483-4e37-a5aa-041a350b2c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170566652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2170566652
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.504287426
Short name T267
Test name
Test status
Simulation time 112210596579 ps
CPU time 33.77 seconds
Started Jul 07 05:14:16 PM PDT 24
Finished Jul 07 05:14:50 PM PDT 24
Peak memory 199892 kb
Host smart-53d94f36-0a1f-4ef0-a482-032d09804041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504287426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.504287426
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.56137206
Short name T837
Test name
Test status
Simulation time 5606087915 ps
CPU time 5.08 seconds
Started Jul 07 05:14:16 PM PDT 24
Finished Jul 07 05:14:22 PM PDT 24
Peak memory 196068 kb
Host smart-8121f413-65eb-4d1a-8250-95918c995ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56137206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.56137206
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.742865340
Short name T402
Test name
Test status
Simulation time 348370258 ps
CPU time 1.1 seconds
Started Jul 07 05:14:14 PM PDT 24
Finished Jul 07 05:14:15 PM PDT 24
Peak memory 198708 kb
Host smart-0784d9e3-0a19-4b38-aef8-1a20ae40cb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742865340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.742865340
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3789213406
Short name T1144
Test name
Test status
Simulation time 991379706757 ps
CPU time 1018 seconds
Started Jul 07 05:14:17 PM PDT 24
Finished Jul 07 05:31:16 PM PDT 24
Peak memory 231052 kb
Host smart-b5310f57-cc0d-4d59-81b1-4eaf9bafe1f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789213406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3789213406
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1456697608
Short name T530
Test name
Test status
Simulation time 2294205585 ps
CPU time 2.59 seconds
Started Jul 07 05:14:15 PM PDT 24
Finished Jul 07 05:14:18 PM PDT 24
Peak memory 198176 kb
Host smart-0d9150d6-3328-4e5e-ae2a-afa138c4b62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456697608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1456697608
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3011964800
Short name T825
Test name
Test status
Simulation time 34155443028 ps
CPU time 62.33 seconds
Started Jul 07 05:14:10 PM PDT 24
Finished Jul 07 05:15:13 PM PDT 24
Peak memory 199984 kb
Host smart-3fb36412-cb02-4dbf-8e25-0d3306fc6bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011964800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3011964800
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.437798739
Short name T934
Test name
Test status
Simulation time 31916969026 ps
CPU time 13.4 seconds
Started Jul 07 05:18:21 PM PDT 24
Finished Jul 07 05:18:35 PM PDT 24
Peak memory 199524 kb
Host smart-7e73d793-32b8-425f-a4bc-4edfafc33214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437798739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.437798739
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.679289722
Short name T1131
Test name
Test status
Simulation time 23856529230 ps
CPU time 18.3 seconds
Started Jul 07 05:18:22 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 199988 kb
Host smart-6ed093a9-0207-4d68-a51c-2e5a44e5715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679289722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.679289722
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1890695617
Short name T206
Test name
Test status
Simulation time 19224672042 ps
CPU time 20 seconds
Started Jul 07 05:18:22 PM PDT 24
Finished Jul 07 05:18:42 PM PDT 24
Peak memory 199984 kb
Host smart-0032b826-68f9-4ee4-9a47-01d4ce8cb923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890695617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1890695617
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3010032557
Short name T236
Test name
Test status
Simulation time 16008385718 ps
CPU time 6.85 seconds
Started Jul 07 05:18:22 PM PDT 24
Finished Jul 07 05:18:29 PM PDT 24
Peak memory 199780 kb
Host smart-ea24002f-d6d4-4cba-b58b-f9af95eb7230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010032557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3010032557
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1926085146
Short name T1010
Test name
Test status
Simulation time 111837523429 ps
CPU time 169.94 seconds
Started Jul 07 05:18:22 PM PDT 24
Finished Jul 07 05:21:12 PM PDT 24
Peak memory 199940 kb
Host smart-91103aa3-9599-436c-a921-f80f2b5c62fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926085146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1926085146
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2848862159
Short name T848
Test name
Test status
Simulation time 239857145809 ps
CPU time 103.36 seconds
Started Jul 07 05:18:21 PM PDT 24
Finished Jul 07 05:20:04 PM PDT 24
Peak memory 199896 kb
Host smart-b3b1def8-6db5-42d7-93ed-18af6ef85104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848862159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2848862159
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3792490881
Short name T445
Test name
Test status
Simulation time 56912543337 ps
CPU time 141.58 seconds
Started Jul 07 05:18:22 PM PDT 24
Finished Jul 07 05:20:44 PM PDT 24
Peak memory 199888 kb
Host smart-add2d38d-8b5b-4510-bd9e-d0cbb1939834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792490881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3792490881
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.871231780
Short name T1001
Test name
Test status
Simulation time 16155080296 ps
CPU time 24.2 seconds
Started Jul 07 05:18:24 PM PDT 24
Finished Jul 07 05:18:48 PM PDT 24
Peak memory 199928 kb
Host smart-ba53d7a9-cc4f-45a8-8be6-df18d24d4ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871231780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.871231780
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3535343208
Short name T915
Test name
Test status
Simulation time 28628492628 ps
CPU time 44.21 seconds
Started Jul 07 05:18:24 PM PDT 24
Finished Jul 07 05:19:08 PM PDT 24
Peak memory 199876 kb
Host smart-8a5637b4-336b-4e31-a457-0737a9efc2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535343208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3535343208
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2374734366
Short name T954
Test name
Test status
Simulation time 48213552 ps
CPU time 0.55 seconds
Started Jul 07 05:14:24 PM PDT 24
Finished Jul 07 05:14:25 PM PDT 24
Peak memory 194756 kb
Host smart-d5c4a936-be18-4ddc-acd3-c74de0a7f2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374734366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2374734366
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3064801219
Short name T406
Test name
Test status
Simulation time 50816009909 ps
CPU time 39.31 seconds
Started Jul 07 05:14:23 PM PDT 24
Finished Jul 07 05:15:03 PM PDT 24
Peak memory 199240 kb
Host smart-5a27f27c-f870-4b86-9e47-023d9658987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064801219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3064801219
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3071425786
Short name T1005
Test name
Test status
Simulation time 24068446721 ps
CPU time 12.46 seconds
Started Jul 07 05:14:23 PM PDT 24
Finished Jul 07 05:14:36 PM PDT 24
Peak memory 199668 kb
Host smart-244910a0-5191-4d97-b496-b0d0134f26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071425786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3071425786
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.160401224
Short name T660
Test name
Test status
Simulation time 13854037064 ps
CPU time 26.92 seconds
Started Jul 07 05:14:20 PM PDT 24
Finished Jul 07 05:14:47 PM PDT 24
Peak memory 199896 kb
Host smart-d039d033-834e-4314-8c58-c9ec25ac31b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160401224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.160401224
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3557198854
Short name T727
Test name
Test status
Simulation time 11220697110 ps
CPU time 14.77 seconds
Started Jul 07 05:14:20 PM PDT 24
Finished Jul 07 05:14:35 PM PDT 24
Peak memory 199880 kb
Host smart-c4737a4c-d4c7-4833-ae07-9b7b0f5e8694
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557198854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3557198854
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.180241371
Short name T435
Test name
Test status
Simulation time 39499360885 ps
CPU time 138.93 seconds
Started Jul 07 05:14:27 PM PDT 24
Finished Jul 07 05:16:46 PM PDT 24
Peak memory 199956 kb
Host smart-94adccb6-cacd-4952-b558-ccdb6ed8b455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=180241371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.180241371
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3635758671
Short name T381
Test name
Test status
Simulation time 5609817706 ps
CPU time 10.06 seconds
Started Jul 07 05:14:27 PM PDT 24
Finished Jul 07 05:14:38 PM PDT 24
Peak memory 199848 kb
Host smart-8e9eb78d-ad69-4c19-9175-2bcdc9e2b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635758671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3635758671
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.954643987
Short name T676
Test name
Test status
Simulation time 92900451923 ps
CPU time 40.39 seconds
Started Jul 07 05:14:21 PM PDT 24
Finished Jul 07 05:15:02 PM PDT 24
Peak memory 200008 kb
Host smart-dfe85844-fbc5-4946-9276-a4ad2cc297ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954643987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.954643987
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3244525079
Short name T803
Test name
Test status
Simulation time 6507351205 ps
CPU time 375.55 seconds
Started Jul 07 05:14:25 PM PDT 24
Finished Jul 07 05:20:41 PM PDT 24
Peak memory 199964 kb
Host smart-acca93d1-8267-4b71-82ae-cbf3c6e53ecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244525079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3244525079
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3951987090
Short name T528
Test name
Test status
Simulation time 2238382689 ps
CPU time 3.57 seconds
Started Jul 07 05:14:19 PM PDT 24
Finished Jul 07 05:14:23 PM PDT 24
Peak memory 198048 kb
Host smart-e85f1951-4684-47ae-b038-2ee7e2aeb9fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951987090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3951987090
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1059323319
Short name T713
Test name
Test status
Simulation time 42572887419 ps
CPU time 65.45 seconds
Started Jul 07 05:14:19 PM PDT 24
Finished Jul 07 05:15:25 PM PDT 24
Peak memory 195776 kb
Host smart-c9248a86-d331-4f19-aab3-8be15d6c21bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059323319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1059323319
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.213681258
Short name T637
Test name
Test status
Simulation time 292907847 ps
CPU time 1.42 seconds
Started Jul 07 05:14:20 PM PDT 24
Finished Jul 07 05:14:22 PM PDT 24
Peak memory 198520 kb
Host smart-2fbd6d7c-cc9b-4716-9b4e-9969394467ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213681258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.213681258
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2632389013
Short name T403
Test name
Test status
Simulation time 248048568852 ps
CPU time 988.61 seconds
Started Jul 07 05:14:26 PM PDT 24
Finished Jul 07 05:30:55 PM PDT 24
Peak memory 199948 kb
Host smart-7d86a0dc-8299-4eb1-a69e-f21eb4b276d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632389013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2632389013
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.334479580
Short name T1085
Test name
Test status
Simulation time 42966075275 ps
CPU time 874.13 seconds
Started Jul 07 05:14:24 PM PDT 24
Finished Jul 07 05:28:59 PM PDT 24
Peak memory 216556 kb
Host smart-966cd79e-42bb-4900-8631-6526abc42833
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334479580 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.334479580
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1619444980
Short name T549
Test name
Test status
Simulation time 630747091 ps
CPU time 2.36 seconds
Started Jul 07 05:14:19 PM PDT 24
Finished Jul 07 05:14:22 PM PDT 24
Peak memory 198664 kb
Host smart-5f90198f-a635-4918-b0e9-deb99a3d5906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619444980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1619444980
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.705314585
Short name T987
Test name
Test status
Simulation time 45769412742 ps
CPU time 8.39 seconds
Started Jul 07 05:14:20 PM PDT 24
Finished Jul 07 05:14:29 PM PDT 24
Peak memory 197596 kb
Host smart-983a2907-28a3-44ae-8135-def49aae6ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705314585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.705314585
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.526477947
Short name T1006
Test name
Test status
Simulation time 37885316801 ps
CPU time 21.23 seconds
Started Jul 07 05:18:21 PM PDT 24
Finished Jul 07 05:18:43 PM PDT 24
Peak memory 199932 kb
Host smart-5a54f319-8f88-44c3-bc2e-4c307a5ddcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526477947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.526477947
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3619847023
Short name T159
Test name
Test status
Simulation time 80511473765 ps
CPU time 51.41 seconds
Started Jul 07 05:18:29 PM PDT 24
Finished Jul 07 05:19:21 PM PDT 24
Peak memory 199924 kb
Host smart-05b1f6b3-c3e0-4bcb-a12a-8f313115b5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619847023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3619847023
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3792475670
Short name T74
Test name
Test status
Simulation time 296814245990 ps
CPU time 29.42 seconds
Started Jul 07 05:18:29 PM PDT 24
Finished Jul 07 05:18:59 PM PDT 24
Peak memory 199936 kb
Host smart-8baad51e-6586-456d-b98b-1bfcc8884856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792475670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3792475670
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3069675985
Short name T769
Test name
Test status
Simulation time 205088958807 ps
CPU time 154.99 seconds
Started Jul 07 05:18:31 PM PDT 24
Finished Jul 07 05:21:06 PM PDT 24
Peak memory 199952 kb
Host smart-cbfe4f2f-784a-4017-8b11-9936b4bf4742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069675985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3069675985
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3947568832
Short name T343
Test name
Test status
Simulation time 57289073611 ps
CPU time 24.76 seconds
Started Jul 07 05:18:29 PM PDT 24
Finished Jul 07 05:18:54 PM PDT 24
Peak memory 199980 kb
Host smart-24674fd4-df0d-430b-ae96-91e408f4e12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947568832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3947568832
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1913420401
Short name T625
Test name
Test status
Simulation time 123412014166 ps
CPU time 104.68 seconds
Started Jul 07 05:18:28 PM PDT 24
Finished Jul 07 05:20:13 PM PDT 24
Peak memory 199652 kb
Host smart-e1ce60f2-600f-4116-9caf-df836bbbcfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913420401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1913420401
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2376030206
Short name T190
Test name
Test status
Simulation time 177814196681 ps
CPU time 181.81 seconds
Started Jul 07 05:18:26 PM PDT 24
Finished Jul 07 05:21:29 PM PDT 24
Peak memory 199880 kb
Host smart-1c53465f-7c1e-42d8-b9ec-c090ed818583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376030206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2376030206
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1799310736
Short name T197
Test name
Test status
Simulation time 111825364619 ps
CPU time 177.44 seconds
Started Jul 07 05:18:30 PM PDT 24
Finished Jul 07 05:21:27 PM PDT 24
Peak memory 199884 kb
Host smart-f54ded3c-6e4e-4c74-b5de-06bcabc24c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799310736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1799310736
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3628674254
Short name T389
Test name
Test status
Simulation time 117905058199 ps
CPU time 43.12 seconds
Started Jul 07 05:18:29 PM PDT 24
Finished Jul 07 05:19:12 PM PDT 24
Peak memory 199980 kb
Host smart-fa5c2930-2df8-41d7-b95e-f550af179bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628674254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3628674254
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1095838419
Short name T737
Test name
Test status
Simulation time 12695130 ps
CPU time 0.55 seconds
Started Jul 07 05:12:42 PM PDT 24
Finished Jul 07 05:12:43 PM PDT 24
Peak memory 195296 kb
Host smart-63cb5906-2501-4612-830a-37c12c4a3fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095838419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1095838419
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3838633064
Short name T1155
Test name
Test status
Simulation time 152846837742 ps
CPU time 84.5 seconds
Started Jul 07 05:12:46 PM PDT 24
Finished Jul 07 05:14:11 PM PDT 24
Peak memory 199872 kb
Host smart-68ae99de-9412-4ca9-b7f2-49b982ebe9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838633064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3838633064
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1847766756
Short name T750
Test name
Test status
Simulation time 83993285592 ps
CPU time 32.98 seconds
Started Jul 07 05:12:43 PM PDT 24
Finished Jul 07 05:13:17 PM PDT 24
Peak memory 198488 kb
Host smart-1e4c8039-a3b8-4666-9578-e7badf929e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847766756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1847766756
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.2139693980
Short name T1066
Test name
Test status
Simulation time 4960476519 ps
CPU time 5.56 seconds
Started Jul 07 05:12:40 PM PDT 24
Finished Jul 07 05:12:46 PM PDT 24
Peak memory 199912 kb
Host smart-4630c7cb-5728-4a18-95c9-00e343e3f97e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139693980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2139693980
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2597614049
Short name T577
Test name
Test status
Simulation time 109342761939 ps
CPU time 414.32 seconds
Started Jul 07 05:12:46 PM PDT 24
Finished Jul 07 05:19:41 PM PDT 24
Peak memory 199868 kb
Host smart-02d92afa-3f6a-4522-8c51-076f33ec790a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597614049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2597614049
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.161619106
Short name T457
Test name
Test status
Simulation time 2214059411 ps
CPU time 7 seconds
Started Jul 07 05:12:43 PM PDT 24
Finished Jul 07 05:12:50 PM PDT 24
Peak memory 199824 kb
Host smart-64415085-622b-463a-8b17-7c3090681b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161619106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.161619106
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.145816119
Short name T780
Test name
Test status
Simulation time 158387562663 ps
CPU time 63.96 seconds
Started Jul 07 05:12:45 PM PDT 24
Finished Jul 07 05:13:49 PM PDT 24
Peak memory 208424 kb
Host smart-6ed078f1-f9a5-4306-97e7-af905b359a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145816119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.145816119
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3491529521
Short name T966
Test name
Test status
Simulation time 11885093599 ps
CPU time 139.43 seconds
Started Jul 07 05:12:42 PM PDT 24
Finished Jul 07 05:15:02 PM PDT 24
Peak memory 199920 kb
Host smart-618bcee8-1bf7-4e90-9912-c9c2ebb6995b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491529521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3491529521
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2125566901
Short name T621
Test name
Test status
Simulation time 6936512467 ps
CPU time 17.12 seconds
Started Jul 07 05:12:44 PM PDT 24
Finished Jul 07 05:13:02 PM PDT 24
Peak memory 199436 kb
Host smart-ff4e9964-1b4c-4120-b8aa-c8d83ef5300f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125566901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2125566901
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3484698576
Short name T759
Test name
Test status
Simulation time 70501399681 ps
CPU time 29.54 seconds
Started Jul 07 05:12:40 PM PDT 24
Finished Jul 07 05:13:10 PM PDT 24
Peak memory 199624 kb
Host smart-d2c72014-e21c-472c-b50a-713247148bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484698576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3484698576
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1757575834
Short name T1047
Test name
Test status
Simulation time 49250068576 ps
CPU time 18.39 seconds
Started Jul 07 05:12:41 PM PDT 24
Finished Jul 07 05:13:00 PM PDT 24
Peak memory 196416 kb
Host smart-8a8a2cc7-3f8b-4867-ad18-d6bc1bf3ce58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757575834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1757575834
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1014603500
Short name T30
Test name
Test status
Simulation time 205046195 ps
CPU time 0.9 seconds
Started Jul 07 05:12:47 PM PDT 24
Finished Jul 07 05:12:49 PM PDT 24
Peak memory 218596 kb
Host smart-030cf2e2-3121-4381-9d4b-859a1e8f071e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014603500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1014603500
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1003818086
Short name T50
Test name
Test status
Simulation time 739839777 ps
CPU time 1.14 seconds
Started Jul 07 05:12:43 PM PDT 24
Finished Jul 07 05:12:44 PM PDT 24
Peak memory 198420 kb
Host smart-76974652-b891-47db-82ab-c0d5e162867d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003818086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1003818086
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1747820689
Short name T12
Test name
Test status
Simulation time 474029027889 ps
CPU time 346.81 seconds
Started Jul 07 05:12:43 PM PDT 24
Finished Jul 07 05:18:31 PM PDT 24
Peak memory 199888 kb
Host smart-cd7e8dab-831d-4faf-b58d-c72cfbfd9c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747820689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1747820689
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3224336366
Short name T729
Test name
Test status
Simulation time 22566829428 ps
CPU time 200.09 seconds
Started Jul 07 05:12:42 PM PDT 24
Finished Jul 07 05:16:03 PM PDT 24
Peak memory 216156 kb
Host smart-dad70c38-ac01-4d8a-ab9b-a32a5a68bd6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224336366 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3224336366
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.937165311
Short name T1162
Test name
Test status
Simulation time 1294026026 ps
CPU time 2.07 seconds
Started Jul 07 05:12:41 PM PDT 24
Finished Jul 07 05:12:43 PM PDT 24
Peak memory 198452 kb
Host smart-31264150-2872-4b9c-ac6b-f8fde438c5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937165311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.937165311
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.519785523
Short name T853
Test name
Test status
Simulation time 121818673229 ps
CPU time 185.83 seconds
Started Jul 07 05:12:43 PM PDT 24
Finished Jul 07 05:15:50 PM PDT 24
Peak memory 199948 kb
Host smart-4b8cc030-0af5-4393-bc51-e0c800ff566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519785523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.519785523
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3608018554
Short name T654
Test name
Test status
Simulation time 46057589 ps
CPU time 0.55 seconds
Started Jul 07 05:14:28 PM PDT 24
Finished Jul 07 05:14:29 PM PDT 24
Peak memory 195220 kb
Host smart-0460b423-237a-4303-9fb9-0c16489590a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608018554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3608018554
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3555549699
Short name T160
Test name
Test status
Simulation time 148662713834 ps
CPU time 175.56 seconds
Started Jul 07 05:14:26 PM PDT 24
Finished Jul 07 05:17:22 PM PDT 24
Peak memory 199948 kb
Host smart-4a0e75a9-936e-4dfb-bfc5-8d4eaf9deb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555549699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3555549699
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1751754867
Short name T1062
Test name
Test status
Simulation time 107390867807 ps
CPU time 32.65 seconds
Started Jul 07 05:14:23 PM PDT 24
Finished Jul 07 05:14:56 PM PDT 24
Peak memory 199908 kb
Host smart-a1977cf5-d8c0-4b95-9d24-8c6c64a692e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751754867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1751754867
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4095904264
Short name T922
Test name
Test status
Simulation time 51167202879 ps
CPU time 38.88 seconds
Started Jul 07 05:14:30 PM PDT 24
Finished Jul 07 05:15:09 PM PDT 24
Peak memory 199912 kb
Host smart-d3173d6b-8303-489e-9de2-7ad8c0d94a65
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095904264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4095904264
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2700811592
Short name T1077
Test name
Test status
Simulation time 131705511708 ps
CPU time 483.12 seconds
Started Jul 07 05:14:29 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 199904 kb
Host smart-432bb8ef-9811-4a12-8614-d1fd14cb12df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700811592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2700811592
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.4066666331
Short name T951
Test name
Test status
Simulation time 478469367 ps
CPU time 1.34 seconds
Started Jul 07 05:14:28 PM PDT 24
Finished Jul 07 05:14:30 PM PDT 24
Peak memory 195408 kb
Host smart-89a33ebf-69f4-455b-9ef4-23b11a2b9650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066666331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.4066666331
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1767365403
Short name T601
Test name
Test status
Simulation time 404869273442 ps
CPU time 63.52 seconds
Started Jul 07 05:14:29 PM PDT 24
Finished Jul 07 05:15:33 PM PDT 24
Peak memory 200040 kb
Host smart-caee8b56-465a-465c-8b84-9f0a69b2d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767365403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1767365403
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1768083246
Short name T800
Test name
Test status
Simulation time 13169986776 ps
CPU time 135.69 seconds
Started Jul 07 05:14:28 PM PDT 24
Finished Jul 07 05:16:43 PM PDT 24
Peak memory 199964 kb
Host smart-01056cf3-550c-4f31-8d39-b9ea05cc09fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768083246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1768083246
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2410229210
Short name T916
Test name
Test status
Simulation time 2329603760 ps
CPU time 7.15 seconds
Started Jul 07 05:14:30 PM PDT 24
Finished Jul 07 05:14:37 PM PDT 24
Peak memory 198340 kb
Host smart-6c8c5675-88b5-4259-8a36-fc00b542aa1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410229210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2410229210
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1344419498
Short name T148
Test name
Test status
Simulation time 59871167580 ps
CPU time 120.57 seconds
Started Jul 07 05:14:28 PM PDT 24
Finished Jul 07 05:16:29 PM PDT 24
Peak memory 199800 kb
Host smart-2914dd5a-58bd-402b-b98e-02b166f73564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344419498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1344419498
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1386474976
Short name T71
Test name
Test status
Simulation time 42706474242 ps
CPU time 14.97 seconds
Started Jul 07 05:14:28 PM PDT 24
Finished Jul 07 05:14:43 PM PDT 24
Peak memory 196604 kb
Host smart-cd23505c-96b5-4d71-b081-f39e399443ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386474976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1386474976
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.816192924
Short name T693
Test name
Test status
Simulation time 11575435982 ps
CPU time 27.14 seconds
Started Jul 07 05:14:25 PM PDT 24
Finished Jul 07 05:14:53 PM PDT 24
Peak memory 199948 kb
Host smart-61cbaf84-8ec9-492a-a65e-ce2560f284dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816192924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.816192924
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3903310661
Short name T879
Test name
Test status
Simulation time 371785346913 ps
CPU time 251.52 seconds
Started Jul 07 05:14:28 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 208372 kb
Host smart-2c1ff655-26f9-4481-b2f4-61b29e6d1dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903310661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3903310661
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2890562935
Short name T156
Test name
Test status
Simulation time 210506357792 ps
CPU time 660.77 seconds
Started Jul 07 05:14:29 PM PDT 24
Finished Jul 07 05:25:30 PM PDT 24
Peak memory 216436 kb
Host smart-94daa543-f73a-4e3a-b726-0a72a447609e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890562935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2890562935
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1012923438
Short name T671
Test name
Test status
Simulation time 6747376965 ps
CPU time 25.79 seconds
Started Jul 07 05:14:27 PM PDT 24
Finished Jul 07 05:14:53 PM PDT 24
Peak memory 199876 kb
Host smart-da337348-5bad-4f87-93d0-da2af096b913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012923438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1012923438
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.452897062
Short name T885
Test name
Test status
Simulation time 77389469372 ps
CPU time 146.7 seconds
Started Jul 07 05:14:23 PM PDT 24
Finished Jul 07 05:16:50 PM PDT 24
Peak memory 199944 kb
Host smart-4a1f0349-9c7c-4dec-829b-fdf024dd1011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452897062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.452897062
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.4236363889
Short name T558
Test name
Test status
Simulation time 30593771 ps
CPU time 0.54 seconds
Started Jul 07 05:14:39 PM PDT 24
Finished Jul 07 05:14:40 PM PDT 24
Peak memory 194720 kb
Host smart-13259b0b-a17e-4080-bb98-8648fca2c342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236363889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.4236363889
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2374458023
Short name T172
Test name
Test status
Simulation time 54522478020 ps
CPU time 15.1 seconds
Started Jul 07 05:14:29 PM PDT 24
Finished Jul 07 05:14:44 PM PDT 24
Peak memory 199916 kb
Host smart-b8539a0c-6ad2-406a-81bb-9d21432ff2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374458023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2374458023
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1832576609
Short name T1008
Test name
Test status
Simulation time 14532313537 ps
CPU time 25.22 seconds
Started Jul 07 05:14:28 PM PDT 24
Finished Jul 07 05:14:54 PM PDT 24
Peak memory 199980 kb
Host smart-b45e7b9f-9f83-4f51-99a6-d938c8312651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832576609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1832576609
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2249575536
Short name T303
Test name
Test status
Simulation time 102248216329 ps
CPU time 41.7 seconds
Started Jul 07 05:14:31 PM PDT 24
Finished Jul 07 05:15:13 PM PDT 24
Peak memory 199952 kb
Host smart-dd9fdc98-4903-4a0c-8373-97772819021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249575536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2249575536
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1222942567
Short name T952
Test name
Test status
Simulation time 46563365086 ps
CPU time 32.48 seconds
Started Jul 07 05:14:32 PM PDT 24
Finished Jul 07 05:15:05 PM PDT 24
Peak memory 199936 kb
Host smart-983d3649-4f3a-4604-9e40-755f9b877c6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222942567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1222942567
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3324371509
Short name T1100
Test name
Test status
Simulation time 86737070553 ps
CPU time 204.45 seconds
Started Jul 07 05:14:36 PM PDT 24
Finished Jul 07 05:18:01 PM PDT 24
Peak memory 199868 kb
Host smart-3d1a870b-6b98-4298-9e74-2f664c50d7a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324371509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3324371509
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3101130170
Short name T429
Test name
Test status
Simulation time 111428459 ps
CPU time 0.8 seconds
Started Jul 07 05:14:38 PM PDT 24
Finished Jul 07 05:14:39 PM PDT 24
Peak memory 195900 kb
Host smart-e6ccca31-04af-4951-8957-73ad901549bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101130170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3101130170
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2024073712
Short name T809
Test name
Test status
Simulation time 81493383854 ps
CPU time 465.57 seconds
Started Jul 07 05:14:32 PM PDT 24
Finished Jul 07 05:22:18 PM PDT 24
Peak memory 200228 kb
Host smart-630232f2-28ef-4ada-91d9-da5c287a8900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024073712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2024073712
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3681697706
Short name T305
Test name
Test status
Simulation time 7715116886 ps
CPU time 472.2 seconds
Started Jul 07 05:14:39 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 199936 kb
Host smart-2f86d9e7-6a99-4b2b-aeda-42cc8090dac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681697706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3681697706
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1089495905
Short name T425
Test name
Test status
Simulation time 2356114791 ps
CPU time 3.56 seconds
Started Jul 07 05:14:32 PM PDT 24
Finished Jul 07 05:14:36 PM PDT 24
Peak memory 198440 kb
Host smart-672a5ebd-4e79-4740-add5-216b883aa9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089495905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1089495905
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.987328681
Short name T1152
Test name
Test status
Simulation time 54458746639 ps
CPU time 81.59 seconds
Started Jul 07 05:14:34 PM PDT 24
Finished Jul 07 05:15:56 PM PDT 24
Peak memory 199944 kb
Host smart-990c1d8e-fa69-46cc-8ae2-b35178fd3109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987328681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.987328681
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.479906192
Short name T541
Test name
Test status
Simulation time 5692964376 ps
CPU time 2.98 seconds
Started Jul 07 05:14:33 PM PDT 24
Finished Jul 07 05:14:36 PM PDT 24
Peak memory 196068 kb
Host smart-6697d73a-a6d8-48ba-b0c5-1a939dc3776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479906192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.479906192
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3670997246
Short name T790
Test name
Test status
Simulation time 467898429 ps
CPU time 1.33 seconds
Started Jul 07 05:14:28 PM PDT 24
Finished Jul 07 05:14:30 PM PDT 24
Peak memory 199624 kb
Host smart-9df0dd43-44d0-454d-b3af-62143e587c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670997246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3670997246
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1547214223
Short name T835
Test name
Test status
Simulation time 389903660447 ps
CPU time 177.28 seconds
Started Jul 07 05:14:38 PM PDT 24
Finished Jul 07 05:17:36 PM PDT 24
Peak memory 199720 kb
Host smart-32a8452c-4fcf-4168-a517-99aa919fe1f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547214223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1547214223
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1508881871
Short name T79
Test name
Test status
Simulation time 207936909130 ps
CPU time 372.95 seconds
Started Jul 07 05:14:36 PM PDT 24
Finished Jul 07 05:20:49 PM PDT 24
Peak memory 216424 kb
Host smart-f6e331c4-b1e1-47c7-94a1-5ff5f15cae9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508881871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1508881871
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.929906982
Short name T1018
Test name
Test status
Simulation time 1883199081 ps
CPU time 1.59 seconds
Started Jul 07 05:14:39 PM PDT 24
Finished Jul 07 05:14:41 PM PDT 24
Peak memory 198256 kb
Host smart-13a61c77-e5e3-480d-8f5e-a16eb8cd216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929906982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.929906982
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1371756390
Short name T1043
Test name
Test status
Simulation time 71187381639 ps
CPU time 44.04 seconds
Started Jul 07 05:14:30 PM PDT 24
Finished Jul 07 05:15:14 PM PDT 24
Peak memory 199928 kb
Host smart-f37f477c-bd5a-47b3-affb-549ed02d167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371756390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1371756390
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1398958133
Short name T639
Test name
Test status
Simulation time 11586696 ps
CPU time 0.54 seconds
Started Jul 07 05:14:39 PM PDT 24
Finished Jul 07 05:14:40 PM PDT 24
Peak memory 195304 kb
Host smart-ee6b4016-cbe8-47e5-96e4-aada02b9e735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398958133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1398958133
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.864106213
Short name T990
Test name
Test status
Simulation time 107275465826 ps
CPU time 166 seconds
Started Jul 07 05:14:37 PM PDT 24
Finished Jul 07 05:17:23 PM PDT 24
Peak memory 199880 kb
Host smart-ab5dd2de-a165-469c-88b6-b01de5c96120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864106213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.864106213
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1056583191
Short name T1051
Test name
Test status
Simulation time 124774302092 ps
CPU time 30.94 seconds
Started Jul 07 05:14:36 PM PDT 24
Finished Jul 07 05:15:07 PM PDT 24
Peak memory 199964 kb
Host smart-301a25d3-4bc8-459d-99ad-77347980eeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056583191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1056583191
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.505227849
Short name T187
Test name
Test status
Simulation time 28239063753 ps
CPU time 46.98 seconds
Started Jul 07 05:14:38 PM PDT 24
Finished Jul 07 05:15:25 PM PDT 24
Peak memory 199964 kb
Host smart-4aff85b7-2ffc-40bc-a5ca-12b61b70a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505227849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.505227849
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.8669880
Short name T374
Test name
Test status
Simulation time 194523494915 ps
CPU time 24.27 seconds
Started Jul 07 05:14:37 PM PDT 24
Finished Jul 07 05:15:02 PM PDT 24
Peak memory 199324 kb
Host smart-36dd51d6-aca4-4d08-853a-6cf19af96828
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8669880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.8669880
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3581162882
Short name T788
Test name
Test status
Simulation time 114473786503 ps
CPU time 413.15 seconds
Started Jul 07 05:14:40 PM PDT 24
Finished Jul 07 05:21:33 PM PDT 24
Peak memory 199920 kb
Host smart-bfea5946-b23e-4619-b4ef-18b422835803
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581162882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3581162882
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.420457211
Short name T1141
Test name
Test status
Simulation time 3788616549 ps
CPU time 8.95 seconds
Started Jul 07 05:14:41 PM PDT 24
Finished Jul 07 05:14:50 PM PDT 24
Peak memory 199820 kb
Host smart-8c0a40b1-0797-41bc-9676-9b9079d80f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420457211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.420457211
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.276421144
Short name T114
Test name
Test status
Simulation time 48066468587 ps
CPU time 24.48 seconds
Started Jul 07 05:14:40 PM PDT 24
Finished Jul 07 05:15:05 PM PDT 24
Peak memory 198852 kb
Host smart-34d5e1f0-51cc-41a3-8772-5424dae5961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276421144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.276421144
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1972325547
Short name T811
Test name
Test status
Simulation time 15651358126 ps
CPU time 224.23 seconds
Started Jul 07 05:14:40 PM PDT 24
Finished Jul 07 05:18:24 PM PDT 24
Peak memory 199876 kb
Host smart-7eeec077-b93d-4331-8a14-e079fc2d7d99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972325547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1972325547
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.4249508208
Short name T16
Test name
Test status
Simulation time 5076466872 ps
CPU time 11.06 seconds
Started Jul 07 05:14:38 PM PDT 24
Finished Jul 07 05:14:49 PM PDT 24
Peak memory 199008 kb
Host smart-62d3132c-96a5-4913-8c80-fcd88eb9faea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249508208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4249508208
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.577684874
Short name T555
Test name
Test status
Simulation time 149553506583 ps
CPU time 56.1 seconds
Started Jul 07 05:14:39 PM PDT 24
Finished Jul 07 05:15:36 PM PDT 24
Peak memory 199880 kb
Host smart-ff72f97e-7e85-46c7-9a2d-c9dcab7390a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577684874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.577684874
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3014865476
Short name T606
Test name
Test status
Simulation time 4796771144 ps
CPU time 3.87 seconds
Started Jul 07 05:14:36 PM PDT 24
Finished Jul 07 05:14:40 PM PDT 24
Peak memory 196212 kb
Host smart-8cf8ba7b-f049-4f12-8a9c-b0a7fd4650a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014865476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3014865476
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2984387008
Short name T41
Test name
Test status
Simulation time 655074400 ps
CPU time 1.56 seconds
Started Jul 07 05:14:36 PM PDT 24
Finished Jul 07 05:14:37 PM PDT 24
Peak memory 198712 kb
Host smart-08cd711f-3f71-4fec-b58f-43a0d93006b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984387008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2984387008
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.77894585
Short name T439
Test name
Test status
Simulation time 146780834379 ps
CPU time 130.63 seconds
Started Jul 07 05:15:03 PM PDT 24
Finished Jul 07 05:17:14 PM PDT 24
Peak memory 199808 kb
Host smart-f93973f4-61fc-4333-a629-9c3bd3a1fc72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77894585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.77894585
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2365822324
Short name T801
Test name
Test status
Simulation time 844536890856 ps
CPU time 892.74 seconds
Started Jul 07 05:14:39 PM PDT 24
Finished Jul 07 05:29:33 PM PDT 24
Peak memory 224916 kb
Host smart-a41dccaf-7ab5-4a83-b05d-0f0440ba8ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365822324 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2365822324
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4000809907
Short name T905
Test name
Test status
Simulation time 687016937 ps
CPU time 2.16 seconds
Started Jul 07 05:14:38 PM PDT 24
Finished Jul 07 05:14:41 PM PDT 24
Peak memory 199024 kb
Host smart-b54c2fe4-4961-4bca-9c23-ac41db925d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000809907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4000809907
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1887760960
Short name T1158
Test name
Test status
Simulation time 7503952515 ps
CPU time 12.96 seconds
Started Jul 07 05:14:37 PM PDT 24
Finished Jul 07 05:14:50 PM PDT 24
Peak memory 199688 kb
Host smart-df675e24-3c7e-4fb4-bd91-d7ca6a657c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887760960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1887760960
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.251071427
Short name T680
Test name
Test status
Simulation time 12435397 ps
CPU time 0.55 seconds
Started Jul 07 05:14:45 PM PDT 24
Finished Jul 07 05:14:46 PM PDT 24
Peak memory 194520 kb
Host smart-294a501c-74c2-4100-a5a8-d4e92f0c4a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251071427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.251071427
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2786284276
Short name T110
Test name
Test status
Simulation time 146633044973 ps
CPU time 196 seconds
Started Jul 07 05:14:44 PM PDT 24
Finished Jul 07 05:18:00 PM PDT 24
Peak memory 199908 kb
Host smart-d3c4dad7-952f-47f1-9851-9919b2f8ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786284276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2786284276
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3937938252
Short name T141
Test name
Test status
Simulation time 35759457186 ps
CPU time 12.12 seconds
Started Jul 07 05:14:44 PM PDT 24
Finished Jul 07 05:14:57 PM PDT 24
Peak memory 199840 kb
Host smart-c55bb000-4f87-4648-8be9-1ac5b21b9952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937938252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3937938252
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1785848742
Short name T289
Test name
Test status
Simulation time 16261304364 ps
CPU time 27.4 seconds
Started Jul 07 05:14:43 PM PDT 24
Finished Jul 07 05:15:11 PM PDT 24
Peak memory 199848 kb
Host smart-ea7eff31-3297-48ed-b889-8875b51a06d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785848742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1785848742
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1043305341
Short name T1031
Test name
Test status
Simulation time 3252481186 ps
CPU time 4.74 seconds
Started Jul 07 05:14:43 PM PDT 24
Finished Jul 07 05:14:48 PM PDT 24
Peak memory 196692 kb
Host smart-6186fcc0-b8be-46e2-8a24-591cfece9637
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043305341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1043305341
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1419644749
Short name T413
Test name
Test status
Simulation time 88408282357 ps
CPU time 255.35 seconds
Started Jul 07 05:14:44 PM PDT 24
Finished Jul 07 05:19:00 PM PDT 24
Peak memory 200176 kb
Host smart-b9bc4936-964f-48f1-a516-5d2ccc0117e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419644749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1419644749
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2997309792
Short name T1050
Test name
Test status
Simulation time 8816337536 ps
CPU time 10.04 seconds
Started Jul 07 05:14:46 PM PDT 24
Finished Jul 07 05:14:56 PM PDT 24
Peak memory 199332 kb
Host smart-41875c18-f87c-46f5-91ed-fba77f88d463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997309792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2997309792
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3417015583
Short name T273
Test name
Test status
Simulation time 133247017583 ps
CPU time 89.89 seconds
Started Jul 07 05:14:43 PM PDT 24
Finished Jul 07 05:16:14 PM PDT 24
Peak memory 200088 kb
Host smart-81927c3c-404e-4d16-8b2e-98f52f5d804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417015583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3417015583
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1416278039
Short name T432
Test name
Test status
Simulation time 19523786909 ps
CPU time 873.43 seconds
Started Jul 07 05:14:46 PM PDT 24
Finished Jul 07 05:29:20 PM PDT 24
Peak memory 199900 kb
Host smart-cca2f20e-a15a-4cf6-aaa3-074b3753d6ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416278039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1416278039
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.4180449823
Short name T886
Test name
Test status
Simulation time 1596655441 ps
CPU time 1.71 seconds
Started Jul 07 05:14:44 PM PDT 24
Finished Jul 07 05:14:46 PM PDT 24
Peak memory 198488 kb
Host smart-d510db69-ede3-43e1-ac1f-9fd810ba8438
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180449823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.4180449823
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.694986516
Short name T153
Test name
Test status
Simulation time 48934780157 ps
CPU time 23.92 seconds
Started Jul 07 05:14:45 PM PDT 24
Finished Jul 07 05:15:09 PM PDT 24
Peak memory 199912 kb
Host smart-4c0d6406-c20f-4417-9b68-753ec60ba918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694986516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.694986516
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1132667687
Short name T616
Test name
Test status
Simulation time 42552138821 ps
CPU time 64.06 seconds
Started Jul 07 05:14:47 PM PDT 24
Finished Jul 07 05:15:51 PM PDT 24
Peak memory 196404 kb
Host smart-33b442eb-5304-4b32-98ae-2a6ced9e8df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132667687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1132667687
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3019523066
Short name T297
Test name
Test status
Simulation time 473033252 ps
CPU time 2.18 seconds
Started Jul 07 05:14:41 PM PDT 24
Finished Jul 07 05:14:44 PM PDT 24
Peak memory 199816 kb
Host smart-88805598-7836-4c0f-8dd6-b3bafb6f986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019523066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3019523066
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2657640088
Short name T1042
Test name
Test status
Simulation time 78005374121 ps
CPU time 75.15 seconds
Started Jul 07 05:14:44 PM PDT 24
Finished Jul 07 05:15:59 PM PDT 24
Peak memory 199884 kb
Host smart-3e3f61a7-e391-4d91-81ab-f577aed77240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657640088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2657640088
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2353868264
Short name T95
Test name
Test status
Simulation time 133018867566 ps
CPU time 199.59 seconds
Started Jul 07 05:14:46 PM PDT 24
Finished Jul 07 05:18:06 PM PDT 24
Peak memory 216476 kb
Host smart-14a649c2-65be-4d06-8e26-7ee2102d760b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353868264 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2353868264
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1112399346
Short name T618
Test name
Test status
Simulation time 5743755998 ps
CPU time 1.97 seconds
Started Jul 07 05:14:46 PM PDT 24
Finished Jul 07 05:14:48 PM PDT 24
Peak memory 198640 kb
Host smart-fe076317-d2ab-488a-8666-68ae90c2f812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112399346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1112399346
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3340240205
Short name T296
Test name
Test status
Simulation time 55913643713 ps
CPU time 73.51 seconds
Started Jul 07 05:14:45 PM PDT 24
Finished Jul 07 05:15:59 PM PDT 24
Peak memory 199880 kb
Host smart-e38e2f9f-88e8-4541-8752-34cf45102121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340240205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3340240205
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3749640032
Short name T970
Test name
Test status
Simulation time 42031831 ps
CPU time 0.55 seconds
Started Jul 07 05:14:56 PM PDT 24
Finished Jul 07 05:14:57 PM PDT 24
Peak memory 195304 kb
Host smart-6d589a14-7ad4-41ac-8dde-6607e4569ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749640032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3749640032
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.679170926
Short name T182
Test name
Test status
Simulation time 306107620502 ps
CPU time 204.35 seconds
Started Jul 07 05:14:51 PM PDT 24
Finished Jul 07 05:18:16 PM PDT 24
Peak memory 200000 kb
Host smart-3df0580f-8fc3-4d0c-be5f-a8dfb788ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679170926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.679170926
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2515344801
Short name T883
Test name
Test status
Simulation time 126271436196 ps
CPU time 248.23 seconds
Started Jul 07 05:14:50 PM PDT 24
Finished Jul 07 05:18:59 PM PDT 24
Peak memory 199872 kb
Host smart-620b0185-aa23-410d-843f-66aac0cd7e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515344801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2515344801
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3385508913
Short name T222
Test name
Test status
Simulation time 55523992769 ps
CPU time 62.02 seconds
Started Jul 07 05:14:51 PM PDT 24
Finished Jul 07 05:15:53 PM PDT 24
Peak memory 199952 kb
Host smart-e76d965f-1bcf-493c-8bf3-a88d18e737cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385508913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3385508913
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1250174406
Short name T690
Test name
Test status
Simulation time 385077944993 ps
CPU time 150 seconds
Started Jul 07 05:14:49 PM PDT 24
Finished Jul 07 05:17:20 PM PDT 24
Peak memory 199312 kb
Host smart-98bfacfe-6c8b-443c-9c97-9b2f333c8ebc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250174406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1250174406
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3951393102
Short name T1176
Test name
Test status
Simulation time 83226446637 ps
CPU time 456.97 seconds
Started Jul 07 05:14:55 PM PDT 24
Finished Jul 07 05:22:32 PM PDT 24
Peak memory 199872 kb
Host smart-a0ba8c40-2ef9-42e3-9e9f-0e713c9cb6e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951393102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3951393102
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3309082971
Short name T375
Test name
Test status
Simulation time 9411415212 ps
CPU time 21.19 seconds
Started Jul 07 05:14:49 PM PDT 24
Finished Jul 07 05:15:11 PM PDT 24
Peak memory 199348 kb
Host smart-6fdc2f67-77ab-49b5-b9f3-8307723327a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309082971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3309082971
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.992586754
Short name T441
Test name
Test status
Simulation time 115565992096 ps
CPU time 167.08 seconds
Started Jul 07 05:14:52 PM PDT 24
Finished Jul 07 05:17:40 PM PDT 24
Peak memory 200096 kb
Host smart-66a81263-243d-4685-8a71-28effaf6512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992586754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.992586754
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1324614063
Short name T356
Test name
Test status
Simulation time 7695763422 ps
CPU time 475.57 seconds
Started Jul 07 05:14:54 PM PDT 24
Finished Jul 07 05:22:50 PM PDT 24
Peak memory 199928 kb
Host smart-c0ee18a8-a7c6-492d-86ee-73e4bedf7462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324614063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1324614063
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3804094911
Short name T807
Test name
Test status
Simulation time 4760367020 ps
CPU time 6.48 seconds
Started Jul 07 05:14:48 PM PDT 24
Finished Jul 07 05:14:55 PM PDT 24
Peak memory 198784 kb
Host smart-1ed76b9d-c07b-49fc-84c6-eb33451a71e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804094911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3804094911
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.132546141
Short name T914
Test name
Test status
Simulation time 62409258891 ps
CPU time 25.69 seconds
Started Jul 07 05:14:50 PM PDT 24
Finished Jul 07 05:15:16 PM PDT 24
Peak memory 199828 kb
Host smart-b1ff33bd-7344-4a69-9296-247b24be4c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132546141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.132546141
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2160282929
Short name T285
Test name
Test status
Simulation time 4737006576 ps
CPU time 2.1 seconds
Started Jul 07 05:14:49 PM PDT 24
Finished Jul 07 05:14:51 PM PDT 24
Peak memory 196404 kb
Host smart-a294d965-4a36-464c-b3cc-c7223482d5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160282929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2160282929
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.945130657
Short name T602
Test name
Test status
Simulation time 479006680 ps
CPU time 2.15 seconds
Started Jul 07 05:14:49 PM PDT 24
Finished Jul 07 05:14:52 PM PDT 24
Peak memory 199664 kb
Host smart-90b061ca-308d-4737-8f48-d81a0736d49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945130657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.945130657
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.573728297
Short name T923
Test name
Test status
Simulation time 210096277018 ps
CPU time 183.28 seconds
Started Jul 07 05:14:53 PM PDT 24
Finished Jul 07 05:17:57 PM PDT 24
Peak memory 208192 kb
Host smart-6259f2f8-135b-4f62-a022-59065e1a7dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573728297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.573728297
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1316176723
Short name T118
Test name
Test status
Simulation time 48508514623 ps
CPU time 440.99 seconds
Started Jul 07 05:14:54 PM PDT 24
Finished Jul 07 05:22:16 PM PDT 24
Peak memory 216628 kb
Host smart-d9c07d11-5829-4b40-9f02-9749cd1afb81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316176723 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1316176723
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.613706546
Short name T640
Test name
Test status
Simulation time 817789411 ps
CPU time 2.1 seconds
Started Jul 07 05:14:50 PM PDT 24
Finished Jul 07 05:14:52 PM PDT 24
Peak memory 198244 kb
Host smart-240b3ecc-f77e-4411-9684-5db3a0df57f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613706546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.613706546
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.16404212
Short name T877
Test name
Test status
Simulation time 12814514456 ps
CPU time 10.52 seconds
Started Jul 07 05:14:49 PM PDT 24
Finished Jul 07 05:15:00 PM PDT 24
Peak memory 199908 kb
Host smart-fc205355-02ae-4162-80f4-2953bf218049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16404212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.16404212
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1541430830
Short name T334
Test name
Test status
Simulation time 11095399 ps
CPU time 0.54 seconds
Started Jul 07 05:15:00 PM PDT 24
Finished Jul 07 05:15:01 PM PDT 24
Peak memory 195588 kb
Host smart-720f4c83-63c6-46ee-adf9-76e64fc6834b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541430830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1541430830
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3970581125
Short name T968
Test name
Test status
Simulation time 198053746171 ps
CPU time 22.36 seconds
Started Jul 07 05:14:52 PM PDT 24
Finished Jul 07 05:15:15 PM PDT 24
Peak memory 199984 kb
Host smart-2b696b87-3195-456b-84db-a27b52347802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970581125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3970581125
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.520459939
Short name T884
Test name
Test status
Simulation time 112808949506 ps
CPU time 250.64 seconds
Started Jul 07 05:14:54 PM PDT 24
Finished Jul 07 05:19:05 PM PDT 24
Peak memory 199912 kb
Host smart-3c19b666-3344-4fbb-b037-0c0a3dd9ae0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520459939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.520459939
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2627896911
Short name T213
Test name
Test status
Simulation time 55071645079 ps
CPU time 47.35 seconds
Started Jul 07 05:14:54 PM PDT 24
Finished Jul 07 05:15:42 PM PDT 24
Peak memory 199940 kb
Host smart-769342b9-d031-4365-9822-0f874cbfca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627896911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2627896911
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2390801497
Short name T1103
Test name
Test status
Simulation time 217116326629 ps
CPU time 63.43 seconds
Started Jul 07 05:14:53 PM PDT 24
Finished Jul 07 05:15:56 PM PDT 24
Peak memory 199792 kb
Host smart-0b774e41-c020-4787-b298-73d53e83f5b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390801497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2390801497
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.439505526
Short name T531
Test name
Test status
Simulation time 89328824489 ps
CPU time 188.34 seconds
Started Jul 07 05:14:57 PM PDT 24
Finished Jul 07 05:18:05 PM PDT 24
Peak memory 199828 kb
Host smart-5b8fc7ab-3f5f-426d-963d-d8e4a67ae7c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439505526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.439505526
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.739667633
Short name T311
Test name
Test status
Simulation time 5866373489 ps
CPU time 7.48 seconds
Started Jul 07 05:14:56 PM PDT 24
Finished Jul 07 05:15:04 PM PDT 24
Peak memory 199952 kb
Host smart-490b0b58-dbba-4596-b7ff-810f839564df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739667633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.739667633
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3231775635
Short name T449
Test name
Test status
Simulation time 23003958305 ps
CPU time 9.3 seconds
Started Jul 07 05:14:55 PM PDT 24
Finished Jul 07 05:15:05 PM PDT 24
Peak memory 199880 kb
Host smart-a30d9457-69d9-4eaa-8a67-0847cc1761ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231775635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3231775635
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2043099429
Short name T258
Test name
Test status
Simulation time 6376347582 ps
CPU time 339.42 seconds
Started Jul 07 05:14:58 PM PDT 24
Finished Jul 07 05:20:37 PM PDT 24
Peak memory 199956 kb
Host smart-b85b4b2f-1359-444d-a5a2-8ae8d46896f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043099429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2043099429
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.77209185
Short name T440
Test name
Test status
Simulation time 5471062912 ps
CPU time 11.53 seconds
Started Jul 07 05:14:55 PM PDT 24
Finished Jul 07 05:15:06 PM PDT 24
Peak memory 198856 kb
Host smart-e7078fb7-3e50-48d8-8949-5a1b59f6a4af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77209185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.77209185
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1390239338
Short name T7
Test name
Test status
Simulation time 85350419355 ps
CPU time 33.72 seconds
Started Jul 07 05:14:54 PM PDT 24
Finished Jul 07 05:15:28 PM PDT 24
Peak memory 199640 kb
Host smart-c2e8dc1b-aef4-457e-9577-12f4c18e8b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390239338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1390239338
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3971574855
Short name T522
Test name
Test status
Simulation time 3857701598 ps
CPU time 6.51 seconds
Started Jul 07 05:14:55 PM PDT 24
Finished Jul 07 05:15:02 PM PDT 24
Peak memory 196668 kb
Host smart-2c5082fe-0827-4fdb-86ab-44c52cb2fe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971574855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3971574855
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2341911681
Short name T839
Test name
Test status
Simulation time 104069809 ps
CPU time 0.95 seconds
Started Jul 07 05:14:53 PM PDT 24
Finished Jul 07 05:14:54 PM PDT 24
Peak memory 198460 kb
Host smart-7f92981c-c2c0-4ad3-82c5-126b3e0e2df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341911681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2341911681
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2088346122
Short name T1146
Test name
Test status
Simulation time 179824066353 ps
CPU time 1233.33 seconds
Started Jul 07 05:14:58 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 199892 kb
Host smart-665f6885-3766-45ca-8217-45e7bbb71a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088346122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2088346122
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2546908597
Short name T69
Test name
Test status
Simulation time 472330485833 ps
CPU time 700.61 seconds
Started Jul 07 05:14:59 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 227232 kb
Host smart-d3d0c3b5-2f52-4427-8389-0f5a3ab38840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546908597 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2546908597
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4123880242
Short name T355
Test name
Test status
Simulation time 2934877825 ps
CPU time 1.47 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:15:04 PM PDT 24
Peak memory 198752 kb
Host smart-b663610c-1b34-426d-b704-0e888cd4246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123880242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4123880242
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3803446213
Short name T1038
Test name
Test status
Simulation time 14063973400 ps
CPU time 23.05 seconds
Started Jul 07 05:14:56 PM PDT 24
Finished Jul 07 05:15:19 PM PDT 24
Peak memory 199996 kb
Host smart-f093e924-a215-428f-a741-49d811a73bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803446213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3803446213
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.423933208
Short name T76
Test name
Test status
Simulation time 46377698 ps
CPU time 0.59 seconds
Started Jul 07 05:15:03 PM PDT 24
Finished Jul 07 05:15:03 PM PDT 24
Peak memory 195300 kb
Host smart-29be625b-0f40-4cba-a6b0-95c3608abbfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423933208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.423933208
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1363040913
Short name T791
Test name
Test status
Simulation time 50553382743 ps
CPU time 37.71 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:15:40 PM PDT 24
Peak memory 199912 kb
Host smart-2da22076-e73a-44ce-9217-28f6a52fd693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363040913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1363040913
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2972033279
Short name T995
Test name
Test status
Simulation time 117598253595 ps
CPU time 105.18 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:16:47 PM PDT 24
Peak memory 199860 kb
Host smart-3fb73e67-a2ce-487f-9f6e-9e7020466a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972033279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2972033279
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.186578163
Short name T778
Test name
Test status
Simulation time 8654913889 ps
CPU time 8.91 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:15:11 PM PDT 24
Peak memory 199976 kb
Host smart-8862c848-d62d-4f06-b539-b3a7b0f3d754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186578163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.186578163
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3914979580
Short name T1037
Test name
Test status
Simulation time 148534414542 ps
CPU time 100.94 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:16:43 PM PDT 24
Peak memory 199896 kb
Host smart-6aafa113-ae26-4024-90b1-143a7ae6d8af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914979580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3914979580
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1799452285
Short name T424
Test name
Test status
Simulation time 92521370024 ps
CPU time 548.1 seconds
Started Jul 07 05:15:03 PM PDT 24
Finished Jul 07 05:24:12 PM PDT 24
Peak memory 199924 kb
Host smart-44cc4caa-d34b-4921-80a5-b751afb648fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799452285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1799452285
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2051843309
Short name T829
Test name
Test status
Simulation time 5011193644 ps
CPU time 9.52 seconds
Started Jul 07 05:15:04 PM PDT 24
Finished Jul 07 05:15:14 PM PDT 24
Peak memory 199628 kb
Host smart-f8896fe1-0ddb-4059-89e1-bf13afa5617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051843309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2051843309
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2711155060
Short name T1027
Test name
Test status
Simulation time 91598962493 ps
CPU time 54.71 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:17:15 PM PDT 24
Peak memory 200144 kb
Host smart-6333eb33-17c6-4b36-a268-313f2054c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711155060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2711155060
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1931404793
Short name T1074
Test name
Test status
Simulation time 20859794077 ps
CPU time 195.39 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:18:17 PM PDT 24
Peak memory 199904 kb
Host smart-d3dcac44-e3ac-4cf9-8b73-21067b180288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931404793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1931404793
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1678132700
Short name T109
Test name
Test status
Simulation time 6897619394 ps
CPU time 16.54 seconds
Started Jul 07 05:14:58 PM PDT 24
Finished Jul 07 05:15:15 PM PDT 24
Peak memory 198016 kb
Host smart-24de02b5-8a25-4760-9b2f-470e4bc7d957
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678132700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1678132700
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.817393749
Short name T851
Test name
Test status
Simulation time 63866331139 ps
CPU time 102 seconds
Started Jul 07 05:15:03 PM PDT 24
Finished Jul 07 05:16:45 PM PDT 24
Peak memory 199844 kb
Host smart-8f651847-9091-45f4-8590-5fecedf48084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817393749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.817393749
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.429469961
Short name T554
Test name
Test status
Simulation time 5124431680 ps
CPU time 1.12 seconds
Started Jul 07 05:15:10 PM PDT 24
Finished Jul 07 05:15:11 PM PDT 24
Peak memory 196408 kb
Host smart-c16b171b-b5aa-4c2d-b1ce-60f414f16f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429469961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.429469961
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2010456680
Short name T49
Test name
Test status
Simulation time 5687141196 ps
CPU time 8.66 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:15:11 PM PDT 24
Peak memory 199692 kb
Host smart-7099a96f-96ec-4507-9da7-82c575cba566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010456680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2010456680
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2590429302
Short name T390
Test name
Test status
Simulation time 272515422051 ps
CPU time 394.05 seconds
Started Jul 07 05:15:10 PM PDT 24
Finished Jul 07 05:21:44 PM PDT 24
Peak memory 199948 kb
Host smart-5b6ff5b9-e0ac-45a3-8a33-314ce58e333e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590429302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2590429302
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3337529293
Short name T61
Test name
Test status
Simulation time 315607966741 ps
CPU time 1103.22 seconds
Started Jul 07 05:15:03 PM PDT 24
Finished Jul 07 05:33:27 PM PDT 24
Peak memory 224860 kb
Host smart-1c64a362-9ef1-4f79-bf03-807865acfe14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337529293 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3337529293
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3707322409
Short name T878
Test name
Test status
Simulation time 3968546284 ps
CPU time 1.8 seconds
Started Jul 07 05:15:03 PM PDT 24
Finished Jul 07 05:15:05 PM PDT 24
Peak memory 198892 kb
Host smart-c9a8c8ab-0493-4838-ac3b-4f08809d8aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707322409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3707322409
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1913742411
Short name T5
Test name
Test status
Simulation time 146356979914 ps
CPU time 40.49 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:15:43 PM PDT 24
Peak memory 199924 kb
Host smart-15606519-85e3-4dba-8462-696e860922ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913742411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1913742411
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1732616573
Short name T975
Test name
Test status
Simulation time 34517199 ps
CPU time 0.56 seconds
Started Jul 07 05:15:12 PM PDT 24
Finished Jul 07 05:15:13 PM PDT 24
Peak memory 194872 kb
Host smart-ef5bfa54-0cf4-48af-a135-597bd599c367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732616573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1732616573
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2818473593
Short name T488
Test name
Test status
Simulation time 34748399491 ps
CPU time 16.7 seconds
Started Jul 07 05:15:04 PM PDT 24
Finished Jul 07 05:15:21 PM PDT 24
Peak memory 199972 kb
Host smart-72fb37f3-15ca-48cb-9f5d-9fb9f427f71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818473593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2818473593
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4258357638
Short name T176
Test name
Test status
Simulation time 82905024293 ps
CPU time 74.12 seconds
Started Jul 07 05:15:10 PM PDT 24
Finished Jul 07 05:16:25 PM PDT 24
Peak memory 199908 kb
Host smart-97ff2afb-0124-40d1-a343-bdd61c0545c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258357638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4258357638
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1279827262
Short name T427
Test name
Test status
Simulation time 125536024601 ps
CPU time 58.47 seconds
Started Jul 07 05:15:11 PM PDT 24
Finished Jul 07 05:16:10 PM PDT 24
Peak memory 199916 kb
Host smart-08330153-a2e1-4889-b82f-4930c169d544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279827262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1279827262
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3746220000
Short name T730
Test name
Test status
Simulation time 54264146766 ps
CPU time 43.49 seconds
Started Jul 07 05:15:08 PM PDT 24
Finished Jul 07 05:15:51 PM PDT 24
Peak memory 199964 kb
Host smart-8141c1a0-759a-49e9-a3f0-cf9bbbb7eac9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746220000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3746220000
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1111662385
Short name T672
Test name
Test status
Simulation time 103564556777 ps
CPU time 439.37 seconds
Started Jul 07 05:15:13 PM PDT 24
Finished Jul 07 05:22:33 PM PDT 24
Peak memory 199916 kb
Host smart-f6cb1907-c253-4af0-a08f-6f4887ce1aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1111662385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1111662385
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2591300732
Short name T387
Test name
Test status
Simulation time 8411660126 ps
CPU time 6.36 seconds
Started Jul 07 05:15:13 PM PDT 24
Finished Jul 07 05:15:20 PM PDT 24
Peak memory 199884 kb
Host smart-292df450-2e62-44c9-9ee1-32947f3e2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591300732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2591300732
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2046297003
Short name T766
Test name
Test status
Simulation time 53911393126 ps
CPU time 111.94 seconds
Started Jul 07 05:15:06 PM PDT 24
Finished Jul 07 05:16:58 PM PDT 24
Peak memory 200020 kb
Host smart-1fb98cda-4c0f-4354-8552-cc152b7bde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046297003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2046297003
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1388100625
Short name T823
Test name
Test status
Simulation time 6972083514 ps
CPU time 363.65 seconds
Started Jul 07 05:15:11 PM PDT 24
Finished Jul 07 05:21:15 PM PDT 24
Peak memory 199964 kb
Host smart-b457c345-823e-4e03-9377-531c8b0d393b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388100625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1388100625
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2323734401
Short name T386
Test name
Test status
Simulation time 3730962945 ps
CPU time 29.48 seconds
Started Jul 07 05:15:11 PM PDT 24
Finished Jul 07 05:15:41 PM PDT 24
Peak memory 198508 kb
Host smart-d4584fa5-9fa0-4ded-b8c5-ef8b019655ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323734401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2323734401
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.532806684
Short name T702
Test name
Test status
Simulation time 19434779698 ps
CPU time 35.15 seconds
Started Jul 07 05:15:07 PM PDT 24
Finished Jul 07 05:15:42 PM PDT 24
Peak memory 199980 kb
Host smart-82f848f9-4d08-43fd-8c6d-f1a2bce9f42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532806684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.532806684
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1958678106
Short name T925
Test name
Test status
Simulation time 599570368 ps
CPU time 1.53 seconds
Started Jul 07 05:15:06 PM PDT 24
Finished Jul 07 05:15:08 PM PDT 24
Peak memory 195508 kb
Host smart-28d4aefe-809b-4e2d-a25e-71aba4ef15ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958678106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1958678106
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2810613747
Short name T575
Test name
Test status
Simulation time 280140599 ps
CPU time 1.45 seconds
Started Jul 07 05:15:10 PM PDT 24
Finished Jul 07 05:15:12 PM PDT 24
Peak memory 199464 kb
Host smart-bde15fdc-46eb-4f4f-a4b7-d2915d02f6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810613747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2810613747
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2070917358
Short name T899
Test name
Test status
Simulation time 62801602419 ps
CPU time 498.23 seconds
Started Jul 07 05:15:12 PM PDT 24
Finished Jul 07 05:23:30 PM PDT 24
Peak memory 199964 kb
Host smart-c710a196-1543-4789-bead-8cd477dd41d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070917358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2070917358
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3619068873
Short name T810
Test name
Test status
Simulation time 29225232424 ps
CPU time 377.59 seconds
Started Jul 07 05:15:10 PM PDT 24
Finished Jul 07 05:21:28 PM PDT 24
Peak memory 216408 kb
Host smart-0eaca0d2-2408-4f37-89fd-6eb6b81a9f18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619068873 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3619068873
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1214473978
Short name T822
Test name
Test status
Simulation time 6177658848 ps
CPU time 16.22 seconds
Started Jul 07 05:15:06 PM PDT 24
Finished Jul 07 05:15:22 PM PDT 24
Peak memory 199684 kb
Host smart-0ad18236-3a94-447b-9a6d-839e10688c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214473978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1214473978
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2499699888
Short name T380
Test name
Test status
Simulation time 6839711902 ps
CPU time 10.96 seconds
Started Jul 07 05:15:02 PM PDT 24
Finished Jul 07 05:15:14 PM PDT 24
Peak memory 197576 kb
Host smart-e3e2d44c-1e01-4ad7-b4fa-f9850f44b9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499699888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2499699888
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.594640238
Short name T511
Test name
Test status
Simulation time 14369288 ps
CPU time 0.54 seconds
Started Jul 07 05:15:14 PM PDT 24
Finished Jul 07 05:15:15 PM PDT 24
Peak memory 195200 kb
Host smart-a6039db9-0764-44f4-a107-7060a44e2ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594640238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.594640238
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1197475781
Short name T828
Test name
Test status
Simulation time 32353041781 ps
CPU time 52.73 seconds
Started Jul 07 05:15:12 PM PDT 24
Finished Jul 07 05:16:05 PM PDT 24
Peak memory 199904 kb
Host smart-8cdd360c-923f-4e56-b8ef-f41b7de1f65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197475781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1197475781
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.4033340866
Short name T259
Test name
Test status
Simulation time 247190452830 ps
CPU time 76.1 seconds
Started Jul 07 05:15:12 PM PDT 24
Finished Jul 07 05:16:28 PM PDT 24
Peak memory 199892 kb
Host smart-889dcb00-e344-4628-82d8-69da0bb8ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033340866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.4033340866
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.150638160
Short name T1041
Test name
Test status
Simulation time 15673565551 ps
CPU time 15.59 seconds
Started Jul 07 05:15:11 PM PDT 24
Finished Jul 07 05:15:27 PM PDT 24
Peak memory 199936 kb
Host smart-0c75d94b-70f6-4405-bb23-d6e7053e8310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150638160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.150638160
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3085002181
Short name T786
Test name
Test status
Simulation time 29923592629 ps
CPU time 14.14 seconds
Started Jul 07 05:15:14 PM PDT 24
Finished Jul 07 05:15:28 PM PDT 24
Peak memory 199924 kb
Host smart-6facb48c-2fb0-4ae4-95a2-23aa1efc6d4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085002181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3085002181
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.807859269
Short name T978
Test name
Test status
Simulation time 108297269445 ps
CPU time 560.94 seconds
Started Jul 07 05:15:15 PM PDT 24
Finished Jul 07 05:24:36 PM PDT 24
Peak memory 199880 kb
Host smart-cab4481a-d4ed-4deb-8a11-b4446c0181da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807859269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.807859269
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3573358992
Short name T945
Test name
Test status
Simulation time 4121322915 ps
CPU time 4.03 seconds
Started Jul 07 05:15:15 PM PDT 24
Finished Jul 07 05:15:19 PM PDT 24
Peak memory 199732 kb
Host smart-2795f312-7dc5-49cb-8371-210161abc5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573358992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3573358992
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.4010311344
Short name T497
Test name
Test status
Simulation time 105364348437 ps
CPU time 123.4 seconds
Started Jul 07 05:15:10 PM PDT 24
Finished Jul 07 05:17:14 PM PDT 24
Peak memory 200148 kb
Host smart-6896938e-07b7-4467-be1d-663769334b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010311344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.4010311344
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4126399680
Short name T1084
Test name
Test status
Simulation time 1597433039 ps
CPU time 49.68 seconds
Started Jul 07 05:15:17 PM PDT 24
Finished Jul 07 05:16:07 PM PDT 24
Peak memory 199844 kb
Host smart-36073c56-7e1e-4ed3-9f63-41e513a32788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126399680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4126399680
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3820922940
Short name T782
Test name
Test status
Simulation time 4130919503 ps
CPU time 32.01 seconds
Started Jul 07 05:15:11 PM PDT 24
Finished Jul 07 05:15:43 PM PDT 24
Peak memory 197884 kb
Host smart-3e5203d1-4a60-4367-a990-1a4569889367
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820922940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3820922940
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2952699271
Short name T338
Test name
Test status
Simulation time 18760378061 ps
CPU time 31.62 seconds
Started Jul 07 05:15:14 PM PDT 24
Finished Jul 07 05:15:46 PM PDT 24
Peak memory 199840 kb
Host smart-33e265df-2c5b-44fd-9e93-e065460d8910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952699271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2952699271
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.453283172
Short name T664
Test name
Test status
Simulation time 5586269282 ps
CPU time 7.97 seconds
Started Jul 07 05:15:15 PM PDT 24
Finished Jul 07 05:15:24 PM PDT 24
Peak memory 196372 kb
Host smart-b2d59fbe-1ace-438b-b8d4-906270befa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453283172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.453283172
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3102284865
Short name T857
Test name
Test status
Simulation time 661237700 ps
CPU time 1.91 seconds
Started Jul 07 05:15:10 PM PDT 24
Finished Jul 07 05:15:13 PM PDT 24
Peak memory 198300 kb
Host smart-58426742-a56b-4365-826e-3e10bd06e63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102284865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3102284865
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.841654767
Short name T131
Test name
Test status
Simulation time 249350291543 ps
CPU time 276.36 seconds
Started Jul 07 05:15:14 PM PDT 24
Finished Jul 07 05:19:51 PM PDT 24
Peak memory 208348 kb
Host smart-a2a0eb33-e37a-436d-8827-7a34901e9aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841654767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.841654767
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2330233248
Short name T560
Test name
Test status
Simulation time 56615869465 ps
CPU time 1576.13 seconds
Started Jul 07 05:15:15 PM PDT 24
Finished Jul 07 05:41:31 PM PDT 24
Peak memory 214632 kb
Host smart-8b3a6706-c7fd-4976-9eef-5f6908f581d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330233248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2330233248
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1670886775
Short name T1110
Test name
Test status
Simulation time 773702790 ps
CPU time 2.2 seconds
Started Jul 07 05:15:18 PM PDT 24
Finished Jul 07 05:15:20 PM PDT 24
Peak memory 198712 kb
Host smart-def3e1e4-3516-443a-9576-236519988753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670886775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1670886775
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2825309496
Short name T370
Test name
Test status
Simulation time 175517516335 ps
CPU time 22.75 seconds
Started Jul 07 05:15:11 PM PDT 24
Finished Jul 07 05:15:34 PM PDT 24
Peak memory 199476 kb
Host smart-d2cf00cc-a441-43ee-a3d7-28d057d6c1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825309496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2825309496
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_fifo_full.942662273
Short name T644
Test name
Test status
Simulation time 33465278453 ps
CPU time 14.96 seconds
Started Jul 07 05:15:16 PM PDT 24
Finished Jul 07 05:15:31 PM PDT 24
Peak memory 199852 kb
Host smart-df3320ea-9e7c-4b1d-ba78-7234fba01e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942662273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.942662273
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.4294024736
Short name T758
Test name
Test status
Simulation time 117584804743 ps
CPU time 29.35 seconds
Started Jul 07 05:15:28 PM PDT 24
Finished Jul 07 05:15:57 PM PDT 24
Peak memory 199952 kb
Host smart-c9f222d2-915e-4eee-99ad-04ce765a03a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294024736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4294024736
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2481193203
Short name T111
Test name
Test status
Simulation time 27475000765 ps
CPU time 24.78 seconds
Started Jul 07 05:15:17 PM PDT 24
Finished Jul 07 05:15:42 PM PDT 24
Peak memory 199976 kb
Host smart-4e6f39c7-3cb3-4a7a-abcc-abb2a1ff72e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481193203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2481193203
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2907934479
Short name T661
Test name
Test status
Simulation time 24960020395 ps
CPU time 57.4 seconds
Started Jul 07 05:15:21 PM PDT 24
Finished Jul 07 05:16:18 PM PDT 24
Peak memory 199828 kb
Host smart-66d465d3-0b47-400c-88fa-a73d174226fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907934479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2907934479
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1122198866
Short name T827
Test name
Test status
Simulation time 77030655035 ps
CPU time 485.63 seconds
Started Jul 07 05:15:19 PM PDT 24
Finished Jul 07 05:23:25 PM PDT 24
Peak memory 199848 kb
Host smart-270bfcbd-0618-47c9-bfc1-b29577aba79c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122198866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1122198866
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3861952457
Short name T595
Test name
Test status
Simulation time 9213867413 ps
CPU time 2.64 seconds
Started Jul 07 05:15:21 PM PDT 24
Finished Jul 07 05:15:24 PM PDT 24
Peak memory 200088 kb
Host smart-9c423714-e1a1-446c-aaec-0ba254c0c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861952457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3861952457
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.621675464
Short name T464
Test name
Test status
Simulation time 14968785549 ps
CPU time 25.38 seconds
Started Jul 07 05:15:23 PM PDT 24
Finished Jul 07 05:15:48 PM PDT 24
Peak memory 200100 kb
Host smart-af6a6489-4d71-438d-becd-f96e1660eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621675464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.621675464
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1585330523
Short name T927
Test name
Test status
Simulation time 37966593561 ps
CPU time 218.88 seconds
Started Jul 07 05:15:22 PM PDT 24
Finished Jul 07 05:19:01 PM PDT 24
Peak memory 199980 kb
Host smart-407ea221-55fe-4b3c-88d8-fbd0ff3e8007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585330523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1585330523
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2020472401
Short name T1135
Test name
Test status
Simulation time 2755734546 ps
CPU time 5.26 seconds
Started Jul 07 05:15:28 PM PDT 24
Finished Jul 07 05:15:33 PM PDT 24
Peak memory 199148 kb
Host smart-f3c4b5b9-b9b7-40b8-8f40-9f72ae3e5d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020472401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2020472401
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2404755554
Short name T532
Test name
Test status
Simulation time 97866362511 ps
CPU time 165.13 seconds
Started Jul 07 05:15:18 PM PDT 24
Finished Jul 07 05:18:04 PM PDT 24
Peak memory 199900 kb
Host smart-9334c8b1-90d5-4b52-b62b-459980d736e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404755554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2404755554
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1914359760
Short name T731
Test name
Test status
Simulation time 7681095825 ps
CPU time 3.24 seconds
Started Jul 07 05:15:24 PM PDT 24
Finished Jul 07 05:15:28 PM PDT 24
Peak memory 196032 kb
Host smart-e99fb610-30df-413b-b921-9130cb755d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914359760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1914359760
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1166081378
Short name T33
Test name
Test status
Simulation time 529763040 ps
CPU time 1.21 seconds
Started Jul 07 05:15:17 PM PDT 24
Finished Jul 07 05:15:19 PM PDT 24
Peak memory 199684 kb
Host smart-f73b3963-636b-486a-883f-af48b660c11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166081378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1166081378
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3529743871
Short name T1058
Test name
Test status
Simulation time 380202624859 ps
CPU time 472.77 seconds
Started Jul 07 05:15:25 PM PDT 24
Finished Jul 07 05:23:18 PM PDT 24
Peak memory 208404 kb
Host smart-54bd4d50-12c6-47cf-b1a2-7cd2ee1c2704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529743871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3529743871
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2274533912
Short name T581
Test name
Test status
Simulation time 176099835999 ps
CPU time 456.82 seconds
Started Jul 07 05:15:22 PM PDT 24
Finished Jul 07 05:22:59 PM PDT 24
Peak memory 224732 kb
Host smart-d407fa23-6ab5-43be-9c93-ebe676f9285c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274533912 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2274533912
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2948169314
Short name T624
Test name
Test status
Simulation time 10392200829 ps
CPU time 5.79 seconds
Started Jul 07 05:15:24 PM PDT 24
Finished Jul 07 05:15:30 PM PDT 24
Peak memory 199940 kb
Host smart-a57cdb6c-3f8f-4e09-8138-01b3e2b199d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948169314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2948169314
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.22562409
Short name T461
Test name
Test status
Simulation time 102652537919 ps
CPU time 55.85 seconds
Started Jul 07 05:15:18 PM PDT 24
Finished Jul 07 05:16:14 PM PDT 24
Peak memory 199944 kb
Host smart-227f78ea-9f78-4045-af17-5c07334eeea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22562409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.22562409
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2427073067
Short name T904
Test name
Test status
Simulation time 25218792 ps
CPU time 0.55 seconds
Started Jul 07 05:12:46 PM PDT 24
Finished Jul 07 05:12:47 PM PDT 24
Peak memory 195292 kb
Host smart-e7af780b-7dd3-4025-aed7-4d0c45f87c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427073067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2427073067
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.34964229
Short name T783
Test name
Test status
Simulation time 135678610355 ps
CPU time 109.64 seconds
Started Jul 07 05:12:48 PM PDT 24
Finished Jul 07 05:14:39 PM PDT 24
Peak memory 199912 kb
Host smart-cb5780d9-cb62-4120-9bfc-e0d95b637b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34964229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.34964229
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1127071298
Short name T775
Test name
Test status
Simulation time 359732170431 ps
CPU time 68.71 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:14:04 PM PDT 24
Peak memory 199908 kb
Host smart-3f98cd4d-5697-49ef-8de1-0c2f3e4d87f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127071298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1127071298
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.4291252762
Short name T537
Test name
Test status
Simulation time 9134541222 ps
CPU time 12.41 seconds
Started Jul 07 05:12:48 PM PDT 24
Finished Jul 07 05:13:02 PM PDT 24
Peak memory 199784 kb
Host smart-ec554f78-b96a-4cd7-9112-70e51bc9bdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291252762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.4291252762
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2708181771
Short name T330
Test name
Test status
Simulation time 41413557656 ps
CPU time 25.52 seconds
Started Jul 07 05:12:54 PM PDT 24
Finished Jul 07 05:13:20 PM PDT 24
Peak memory 199940 kb
Host smart-b2e6b228-3717-414d-812d-a01cf27e64a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708181771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2708181771
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3259608441
Short name T587
Test name
Test status
Simulation time 79760827631 ps
CPU time 297.66 seconds
Started Jul 07 05:12:49 PM PDT 24
Finished Jul 07 05:17:48 PM PDT 24
Peak memory 199876 kb
Host smart-5b8d79ee-c327-4f38-9637-adbbc1db8e2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259608441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3259608441
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2089221289
Short name T313
Test name
Test status
Simulation time 4139048716 ps
CPU time 5.49 seconds
Started Jul 07 05:12:47 PM PDT 24
Finished Jul 07 05:12:54 PM PDT 24
Peak memory 198648 kb
Host smart-fa928d27-6bb3-4106-bcc8-ff17b020eccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089221289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2089221289
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.564517503
Short name T358
Test name
Test status
Simulation time 84992626280 ps
CPU time 33.98 seconds
Started Jul 07 05:12:44 PM PDT 24
Finished Jul 07 05:13:19 PM PDT 24
Peak memory 200076 kb
Host smart-ade08fe1-303a-4cc8-9698-9a32199475a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564517503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.564517503
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2110881574
Short name T1003
Test name
Test status
Simulation time 22196143128 ps
CPU time 594.15 seconds
Started Jul 07 05:12:54 PM PDT 24
Finished Jul 07 05:22:49 PM PDT 24
Peak memory 199912 kb
Host smart-9b0b68ce-2c85-4e43-9acf-89fcbb92294e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110881574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2110881574
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3816574706
Short name T340
Test name
Test status
Simulation time 6000499563 ps
CPU time 41.04 seconds
Started Jul 07 05:12:44 PM PDT 24
Finished Jul 07 05:13:26 PM PDT 24
Peak memory 199180 kb
Host smart-eb1f7f99-00c5-4cee-81c8-75879518d88b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816574706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3816574706
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2765486620
Short name T147
Test name
Test status
Simulation time 35664388693 ps
CPU time 60.88 seconds
Started Jul 07 05:12:46 PM PDT 24
Finished Jul 07 05:13:48 PM PDT 24
Peak memory 199828 kb
Host smart-ba3bc26b-7372-4021-8202-4f8c3a8653e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765486620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2765486620
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3891269288
Short name T448
Test name
Test status
Simulation time 43465768196 ps
CPU time 16.18 seconds
Started Jul 07 05:12:49 PM PDT 24
Finished Jul 07 05:13:06 PM PDT 24
Peak memory 196040 kb
Host smart-02d19cb0-04e6-402e-a4eb-115c7575cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891269288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3891269288
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1839717514
Short name T106
Test name
Test status
Simulation time 68994322 ps
CPU time 0.79 seconds
Started Jul 07 05:12:47 PM PDT 24
Finished Jul 07 05:12:48 PM PDT 24
Peak memory 218272 kb
Host smart-c6a4ac3c-b910-494d-a07c-be1c62926b58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839717514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1839717514
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2968487453
Short name T108
Test name
Test status
Simulation time 293976689 ps
CPU time 1.56 seconds
Started Jul 07 05:12:41 PM PDT 24
Finished Jul 07 05:12:42 PM PDT 24
Peak memory 198864 kb
Host smart-de349e2f-96e7-47ad-a1af-7b0815263dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968487453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2968487453
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.4214974069
Short name T321
Test name
Test status
Simulation time 116672892949 ps
CPU time 104.28 seconds
Started Jul 07 05:12:53 PM PDT 24
Finished Jul 07 05:14:37 PM PDT 24
Peak memory 199820 kb
Host smart-0964e102-a058-482d-8775-3b0fc5bb486f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214974069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4214974069
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3724563714
Short name T286
Test name
Test status
Simulation time 1470524004 ps
CPU time 2.22 seconds
Started Jul 07 05:12:45 PM PDT 24
Finished Jul 07 05:12:48 PM PDT 24
Peak memory 197692 kb
Host smart-e28ca00d-084a-4b5f-9b77-7b77a35efe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724563714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3724563714
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1497697228
Short name T376
Test name
Test status
Simulation time 96224913911 ps
CPU time 153.26 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:15:28 PM PDT 24
Peak memory 199896 kb
Host smart-b984a5e6-5215-45d6-a5cf-0a99e51f58d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497697228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1497697228
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1290049111
Short name T1105
Test name
Test status
Simulation time 22164611 ps
CPU time 0.56 seconds
Started Jul 07 05:15:29 PM PDT 24
Finished Jul 07 05:15:29 PM PDT 24
Peak memory 195572 kb
Host smart-9d237e88-a54b-4a6f-9e41-497bf743a3e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290049111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1290049111
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2931243146
Short name T121
Test name
Test status
Simulation time 28215462567 ps
CPU time 44.17 seconds
Started Jul 07 05:15:24 PM PDT 24
Finished Jul 07 05:16:09 PM PDT 24
Peak memory 199972 kb
Host smart-fe52b59d-393c-4d99-b34f-51736c379bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931243146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2931243146
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1054302283
Short name T354
Test name
Test status
Simulation time 97903022511 ps
CPU time 37.66 seconds
Started Jul 07 05:15:26 PM PDT 24
Finished Jul 07 05:16:04 PM PDT 24
Peak memory 199416 kb
Host smart-a66b094f-c84a-4a5e-a826-dde9addf700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054302283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1054302283
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2697904655
Short name T535
Test name
Test status
Simulation time 22902342796 ps
CPU time 36.13 seconds
Started Jul 07 05:15:27 PM PDT 24
Finished Jul 07 05:16:04 PM PDT 24
Peak memory 199964 kb
Host smart-c6a1cc0f-0146-4040-87e6-048a050e7e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697904655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2697904655
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2301959317
Short name T588
Test name
Test status
Simulation time 8264748612 ps
CPU time 3.89 seconds
Started Jul 07 05:15:24 PM PDT 24
Finished Jul 07 05:15:28 PM PDT 24
Peak memory 196668 kb
Host smart-dcfd46ce-0dfa-4140-a278-f8c96506e9a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301959317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2301959317
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1119576954
Short name T707
Test name
Test status
Simulation time 116724441885 ps
CPU time 493.33 seconds
Started Jul 07 05:15:28 PM PDT 24
Finished Jul 07 05:23:42 PM PDT 24
Peak memory 199968 kb
Host smart-00e3ff5f-3c15-4ef9-9dee-b56154481c08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119576954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1119576954
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1816220845
Short name T24
Test name
Test status
Simulation time 2517507929 ps
CPU time 1.4 seconds
Started Jul 07 05:15:25 PM PDT 24
Finished Jul 07 05:15:26 PM PDT 24
Peak memory 198488 kb
Host smart-28357f02-804b-49db-b7fd-22be56b7be72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816220845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1816220845
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3087512124
Short name T1115
Test name
Test status
Simulation time 12242710814 ps
CPU time 17.09 seconds
Started Jul 07 05:15:26 PM PDT 24
Finished Jul 07 05:15:43 PM PDT 24
Peak memory 196940 kb
Host smart-c5a9eac7-45e9-4655-91c9-7f963c4d9a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087512124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3087512124
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1334183165
Short name T701
Test name
Test status
Simulation time 7620208281 ps
CPU time 440.89 seconds
Started Jul 07 05:15:26 PM PDT 24
Finished Jul 07 05:22:47 PM PDT 24
Peak memory 199916 kb
Host smart-84caa164-e86b-44c0-a491-c32fdb1b434b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334183165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1334183165
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2573400723
Short name T650
Test name
Test status
Simulation time 3762746896 ps
CPU time 9.65 seconds
Started Jul 07 05:15:26 PM PDT 24
Finished Jul 07 05:15:36 PM PDT 24
Peak memory 198008 kb
Host smart-3d29be76-c597-4e5b-9e8a-c081a0ba577b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573400723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2573400723
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2015059148
Short name T684
Test name
Test status
Simulation time 28066531162 ps
CPU time 43.81 seconds
Started Jul 07 05:15:25 PM PDT 24
Finished Jul 07 05:16:09 PM PDT 24
Peak memory 199824 kb
Host smart-f69e3904-8b38-41f3-bf83-7aa1fd0c4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015059148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2015059148
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1095316672
Short name T821
Test name
Test status
Simulation time 2611259495 ps
CPU time 1.45 seconds
Started Jul 07 05:15:24 PM PDT 24
Finished Jul 07 05:15:25 PM PDT 24
Peak memory 195924 kb
Host smart-927cf3e3-0fe9-4154-9798-ec42aa773800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095316672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1095316672
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3667245550
Short name T507
Test name
Test status
Simulation time 508556043 ps
CPU time 1.92 seconds
Started Jul 07 05:15:25 PM PDT 24
Finished Jul 07 05:15:27 PM PDT 24
Peak memory 198340 kb
Host smart-fa366d92-3a93-4f3d-844a-29b565da786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667245550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3667245550
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3050792319
Short name T1054
Test name
Test status
Simulation time 525531572242 ps
CPU time 476.22 seconds
Started Jul 07 05:15:30 PM PDT 24
Finished Jul 07 05:23:27 PM PDT 24
Peak memory 200228 kb
Host smart-c72ddcdb-c8cd-47ae-bf7f-9f54f597c2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050792319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3050792319
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.430401181
Short name T955
Test name
Test status
Simulation time 29763142521 ps
CPU time 830.23 seconds
Started Jul 07 05:15:28 PM PDT 24
Finished Jul 07 05:29:18 PM PDT 24
Peak memory 209764 kb
Host smart-c68855a7-3608-4dfa-a86b-3846e8cf2600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430401181 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.430401181
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2983650979
Short name T597
Test name
Test status
Simulation time 1452716538 ps
CPU time 2.07 seconds
Started Jul 07 05:15:28 PM PDT 24
Finished Jul 07 05:15:30 PM PDT 24
Peak memory 198680 kb
Host smart-fca7dbe6-d257-46e0-8471-66a6f3f22656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983650979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2983650979
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.581815441
Short name T1065
Test name
Test status
Simulation time 44881559099 ps
CPU time 39.02 seconds
Started Jul 07 05:15:24 PM PDT 24
Finished Jul 07 05:16:03 PM PDT 24
Peak memory 199836 kb
Host smart-b12964ce-fdf6-46d4-8699-badc4d3ce3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581815441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.581815441
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3702730692
Short name T483
Test name
Test status
Simulation time 41825022 ps
CPU time 0.58 seconds
Started Jul 07 05:15:34 PM PDT 24
Finished Jul 07 05:15:35 PM PDT 24
Peak memory 195224 kb
Host smart-fd7a4809-aada-4ba5-afa5-11887a2abd8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702730692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3702730692
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3428764693
Short name T519
Test name
Test status
Simulation time 113774249754 ps
CPU time 168.05 seconds
Started Jul 07 05:15:28 PM PDT 24
Finished Jul 07 05:18:17 PM PDT 24
Peak memory 199948 kb
Host smart-446d4175-28f4-4c40-9530-567a959a4d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428764693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3428764693
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2589949647
Short name T423
Test name
Test status
Simulation time 23688103145 ps
CPU time 39.26 seconds
Started Jul 07 05:15:31 PM PDT 24
Finished Jul 07 05:16:10 PM PDT 24
Peak memory 199732 kb
Host smart-00054f85-97b1-4bb0-9636-9744655fdcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589949647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2589949647
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2509418614
Short name T220
Test name
Test status
Simulation time 40687289736 ps
CPU time 19.13 seconds
Started Jul 07 05:15:31 PM PDT 24
Finished Jul 07 05:15:50 PM PDT 24
Peak memory 199868 kb
Host smart-1c439fbb-cd11-45c0-ae5a-8f2ed6b983b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509418614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2509418614
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.402742806
Short name T1053
Test name
Test status
Simulation time 3470393441 ps
CPU time 1.79 seconds
Started Jul 07 05:15:30 PM PDT 24
Finished Jul 07 05:15:32 PM PDT 24
Peak memory 195932 kb
Host smart-43683085-bc11-474e-924f-040d278b837c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402742806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.402742806
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2995331505
Short name T283
Test name
Test status
Simulation time 120222015056 ps
CPU time 272.46 seconds
Started Jul 07 05:15:36 PM PDT 24
Finished Jul 07 05:20:09 PM PDT 24
Peak memory 199968 kb
Host smart-1ae0cc67-f63d-45a1-8c82-0efdaa718955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995331505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2995331505
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1728148970
Short name T725
Test name
Test status
Simulation time 2640885290 ps
CPU time 7.36 seconds
Started Jul 07 05:15:37 PM PDT 24
Finished Jul 07 05:15:45 PM PDT 24
Peak memory 199952 kb
Host smart-0f772621-2303-4e18-94ef-a67c94022320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728148970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1728148970
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3447533415
Short name T981
Test name
Test status
Simulation time 57636480265 ps
CPU time 87.52 seconds
Started Jul 07 05:15:30 PM PDT 24
Finished Jul 07 05:16:57 PM PDT 24
Peak memory 208240 kb
Host smart-e4ef2d5c-c2da-4b62-91d5-a01b75873f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447533415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3447533415
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3373643968
Short name T43
Test name
Test status
Simulation time 18767659182 ps
CPU time 107.98 seconds
Started Jul 07 05:15:29 PM PDT 24
Finished Jul 07 05:17:17 PM PDT 24
Peak memory 199844 kb
Host smart-86eb5158-2ae7-40d3-a4f6-429868897280
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373643968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3373643968
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1167891239
Short name T333
Test name
Test status
Simulation time 2668225635 ps
CPU time 3.56 seconds
Started Jul 07 05:15:31 PM PDT 24
Finished Jul 07 05:15:34 PM PDT 24
Peak memory 198348 kb
Host smart-f3b28757-29ea-4aab-8f99-5d91fda27a75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167891239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1167891239
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2213049515
Short name T171
Test name
Test status
Simulation time 100077694211 ps
CPU time 11.96 seconds
Started Jul 07 05:15:30 PM PDT 24
Finished Jul 07 05:15:42 PM PDT 24
Peak memory 199768 kb
Host smart-74e45bdc-6a23-4591-baa2-fef04fe19f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213049515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2213049515
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.264338729
Short name T946
Test name
Test status
Simulation time 3120427255 ps
CPU time 5.35 seconds
Started Jul 07 05:15:30 PM PDT 24
Finished Jul 07 05:15:35 PM PDT 24
Peak memory 195880 kb
Host smart-eba26c6c-85f6-4979-bbc1-086b1ff8bf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264338729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.264338729
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1567005745
Short name T591
Test name
Test status
Simulation time 634485724 ps
CPU time 2.41 seconds
Started Jul 07 05:15:30 PM PDT 24
Finished Jul 07 05:15:33 PM PDT 24
Peak memory 198696 kb
Host smart-e234b767-b1b8-4def-b7a4-0af55c99de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567005745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1567005745
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.4084411652
Short name T1059
Test name
Test status
Simulation time 258515497838 ps
CPU time 1328.31 seconds
Started Jul 07 05:15:33 PM PDT 24
Finished Jul 07 05:37:42 PM PDT 24
Peak memory 199840 kb
Host smart-b4f24b85-adec-4420-b92b-5bb8f15299f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084411652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4084411652
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2755797761
Short name T350
Test name
Test status
Simulation time 7615523470 ps
CPU time 9.58 seconds
Started Jul 07 05:15:31 PM PDT 24
Finished Jul 07 05:15:40 PM PDT 24
Peak memory 199972 kb
Host smart-b24eb534-a645-404e-ae47-d102893ff95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755797761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2755797761
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1348555051
Short name T260
Test name
Test status
Simulation time 37832788995 ps
CPU time 52.4 seconds
Started Jul 07 05:15:32 PM PDT 24
Finished Jul 07 05:16:25 PM PDT 24
Peak memory 199984 kb
Host smart-39bba308-517e-4f62-99c9-52a0d7864db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348555051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1348555051
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1703628966
Short name T470
Test name
Test status
Simulation time 35307310 ps
CPU time 0.56 seconds
Started Jul 07 05:15:40 PM PDT 24
Finished Jul 07 05:15:41 PM PDT 24
Peak memory 195276 kb
Host smart-f6440e7e-5218-46a5-8dd4-e4d0f02265ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703628966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1703628966
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1668386314
Short name T889
Test name
Test status
Simulation time 32570277924 ps
CPU time 13.59 seconds
Started Jul 07 05:15:33 PM PDT 24
Finished Jul 07 05:15:47 PM PDT 24
Peak memory 199976 kb
Host smart-ba28ccca-c7f7-4ab9-b545-10038762eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668386314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1668386314
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1300193680
Short name T48
Test name
Test status
Simulation time 196390153990 ps
CPU time 129.48 seconds
Started Jul 07 05:15:35 PM PDT 24
Finished Jul 07 05:17:44 PM PDT 24
Peak memory 199772 kb
Host smart-460e38bb-4f49-4bd2-bb72-6ee025ff9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300193680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1300193680
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3423432883
Short name T169
Test name
Test status
Simulation time 16878642794 ps
CPU time 27.97 seconds
Started Jul 07 05:15:40 PM PDT 24
Finished Jul 07 05:16:09 PM PDT 24
Peak memory 200040 kb
Host smart-d374d519-a8e4-4f2e-96d7-0ab900abf48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423432883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3423432883
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2512138805
Short name T332
Test name
Test status
Simulation time 26296481109 ps
CPU time 11.19 seconds
Started Jul 07 05:15:38 PM PDT 24
Finished Jul 07 05:15:49 PM PDT 24
Peak memory 199208 kb
Host smart-44232a4f-fc63-4bea-b8be-19cbe7487984
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512138805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2512138805
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.151237657
Short name T416
Test name
Test status
Simulation time 105041701181 ps
CPU time 311.87 seconds
Started Jul 07 05:15:40 PM PDT 24
Finished Jul 07 05:20:52 PM PDT 24
Peak memory 199888 kb
Host smart-3b352a3a-f212-4a44-8828-95c0d8b0778c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151237657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.151237657
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3527960110
Short name T738
Test name
Test status
Simulation time 593881991 ps
CPU time 0.83 seconds
Started Jul 07 05:15:40 PM PDT 24
Finished Jul 07 05:15:41 PM PDT 24
Peak memory 195932 kb
Host smart-c4c81215-ef24-4186-affc-e920bd02350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527960110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3527960110
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1221784241
Short name T540
Test name
Test status
Simulation time 10315075324 ps
CPU time 16.16 seconds
Started Jul 07 05:15:39 PM PDT 24
Finished Jul 07 05:15:56 PM PDT 24
Peak memory 196276 kb
Host smart-f257c764-338b-473e-b411-e9079eeee407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221784241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1221784241
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2894442186
Short name T288
Test name
Test status
Simulation time 9216940808 ps
CPU time 449.94 seconds
Started Jul 07 05:15:39 PM PDT 24
Finished Jul 07 05:23:10 PM PDT 24
Peak memory 199808 kb
Host smart-414686f4-1f1b-4e6d-a892-8822b53f2397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894442186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2894442186
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1152367428
Short name T351
Test name
Test status
Simulation time 7786960744 ps
CPU time 15.34 seconds
Started Jul 07 05:15:42 PM PDT 24
Finished Jul 07 05:15:58 PM PDT 24
Peak memory 199032 kb
Host smart-db081ba1-aa7e-4099-b7bd-3a3eb27eae31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152367428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1152367428
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.21245451
Short name T510
Test name
Test status
Simulation time 100094090780 ps
CPU time 152.46 seconds
Started Jul 07 05:15:41 PM PDT 24
Finished Jul 07 05:18:13 PM PDT 24
Peak memory 199972 kb
Host smart-e91b7ec4-3e4e-41d0-8df5-db827162ed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21245451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.21245451
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4219409286
Short name T1068
Test name
Test status
Simulation time 2404041618 ps
CPU time 4.34 seconds
Started Jul 07 05:15:39 PM PDT 24
Finished Jul 07 05:15:43 PM PDT 24
Peak memory 195816 kb
Host smart-73a01a7c-039a-421a-8824-6092c6694969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219409286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4219409286
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3157686778
Short name T943
Test name
Test status
Simulation time 933946129 ps
CPU time 3.79 seconds
Started Jul 07 05:15:34 PM PDT 24
Finished Jul 07 05:15:38 PM PDT 24
Peak memory 198756 kb
Host smart-8309afe8-f080-433f-b662-2af26af8bf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157686778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3157686778
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3223147876
Short name T436
Test name
Test status
Simulation time 53069792519 ps
CPU time 971.58 seconds
Started Jul 07 05:15:38 PM PDT 24
Finished Jul 07 05:31:50 PM PDT 24
Peak memory 199980 kb
Host smart-00c9277c-df2c-4b59-8864-cf3347138bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223147876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3223147876
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1063131037
Short name T576
Test name
Test status
Simulation time 113820161249 ps
CPU time 344.54 seconds
Started Jul 07 05:15:37 PM PDT 24
Finished Jul 07 05:21:22 PM PDT 24
Peak memory 216676 kb
Host smart-38f9c3af-be2a-4388-967b-1188d057d19b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063131037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1063131037
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1641834671
Short name T798
Test name
Test status
Simulation time 8275260398 ps
CPU time 6.33 seconds
Started Jul 07 05:15:38 PM PDT 24
Finished Jul 07 05:15:44 PM PDT 24
Peak memory 199400 kb
Host smart-4be3b387-c7f6-4ccc-8cfe-24eb3946ff4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641834671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1641834671
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1584693430
Short name T471
Test name
Test status
Simulation time 43147598793 ps
CPU time 61.28 seconds
Started Jul 07 05:15:34 PM PDT 24
Finished Jul 07 05:16:36 PM PDT 24
Peak memory 200196 kb
Host smart-1a52fe79-b726-4c11-98d3-7d76eac913a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584693430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1584693430
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.211872054
Short name T876
Test name
Test status
Simulation time 36741496 ps
CPU time 0.55 seconds
Started Jul 07 05:15:46 PM PDT 24
Finished Jul 07 05:15:47 PM PDT 24
Peak memory 194748 kb
Host smart-88e83592-2e33-4aac-846b-c609587e1c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211872054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.211872054
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2286442984
Short name T275
Test name
Test status
Simulation time 85130947903 ps
CPU time 199.7 seconds
Started Jul 07 05:15:41 PM PDT 24
Finished Jul 07 05:19:01 PM PDT 24
Peak memory 199972 kb
Host smart-50c9eac8-b512-4b24-8c2c-8ae54ce79178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286442984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2286442984
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1180685373
Short name T988
Test name
Test status
Simulation time 24972241345 ps
CPU time 15.3 seconds
Started Jul 07 05:15:39 PM PDT 24
Finished Jul 07 05:15:55 PM PDT 24
Peak memory 199976 kb
Host smart-2af962b5-8edd-455b-9de4-93d5bb780af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180685373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1180685373
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3538379809
Short name T888
Test name
Test status
Simulation time 123572915485 ps
CPU time 18.11 seconds
Started Jul 07 05:15:43 PM PDT 24
Finished Jul 07 05:16:01 PM PDT 24
Peak memory 199932 kb
Host smart-8545654b-ef93-4958-9351-c0e842adc12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538379809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3538379809
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2004838548
Short name T493
Test name
Test status
Simulation time 82273609888 ps
CPU time 141.74 seconds
Started Jul 07 05:15:41 PM PDT 24
Finished Jul 07 05:18:03 PM PDT 24
Peak memory 199908 kb
Host smart-ab55bbaf-53f5-4bd5-b882-d471d13a940d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004838548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2004838548
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.305987661
Short name T264
Test name
Test status
Simulation time 42351499046 ps
CPU time 192.54 seconds
Started Jul 07 05:15:48 PM PDT 24
Finished Jul 07 05:19:01 PM PDT 24
Peak memory 199952 kb
Host smart-fe30b6f6-0203-4e88-81c4-888fe04589a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305987661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.305987661
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.530602192
Short name T647
Test name
Test status
Simulation time 5060322623 ps
CPU time 10.83 seconds
Started Jul 07 05:15:47 PM PDT 24
Finished Jul 07 05:15:58 PM PDT 24
Peak memory 199876 kb
Host smart-dc2fd871-4fe7-4cc6-8be3-7ee8ec81f6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530602192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.530602192
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1854524313
Short name T779
Test name
Test status
Simulation time 43711814974 ps
CPU time 63.88 seconds
Started Jul 07 05:15:42 PM PDT 24
Finished Jul 07 05:16:46 PM PDT 24
Peak memory 200056 kb
Host smart-007511c8-3d4c-4332-bd08-a8dea054687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854524313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1854524313
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1277437409
Short name T1168
Test name
Test status
Simulation time 20879031732 ps
CPU time 1065.57 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:33:42 PM PDT 24
Peak memory 200028 kb
Host smart-a4fbaa5d-d1ab-4e94-a3f1-906938d7c7c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1277437409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1277437409
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1128673127
Short name T352
Test name
Test status
Simulation time 2842950871 ps
CPU time 10.92 seconds
Started Jul 07 05:15:43 PM PDT 24
Finished Jul 07 05:15:54 PM PDT 24
Peak memory 198564 kb
Host smart-c55623d0-a1f0-44ec-a9b8-adb32c208313
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128673127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1128673127
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1891956167
Short name T941
Test name
Test status
Simulation time 39644314431 ps
CPU time 17.84 seconds
Started Jul 07 05:15:44 PM PDT 24
Finished Jul 07 05:16:02 PM PDT 24
Peak memory 199892 kb
Host smart-673a913d-ac35-4414-90d2-7f1d9f197fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891956167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1891956167
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3469377072
Short name T1032
Test name
Test status
Simulation time 3139413824 ps
CPU time 2.98 seconds
Started Jul 07 05:15:43 PM PDT 24
Finished Jul 07 05:15:46 PM PDT 24
Peak memory 195916 kb
Host smart-acb26e0e-4818-45c7-9ffb-a81cff1f1779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469377072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3469377072
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.661628101
Short name T726
Test name
Test status
Simulation time 5699138818 ps
CPU time 6.2 seconds
Started Jul 07 05:15:39 PM PDT 24
Finished Jul 07 05:15:46 PM PDT 24
Peak memory 199564 kb
Host smart-ac10f9f4-6f6a-46d1-bb9d-590518cf642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661628101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.661628101
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1278086823
Short name T740
Test name
Test status
Simulation time 270441576081 ps
CPU time 44.78 seconds
Started Jul 07 05:15:46 PM PDT 24
Finished Jul 07 05:16:31 PM PDT 24
Peak memory 200252 kb
Host smart-30e30acb-b19e-4ad6-be7e-2d46f5386529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278086823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1278086823
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.287302595
Short name T452
Test name
Test status
Simulation time 86770542589 ps
CPU time 466.43 seconds
Started Jul 07 05:15:48 PM PDT 24
Finished Jul 07 05:23:35 PM PDT 24
Peak memory 225956 kb
Host smart-d5bef577-626f-40b0-a591-c01b79af7bca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287302595 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.287302595
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3692755461
Short name T742
Test name
Test status
Simulation time 740584209 ps
CPU time 2.34 seconds
Started Jul 07 05:15:44 PM PDT 24
Finished Jul 07 05:15:46 PM PDT 24
Peak memory 198448 kb
Host smart-ebb20ecc-cd75-4016-be4f-77a467ed794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692755461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3692755461
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1431633881
Short name T944
Test name
Test status
Simulation time 97263246649 ps
CPU time 225.16 seconds
Started Jul 07 05:15:42 PM PDT 24
Finished Jul 07 05:19:28 PM PDT 24
Peak memory 200004 kb
Host smart-ac71b946-cc4a-46a0-82a1-48eee6ade85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431633881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1431633881
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3609468797
Short name T1014
Test name
Test status
Simulation time 14254952 ps
CPU time 0.55 seconds
Started Jul 07 05:15:46 PM PDT 24
Finished Jul 07 05:15:47 PM PDT 24
Peak memory 195576 kb
Host smart-b075c797-df94-4152-b82c-8dc529f20887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609468797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3609468797
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3700232150
Short name T1064
Test name
Test status
Simulation time 130764603684 ps
CPU time 119.42 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:17:55 PM PDT 24
Peak memory 200000 kb
Host smart-daf9b593-6817-4f2e-94cd-231f2bf414cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700232150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3700232150
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2899385182
Short name T670
Test name
Test status
Simulation time 108889110994 ps
CPU time 193.24 seconds
Started Jul 07 05:15:48 PM PDT 24
Finished Jul 07 05:19:01 PM PDT 24
Peak memory 199928 kb
Host smart-1d149999-908d-46a6-93bf-8ed7b0a57d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899385182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2899385182
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1484471713
Short name T247
Test name
Test status
Simulation time 166371391469 ps
CPU time 107.63 seconds
Started Jul 07 05:15:46 PM PDT 24
Finished Jul 07 05:17:34 PM PDT 24
Peak memory 199976 kb
Host smart-02f3e4ac-3cb1-4fa1-b31a-b9a37924c8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484471713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1484471713
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2193876632
Short name T1124
Test name
Test status
Simulation time 28702684797 ps
CPU time 43.66 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:16:39 PM PDT 24
Peak memory 198540 kb
Host smart-c6f6ed37-fd9c-44aa-b31c-dbf241614038
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193876632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2193876632
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.163466272
Short name T394
Test name
Test status
Simulation time 226412093878 ps
CPU time 146.97 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:18:23 PM PDT 24
Peak memory 199940 kb
Host smart-dce1b693-5b8f-4f1c-9c59-17ff8c140ed8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163466272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.163466272
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.687656698
Short name T547
Test name
Test status
Simulation time 2801057889 ps
CPU time 4.11 seconds
Started Jul 07 05:15:45 PM PDT 24
Finished Jul 07 05:15:50 PM PDT 24
Peak memory 198776 kb
Host smart-8bc8c511-f412-4336-b63f-688acd9e3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687656698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.687656698
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2867695933
Short name T865
Test name
Test status
Simulation time 17904609993 ps
CPU time 16.18 seconds
Started Jul 07 05:15:46 PM PDT 24
Finished Jul 07 05:16:02 PM PDT 24
Peak memory 198504 kb
Host smart-6887ad6f-9339-4dca-b7f4-1b0f13e33aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867695933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2867695933
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2187135143
Short name T962
Test name
Test status
Simulation time 26356082095 ps
CPU time 139.03 seconds
Started Jul 07 05:15:50 PM PDT 24
Finished Jul 07 05:18:09 PM PDT 24
Peak memory 199888 kb
Host smart-d8902eba-3b29-4400-a254-88e11d0a4536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187135143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2187135143
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.603038626
Short name T1026
Test name
Test status
Simulation time 7548974696 ps
CPU time 11.84 seconds
Started Jul 07 05:15:50 PM PDT 24
Finished Jul 07 05:16:02 PM PDT 24
Peak memory 198744 kb
Host smart-e9513558-f126-4eba-9854-582d3d226a81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603038626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.603038626
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.975830652
Short name T765
Test name
Test status
Simulation time 148316574428 ps
CPU time 76.29 seconds
Started Jul 07 05:15:49 PM PDT 24
Finished Jul 07 05:17:06 PM PDT 24
Peak memory 199928 kb
Host smart-10014f75-5872-412b-a169-a3e7ef4c80e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975830652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.975830652
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1558744644
Short name T401
Test name
Test status
Simulation time 4329902430 ps
CPU time 1.47 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:15:57 PM PDT 24
Peak memory 196468 kb
Host smart-f9e21191-a3cd-4734-9398-4d48b16da3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558744644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1558744644
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3306701421
Short name T559
Test name
Test status
Simulation time 893734743 ps
CPU time 2.27 seconds
Started Jul 07 05:15:46 PM PDT 24
Finished Jul 07 05:15:49 PM PDT 24
Peak memory 199748 kb
Host smart-c84b258f-911a-4c34-9527-f425d75ca73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306701421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3306701421
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3819620055
Short name T566
Test name
Test status
Simulation time 81573907616 ps
CPU time 953.09 seconds
Started Jul 07 05:15:45 PM PDT 24
Finished Jul 07 05:31:39 PM PDT 24
Peak memory 199892 kb
Host smart-578871f8-a405-4514-8a35-ec67d508823b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819620055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3819620055
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3385920756
Short name T918
Test name
Test status
Simulation time 110668971459 ps
CPU time 643.12 seconds
Started Jul 07 05:15:50 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 224748 kb
Host smart-7387cb9a-446f-48cc-b34a-4e367a276bdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385920756 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3385920756
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.358750244
Short name T902
Test name
Test status
Simulation time 1520699425 ps
CPU time 1.86 seconds
Started Jul 07 05:15:49 PM PDT 24
Finished Jul 07 05:15:52 PM PDT 24
Peak memory 198372 kb
Host smart-ebdb92de-e18d-4591-b3b5-0061d834514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358750244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.358750244
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2720674006
Short name T268
Test name
Test status
Simulation time 56656920148 ps
CPU time 23.26 seconds
Started Jul 07 05:15:49 PM PDT 24
Finished Jul 07 05:16:13 PM PDT 24
Peak memory 199956 kb
Host smart-4728241e-13db-4c9b-a9cc-efec2d90a018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720674006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2720674006
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3180599428
Short name T553
Test name
Test status
Simulation time 21618851 ps
CPU time 0.53 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:15:56 PM PDT 24
Peak memory 194244 kb
Host smart-74ee7342-4bda-4b50-8fa0-b2d9cf5495d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180599428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3180599428
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.360976933
Short name T728
Test name
Test status
Simulation time 39119675546 ps
CPU time 57.32 seconds
Started Jul 07 05:15:51 PM PDT 24
Finished Jul 07 05:16:49 PM PDT 24
Peak memory 199928 kb
Host smart-e2165970-caf8-48d1-ac35-5e6d40b871e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360976933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.360976933
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.153646884
Short name T177
Test name
Test status
Simulation time 23594687767 ps
CPU time 52 seconds
Started Jul 07 05:15:53 PM PDT 24
Finished Jul 07 05:16:45 PM PDT 24
Peak memory 199704 kb
Host smart-0e711468-605c-4546-b85c-4439c232ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153646884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.153646884
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3047107100
Short name T948
Test name
Test status
Simulation time 60647637506 ps
CPU time 22.79 seconds
Started Jul 07 05:15:52 PM PDT 24
Finished Jul 07 05:16:15 PM PDT 24
Peak memory 199956 kb
Host smart-565171bd-3d64-4652-a0ca-058da2ff121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047107100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3047107100
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2797142448
Short name T686
Test name
Test status
Simulation time 18477269381 ps
CPU time 23.27 seconds
Started Jul 07 05:15:53 PM PDT 24
Finished Jul 07 05:16:16 PM PDT 24
Peak memory 197612 kb
Host smart-c748cdfa-2f20-44e1-a8ec-e9644b7c4159
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797142448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2797142448
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_loopback.3730300628
Short name T898
Test name
Test status
Simulation time 6672666229 ps
CPU time 3.2 seconds
Started Jul 07 05:15:52 PM PDT 24
Finished Jul 07 05:15:55 PM PDT 24
Peak memory 198852 kb
Host smart-b1a42029-4659-4c31-8a46-10987cbcb98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730300628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3730300628
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.904620083
Short name T957
Test name
Test status
Simulation time 277716503264 ps
CPU time 57.56 seconds
Started Jul 07 05:15:51 PM PDT 24
Finished Jul 07 05:16:49 PM PDT 24
Peak memory 207704 kb
Host smart-1c4f940d-8702-412a-8d3f-557cc9c1bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904620083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.904620083
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1585954823
Short name T113
Test name
Test status
Simulation time 7659915489 ps
CPU time 393.69 seconds
Started Jul 07 05:15:52 PM PDT 24
Finished Jul 07 05:22:26 PM PDT 24
Peak memory 199892 kb
Host smart-722220ee-dd1d-4aa0-ad60-704a7cad04ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585954823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1585954823
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2174767622
Short name T797
Test name
Test status
Simulation time 5565827988 ps
CPU time 49.85 seconds
Started Jul 07 05:15:52 PM PDT 24
Finished Jul 07 05:16:42 PM PDT 24
Peak memory 198844 kb
Host smart-a2c17552-06b3-4302-b9e3-6d9c7ce72540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174767622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2174767622
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1745449359
Short name T971
Test name
Test status
Simulation time 30895558365 ps
CPU time 15.8 seconds
Started Jul 07 05:15:54 PM PDT 24
Finished Jul 07 05:16:10 PM PDT 24
Peak memory 199920 kb
Host smart-56663cb4-5bb5-4913-bbf9-b28eaaebe039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745449359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1745449359
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4221696523
Short name T495
Test name
Test status
Simulation time 45443585977 ps
CPU time 16.57 seconds
Started Jul 07 05:15:50 PM PDT 24
Finished Jul 07 05:16:07 PM PDT 24
Peak memory 195644 kb
Host smart-d835f97b-cf7a-4cc6-9b57-614779c686b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221696523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4221696523
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2991441764
Short name T500
Test name
Test status
Simulation time 667832522 ps
CPU time 3.14 seconds
Started Jul 07 05:15:46 PM PDT 24
Finished Jul 07 05:15:50 PM PDT 24
Peak memory 199928 kb
Host smart-340a6f4a-112d-43d3-b73b-eb63144f8686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991441764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2991441764
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1193543408
Short name T146
Test name
Test status
Simulation time 376256535927 ps
CPU time 80.81 seconds
Started Jul 07 05:15:56 PM PDT 24
Finished Jul 07 05:17:17 PM PDT 24
Peak memory 199824 kb
Host smart-da9377e5-f7db-40ac-b2bd-46680bc0d619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193543408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1193543408
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2345161909
Short name T211
Test name
Test status
Simulation time 217347234749 ps
CPU time 428.63 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:23:04 PM PDT 24
Peak memory 224748 kb
Host smart-b3b72410-12d1-4d38-81b3-89a2430000ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345161909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2345161909
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.4230805268
Short name T687
Test name
Test status
Simulation time 1249415536 ps
CPU time 5.53 seconds
Started Jul 07 05:15:52 PM PDT 24
Finished Jul 07 05:15:58 PM PDT 24
Peak memory 199724 kb
Host smart-be6d6599-c33f-4d2b-a568-e7d76069c7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230805268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4230805268
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3664302000
Short name T533
Test name
Test status
Simulation time 36595239993 ps
CPU time 29.05 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:16:25 PM PDT 24
Peak memory 198728 kb
Host smart-901baade-5cc4-4d9a-ad51-c4f9198dea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664302000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3664302000
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3116740932
Short name T496
Test name
Test status
Simulation time 12519200 ps
CPU time 0.55 seconds
Started Jul 07 05:15:59 PM PDT 24
Finished Jul 07 05:16:00 PM PDT 24
Peak memory 194740 kb
Host smart-7befc32f-ea6c-4913-a1eb-f9837cd2b96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116740932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3116740932
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3577997707
Short name T1172
Test name
Test status
Simulation time 135801390387 ps
CPU time 315.96 seconds
Started Jul 07 05:15:56 PM PDT 24
Finished Jul 07 05:21:12 PM PDT 24
Peak memory 199908 kb
Host smart-c09f37c4-6f3a-48c3-a39d-79ea9d0fe4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577997707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3577997707
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3407757497
Short name T882
Test name
Test status
Simulation time 15566262402 ps
CPU time 43.8 seconds
Started Jul 07 05:15:55 PM PDT 24
Finished Jul 07 05:16:39 PM PDT 24
Peak memory 199900 kb
Host smart-850a1b6e-4ee8-4408-9f38-e59aaf5af1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407757497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3407757497
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2998085785
Short name T357
Test name
Test status
Simulation time 32413007018 ps
CPU time 12.14 seconds
Started Jul 07 05:15:57 PM PDT 24
Finished Jul 07 05:16:09 PM PDT 24
Peak memory 199972 kb
Host smart-5b90d215-2eb5-4048-8c8b-8aaceab179ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998085785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2998085785
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3807965413
Short name T451
Test name
Test status
Simulation time 53242323381 ps
CPU time 42.94 seconds
Started Jul 07 05:15:58 PM PDT 24
Finished Jul 07 05:16:41 PM PDT 24
Peak memory 199916 kb
Host smart-ee239a75-feeb-403f-8f10-a431d5075c85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807965413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3807965413
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1272382286
Short name T1111
Test name
Test status
Simulation time 94458738417 ps
CPU time 709.26 seconds
Started Jul 07 05:16:02 PM PDT 24
Finished Jul 07 05:27:52 PM PDT 24
Peak memory 199972 kb
Host smart-3b08150c-96b5-4a87-90ca-2e9156d861b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272382286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1272382286
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2772959115
Short name T314
Test name
Test status
Simulation time 10342377022 ps
CPU time 10.39 seconds
Started Jul 07 05:16:03 PM PDT 24
Finished Jul 07 05:16:14 PM PDT 24
Peak memory 199796 kb
Host smart-845da965-7922-44c2-ad64-e6bb1b36d545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772959115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2772959115
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1136031515
Short name T414
Test name
Test status
Simulation time 28296476922 ps
CPU time 46.08 seconds
Started Jul 07 05:16:02 PM PDT 24
Finished Jul 07 05:16:49 PM PDT 24
Peak memory 199372 kb
Host smart-a7ce1a5b-c1f1-4ed3-8f20-8d30af374980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136031515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1136031515
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2619268584
Short name T1069
Test name
Test status
Simulation time 12699480055 ps
CPU time 607.33 seconds
Started Jul 07 05:16:02 PM PDT 24
Finished Jul 07 05:26:10 PM PDT 24
Peak memory 199904 kb
Host smart-b496596c-81c4-4f6d-872e-3babbc3bf7ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2619268584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2619268584
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1470152515
Short name T70
Test name
Test status
Simulation time 2205781099 ps
CPU time 11.73 seconds
Started Jul 07 05:15:56 PM PDT 24
Finished Jul 07 05:16:09 PM PDT 24
Peak memory 198232 kb
Host smart-53a5a37e-6906-4fe8-97a8-d49d8c78a881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470152515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1470152515
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1423118781
Short name T450
Test name
Test status
Simulation time 111414687606 ps
CPU time 247.65 seconds
Started Jul 07 05:15:58 PM PDT 24
Finished Jul 07 05:20:06 PM PDT 24
Peak memory 200008 kb
Host smart-fc881a86-7e74-4f2f-a6c7-df6ac2317a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423118781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1423118781
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.777013206
Short name T929
Test name
Test status
Simulation time 5762304777 ps
CPU time 5.4 seconds
Started Jul 07 05:16:04 PM PDT 24
Finished Jul 07 05:16:10 PM PDT 24
Peak memory 196036 kb
Host smart-aa9dc193-c6ae-4c43-8e4b-7f44ce86c1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777013206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.777013206
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3311120117
Short name T716
Test name
Test status
Simulation time 5358593789 ps
CPU time 15.33 seconds
Started Jul 07 05:15:57 PM PDT 24
Finished Jul 07 05:16:13 PM PDT 24
Peak memory 199240 kb
Host smart-51421755-25b2-4dde-8b90-a20e22849ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311120117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3311120117
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3304127689
Short name T224
Test name
Test status
Simulation time 411484847023 ps
CPU time 182.77 seconds
Started Jul 07 05:16:03 PM PDT 24
Finished Jul 07 05:19:06 PM PDT 24
Peak memory 199900 kb
Host smart-096fb768-5a81-4612-bfdb-2f1e97eeec0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304127689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3304127689
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1924246250
Short name T685
Test name
Test status
Simulation time 225381209214 ps
CPU time 975.91 seconds
Started Jul 07 05:16:03 PM PDT 24
Finished Jul 07 05:32:19 PM PDT 24
Peak memory 216440 kb
Host smart-409ac987-cff3-4c23-8ca2-57d2d79c33e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924246250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1924246250
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3967061577
Short name T919
Test name
Test status
Simulation time 2924687611 ps
CPU time 1.89 seconds
Started Jul 07 05:16:02 PM PDT 24
Finished Jul 07 05:16:05 PM PDT 24
Peak memory 198776 kb
Host smart-940974e5-721e-4930-8946-3a34c099ff27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967061577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3967061577
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2320237829
Short name T459
Test name
Test status
Simulation time 21478114024 ps
CPU time 12.33 seconds
Started Jul 07 05:15:58 PM PDT 24
Finished Jul 07 05:16:11 PM PDT 24
Peak memory 200024 kb
Host smart-b79bd927-b8bb-4723-8374-5b7aa480e51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320237829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2320237829
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4220976946
Short name T28
Test name
Test status
Simulation time 11006090 ps
CPU time 0.55 seconds
Started Jul 07 05:16:10 PM PDT 24
Finished Jul 07 05:16:11 PM PDT 24
Peak memory 195148 kb
Host smart-cc0fed8b-b95c-4e16-99a9-e281d0e58d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220976946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4220976946
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1296068782
Short name T607
Test name
Test status
Simulation time 27082850825 ps
CPU time 47.5 seconds
Started Jul 07 05:16:02 PM PDT 24
Finished Jul 07 05:16:50 PM PDT 24
Peak memory 200184 kb
Host smart-267651f6-66a3-43cc-84d3-f599629b4b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296068782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1296068782
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3945458048
Short name T832
Test name
Test status
Simulation time 73871913581 ps
CPU time 29.52 seconds
Started Jul 07 05:16:03 PM PDT 24
Finished Jul 07 05:16:33 PM PDT 24
Peak memory 199684 kb
Host smart-7f70efbc-7e6c-4768-9e6f-d313d85cb477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945458048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3945458048
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1852235894
Short name T580
Test name
Test status
Simulation time 62254354639 ps
CPU time 109.14 seconds
Started Jul 07 05:16:00 PM PDT 24
Finished Jul 07 05:17:50 PM PDT 24
Peak memory 199936 kb
Host smart-d1417baa-82e3-4e6e-a2ea-dc5ee6c8b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852235894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1852235894
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.628468688
Short name T958
Test name
Test status
Simulation time 22454193737 ps
CPU time 58.58 seconds
Started Jul 07 05:16:04 PM PDT 24
Finished Jul 07 05:17:03 PM PDT 24
Peak memory 199972 kb
Host smart-91c72c6b-a031-435a-bfee-dee60a9d87bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628468688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.628468688
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2713066711
Short name T868
Test name
Test status
Simulation time 61920825201 ps
CPU time 629.65 seconds
Started Jul 07 05:16:04 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 199808 kb
Host smart-18344c98-55e7-42a2-8596-b09d8a6d9f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713066711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2713066711
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3412777036
Short name T373
Test name
Test status
Simulation time 6868343580 ps
CPU time 12.78 seconds
Started Jul 07 05:16:06 PM PDT 24
Finished Jul 07 05:16:19 PM PDT 24
Peak memory 199616 kb
Host smart-9415869b-ff89-4766-b9a2-574efea174cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412777036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3412777036
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2438731563
Short name T920
Test name
Test status
Simulation time 78183114840 ps
CPU time 174.79 seconds
Started Jul 07 05:16:07 PM PDT 24
Finished Jul 07 05:19:02 PM PDT 24
Peak memory 200104 kb
Host smart-71fb46a1-860a-461f-b353-eb5f758c2043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438731563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2438731563
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1315760793
Short name T977
Test name
Test status
Simulation time 14586806909 ps
CPU time 764.4 seconds
Started Jul 07 05:16:04 PM PDT 24
Finished Jul 07 05:28:49 PM PDT 24
Peak memory 199888 kb
Host smart-32a3249f-3d60-4fdc-8008-6c4b916afbbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315760793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1315760793
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4035341398
Short name T504
Test name
Test status
Simulation time 5694247734 ps
CPU time 44.63 seconds
Started Jul 07 05:16:05 PM PDT 24
Finished Jul 07 05:16:50 PM PDT 24
Peak memory 199432 kb
Host smart-e4ccd8cc-a33f-4c72-9e68-fb5b427da1df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035341398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4035341398
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3214798520
Short name T623
Test name
Test status
Simulation time 13993206904 ps
CPU time 39.83 seconds
Started Jul 07 05:16:05 PM PDT 24
Finished Jul 07 05:16:45 PM PDT 24
Peak memory 199976 kb
Host smart-0ebf6ae9-eead-4d65-b377-c6cec3af8f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214798520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3214798520
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1198208228
Short name T1073
Test name
Test status
Simulation time 5610398220 ps
CPU time 8.35 seconds
Started Jul 07 05:16:03 PM PDT 24
Finished Jul 07 05:16:12 PM PDT 24
Peak memory 196060 kb
Host smart-6d0472c8-9cd6-47c2-b8ad-97c3db257cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198208228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1198208228
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3309478034
Short name T659
Test name
Test status
Simulation time 129391534 ps
CPU time 0.82 seconds
Started Jul 07 05:16:00 PM PDT 24
Finished Jul 07 05:16:01 PM PDT 24
Peak memory 197916 kb
Host smart-bef47f78-38ca-417c-a6a8-69694f5304fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309478034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3309478034
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.143382489
Short name T722
Test name
Test status
Simulation time 284530136130 ps
CPU time 438.47 seconds
Started Jul 07 05:16:10 PM PDT 24
Finished Jul 07 05:23:29 PM PDT 24
Peak memory 208248 kb
Host smart-7a9dbb0f-fa4f-4a14-b62e-4167bd6c0277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143382489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.143382489
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1902433553
Short name T816
Test name
Test status
Simulation time 6404279232 ps
CPU time 24.61 seconds
Started Jul 07 05:16:03 PM PDT 24
Finished Jul 07 05:16:28 PM PDT 24
Peak memory 199960 kb
Host smart-40a2a726-bdae-4bca-8d97-9df909a24ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902433553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1902433553
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2750009039
Short name T579
Test name
Test status
Simulation time 36529805980 ps
CPU time 16.02 seconds
Started Jul 07 05:16:01 PM PDT 24
Finished Jul 07 05:16:18 PM PDT 24
Peak memory 199924 kb
Host smart-6c85b4ae-3b1f-4924-b6bf-9ddc702bee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750009039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2750009039
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1614807087
Short name T29
Test name
Test status
Simulation time 16074892 ps
CPU time 0.57 seconds
Started Jul 07 05:16:11 PM PDT 24
Finished Jul 07 05:16:12 PM PDT 24
Peak memory 195512 kb
Host smart-328e2801-7f35-4bd0-b0bc-d97787f72d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614807087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1614807087
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2946099624
Short name T155
Test name
Test status
Simulation time 31575216547 ps
CPU time 15.4 seconds
Started Jul 07 05:16:09 PM PDT 24
Finished Jul 07 05:16:25 PM PDT 24
Peak memory 199908 kb
Host smart-d755193c-b049-4407-8e2b-c90b3f45fa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946099624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2946099624
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1098583571
Short name T1030
Test name
Test status
Simulation time 24587326607 ps
CPU time 58.19 seconds
Started Jul 07 05:16:10 PM PDT 24
Finished Jul 07 05:17:08 PM PDT 24
Peak memory 199984 kb
Host smart-64a5ad7f-1cdf-4d92-a63c-67ee93c97328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098583571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1098583571
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3184519300
Short name T219
Test name
Test status
Simulation time 24012765511 ps
CPU time 36.13 seconds
Started Jul 07 05:16:10 PM PDT 24
Finished Jul 07 05:16:47 PM PDT 24
Peak memory 199976 kb
Host smart-336ade0c-ebec-43fd-9896-a74f9f44e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184519300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3184519300
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1202963086
Short name T19
Test name
Test status
Simulation time 58768570278 ps
CPU time 94.02 seconds
Started Jul 07 05:16:11 PM PDT 24
Finished Jul 07 05:17:45 PM PDT 24
Peak memory 199920 kb
Host smart-909b823b-787e-4305-8a55-e0fa706733b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202963086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1202963086
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.433638568
Short name T777
Test name
Test status
Simulation time 91494655463 ps
CPU time 797.12 seconds
Started Jul 07 05:16:14 PM PDT 24
Finished Jul 07 05:29:32 PM PDT 24
Peak memory 199956 kb
Host smart-11108f54-271f-42cb-ba76-d449fe99a3c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433638568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.433638568
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1962116180
Short name T1166
Test name
Test status
Simulation time 5601223368 ps
CPU time 12.46 seconds
Started Jul 07 05:16:15 PM PDT 24
Finished Jul 07 05:16:28 PM PDT 24
Peak memory 199904 kb
Host smart-1bec49f4-b425-4a29-8b7b-9c0c09e19125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962116180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1962116180
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3824276315
Short name T600
Test name
Test status
Simulation time 118969391818 ps
CPU time 106.59 seconds
Started Jul 07 05:16:09 PM PDT 24
Finished Jul 07 05:17:56 PM PDT 24
Peak memory 208280 kb
Host smart-d5701f8b-7369-489c-8cdc-34acbdc57f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824276315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3824276315
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4244924951
Short name T678
Test name
Test status
Simulation time 30789780802 ps
CPU time 1821.37 seconds
Started Jul 07 05:16:11 PM PDT 24
Finished Jul 07 05:46:33 PM PDT 24
Peak memory 199864 kb
Host smart-04a0cf55-7766-4e4e-ad2b-780aafe159ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244924951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4244924951
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.221685766
Short name T485
Test name
Test status
Simulation time 1168079573 ps
CPU time 2.25 seconds
Started Jul 07 05:16:09 PM PDT 24
Finished Jul 07 05:16:12 PM PDT 24
Peak memory 197012 kb
Host smart-55b1b3d9-febc-45bc-894d-38869593eb56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221685766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.221685766
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.433537067
Short name T652
Test name
Test status
Simulation time 124748893215 ps
CPU time 101.53 seconds
Started Jul 07 05:16:13 PM PDT 24
Finished Jul 07 05:17:55 PM PDT 24
Peak memory 199956 kb
Host smart-be704190-d905-4355-b8bc-7adfc280ab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433537067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.433537067
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1337210319
Short name T518
Test name
Test status
Simulation time 72892127322 ps
CPU time 52.55 seconds
Started Jul 07 05:16:15 PM PDT 24
Finished Jul 07 05:17:08 PM PDT 24
Peak memory 196212 kb
Host smart-d5ec231f-2713-455b-8ff2-ff883c108c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337210319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1337210319
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.4216788639
Short name T552
Test name
Test status
Simulation time 496601056 ps
CPU time 1.29 seconds
Started Jul 07 05:16:08 PM PDT 24
Finished Jul 07 05:16:09 PM PDT 24
Peak memory 199980 kb
Host smart-4e902e16-deb4-42ae-ae69-69244903e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216788639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.4216788639
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2650747968
Short name T1130
Test name
Test status
Simulation time 67667852621 ps
CPU time 1553.71 seconds
Started Jul 07 05:16:13 PM PDT 24
Finished Jul 07 05:42:07 PM PDT 24
Peak memory 225000 kb
Host smart-07747cfd-924d-451c-90c0-b2919b0f315a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650747968 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2650747968
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1472522262
Short name T463
Test name
Test status
Simulation time 6052009030 ps
CPU time 20.68 seconds
Started Jul 07 05:16:13 PM PDT 24
Finished Jul 07 05:16:34 PM PDT 24
Peak memory 199888 kb
Host smart-ef8776c4-4293-4d86-905d-765de9493d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472522262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1472522262
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3156931729
Short name T437
Test name
Test status
Simulation time 17583807751 ps
CPU time 29.99 seconds
Started Jul 07 05:16:11 PM PDT 24
Finished Jul 07 05:16:41 PM PDT 24
Peak memory 199968 kb
Host smart-4a9f79f3-d96c-400b-9ae1-dd6ceec3b424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156931729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3156931729
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.4102618406
Short name T335
Test name
Test status
Simulation time 98078397 ps
CPU time 0.55 seconds
Started Jul 07 05:16:20 PM PDT 24
Finished Jul 07 05:16:21 PM PDT 24
Peak memory 195288 kb
Host smart-2e608736-8559-4382-9d1b-d9bc8f6c6540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102618406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4102618406
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2627274766
Short name T1015
Test name
Test status
Simulation time 86418802974 ps
CPU time 147.1 seconds
Started Jul 07 05:16:17 PM PDT 24
Finished Jul 07 05:18:44 PM PDT 24
Peak memory 199908 kb
Host smart-4d67f177-2739-4b30-a55f-370c4e630e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627274766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2627274766
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2085160558
Short name T181
Test name
Test status
Simulation time 435461500126 ps
CPU time 31.61 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:16:51 PM PDT 24
Peak memory 199864 kb
Host smart-60a2a224-a4d8-4888-a21b-f6c70987adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085160558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2085160558
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2665531002
Short name T983
Test name
Test status
Simulation time 71548829073 ps
CPU time 114.79 seconds
Started Jul 07 05:16:17 PM PDT 24
Finished Jul 07 05:18:12 PM PDT 24
Peak memory 199848 kb
Host smart-9aa54ebb-5123-4b85-ac88-931c5d9f6c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665531002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2665531002
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3689370697
Short name T774
Test name
Test status
Simulation time 9945448932 ps
CPU time 14.68 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:16:34 PM PDT 24
Peak memory 198180 kb
Host smart-1bc98131-dbee-426e-877e-e0c18bbdb168
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689370697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3689370697
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1505868389
Short name T302
Test name
Test status
Simulation time 125453401628 ps
CPU time 246.95 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:20:27 PM PDT 24
Peak memory 199984 kb
Host smart-62c40da6-6daa-416c-9e74-1a2cf691bce5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505868389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1505868389
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3360618951
Short name T22
Test name
Test status
Simulation time 1556348377 ps
CPU time 3.14 seconds
Started Jul 07 05:16:17 PM PDT 24
Finished Jul 07 05:16:20 PM PDT 24
Peak memory 198572 kb
Host smart-424a5b5e-29a4-483b-b11b-500c9fc34830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360618951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3360618951
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2238595078
Short name T1024
Test name
Test status
Simulation time 43159273492 ps
CPU time 75.85 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:17:35 PM PDT 24
Peak memory 200140 kb
Host smart-306e0fe9-8375-4333-9c52-b0db571853c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238595078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2238595078
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1432454011
Short name T1163
Test name
Test status
Simulation time 8316031016 ps
CPU time 127.25 seconds
Started Jul 07 05:16:18 PM PDT 24
Finished Jul 07 05:18:25 PM PDT 24
Peak memory 199904 kb
Host smart-f3ba14c6-86f6-4333-b477-904842bdfca5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432454011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1432454011
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1616377072
Short name T1149
Test name
Test status
Simulation time 1711531058 ps
CPU time 2.61 seconds
Started Jul 07 05:16:18 PM PDT 24
Finished Jul 07 05:16:20 PM PDT 24
Peak memory 197752 kb
Host smart-d17b3ade-77a2-4ab4-abe3-ceadd0a0092b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616377072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1616377072
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1699733869
Short name T1055
Test name
Test status
Simulation time 78682828674 ps
CPU time 118.42 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:18:18 PM PDT 24
Peak memory 199936 kb
Host smart-b61ab553-3004-42fc-9695-8d06c20db4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699733869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1699733869
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1640245454
Short name T353
Test name
Test status
Simulation time 2887311752 ps
CPU time 1.75 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:16:21 PM PDT 24
Peak memory 196392 kb
Host smart-1990dd3e-ddd3-41d2-af82-ab0ff2b155ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640245454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1640245454
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2075280109
Short name T1175
Test name
Test status
Simulation time 510685703 ps
CPU time 1.91 seconds
Started Jul 07 05:16:12 PM PDT 24
Finished Jul 07 05:16:14 PM PDT 24
Peak memory 198888 kb
Host smart-75862527-99e3-46db-8869-5f63491ff7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075280109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2075280109
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3082998442
Short name T491
Test name
Test status
Simulation time 316109205478 ps
CPU time 36.22 seconds
Started Jul 07 05:16:18 PM PDT 24
Finished Jul 07 05:16:55 PM PDT 24
Peak memory 199880 kb
Host smart-578c88ec-2b89-4182-b595-a32d3e14bc70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082998442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3082998442
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2333308197
Short name T1134
Test name
Test status
Simulation time 59696291421 ps
CPU time 337.16 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:21:57 PM PDT 24
Peak memory 216500 kb
Host smart-2f90239f-0349-4cf1-b01b-fe97646b25f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333308197 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2333308197
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4057360283
Short name T501
Test name
Test status
Simulation time 6257640868 ps
CPU time 28.22 seconds
Started Jul 07 05:16:21 PM PDT 24
Finished Jul 07 05:16:49 PM PDT 24
Peak memory 199924 kb
Host smart-6d8cd632-f069-4d65-ac16-4fa386680469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057360283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4057360283
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2762087498
Short name T261
Test name
Test status
Simulation time 45994593326 ps
CPU time 16.29 seconds
Started Jul 07 05:16:19 PM PDT 24
Finished Jul 07 05:16:36 PM PDT 24
Peak memory 199980 kb
Host smart-1679cff4-02e3-4c03-ac9b-b1cf399677a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762087498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2762087498
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2695787028
Short name T862
Test name
Test status
Simulation time 93408502 ps
CPU time 0.54 seconds
Started Jul 07 05:13:00 PM PDT 24
Finished Jul 07 05:13:01 PM PDT 24
Peak memory 194944 kb
Host smart-c5ffa5b7-a7ad-4ebe-9281-7821afa4c06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695787028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2695787028
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2867250766
Short name T282
Test name
Test status
Simulation time 177065186874 ps
CPU time 442.07 seconds
Started Jul 07 05:12:49 PM PDT 24
Finished Jul 07 05:20:12 PM PDT 24
Peak memory 199980 kb
Host smart-c4449a94-8d63-4d49-b8de-535ea44dec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867250766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2867250766
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1061758813
Short name T896
Test name
Test status
Simulation time 162196982476 ps
CPU time 70.67 seconds
Started Jul 07 05:12:44 PM PDT 24
Finished Jul 07 05:13:56 PM PDT 24
Peak memory 199996 kb
Host smart-088284d1-9c1a-4d21-b949-659e3af5f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061758813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1061758813
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1261555063
Short name T494
Test name
Test status
Simulation time 166500609871 ps
CPU time 135.19 seconds
Started Jul 07 05:12:47 PM PDT 24
Finished Jul 07 05:15:03 PM PDT 24
Peak memory 199920 kb
Host smart-92b2b548-069f-4de5-96c4-f1880dbb4832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261555063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1261555063
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1433684053
Short name T1016
Test name
Test status
Simulation time 42498821123 ps
CPU time 20.35 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:13:19 PM PDT 24
Peak memory 198084 kb
Host smart-a338c193-e342-41d9-ab79-779c0c3324b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433684053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1433684053
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2796443472
Short name T382
Test name
Test status
Simulation time 104262800604 ps
CPU time 320.57 seconds
Started Jul 07 05:12:50 PM PDT 24
Finished Jul 07 05:18:11 PM PDT 24
Peak memory 200180 kb
Host smart-769f69ea-f44e-45f1-8c3e-f429ba7c71a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796443472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2796443472
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.588846522
Short name T362
Test name
Test status
Simulation time 11939857272 ps
CPU time 22.52 seconds
Started Jul 07 05:12:46 PM PDT 24
Finished Jul 07 05:13:09 PM PDT 24
Peak memory 199740 kb
Host smart-6c6f238b-5f0f-41bd-b6c0-e5da5274e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588846522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.588846522
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3449424009
Short name T642
Test name
Test status
Simulation time 32152324174 ps
CPU time 49.71 seconds
Started Jul 07 05:12:46 PM PDT 24
Finished Jul 07 05:13:36 PM PDT 24
Peak memory 200056 kb
Host smart-e0360818-e91c-423c-a51f-ca1ffac0cc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449424009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3449424009
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2514078887
Short name T799
Test name
Test status
Simulation time 12313644972 ps
CPU time 262.39 seconds
Started Jul 07 05:12:48 PM PDT 24
Finished Jul 07 05:17:12 PM PDT 24
Peak memory 199836 kb
Host smart-5119cbae-7c20-438d-8184-f8297bd23c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514078887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2514078887
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.991561625
Short name T1028
Test name
Test status
Simulation time 7629172389 ps
CPU time 27.42 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:13:23 PM PDT 24
Peak memory 198048 kb
Host smart-09084136-98ee-4cec-b6a0-b007c1f83272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991561625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.991561625
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2284399979
Short name T613
Test name
Test status
Simulation time 143062416008 ps
CPU time 106.71 seconds
Started Jul 07 05:12:48 PM PDT 24
Finished Jul 07 05:14:36 PM PDT 24
Peak memory 199888 kb
Host smart-2e9ffd90-ab19-419e-bf60-80b4630011be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284399979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2284399979
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1732909670
Short name T395
Test name
Test status
Simulation time 5709425050 ps
CPU time 4.43 seconds
Started Jul 07 05:12:46 PM PDT 24
Finished Jul 07 05:12:51 PM PDT 24
Peak memory 195964 kb
Host smart-ffc9162a-9a8a-42f6-a856-36ce4973602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732909670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1732909670
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3839455807
Short name T583
Test name
Test status
Simulation time 856958697 ps
CPU time 2.4 seconds
Started Jul 07 05:12:48 PM PDT 24
Finished Jul 07 05:12:52 PM PDT 24
Peak memory 198492 kb
Host smart-fc2b06a9-8c50-4ea7-aaa2-f1550650cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839455807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3839455807
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1347215106
Short name T218
Test name
Test status
Simulation time 523344303907 ps
CPU time 511.26 seconds
Started Jul 07 05:12:52 PM PDT 24
Finished Jul 07 05:21:24 PM PDT 24
Peak memory 199888 kb
Host smart-82103201-045a-402f-b65d-dc5c08e1cfaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347215106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1347215106
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3608786540
Short name T309
Test name
Test status
Simulation time 5988203530 ps
CPU time 19.85 seconds
Started Jul 07 05:12:48 PM PDT 24
Finished Jul 07 05:13:09 PM PDT 24
Peak memory 199936 kb
Host smart-769ed326-f2df-4a07-9a1b-14110f934f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608786540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3608786540
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2452504259
Short name T430
Test name
Test status
Simulation time 34849423553 ps
CPU time 49.66 seconds
Started Jul 07 05:12:44 PM PDT 24
Finished Jul 07 05:13:35 PM PDT 24
Peak memory 199956 kb
Host smart-3c2cad09-9598-4131-aa65-1d19e015dc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452504259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2452504259
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1477685514
Short name T458
Test name
Test status
Simulation time 6391741541 ps
CPU time 10.13 seconds
Started Jul 07 05:16:21 PM PDT 24
Finished Jul 07 05:16:31 PM PDT 24
Peak memory 199584 kb
Host smart-9fda0f67-34e7-432d-82ba-3a4805f2cad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477685514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1477685514
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2212565327
Short name T37
Test name
Test status
Simulation time 23894439951 ps
CPU time 64.39 seconds
Started Jul 07 05:16:27 PM PDT 24
Finished Jul 07 05:17:32 PM PDT 24
Peak memory 216672 kb
Host smart-f40fa9c4-fd0a-42e2-810f-b0aed3c2f48a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212565327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2212565327
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.407486979
Short name T517
Test name
Test status
Simulation time 76149284870 ps
CPU time 28.07 seconds
Started Jul 07 05:16:24 PM PDT 24
Finished Jul 07 05:16:53 PM PDT 24
Peak memory 199948 kb
Host smart-30dff5ff-3c0c-42b8-ae96-774b2fd5b9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407486979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.407486979
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2896176814
Short name T793
Test name
Test status
Simulation time 170994942041 ps
CPU time 56.02 seconds
Started Jul 07 05:16:20 PM PDT 24
Finished Jul 07 05:17:16 PM PDT 24
Peak memory 199812 kb
Host smart-5b256682-5b10-4a8c-a9f6-66dd0370f9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896176814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2896176814
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.4081231155
Short name T1036
Test name
Test status
Simulation time 64675863986 ps
CPU time 226.04 seconds
Started Jul 07 05:16:23 PM PDT 24
Finished Jul 07 05:20:09 PM PDT 24
Peak memory 208808 kb
Host smart-e9888f08-4d4e-4d4a-8052-84fa53e22647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081231155 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.4081231155
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3310770557
Short name T585
Test name
Test status
Simulation time 20018642460 ps
CPU time 31.1 seconds
Started Jul 07 05:16:21 PM PDT 24
Finished Jul 07 05:16:53 PM PDT 24
Peak memory 199860 kb
Host smart-318575bd-3d1c-48c3-bf0a-e63c9fbd86bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310770557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3310770557
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1318853318
Short name T598
Test name
Test status
Simulation time 57816286665 ps
CPU time 897.03 seconds
Started Jul 07 05:16:22 PM PDT 24
Finished Jul 07 05:31:19 PM PDT 24
Peak memory 216416 kb
Host smart-7144d0fd-ee40-4781-9d67-d4c60b32e806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318853318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1318853318
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1547038763
Short name T846
Test name
Test status
Simulation time 84130634074 ps
CPU time 35.77 seconds
Started Jul 07 05:16:22 PM PDT 24
Finished Jul 07 05:16:58 PM PDT 24
Peak memory 199940 kb
Host smart-ecedf43c-2e1f-458e-b218-7f51611cbacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547038763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1547038763
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2580026829
Short name T760
Test name
Test status
Simulation time 327427836928 ps
CPU time 989.69 seconds
Started Jul 07 05:16:24 PM PDT 24
Finished Jul 07 05:32:54 PM PDT 24
Peak memory 224724 kb
Host smart-de68c310-e2b0-48bd-8a40-c1ba9511f4ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580026829 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2580026829
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.426422699
Short name T703
Test name
Test status
Simulation time 27692787410 ps
CPU time 47.98 seconds
Started Jul 07 05:16:25 PM PDT 24
Finished Jul 07 05:17:14 PM PDT 24
Peak memory 199964 kb
Host smart-af41701d-cb4b-4974-8f9a-f07a53eef28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426422699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.426422699
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1708006406
Short name T38
Test name
Test status
Simulation time 44912353485 ps
CPU time 337.26 seconds
Started Jul 07 05:16:23 PM PDT 24
Finished Jul 07 05:22:00 PM PDT 24
Peak memory 215536 kb
Host smart-fd5cd526-5d1a-4216-96f3-9ac49c23f73c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708006406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1708006406
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2690283372
Short name T203
Test name
Test status
Simulation time 116129060475 ps
CPU time 269.39 seconds
Started Jul 07 05:16:24 PM PDT 24
Finished Jul 07 05:20:54 PM PDT 24
Peak memory 199884 kb
Host smart-9b621616-ba77-4565-ab3f-13ab4f03fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690283372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2690283372
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3477871913
Short name T1102
Test name
Test status
Simulation time 105601942356 ps
CPU time 589.99 seconds
Started Jul 07 05:16:23 PM PDT 24
Finished Jul 07 05:26:14 PM PDT 24
Peak memory 224864 kb
Host smart-0b939e8c-d868-49dd-9686-d604cbdc1568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477871913 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3477871913
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3369571070
Short name T298
Test name
Test status
Simulation time 41905906378 ps
CPU time 32.64 seconds
Started Jul 07 05:16:23 PM PDT 24
Finished Jul 07 05:16:56 PM PDT 24
Peak memory 199908 kb
Host smart-6c6c566a-450a-470a-8a1c-a57a36d26e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369571070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3369571070
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2610676086
Short name T68
Test name
Test status
Simulation time 243710731475 ps
CPU time 602.23 seconds
Started Jul 07 05:16:23 PM PDT 24
Finished Jul 07 05:26:26 PM PDT 24
Peak memory 216496 kb
Host smart-14a2fd23-6ce2-49e1-bf22-342a6f177e2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610676086 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2610676086
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2671861931
Short name T465
Test name
Test status
Simulation time 21430293674 ps
CPU time 34.77 seconds
Started Jul 07 05:16:23 PM PDT 24
Finished Jul 07 05:16:58 PM PDT 24
Peak memory 199920 kb
Host smart-82af755c-8460-423c-a755-14876e2073cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671861931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2671861931
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2357873372
Short name T144
Test name
Test status
Simulation time 120257050262 ps
CPU time 15.87 seconds
Started Jul 07 05:16:27 PM PDT 24
Finished Jul 07 05:16:43 PM PDT 24
Peak memory 199996 kb
Host smart-2da61da0-66c1-4ad8-bc3c-25abd1fd78e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357873372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2357873372
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1931147046
Short name T64
Test name
Test status
Simulation time 74818637053 ps
CPU time 197.32 seconds
Started Jul 07 05:16:26 PM PDT 24
Finished Jul 07 05:19:43 PM PDT 24
Peak memory 216484 kb
Host smart-2ffe9635-7dc4-4398-96c7-a0ce4fa62da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931147046 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1931147046
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2995021395
Short name T1039
Test name
Test status
Simulation time 36306748 ps
CPU time 0.55 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:12:58 PM PDT 24
Peak memory 195308 kb
Host smart-9584c024-b55e-4023-9751-900440767183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995021395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2995021395
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1315311846
Short name T942
Test name
Test status
Simulation time 103359264208 ps
CPU time 154.63 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:15:30 PM PDT 24
Peak memory 199944 kb
Host smart-be077982-7516-46ff-a012-722f8d1359b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315311846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1315311846
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1941351971
Short name T668
Test name
Test status
Simulation time 68717038374 ps
CPU time 25.1 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:13:25 PM PDT 24
Peak memory 199928 kb
Host smart-1723c7e5-86ef-4c53-b200-5284c77dbeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941351971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1941351971
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.1534952516
Short name T907
Test name
Test status
Simulation time 16651904547 ps
CPU time 24 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:13:21 PM PDT 24
Peak memory 199912 kb
Host smart-91c8b436-9744-431a-9322-3f635279ef31
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534952516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1534952516
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4116233770
Short name T1143
Test name
Test status
Simulation time 146408164777 ps
CPU time 150.83 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:15:32 PM PDT 24
Peak memory 199916 kb
Host smart-4f8a4034-6159-480d-8c1c-f5f170ab0516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116233770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4116233770
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2094313749
Short name T460
Test name
Test status
Simulation time 8561798757 ps
CPU time 7.8 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:13:07 PM PDT 24
Peak memory 199872 kb
Host smart-93d027e1-dd4f-4a8a-b063-8dfa074d3161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094313749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2094313749
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3516388507
Short name T300
Test name
Test status
Simulation time 26982255345 ps
CPU time 22.27 seconds
Started Jul 07 05:12:48 PM PDT 24
Finished Jul 07 05:13:12 PM PDT 24
Peak memory 198800 kb
Host smart-f564e8fd-ec94-4156-aae7-64d8d484a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516388507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3516388507
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2644965444
Short name T2
Test name
Test status
Simulation time 30496298209 ps
CPU time 824.4 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 199980 kb
Host smart-f242a41b-d0c7-44de-b54d-eca62d840465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644965444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2644965444
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.516729011
Short name T1096
Test name
Test status
Simulation time 3997768740 ps
CPU time 29.62 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:13:25 PM PDT 24
Peak memory 197872 kb
Host smart-c9a3d480-9a17-42a7-a7fc-bd029ce2cb26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516729011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.516729011
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.859801197
Short name T399
Test name
Test status
Simulation time 15068290525 ps
CPU time 22.28 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:13:18 PM PDT 24
Peak memory 199740 kb
Host smart-5d68f78b-7b73-4844-ac78-70fff7a3af55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859801197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.859801197
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2750631898
Short name T1029
Test name
Test status
Simulation time 4523606172 ps
CPU time 2.34 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:13:00 PM PDT 24
Peak memory 196404 kb
Host smart-21de3d22-8fac-460a-b5be-71de02fb9803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750631898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2750631898
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2804622985
Short name T1159
Test name
Test status
Simulation time 5542658030 ps
CPU time 14.22 seconds
Started Jul 07 05:12:54 PM PDT 24
Finished Jul 07 05:13:09 PM PDT 24
Peak memory 199816 kb
Host smart-fd29c8f4-3a90-483b-8ede-42ae44ef3b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804622985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2804622985
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.4210602104
Short name T752
Test name
Test status
Simulation time 236107800841 ps
CPU time 209.85 seconds
Started Jul 07 05:12:49 PM PDT 24
Finished Jul 07 05:16:20 PM PDT 24
Peak memory 199892 kb
Host smart-4dc24695-31d3-4c17-bf33-3032f470e65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210602104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4210602104
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.4037561065
Short name T174
Test name
Test status
Simulation time 204550158567 ps
CPU time 2175.57 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:49:14 PM PDT 24
Peak memory 224676 kb
Host smart-69f98597-4307-4ddd-8fea-ab420524796c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037561065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.4037561065
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1552017543
Short name T1009
Test name
Test status
Simulation time 13666010352 ps
CPU time 18.85 seconds
Started Jul 07 05:12:52 PM PDT 24
Finished Jul 07 05:13:11 PM PDT 24
Peak memory 199944 kb
Host smart-834d7494-bdab-4310-a7ee-c1e51c28407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552017543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1552017543
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.627183486
Short name T317
Test name
Test status
Simulation time 107253804542 ps
CPU time 142.11 seconds
Started Jul 07 05:12:54 PM PDT 24
Finished Jul 07 05:15:17 PM PDT 24
Peak memory 199968 kb
Host smart-87f15862-8f90-4e8b-b174-a053cd5dd08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627183486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.627183486
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2208411958
Short name T931
Test name
Test status
Simulation time 102237300545 ps
CPU time 43.84 seconds
Started Jul 07 05:16:28 PM PDT 24
Finished Jul 07 05:17:12 PM PDT 24
Peak memory 199872 kb
Host smart-85bf4eb3-fe74-4041-8546-fc700f4bd9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208411958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2208411958
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.4182430023
Short name T1138
Test name
Test status
Simulation time 203907459924 ps
CPU time 2256.34 seconds
Started Jul 07 05:16:28 PM PDT 24
Finished Jul 07 05:54:05 PM PDT 24
Peak memory 241216 kb
Host smart-9232ab6a-8365-4e89-867e-4bb85f4edd98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182430023 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.4182430023
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.439262435
Short name T991
Test name
Test status
Simulation time 19494469054 ps
CPU time 38.27 seconds
Started Jul 07 05:16:25 PM PDT 24
Finished Jul 07 05:17:04 PM PDT 24
Peak memory 199900 kb
Host smart-7db2f86e-e353-40fd-b994-b91f9899c260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439262435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.439262435
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3286148982
Short name T545
Test name
Test status
Simulation time 39938999096 ps
CPU time 135.04 seconds
Started Jul 07 05:16:25 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 215792 kb
Host smart-f0b19852-429d-4d9b-8275-32b9efcab031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286148982 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3286148982
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3935489779
Short name T515
Test name
Test status
Simulation time 39422553082 ps
CPU time 33.01 seconds
Started Jul 07 05:16:27 PM PDT 24
Finished Jul 07 05:17:00 PM PDT 24
Peak memory 199948 kb
Host smart-c9d9c689-552f-4633-a027-9dce389342f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935489779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3935489779
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1926308472
Short name T1088
Test name
Test status
Simulation time 113595987566 ps
CPU time 196.06 seconds
Started Jul 07 05:16:27 PM PDT 24
Finished Jul 07 05:19:43 PM PDT 24
Peak memory 208332 kb
Host smart-dccb3908-14ad-4e0b-baa8-9ad991a85b3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926308472 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1926308472
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.291281235
Short name T318
Test name
Test status
Simulation time 183673635245 ps
CPU time 55.34 seconds
Started Jul 07 05:16:27 PM PDT 24
Finished Jul 07 05:17:23 PM PDT 24
Peak memory 199968 kb
Host smart-cc4da507-de2b-44cd-907c-719d90bb0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291281235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.291281235
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2120799252
Short name T959
Test name
Test status
Simulation time 59243080839 ps
CPU time 529.14 seconds
Started Jul 07 05:16:33 PM PDT 24
Finished Jul 07 05:25:22 PM PDT 24
Peak memory 224948 kb
Host smart-72e55a45-a049-467f-af1f-eb20ef3956ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120799252 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2120799252
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1857409769
Short name T392
Test name
Test status
Simulation time 104079435969 ps
CPU time 74.25 seconds
Started Jul 07 05:16:30 PM PDT 24
Finished Jul 07 05:17:44 PM PDT 24
Peak memory 199708 kb
Host smart-b946a4de-38a6-4d46-abd8-78a327225e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857409769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1857409769
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.761235898
Short name T830
Test name
Test status
Simulation time 65693966195 ps
CPU time 711.97 seconds
Started Jul 07 05:16:32 PM PDT 24
Finished Jul 07 05:28:24 PM PDT 24
Peak memory 224816 kb
Host smart-b5d77521-abc8-48b7-8f02-f49420f0a03b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761235898 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.761235898
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1609259845
Short name T192
Test name
Test status
Simulation time 63528171256 ps
CPU time 68.19 seconds
Started Jul 07 05:16:30 PM PDT 24
Finished Jul 07 05:17:38 PM PDT 24
Peak memory 199956 kb
Host smart-7e479c4d-aa91-4b80-98c9-925e96c18d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609259845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1609259845
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2477257535
Short name T304
Test name
Test status
Simulation time 20519543778 ps
CPU time 239.39 seconds
Started Jul 07 05:16:30 PM PDT 24
Finished Jul 07 05:20:30 PM PDT 24
Peak memory 216476 kb
Host smart-315e5375-7a51-4cc9-aa81-fbf06c68e2ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477257535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2477257535
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.114230307
Short name T1099
Test name
Test status
Simulation time 89719620768 ps
CPU time 129.72 seconds
Started Jul 07 05:16:31 PM PDT 24
Finished Jul 07 05:18:40 PM PDT 24
Peak memory 199944 kb
Host smart-69ba0a41-2a70-4620-83c3-ef17a7b0a7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114230307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.114230307
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3672806428
Short name T854
Test name
Test status
Simulation time 204417701536 ps
CPU time 159.02 seconds
Started Jul 07 05:16:33 PM PDT 24
Finished Jul 07 05:19:12 PM PDT 24
Peak memory 216480 kb
Host smart-29a695eb-35f3-4c25-818e-a6be3836770d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672806428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3672806428
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.806281056
Short name T773
Test name
Test status
Simulation time 62767997628 ps
CPU time 499.24 seconds
Started Jul 07 05:16:31 PM PDT 24
Finished Jul 07 05:24:51 PM PDT 24
Peak memory 216672 kb
Host smart-5e25ef25-cfab-4c9f-b22a-947c73ff45fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806281056 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.806281056
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1077458830
Short name T733
Test name
Test status
Simulation time 49543178186 ps
CPU time 69.25 seconds
Started Jul 07 05:16:32 PM PDT 24
Finished Jul 07 05:17:42 PM PDT 24
Peak memory 199908 kb
Host smart-37879ad6-06a2-4f6f-bc4a-458a9a835718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077458830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1077458830
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2596722680
Short name T732
Test name
Test status
Simulation time 307050743745 ps
CPU time 322.5 seconds
Started Jul 07 05:16:30 PM PDT 24
Finished Jul 07 05:21:53 PM PDT 24
Peak memory 216416 kb
Host smart-5d88e3c9-8718-431f-9d20-56adc956edb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596722680 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2596722680
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3886961217
Short name T805
Test name
Test status
Simulation time 119807804838 ps
CPU time 48.1 seconds
Started Jul 07 05:16:29 PM PDT 24
Finished Jul 07 05:17:17 PM PDT 24
Peak memory 199908 kb
Host smart-1bd7f8ca-a719-4793-8041-064ffc782286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886961217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3886961217
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2081999857
Short name T719
Test name
Test status
Simulation time 107836816742 ps
CPU time 326.52 seconds
Started Jul 07 05:16:31 PM PDT 24
Finished Jul 07 05:21:58 PM PDT 24
Peak memory 216040 kb
Host smart-975c0f43-1a12-4ee1-ac2d-d8a44f858abf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081999857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2081999857
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2868432859
Short name T536
Test name
Test status
Simulation time 11140046 ps
CPU time 0.55 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:12:59 PM PDT 24
Peak memory 195220 kb
Host smart-c2021068-2b68-4d43-a43f-cfd6b4a846d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868432859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2868432859
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3865582736
Short name T679
Test name
Test status
Simulation time 168992763867 ps
CPU time 133.71 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:15:13 PM PDT 24
Peak memory 199932 kb
Host smart-6776fdcc-af2b-43eb-acb7-97008e1a2508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865582736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3865582736
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.523469977
Short name T145
Test name
Test status
Simulation time 28990429617 ps
CPU time 31.54 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:13:32 PM PDT 24
Peak memory 199932 kb
Host smart-e243a43f-51a6-46cc-a8f4-edd405f6612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523469977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.523469977
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.366477899
Short name T397
Test name
Test status
Simulation time 18592961317 ps
CPU time 38.94 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:13:36 PM PDT 24
Peak memory 199976 kb
Host smart-d8dbd6ef-0492-4513-bb17-90922dad1cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366477899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.366477899
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3381085112
Short name T486
Test name
Test status
Simulation time 9959568592 ps
CPU time 13.34 seconds
Started Jul 07 05:12:51 PM PDT 24
Finished Jul 07 05:13:04 PM PDT 24
Peak memory 199028 kb
Host smart-dd212209-f73b-4342-a657-cc5a03749f3c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381085112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3381085112
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3207816368
Short name T961
Test name
Test status
Simulation time 83032721843 ps
CPU time 257.07 seconds
Started Jul 07 05:12:49 PM PDT 24
Finished Jul 07 05:17:07 PM PDT 24
Peak memory 199780 kb
Host smart-12512d47-6a35-4ab9-8763-83c5db693b12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207816368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3207816368
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2073340626
Short name T573
Test name
Test status
Simulation time 467147180 ps
CPU time 1.27 seconds
Started Jul 07 05:12:53 PM PDT 24
Finished Jul 07 05:12:55 PM PDT 24
Peak memory 197208 kb
Host smart-6c4c986a-7edc-4a10-91eb-0d03caf614ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073340626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2073340626
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2928197797
Short name T947
Test name
Test status
Simulation time 37685684481 ps
CPU time 19.74 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:13:20 PM PDT 24
Peak memory 199092 kb
Host smart-4ee5625a-ab76-4b7a-b64b-7de4f2abe2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928197797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2928197797
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3629191042
Short name T476
Test name
Test status
Simulation time 16735986412 ps
CPU time 81.38 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:14:19 PM PDT 24
Peak memory 199936 kb
Host smart-f58cdbd4-467e-40d2-8226-ac404b1791b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629191042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3629191042
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1691832723
Short name T367
Test name
Test status
Simulation time 6365491976 ps
CPU time 52.97 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:13:54 PM PDT 24
Peak memory 199196 kb
Host smart-eea445c2-8490-454e-9383-ed15c8de25b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1691832723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1691832723
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1078136692
Short name T1082
Test name
Test status
Simulation time 57510138755 ps
CPU time 104.42 seconds
Started Jul 07 05:12:51 PM PDT 24
Finished Jul 07 05:14:35 PM PDT 24
Peak memory 199992 kb
Host smart-82a104c5-a4b4-4306-aaba-d44dbefd0b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078136692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1078136692
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1583162783
Short name T489
Test name
Test status
Simulation time 3484103045 ps
CPU time 6.34 seconds
Started Jul 07 05:12:51 PM PDT 24
Finished Jul 07 05:12:57 PM PDT 24
Peak memory 196404 kb
Host smart-46c61990-e6d0-4a15-8fff-67c7be3907ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583162783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1583162783
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.964903600
Short name T627
Test name
Test status
Simulation time 158670713 ps
CPU time 0.77 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:12:59 PM PDT 24
Peak memory 196880 kb
Host smart-8ce66f8c-aae8-46d5-a065-0b77ba53e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964903600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.964903600
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3735416042
Short name T178
Test name
Test status
Simulation time 277578163855 ps
CPU time 842.67 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 216512 kb
Host smart-332683f0-1684-4bb3-9af3-356100661606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735416042 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3735416042
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3708634265
Short name T936
Test name
Test status
Simulation time 6398032445 ps
CPU time 14.85 seconds
Started Jul 07 05:12:53 PM PDT 24
Finished Jul 07 05:13:09 PM PDT 24
Peak memory 199740 kb
Host smart-d2101cad-daa5-42ee-8900-b0db97df03d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708634265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3708634265
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1403449510
Short name T1170
Test name
Test status
Simulation time 88718776383 ps
CPU time 44.8 seconds
Started Jul 07 05:12:53 PM PDT 24
Finished Jul 07 05:13:39 PM PDT 24
Peak memory 199900 kb
Host smart-e7e90d27-d683-46bb-9ca6-e26bc795fc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403449510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1403449510
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1306116327
Short name T472
Test name
Test status
Simulation time 17219139824 ps
CPU time 8.08 seconds
Started Jul 07 05:16:31 PM PDT 24
Finished Jul 07 05:16:39 PM PDT 24
Peak memory 199916 kb
Host smart-f7ff59ad-e483-4dc7-88a3-d99854a1e4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306116327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1306116327
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.236948837
Short name T1153
Test name
Test status
Simulation time 345453279950 ps
CPU time 339.53 seconds
Started Jul 07 05:16:31 PM PDT 24
Finished Jul 07 05:22:11 PM PDT 24
Peak memory 225580 kb
Host smart-f381981e-4cf7-4a01-a25d-705a9c1dc9bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236948837 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.236948837
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3818855783
Short name T1147
Test name
Test status
Simulation time 99624573480 ps
CPU time 70.83 seconds
Started Jul 07 05:16:31 PM PDT 24
Finished Jul 07 05:17:42 PM PDT 24
Peak memory 199904 kb
Host smart-ea49b24c-61ec-47de-933e-e9339a80a106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818855783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3818855783
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.601594785
Short name T1035
Test name
Test status
Simulation time 124456277992 ps
CPU time 64.83 seconds
Started Jul 07 05:16:31 PM PDT 24
Finished Jul 07 05:17:36 PM PDT 24
Peak memory 199808 kb
Host smart-39ca58fb-811f-4f89-8445-272a26a736ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601594785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.601594785
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1823274005
Short name T307
Test name
Test status
Simulation time 15956128344 ps
CPU time 49.62 seconds
Started Jul 07 05:16:32 PM PDT 24
Finished Jul 07 05:17:22 PM PDT 24
Peak memory 216464 kb
Host smart-c6bfafbc-446d-4741-aeff-8e114d22e7b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823274005 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1823274005
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3311663838
Short name T198
Test name
Test status
Simulation time 80636916885 ps
CPU time 197.3 seconds
Started Jul 07 05:16:32 PM PDT 24
Finished Jul 07 05:19:50 PM PDT 24
Peak memory 199868 kb
Host smart-8e5359a4-4962-45d5-afc4-0b008e3e7500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311663838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3311663838
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2388703350
Short name T804
Test name
Test status
Simulation time 136781930605 ps
CPU time 520.4 seconds
Started Jul 07 05:16:38 PM PDT 24
Finished Jul 07 05:25:19 PM PDT 24
Peak memory 214668 kb
Host smart-1ee8bb11-d8aa-4e99-8537-866eabbc9d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388703350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2388703350
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3941110408
Short name T112
Test name
Test status
Simulation time 33746884551 ps
CPU time 699.24 seconds
Started Jul 07 05:16:34 PM PDT 24
Finished Jul 07 05:28:14 PM PDT 24
Peak memory 208908 kb
Host smart-772d628d-48b1-4631-af2b-132317a8fdd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941110408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3941110408
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.940183992
Short name T808
Test name
Test status
Simulation time 31147328723 ps
CPU time 25.96 seconds
Started Jul 07 05:16:35 PM PDT 24
Finished Jul 07 05:17:02 PM PDT 24
Peak memory 199932 kb
Host smart-84937326-0ea4-4046-8293-1271c05a6079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940183992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.940183992
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1257256150
Short name T409
Test name
Test status
Simulation time 8319450489 ps
CPU time 13.07 seconds
Started Jul 07 05:16:41 PM PDT 24
Finished Jul 07 05:16:54 PM PDT 24
Peak memory 199664 kb
Host smart-b612f0b8-e321-413f-acd7-deae087e5ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257256150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1257256150
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2426287810
Short name T134
Test name
Test status
Simulation time 123805736134 ps
CPU time 357.98 seconds
Started Jul 07 05:16:36 PM PDT 24
Finished Jul 07 05:22:35 PM PDT 24
Peak memory 211488 kb
Host smart-cc130937-07cb-4a79-baed-65deaf97cbd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426287810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2426287810
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.118350255
Short name T1044
Test name
Test status
Simulation time 39729452057 ps
CPU time 31.17 seconds
Started Jul 07 05:16:41 PM PDT 24
Finished Jul 07 05:17:13 PM PDT 24
Peak memory 199884 kb
Host smart-9217444b-be60-4a0f-90f0-d1d525e77c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118350255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.118350255
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.248854738
Short name T963
Test name
Test status
Simulation time 26218641531 ps
CPU time 313.23 seconds
Started Jul 07 05:16:37 PM PDT 24
Finished Jul 07 05:21:50 PM PDT 24
Peak memory 216672 kb
Host smart-97005500-c060-43d6-ac9e-ff1ad0f9350e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248854738 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.248854738
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2122649019
Short name T475
Test name
Test status
Simulation time 58852470202 ps
CPU time 19.67 seconds
Started Jul 07 05:16:35 PM PDT 24
Finished Jul 07 05:16:55 PM PDT 24
Peak memory 199908 kb
Host smart-38908a2c-09e1-491a-809d-ace52cd239e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122649019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2122649019
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2550596557
Short name T180
Test name
Test status
Simulation time 101717962628 ps
CPU time 1536.52 seconds
Started Jul 07 05:16:35 PM PDT 24
Finished Jul 07 05:42:11 PM PDT 24
Peak memory 216704 kb
Host smart-cb41833d-4ef8-4cb7-b47c-c289db1f48ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550596557 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2550596557
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1240916224
Short name T1033
Test name
Test status
Simulation time 17831586062 ps
CPU time 27.71 seconds
Started Jul 07 05:16:41 PM PDT 24
Finished Jul 07 05:17:09 PM PDT 24
Peak memory 199880 kb
Host smart-252a789b-ab6c-4acc-a052-765a5008dd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240916224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1240916224
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2987729675
Short name T1129
Test name
Test status
Simulation time 33913694308 ps
CPU time 1305.9 seconds
Started Jul 07 05:16:41 PM PDT 24
Finished Jul 07 05:38:28 PM PDT 24
Peak memory 215344 kb
Host smart-02f2d588-1875-45f9-87f9-bd6e61e3efd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987729675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2987729675
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.63602316
Short name T503
Test name
Test status
Simulation time 16156882 ps
CPU time 0.57 seconds
Started Jul 07 05:12:58 PM PDT 24
Finished Jul 07 05:12:59 PM PDT 24
Peak memory 195292 kb
Host smart-35ed414f-4c40-438c-b481-670af9cbea01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63602316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.63602316
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.622498874
Short name T521
Test name
Test status
Simulation time 34916528187 ps
CPU time 17.14 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:13:13 PM PDT 24
Peak memory 199940 kb
Host smart-51fcc5fd-763d-4963-aa0a-f8d3f5eb7698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622498874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.622498874
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2628906097
Short name T442
Test name
Test status
Simulation time 8100796754 ps
CPU time 13.49 seconds
Started Jul 07 05:13:00 PM PDT 24
Finished Jul 07 05:13:14 PM PDT 24
Peak memory 199848 kb
Host smart-874f2713-6bbc-481a-acdb-241a523ac90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628906097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2628906097
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1161577446
Short name T1128
Test name
Test status
Simulation time 42885469848 ps
CPU time 61.09 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:13:59 PM PDT 24
Peak memory 199924 kb
Host smart-606dd1e6-5cd3-479c-8795-915899f930e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161577446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1161577446
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.488884499
Short name T412
Test name
Test status
Simulation time 1108872113 ps
CPU time 1.65 seconds
Started Jul 07 05:12:51 PM PDT 24
Finished Jul 07 05:12:53 PM PDT 24
Peak memory 199836 kb
Host smart-e92949cd-7aec-49a5-b210-1dade5ed0e99
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488884499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.488884499
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2423894839
Short name T1112
Test name
Test status
Simulation time 36806767131 ps
CPU time 140.52 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:15:21 PM PDT 24
Peak memory 199884 kb
Host smart-a7ada42b-8ac8-42a1-a4bb-8040cdc6f630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423894839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2423894839
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.4123544659
Short name T556
Test name
Test status
Simulation time 4443090378 ps
CPU time 5.79 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:13:02 PM PDT 24
Peak memory 199964 kb
Host smart-1d836466-0fc3-4fe4-94dc-ae805c677db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123544659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.4123544659
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1587491513
Short name T369
Test name
Test status
Simulation time 54705044763 ps
CPU time 79.12 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:14:15 PM PDT 24
Peak memory 208296 kb
Host smart-d8d5d296-2786-425c-a60c-fd60d7ad2e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587491513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1587491513
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2761992485
Short name T734
Test name
Test status
Simulation time 20723512941 ps
CPU time 1082.1 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:31:05 PM PDT 24
Peak memory 199852 kb
Host smart-e7615d40-564b-412a-b92b-e13191b9a981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761992485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2761992485
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.593959266
Short name T817
Test name
Test status
Simulation time 2120063419 ps
CPU time 10.93 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:13:14 PM PDT 24
Peak memory 197668 kb
Host smart-70effa9e-456b-4cac-8ab2-148c7cecd1ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593959266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.593959266
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2629308647
Short name T1091
Test name
Test status
Simulation time 44093491065 ps
CPU time 34.69 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:13:31 PM PDT 24
Peak memory 199932 kb
Host smart-197310d6-00cc-4fa9-b054-cf5cb069bada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629308647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2629308647
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1902265731
Short name T826
Test name
Test status
Simulation time 3866424567 ps
CPU time 2.19 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:13:02 PM PDT 24
Peak memory 196224 kb
Host smart-95049c3b-819a-4beb-b6b2-c958084609fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902265731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1902265731
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.371402453
Short name T1164
Test name
Test status
Simulation time 6011476145 ps
CPU time 16.18 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:13:12 PM PDT 24
Peak memory 199704 kb
Host smart-e4962d56-703a-43d1-915c-ee2a59e649ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371402453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.371402453
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2457644549
Short name T721
Test name
Test status
Simulation time 640039950795 ps
CPU time 245.56 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:17:02 PM PDT 24
Peak memory 199888 kb
Host smart-d1c79a7c-57c5-4afc-bfdb-5f107ee2c47c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457644549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2457644549
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.450430425
Short name T949
Test name
Test status
Simulation time 7214100972 ps
CPU time 10.77 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:13:14 PM PDT 24
Peak memory 199736 kb
Host smart-66634695-90b6-4063-aa32-60107a950cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450430425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.450430425
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.573664861
Short name T657
Test name
Test status
Simulation time 96427971332 ps
CPU time 312.8 seconds
Started Jul 07 05:12:55 PM PDT 24
Finished Jul 07 05:18:08 PM PDT 24
Peak memory 199864 kb
Host smart-ec112a1b-243e-4716-816b-bbed0213377f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573664861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.573664861
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3745161206
Short name T208
Test name
Test status
Simulation time 32106078092 ps
CPU time 15.55 seconds
Started Jul 07 05:16:40 PM PDT 24
Finished Jul 07 05:16:56 PM PDT 24
Peak memory 199908 kb
Host smart-f9d9b79b-8404-49ef-a42e-92c54ac18f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745161206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3745161206
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.954208871
Short name T117
Test name
Test status
Simulation time 41793234202 ps
CPU time 466.14 seconds
Started Jul 07 05:16:40 PM PDT 24
Finished Jul 07 05:24:27 PM PDT 24
Peak memory 216480 kb
Host smart-6d2c3b02-564e-4fb9-bd91-256de1e0e875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954208871 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.954208871
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1687271307
Short name T753
Test name
Test status
Simulation time 19475233532 ps
CPU time 28.83 seconds
Started Jul 07 05:16:39 PM PDT 24
Finished Jul 07 05:17:08 PM PDT 24
Peak memory 199532 kb
Host smart-51d58a7f-25bd-4386-b363-6b2c19e2839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687271307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1687271307
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.624737595
Short name T872
Test name
Test status
Simulation time 206273031783 ps
CPU time 628.95 seconds
Started Jul 07 05:16:38 PM PDT 24
Finished Jul 07 05:27:07 PM PDT 24
Peak memory 224836 kb
Host smart-8abb4568-6bbf-46f3-8015-8a86c19a4f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624737595 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.624737595
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2688771856
Short name T543
Test name
Test status
Simulation time 27477761535 ps
CPU time 26.62 seconds
Started Jul 07 05:16:40 PM PDT 24
Finished Jul 07 05:17:07 PM PDT 24
Peak memory 199992 kb
Host smart-b1555084-d4dd-45f0-ba4c-c882fd61e3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688771856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2688771856
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1323115190
Short name T135
Test name
Test status
Simulation time 169513751083 ps
CPU time 399.67 seconds
Started Jul 07 05:16:41 PM PDT 24
Finished Jul 07 05:23:21 PM PDT 24
Peak memory 216676 kb
Host smart-6d27cb71-7946-4da1-9f68-b841f23791de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323115190 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1323115190
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1962926244
Short name T665
Test name
Test status
Simulation time 40878506089 ps
CPU time 18.48 seconds
Started Jul 07 05:16:37 PM PDT 24
Finished Jul 07 05:16:56 PM PDT 24
Peak memory 199932 kb
Host smart-c8df775e-89ff-4cd6-a3f9-2bad1c152d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962926244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1962926244
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2461063137
Short name T120
Test name
Test status
Simulation time 26450778440 ps
CPU time 294.23 seconds
Started Jul 07 05:16:42 PM PDT 24
Finished Jul 07 05:21:37 PM PDT 24
Peak memory 216424 kb
Host smart-1beb7e0f-6eaa-4416-904b-954b546b8ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461063137 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2461063137
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4098852922
Short name T723
Test name
Test status
Simulation time 40285591217 ps
CPU time 114.21 seconds
Started Jul 07 05:16:39 PM PDT 24
Finished Jul 07 05:18:34 PM PDT 24
Peak memory 199848 kb
Host smart-b798bae3-095c-4cdc-956a-6ddf669bbed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098852922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4098852922
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.946272577
Short name T852
Test name
Test status
Simulation time 20544694605 ps
CPU time 241.54 seconds
Started Jul 07 05:16:44 PM PDT 24
Finished Jul 07 05:20:46 PM PDT 24
Peak memory 216544 kb
Host smart-0c410c8c-160f-4b75-a830-1ef5c2c64409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946272577 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.946272577
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3667497441
Short name T615
Test name
Test status
Simulation time 12837517130 ps
CPU time 23.65 seconds
Started Jul 07 05:16:44 PM PDT 24
Finished Jul 07 05:17:08 PM PDT 24
Peak memory 200000 kb
Host smart-e701c7f3-e56b-40cd-b5a2-b911813b02b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667497441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3667497441
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.4252692030
Short name T735
Test name
Test status
Simulation time 31577704389 ps
CPU time 338.55 seconds
Started Jul 07 05:16:45 PM PDT 24
Finished Jul 07 05:22:24 PM PDT 24
Peak memory 216444 kb
Host smart-b2506c70-ce22-4c34-8006-762d07a7f059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252692030 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.4252692030
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3787064702
Short name T631
Test name
Test status
Simulation time 48585740305 ps
CPU time 22.07 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:17:09 PM PDT 24
Peak memory 199740 kb
Host smart-1f2b6fc0-e80f-4a1b-837f-3314cf72cd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787064702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3787064702
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.127240211
Short name T656
Test name
Test status
Simulation time 72678806952 ps
CPU time 356.02 seconds
Started Jul 07 05:16:44 PM PDT 24
Finished Jul 07 05:22:40 PM PDT 24
Peak memory 216388 kb
Host smart-6abd877a-9c91-4041-8973-f861acf65da9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127240211 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.127240211
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.231660956
Short name T908
Test name
Test status
Simulation time 134244305021 ps
CPU time 54.42 seconds
Started Jul 07 05:16:44 PM PDT 24
Finished Jul 07 05:17:39 PM PDT 24
Peak memory 199976 kb
Host smart-45b74615-1f48-426f-831c-ef4d90435621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231660956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.231660956
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.53453570
Short name T468
Test name
Test status
Simulation time 210079737462 ps
CPU time 597.69 seconds
Started Jul 07 05:16:44 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 213928 kb
Host smart-73d55210-d187-4c6a-b2ef-5b69b98efe74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53453570 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.53453570
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.99169347
Short name T360
Test name
Test status
Simulation time 73870985597 ps
CPU time 154.26 seconds
Started Jul 07 05:16:48 PM PDT 24
Finished Jul 07 05:19:23 PM PDT 24
Peak memory 199964 kb
Host smart-8434a642-a427-4305-af80-f062450e9bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99169347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.99169347
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.476426628
Short name T1083
Test name
Test status
Simulation time 141370749649 ps
CPU time 536.36 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:25:44 PM PDT 24
Peak memory 216328 kb
Host smart-b4e301d5-a10b-4078-b67f-f1dd51c3ffc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476426628 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.476426628
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.997743463
Short name T710
Test name
Test status
Simulation time 256345689546 ps
CPU time 41.22 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:17:28 PM PDT 24
Peak memory 199940 kb
Host smart-e7b53d72-f316-4b9a-8a4e-4df3023ec136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997743463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.997743463
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4221113575
Short name T675
Test name
Test status
Simulation time 40209763 ps
CPU time 0.56 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:12:58 PM PDT 24
Peak memory 195220 kb
Host smart-3e6ba87c-749e-41af-9031-466aafa09012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221113575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4221113575
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1607335625
Short name T901
Test name
Test status
Simulation time 52946246072 ps
CPU time 33.35 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:13:31 PM PDT 24
Peak memory 199908 kb
Host smart-acce75bf-4192-4fc4-b589-2842774caa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607335625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1607335625
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.4049335362
Short name T756
Test name
Test status
Simulation time 23196492856 ps
CPU time 19.11 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:13:22 PM PDT 24
Peak memory 199808 kb
Host smart-af2317c8-b531-4cec-92cc-165a8f0bc382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049335362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.4049335362
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.639404442
Short name T523
Test name
Test status
Simulation time 8793268156 ps
CPU time 13.51 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:13:16 PM PDT 24
Peak memory 196824 kb
Host smart-4ae58da9-9b05-4920-a8ef-81ac2a0970ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639404442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.639404442
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.935435602
Short name T993
Test name
Test status
Simulation time 77197835089 ps
CPU time 294.91 seconds
Started Jul 07 05:12:59 PM PDT 24
Finished Jul 07 05:17:55 PM PDT 24
Peak memory 199964 kb
Host smart-59217ace-142b-49c8-a53e-33d9dff4e35f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935435602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.935435602
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2533439253
Short name T124
Test name
Test status
Simulation time 6804477791 ps
CPU time 11.94 seconds
Started Jul 07 05:12:54 PM PDT 24
Finished Jul 07 05:13:06 PM PDT 24
Peak memory 199368 kb
Host smart-311f31dc-1def-401e-90fd-dab5984be790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533439253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2533439253
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3084167057
Short name T514
Test name
Test status
Simulation time 64502553103 ps
CPU time 140.24 seconds
Started Jul 07 05:12:56 PM PDT 24
Finished Jul 07 05:15:16 PM PDT 24
Peak memory 200080 kb
Host smart-5ed9565e-c8de-4d6c-9f80-9f03cad3355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084167057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3084167057
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1933977840
Short name T277
Test name
Test status
Simulation time 17474112907 ps
CPU time 805.98 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:26:24 PM PDT 24
Peak memory 199956 kb
Host smart-c65f7056-7569-422b-ad1c-4b72bdd3d920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933977840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1933977840
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4243247823
Short name T1132
Test name
Test status
Simulation time 1582915944 ps
CPU time 4.36 seconds
Started Jul 07 05:12:57 PM PDT 24
Finished Jul 07 05:13:02 PM PDT 24
Peak memory 199108 kb
Host smart-7fff0e21-2d0b-4766-bc3f-b377a67aac26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4243247823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4243247823
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.44364223
Short name T582
Test name
Test status
Simulation time 2071118066 ps
CPU time 1.44 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:13:04 PM PDT 24
Peak memory 195336 kb
Host smart-d8c4dbca-ec8d-41c7-ba34-646ada875fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44364223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.44364223
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1536611572
Short name T950
Test name
Test status
Simulation time 5902023552 ps
CPU time 9.5 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:13:13 PM PDT 24
Peak memory 199516 kb
Host smart-40d1c37e-df17-4700-9cd5-d3d6a710171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536611572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1536611572
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.433001524
Short name T1013
Test name
Test status
Simulation time 144910270372 ps
CPU time 173.62 seconds
Started Jul 07 05:13:03 PM PDT 24
Finished Jul 07 05:15:57 PM PDT 24
Peak memory 199532 kb
Host smart-f8fd85ba-0bc5-4642-99e3-c31ebf998cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433001524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.433001524
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1639622083
Short name T62
Test name
Test status
Simulation time 21759430801 ps
CPU time 208.68 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:16:31 PM PDT 24
Peak memory 215532 kb
Host smart-0e6cfc85-7671-42fa-b95d-8086745449bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639622083 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1639622083
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3672279225
Short name T310
Test name
Test status
Simulation time 1376803387 ps
CPU time 2.1 seconds
Started Jul 07 05:13:01 PM PDT 24
Finished Jul 07 05:13:04 PM PDT 24
Peak memory 199592 kb
Host smart-6caed7a4-3929-4cc8-9c40-0da768b7332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672279225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3672279225
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2291221184
Short name T749
Test name
Test status
Simulation time 42922867582 ps
CPU time 66.64 seconds
Started Jul 07 05:13:02 PM PDT 24
Finished Jul 07 05:14:10 PM PDT 24
Peak memory 199904 kb
Host smart-fed9a218-6192-4602-8186-f470f8687a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291221184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2291221184
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2706525075
Short name T743
Test name
Test status
Simulation time 68497073905 ps
CPU time 102.01 seconds
Started Jul 07 05:16:43 PM PDT 24
Finished Jul 07 05:18:25 PM PDT 24
Peak memory 199804 kb
Host smart-8acea6cd-7b13-455e-a6a2-1bdb59450c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706525075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2706525075
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2343923354
Short name T509
Test name
Test status
Simulation time 30975642843 ps
CPU time 410.08 seconds
Started Jul 07 05:16:44 PM PDT 24
Finished Jul 07 05:23:35 PM PDT 24
Peak memory 215980 kb
Host smart-2342eb35-1954-4de3-8d96-caf655562aa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343923354 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2343923354
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3165925323
Short name T410
Test name
Test status
Simulation time 49535298727 ps
CPU time 18.95 seconds
Started Jul 07 05:16:43 PM PDT 24
Finished Jul 07 05:17:02 PM PDT 24
Peak memory 199884 kb
Host smart-cfa69821-fc49-4660-aec4-f030781eec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165925323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3165925323
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2143501163
Short name T976
Test name
Test status
Simulation time 441389040903 ps
CPU time 836.69 seconds
Started Jul 07 05:16:44 PM PDT 24
Finished Jul 07 05:30:40 PM PDT 24
Peak memory 225148 kb
Host smart-d483b100-b677-4aa9-a72b-cac1f00d1161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143501163 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2143501163
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3299550460
Short name T60
Test name
Test status
Simulation time 15505072702 ps
CPU time 19.92 seconds
Started Jul 07 05:16:44 PM PDT 24
Finished Jul 07 05:17:05 PM PDT 24
Peak memory 199644 kb
Host smart-682eb72b-70aa-4e52-ab01-af1d98f61dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299550460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3299550460
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1724648216
Short name T150
Test name
Test status
Simulation time 62819964573 ps
CPU time 353.63 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:22:41 PM PDT 24
Peak memory 225964 kb
Host smart-e7e92902-8c50-4590-929d-932309a6de86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724648216 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1724648216
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.887593888
Short name T200
Test name
Test status
Simulation time 13950338061 ps
CPU time 21.18 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:17:08 PM PDT 24
Peak memory 199852 kb
Host smart-8e2eda49-c182-413e-97b5-91cd3d67744a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887593888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.887593888
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.491421676
Short name T1067
Test name
Test status
Simulation time 121712912159 ps
CPU time 505.13 seconds
Started Jul 07 05:16:48 PM PDT 24
Finished Jul 07 05:25:14 PM PDT 24
Peak memory 216360 kb
Host smart-3e5ac46c-7e61-44c1-89d8-45ef4febdb75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491421676 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.491421676
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1314485253
Short name T1072
Test name
Test status
Simulation time 40553017425 ps
CPU time 22.58 seconds
Started Jul 07 05:16:50 PM PDT 24
Finished Jul 07 05:17:13 PM PDT 24
Peak memory 199956 kb
Host smart-9e884f1b-7e6b-4faf-a9fa-69be10ea7bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314485253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1314485253
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1936158373
Short name T385
Test name
Test status
Simulation time 89137468492 ps
CPU time 628.46 seconds
Started Jul 07 05:16:49 PM PDT 24
Finished Jul 07 05:27:18 PM PDT 24
Peak memory 224820 kb
Host smart-6b1c68d3-d41f-42cc-a60e-78656b3d87c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936158373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1936158373
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1459964665
Short name T210
Test name
Test status
Simulation time 127315594999 ps
CPU time 188.43 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:19:56 PM PDT 24
Peak memory 199980 kb
Host smart-e3a3112f-7084-46e6-ba68-05286726789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459964665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1459964665
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1505773549
Short name T36
Test name
Test status
Simulation time 101771675631 ps
CPU time 315.38 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:22:03 PM PDT 24
Peak memory 216504 kb
Host smart-58f470a8-ab2a-4ccd-b68a-125abf725f4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505773549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1505773549
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3438949198
Short name T645
Test name
Test status
Simulation time 25394509264 ps
CPU time 68.04 seconds
Started Jul 07 05:16:48 PM PDT 24
Finished Jul 07 05:17:57 PM PDT 24
Peak memory 199824 kb
Host smart-31f1666f-a5dd-4fdf-8f01-f8937b6e8dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438949198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3438949198
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3327467535
Short name T681
Test name
Test status
Simulation time 36234735096 ps
CPU time 326.23 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:22:14 PM PDT 24
Peak memory 216788 kb
Host smart-5662c648-cfd4-40f2-ac76-4f592c2b8ba0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327467535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3327467535
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2956498019
Short name T617
Test name
Test status
Simulation time 154750107125 ps
CPU time 27.25 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:17:15 PM PDT 24
Peak memory 199892 kb
Host smart-43f92f13-dec9-4e24-a84e-86e2abbda06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956498019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2956498019
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2059425418
Short name T67
Test name
Test status
Simulation time 175315165003 ps
CPU time 588.88 seconds
Started Jul 07 05:16:47 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 216576 kb
Host smart-873ce7f6-0f24-4cd9-a2a3-b6e7e5e75376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059425418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2059425418
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2118972897
Short name T140
Test name
Test status
Simulation time 10030464176 ps
CPU time 14.33 seconds
Started Jul 07 05:16:53 PM PDT 24
Finished Jul 07 05:17:07 PM PDT 24
Peak memory 198816 kb
Host smart-cac5c9ce-1035-4b91-8018-200fe5a8515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118972897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2118972897
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2454307113
Short name T149
Test name
Test status
Simulation time 197694623838 ps
CPU time 781.37 seconds
Started Jul 07 05:16:55 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 224760 kb
Host smart-de86b790-0c26-4ded-92d4-59046ef5d69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454307113 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2454307113
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1106252597
Short name T216
Test name
Test status
Simulation time 162702044838 ps
CPU time 68.29 seconds
Started Jul 07 05:16:50 PM PDT 24
Finished Jul 07 05:17:59 PM PDT 24
Peak memory 199932 kb
Host smart-8bd4567e-6d20-4631-983e-6619bceac3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106252597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1106252597
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3087197498
Short name T712
Test name
Test status
Simulation time 234453159094 ps
CPU time 1047.39 seconds
Started Jul 07 05:16:52 PM PDT 24
Finished Jul 07 05:34:19 PM PDT 24
Peak memory 216696 kb
Host smart-58b37bd4-58cd-4d0c-820e-d0e84c9cb3dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087197498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3087197498
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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