Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	105682	1			T1	2		T3	2		T4	18
all_values[1]	105682	1			T1	2		T3	2		T4	18
all_values[2]	105682	1			T1	2		T3	2		T4	18
all_values[3]	105682	1			T1	2		T3	2		T4	18
all_values[4]	105682	1			T1	2		T3	2		T4	18
all_values[5]	105682	1			T1	2		T3	2		T4	18
all_values[6]	105682	1			T1	2		T3	2		T4	18
all_values[7]	105682	1			T1	2		T3	2		T4	18
all_values[8]	105682	1			T1	2		T3	2		T4	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

480932

1

T1

18

T3

18

T4

80

auto[1]

470206

1

T4

82

T5

307

T6

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

864799

1

T1

13

T3

13

T4

152

auto[1]

86339

1

T1

5

T3

5

T4

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31202	1			T4	6		T8	9		T10	10
all_values[0]	auto[0]	auto[1]	21243	1			T1	2		T3	2		T4	2
all_values[0]	auto[1]	auto[0]	32306	1			T4	8		T5	11		T8	12
all_values[0]	auto[1]	auto[1]	20931	1			T4	2		T5	12		T6	1
all_values[1]	auto[0]	auto[0]	52722	1			T1	2		T3	2		T4	8
all_values[1]	auto[0]	auto[1]	1848	1			T40	7		T41	1		T120	1
all_values[1]	auto[1]	auto[0]	49256	1			T4	10		T5	34		T6	1
all_values[1]	auto[1]	auto[1]	1856	1			T5	2		T8	7		T15	1
all_values[2]	auto[0]	auto[0]	48744	1			T1	1		T3	1		T4	13
all_values[2]	auto[0]	auto[1]	2619	1			T1	1		T3	1		T4	1
all_values[2]	auto[1]	auto[0]	51789	1			T4	3		T5	13		T6	1
all_values[2]	auto[1]	auto[1]	2530	1			T4	1		T5	1		T8	13
all_values[3]	auto[0]	auto[0]	54220	1			T1	2		T3	2		T4	2
all_values[3]	auto[0]	auto[1]	310	1			T12	1		T14	1		T88	1
all_values[3]	auto[1]	auto[0]	50829	1			T4	16		T5	48		T6	1
all_values[3]	auto[1]	auto[1]	323	1			T15	2		T13	3		T18	2
all_values[4]	auto[0]	auto[0]	52799	1			T1	2		T3	2		T4	6
all_values[4]	auto[0]	auto[1]	544	1			T15	4		T17	5		T18	2
all_values[4]	auto[1]	auto[0]	51824	1			T4	12		T5	25		T6	1
all_values[4]	auto[1]	auto[1]	515	1			T16	1		T17	12		T18	2
all_values[5]	auto[0]	auto[0]	52193	1			T1	2		T3	2		T4	8
all_values[5]	auto[0]	auto[1]	194	1			T18	1		T26	2		T33	2
all_values[5]	auto[1]	auto[0]	53102	1			T4	10		T5	64		T8	56
all_values[5]	auto[1]	auto[1]	193	1			T15	2		T18	4		T26	2
all_values[6]	auto[0]	auto[0]	53519	1			T1	2		T3	2		T4	10
all_values[6]	auto[0]	auto[1]	171	1			T26	2		T33	3		T125	1
all_values[6]	auto[1]	auto[0]	51792	1			T4	8		T5	16		T8	49
all_values[6]	auto[1]	auto[1]	200	1			T15	2		T18	4		T26	5
all_values[7]	auto[0]	auto[0]	56522	1			T1	2		T3	2		T4	6
all_values[7]	auto[0]	auto[1]	369	1			T15	2		T13	1		T18	1
all_values[7]	auto[1]	auto[0]	48374	1			T4	12		T5	49		T6	1
all_values[7]	auto[1]	auto[1]	417	1			T19	1		T17	18		T18	3
all_values[8]	auto[0]	auto[0]	35528	1			T4	14		T5	11		T8	12
all_values[8]	auto[0]	auto[1]	16185	1			T1	2		T3	2		T4	4
all_values[8]	auto[1]	auto[0]	38078	1			T5	26		T8	11		T10	10
all_values[8]	auto[1]	auto[1]	15891	1			T5	6		T6	1		T8	44