Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2319	1			T1	1		T3	1		T5	2
auto[BaudRate115200]	2017	1			T4	1		T5	5		T6	9
auto[BaudRate230400]	1960	1			T4	3		T5	3		T6	9
auto[BaudRate128Kbps]	1911	1			T3	1		T4	1		T5	4
auto[BaudRate256Kbps]	2134	1			T4	1		T5	2		T6	6
auto[BaudRate1Mbps]	1824	1			T4	1		T5	2		T6	9
auto[BaudRate1p5Mbps]	1174	1			T1	1		T4	1		T5	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1903	1			T3	2		T6	57		T8	33
freqs[25]	939	1			T45	10		T256	8		T269	2
freqs[48]	397	1			T40	5		T32	21		T134	7
freqs[50]	597	1			T46	19		T47	5		T260	8
freqs[100]	1118	1			T5	19		T11	2		T41	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	403	1			T3	1		T6	12		T8	6
auto[BaudRate9600]	freqs[25]	162	1			T45	1		T256	2		T255	1
auto[BaudRate9600]	freqs[48]	33	1			T40	1		T32	1		T125	2
auto[BaudRate9600]	freqs[50]	80	1			T46	3		T47	5		T187	2
auto[BaudRate9600]	freqs[100]	165	1			T5	2		T25	3		T23	6
auto[BaudRate115200]	freqs[24]	287	1			T6	9		T8	8		T15	4
auto[BaudRate115200]	freqs[25]	116	1			T45	1		T256	2		T255	1
auto[BaudRate115200]	freqs[48]	42	1			T40	2		T134	1		T125	3
auto[BaudRate115200]	freqs[50]	98	1			T46	2		T260	1		T187	2
auto[BaudRate115200]	freqs[100]	161	1			T5	5		T11	2		T25	6
auto[BaudRate230400]	freqs[24]	283	1			T6	9		T8	4		T15	6
auto[BaudRate230400]	freqs[25]	128	1			T45	2		T256	1		T255	1
auto[BaudRate230400]	freqs[48]	51	1			T32	1		T134	2		T125	2
auto[BaudRate230400]	freqs[50]	93	1			T46	4		T187	2		T278	1
auto[BaudRate230400]	freqs[100]	138	1			T5	3		T25	3		T270	1
auto[BaudRate128Kbps]	freqs[24]	248	1			T3	1		T6	9		T8	4
auto[BaudRate128Kbps]	freqs[25]	124	1			T45	1		T256	1		T269	2
auto[BaudRate128Kbps]	freqs[48]	62	1			T40	2		T32	8		T134	1
auto[BaudRate128Kbps]	freqs[50]	80	1			T46	6		T309	1		T157	1
auto[BaudRate128Kbps]	freqs[100]	151	1			T5	4		T41	2		T25	9
auto[BaudRate256Kbps]	freqs[24]	267	1			T6	6		T8	4		T15	15
auto[BaudRate256Kbps]	freqs[25]	166	1			T45	3		T256	2		T255	1
auto[BaudRate256Kbps]	freqs[48]	72	1			T32	7		T134	2		T125	4
auto[BaudRate256Kbps]	freqs[50]	67	1			T46	2		T260	3		T187	1
auto[BaudRate256Kbps]	freqs[100]	178	1			T5	2		T41	1		T25	15
auto[BaudRate1Mbps]	freqs[24]	291	1			T6	9		T8	4		T15	7
auto[BaudRate1Mbps]	freqs[25]	168	1			T45	2		T255	1		T147	2
auto[BaudRate1Mbps]	freqs[48]	71	1			T32	1		T134	1		T125	4
auto[BaudRate1Mbps]	freqs[50]	92	1			T46	2		T260	2		T278	2
auto[BaudRate1Mbps]	freqs[100]	170	1			T5	2		T41	1		T130	2
auto[BaudRate1p5Mbps]	freqs[25]	75	1			T147	2		T282	3		T310	5
auto[BaudRate1p5Mbps]	freqs[48]	66	1			T32	3		T125	2		T141	1
auto[BaudRate1p5Mbps]	freqs[50]	87	1			T260	2		T187	1		T278	2
auto[BaudRate1p5Mbps]	freqs[100]	155	1			T5	1		T41	1		T25	9

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded