Group : uart_env_pkg::uart_env_cov::rx_break_err_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_env_pkg::uart_env_cov::rx_break_err_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_break_err_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_break_level 4 0 4 100.00 100 1 1 0


Summary for Variable cp_break_level

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_break_level

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 381 1 T15 2 T18 5 T22 1
all_levels[1] 33 1 T33 1 T311 2 T312 1
all_levels[2] 61 1 T17 4 T21 1 T22 3
all_levels[3] 40 1 T21 1 T36 2 T151 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%