Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	105682	1			T1	2		T3	2		T4	18
all_pins[1]	105682	1			T1	2		T3	2		T4	18
all_pins[2]	105682	1			T1	2		T3	2		T4	18
all_pins[3]	105682	1			T1	2		T3	2		T4	18
all_pins[4]	105682	1			T1	2		T3	2		T4	18
all_pins[5]	105682	1			T1	2		T3	2		T4	18
all_pins[6]	105682	1			T1	2		T3	2		T4	18
all_pins[7]	105682	1			T1	2		T3	2		T4	18
all_pins[8]	105682	1			T1	2		T3	2		T4	18

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	907256	1			T1	18		T3	18		T4	157
values[0x1]	43882	1			T4	5		T5	22		T6	2
transitions[0x0=>0x1]	34685	1			T4	5		T5	21		T6	1
transitions[0x1=>0x0]	34503	1			T4	4		T5	21		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	84667	1			T1	2		T3	2		T4	16
all_pins[0]	values[0x1]	21015	1			T4	2		T5	12		T6	1
all_pins[0]	transitions[0x0=>0x1]	20382	1			T4	2		T5	12		T6	1
all_pins[0]	transitions[0x1=>0x0]	1217	1			T5	2		T8	7		T18	28
all_pins[1]	values[0x0]	103832	1			T1	2		T3	2		T4	18
all_pins[1]	values[0x1]	1850	1			T5	2		T8	7		T15	1
all_pins[1]	transitions[0x0=>0x1]	1694	1			T5	2		T8	1		T15	1
all_pins[1]	transitions[0x1=>0x0]	2452	1			T4	1		T5	1		T8	7
all_pins[2]	values[0x0]	103074	1			T1	2		T3	2		T4	17
all_pins[2]	values[0x1]	2608	1			T4	1		T5	1		T8	13
all_pins[2]	transitions[0x0=>0x1]	2534	1			T4	1		T5	1		T8	13
all_pins[2]	transitions[0x1=>0x0]	249	1			T15	2		T13	3		T18	2
all_pins[3]	values[0x0]	105359	1			T1	2		T3	2		T4	18
all_pins[3]	values[0x1]	323	1			T15	2		T13	3		T18	2
all_pins[3]	transitions[0x0=>0x1]	271	1			T15	2		T13	3		T118	1
all_pins[3]	transitions[0x1=>0x0]	463	1			T16	1		T17	12		T21	4
all_pins[4]	values[0x0]	105167	1			T1	2		T3	2		T4	18
all_pins[4]	values[0x1]	515	1			T16	1		T17	12		T18	2
all_pins[4]	transitions[0x0=>0x1]	427	1			T16	1		T17	12		T21	3
all_pins[4]	transitions[0x1=>0x0]	177	1			T15	2		T18	2		T22	4
all_pins[5]	values[0x0]	105417	1			T1	2		T3	2		T4	18
all_pins[5]	values[0x1]	265	1			T15	2		T18	4		T21	1
all_pins[5]	transitions[0x0=>0x1]	202	1			T18	1		T21	1		T22	4
all_pins[5]	transitions[0x1=>0x0]	871	1			T4	2		T5	1		T8	3
all_pins[6]	values[0x0]	104748	1			T1	2		T3	2		T4	16
all_pins[6]	values[0x1]	934	1			T4	2		T5	1		T8	3
all_pins[6]	transitions[0x0=>0x1]	871	1			T4	2		T5	1		T8	3
all_pins[6]	transitions[0x1=>0x0]	354	1			T19	1		T17	18		T49	1
all_pins[7]	values[0x0]	105265	1			T1	2		T3	2		T4	18
all_pins[7]	values[0x1]	417	1			T19	1		T17	18		T18	3
all_pins[7]	transitions[0x0=>0x1]	245	1			T19	1		T18	1		T49	1
all_pins[7]	transitions[0x1=>0x0]	15783	1			T5	6		T6	1		T8	44
all_pins[8]	values[0x0]	89727	1			T1	2		T3	2		T4	18
all_pins[8]	values[0x1]	15955	1			T5	6		T6	1		T8	44
all_pins[8]	transitions[0x0=>0x1]	8059	1			T5	5		T8	22		T24	4
all_pins[8]	transitions[0x1=>0x0]	12937	1			T4	1		T5	11		T8	25