Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6718731	1			T4	20		T5	173		T8	131
all_levels[1]	1953593	1			T4	7		T5	48		T8	4
all_levels[2]	377156	1			T5	25		T8	3		T15	264
all_levels[3]	450532	1			T5	27		T8	4		T10	5
all_levels[4]	252139	1			T5	37		T8	1		T15	777
all_levels[5]	276019	1			T5	41		T8	2		T24	4
all_levels[6]	255183	1			T5	34		T8	5		T24	3
all_levels[7]	317952	1			T5	34		T15	266		T39	47
all_levels[8]	243677	1			T5	15		T8	6		T15	264
all_levels[9]	240298	1			T5	27		T8	6		T24	18
all_levels[10]	250084	1			T5	3		T8	5		T24	1
all_levels[11]	222487	1			T4	3		T5	243		T8	1
all_levels[12]	317964	1			T4	3		T5	1		T8	1
all_levels[13]	243486	1			T5	1		T8	3		T24	1
all_levels[14]	208023	1			T5	23		T8	4		T15	145
all_levels[15]	311586	1			T5	2		T8	1		T15	206
all_levels[16]	560408	1			T5	6		T8	3		T24	10
all_levels[17]	331785	1			T5	1		T8	1		T24	1
all_levels[18]	336469	1			T5	5		T8	3		T24	6
all_levels[19]	216024	1			T5	8		T24	5		T15	135
all_levels[20]	221818	1			T5	1		T8	3		T24	1
all_levels[21]	220886	1			T5	2		T24	4		T15	263
all_levels[22]	225254	1			T24	4		T15	263		T39	50
all_levels[23]	168865	1			T8	7		T24	7		T15	267
all_levels[24]	192930	1			T5	10		T8	2		T24	2
all_levels[25]	192954	1			T5	1		T24	4		T15	263
all_levels[26]	249544	1			T5	9		T8	1		T24	9
all_levels[27]	199174	1			T5	3		T8	2		T24	5
all_levels[28]	289559	1			T24	2		T15	206		T39	51
all_levels[29]	179333	1			T8	2		T10	3		T24	7
all_levels[30]	205056	1			T8	2		T24	7		T15	116
all_levels[31]	775825	1			T5	2		T8	7		T24	2
all_levels[32]	12143383	1			T4	18		T5	29		T8	18

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29343446

1

T4

44

T5

811

T8

213

auto[1]

4731

1

T4

7

T8

15

T10

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6716066	1			T4	17		T5	173		T8	126
all_levels[0]	auto[1]	2665	1			T4	3		T8	5		T10	2
all_levels[1]	auto[0]	1953270	1			T4	6		T5	48		T8	4
all_levels[1]	auto[1]	323	1			T4	1		T41	1		T44	1
all_levels[2]	auto[0]	377103	1			T5	25		T8	3		T15	264
all_levels[2]	auto[1]	53	1			T121	3		T255	2		T38	2
all_levels[3]	auto[0]	450363	1			T5	27		T8	4		T10	2
all_levels[3]	auto[1]	169	1			T10	3		T15	14		T17	11
all_levels[4]	auto[0]	252119	1			T5	37		T8	1		T15	777
all_levels[4]	auto[1]	20	1			T161	1		T216	2		T313	1
all_levels[5]	auto[0]	275996	1			T5	41		T8	2		T24	4
all_levels[5]	auto[1]	23	1			T190	2		T314	1		T315	1
all_levels[6]	auto[0]	255147	1			T5	34		T8	4		T24	3
all_levels[6]	auto[1]	36	1			T8	1		T44	1		T136	1
all_levels[7]	auto[0]	317794	1			T5	34		T15	266		T39	47
all_levels[7]	auto[1]	158	1			T141	2		T269	5		T255	1
all_levels[8]	auto[0]	243643	1			T5	15		T8	4		T15	264
all_levels[8]	auto[1]	34	1			T8	2		T135	1		T140	1
all_levels[9]	auto[0]	240267	1			T5	27		T8	6		T24	18
all_levels[9]	auto[1]	31	1			T41	1		T130	3		T140	1
all_levels[10]	auto[0]	250047	1			T5	3		T8	5		T24	1
all_levels[10]	auto[1]	37	1			T46	1		T125	1		T34	1
all_levels[11]	auto[0]	222464	1			T4	2		T5	243		T8	1
all_levels[11]	auto[1]	23	1			T4	1		T303	1		T144	1
all_levels[12]	auto[0]	317938	1			T4	2		T5	1		T8	1
all_levels[12]	auto[1]	26	1			T4	1		T249	1		T33	1
all_levels[13]	auto[0]	243465	1			T5	1		T8	3		T24	1
all_levels[13]	auto[1]	21	1			T139	1		T140	1		T294	3
all_levels[14]	auto[0]	207994	1			T5	23		T8	4		T15	145
all_levels[14]	auto[1]	29	1			T136	2		T279	1		T53	1
all_levels[15]	auto[0]	311444	1			T5	2		T8	1		T15	206
all_levels[15]	auto[1]	142	1			T21	9		T34	1		T303	1
all_levels[16]	auto[0]	560386	1			T5	6		T8	3		T24	10
all_levels[16]	auto[1]	22	1			T42	1		T18	3		T143	1
all_levels[17]	auto[0]	331768	1			T5	1		T8	1		T24	1
all_levels[17]	auto[1]	17	1			T117	1		T105	1		T223	1
all_levels[18]	auto[0]	336429	1			T5	5		T8	3		T24	6
all_levels[18]	auto[1]	40	1			T44	4		T130	3		T18	1
all_levels[19]	auto[0]	216009	1			T5	8		T24	5		T15	135
all_levels[19]	auto[1]	15	1			T137	1		T316	1		T196	1
all_levels[20]	auto[0]	221793	1			T5	1		T8	3		T24	1
all_levels[20]	auto[1]	25	1			T131	1		T139	3		T317	1
all_levels[21]	auto[0]	220859	1			T5	2		T24	4		T15	263
all_levels[21]	auto[1]	27	1			T160	2		T49	1		T187	1
all_levels[22]	auto[0]	225221	1			T24	4		T15	263		T39	50
all_levels[22]	auto[1]	33	1			T116	2		T154	1		T318	19
all_levels[23]	auto[0]	168836	1			T8	7		T24	7		T15	267
all_levels[23]	auto[1]	29	1			T26	1		T251	1		T319	2
all_levels[24]	auto[0]	192922	1			T5	10		T8	2		T24	2
all_levels[24]	auto[1]	8	1			T58	2		T320	1		T321	4
all_levels[25]	auto[0]	192934	1			T5	1		T24	4		T15	263
all_levels[25]	auto[1]	20	1			T125	1		T127	1		T205	1
all_levels[26]	auto[0]	249524	1			T5	9		T8	1		T24	9
all_levels[26]	auto[1]	20	1			T58	1		T156	3		T322	1
all_levels[27]	auto[0]	199162	1			T5	3		T8	2		T24	5
all_levels[27]	auto[1]	12	1			T135	1		T183	3		T145	1
all_levels[28]	auto[0]	289534	1			T24	2		T15	206		T39	51
all_levels[28]	auto[1]	25	1			T315	2		T219	1		T323	1
all_levels[29]	auto[0]	179318	1			T8	2		T10	2		T24	7
all_levels[29]	auto[1]	15	1			T10	1		T117	1		T155	1
all_levels[30]	auto[0]	205035	1			T8	2		T24	7		T15	116
all_levels[30]	auto[1]	21	1			T187	1		T298	2		T324	1
all_levels[31]	auto[0]	775804	1			T5	2		T8	5		T24	2
all_levels[31]	auto[1]	21	1			T8	2		T284	1		T303	2
all_levels[32]	auto[0]	12142792	1			T4	17		T5	29		T8	13
all_levels[32]	auto[1]	591	1			T4	1		T8	5		T24	1