Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
71.43 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 2 5 71.43


Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 7 2 5 71.43 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 2 5 71.43


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[5] 0 1 1
all_levels[6] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 7831 1 T1 2 T3 2 T5 3
all_levels[1] 7492 1 T5 10 T6 1 T8 2
all_levels[2] 7873 1 T8 20 T10 4 T24 8
all_levels[3] 8389 1 T4 2 T8 4 T15 12
all_levels[4] 10757 1 T4 2 T5 41 T8 21

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%