Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	826	1			T15	4		T18	7		T26	7
all_values[1]	826	1			T15	4		T18	7		T26	7
all_values[2]	826	1			T15	4		T18	7		T26	7
all_values[3]	826	1			T15	4		T18	7		T26	7
all_values[4]	826	1			T15	4		T18	7		T26	7
all_values[5]	826	1			T15	4		T18	7		T26	7
all_values[6]	826	1			T15	4		T18	7		T26	7
all_values[7]	826	1			T15	4		T18	7		T26	7
all_values[8]	826	1			T15	4		T18	7		T26	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3972

1

T15

20

T18

30

T26

32

auto[1]

3462

1

T15

16

T18

33

T26

31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2388

1

T15

9

T18

16

T26

25

auto[1]

5046

1

T15

27

T18

47

T26

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4294

1

T15

18

T18

32

T26

37

auto[1]

3140

1

T15

18

T18

31

T26

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	263	1			T15	1		T18	2		T26	2
all_values[0]	auto[0]	auto[1]	auto[1]	211	1			T15	2		T26	2		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	206	1			T15	1		T18	3		T33	1
all_values[0]	auto[1]	auto[1]	auto[1]	146	1			T18	2		T26	3		T33	1
all_values[1]	auto[0]	auto[0]	auto[0]	255	1			T15	1		T18	3		T26	2
all_values[1]	auto[0]	auto[1]	auto[0]	222	1			T15	2		T18	1		T26	2
all_values[1]	auto[1]	auto[0]	auto[1]	198	1			T15	1		T18	1		T26	2
all_values[1]	auto[1]	auto[1]	auto[1]	151	1			T18	2		T26	1		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T15	2		T26	3		T35	2
all_values[2]	auto[0]	auto[0]	auto[1]	67	1			T18	1		T125	1		T34	1
all_values[2]	auto[0]	auto[1]	auto[0]	135	1			T26	3		T33	2		T125	1
all_values[2]	auto[0]	auto[1]	auto[1]	89	1			T18	2		T33	1		T35	1
all_values[2]	auto[1]	auto[0]	auto[1]	189	1			T15	1		T18	3		T33	2
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T15	1		T18	1		T26	1
all_values[3]	auto[0]	auto[0]	auto[0]	181	1			T18	1		T26	4		T125	1
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T33	1		T125	2		T34	1
all_values[3]	auto[0]	auto[1]	auto[0]	171	1			T18	2		T26	2		T33	2
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T15	1		T18	1		T33	1
all_values[3]	auto[1]	auto[0]	auto[1]	169	1			T15	3		T18	2		T33	2
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T18	1		T26	1		T33	1
all_values[4]	auto[0]	auto[0]	auto[0]	131	1			T26	1		T33	1		T125	2
all_values[4]	auto[0]	auto[0]	auto[1]	94	1			T15	1		T33	1		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T18	2		T26	2		T35	1
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T18	1		T26	1		T33	2
all_values[4]	auto[1]	auto[0]	auto[1]	207	1			T15	3		T18	1		T26	2
all_values[4]	auto[1]	auto[1]	auto[1]	171	1			T18	3		T26	1		T33	1
all_values[5]	auto[0]	auto[0]	auto[0]	170	1			T15	1		T18	2		T26	3
all_values[5]	auto[0]	auto[0]	auto[1]	74	1			T33	1		T34	1		T35	1
all_values[5]	auto[0]	auto[1]	auto[0]	135	1			T125	1		T34	1		T35	3
all_values[5]	auto[0]	auto[1]	auto[1]	83	1			T15	1		T18	2		T26	1
all_values[5]	auto[1]	auto[0]	auto[1]	214	1			T15	1		T18	2		T26	3
all_values[5]	auto[1]	auto[1]	auto[1]	150	1			T15	1		T18	1		T33	1
all_values[6]	auto[0]	auto[0]	auto[0]	161	1			T18	1		T125	1		T35	2
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T33	2		T34	1		T126	2
all_values[6]	auto[0]	auto[1]	auto[0]	162	1			T15	1		T18	2		T125	1
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T18	1		T26	2		T33	2
all_values[6]	auto[1]	auto[0]	auto[1]	169	1			T15	1		T26	2		T33	2
all_values[6]	auto[1]	auto[1]	auto[1]	180	1			T15	2		T18	3		T26	3
all_values[7]	auto[0]	auto[0]	auto[0]	191	1			T15	1		T18	2		T125	2
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T26	1		T33	2		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	148	1			T15	1		T26	3		T33	1
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T18	2		T35	1		T127	1
all_values[7]	auto[1]	auto[0]	auto[1]	188	1			T18	2		T26	3		T33	3
all_values[7]	auto[1]	auto[1]	auto[1]	143	1			T15	2		T18	1		T33	1
all_values[8]	auto[0]	auto[0]	auto[1]	267	1			T15	2		T18	2		T26	1
all_values[8]	auto[0]	auto[1]	auto[1]	227	1			T15	1		T18	2		T26	2
all_values[8]	auto[1]	auto[0]	auto[1]	183	1			T18	2		T26	3		T33	3
all_values[8]	auto[1]	auto[1]	auto[1]	149	1			T15	1		T18	1		T26	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal