Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1314
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T1256 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1615379082 Jul 09 04:26:59 PM PDT 24 Jul 09 04:27:06 PM PDT 24 54662654 ps
T1257 /workspace/coverage/cover_reg_top/36.uart_intr_test.2003992653 Jul 09 04:28:09 PM PDT 24 Jul 09 04:28:11 PM PDT 24 25830264 ps
T1258 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2551662999 Jul 09 04:26:50 PM PDT 24 Jul 09 04:26:52 PM PDT 24 11917723 ps
T1259 /workspace/coverage/cover_reg_top/23.uart_intr_test.3218786422 Jul 09 04:28:12 PM PDT 24 Jul 09 04:28:15 PM PDT 24 45186821 ps
T73 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3053428360 Jul 09 04:28:41 PM PDT 24 Jul 09 04:29:00 PM PDT 24 43993015 ps
T1260 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2853798203 Jul 09 04:28:54 PM PDT 24 Jul 09 04:29:08 PM PDT 24 23389960 ps
T1261 /workspace/coverage/cover_reg_top/21.uart_intr_test.376469012 Jul 09 04:28:51 PM PDT 24 Jul 09 04:29:06 PM PDT 24 107456408 ps
T74 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3980609483 Jul 09 04:27:22 PM PDT 24 Jul 09 04:27:27 PM PDT 24 74784831 ps
T1262 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3988840342 Jul 09 04:26:51 PM PDT 24 Jul 09 04:26:53 PM PDT 24 19335527 ps
T1263 /workspace/coverage/cover_reg_top/18.uart_intr_test.4226342807 Jul 09 04:28:11 PM PDT 24 Jul 09 04:28:19 PM PDT 24 53046352 ps
T1264 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1426638736 Jul 09 04:28:08 PM PDT 24 Jul 09 04:28:10 PM PDT 24 47196098 ps
T1265 /workspace/coverage/cover_reg_top/12.uart_intr_test.1695327914 Jul 09 04:28:15 PM PDT 24 Jul 09 04:28:19 PM PDT 24 43917823 ps
T1266 /workspace/coverage/cover_reg_top/9.uart_tl_errors.131164224 Jul 09 04:23:38 PM PDT 24 Jul 09 04:23:39 PM PDT 24 58904386 ps
T1267 /workspace/coverage/cover_reg_top/0.uart_intr_test.2555776399 Jul 09 04:26:57 PM PDT 24 Jul 09 04:27:03 PM PDT 24 44472744 ps
T1268 /workspace/coverage/cover_reg_top/16.uart_intr_test.2353842770 Jul 09 04:28:08 PM PDT 24 Jul 09 04:28:10 PM PDT 24 16167119 ps
T1269 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2442438091 Jul 09 04:28:07 PM PDT 24 Jul 09 04:28:09 PM PDT 24 104693227 ps
T1270 /workspace/coverage/cover_reg_top/11.uart_intr_test.4172858422 Jul 09 04:28:37 PM PDT 24 Jul 09 04:28:49 PM PDT 24 27133008 ps
T1271 /workspace/coverage/cover_reg_top/30.uart_intr_test.124161811 Jul 09 04:28:20 PM PDT 24 Jul 09 04:28:23 PM PDT 24 24218882 ps
T1272 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3330495132 Jul 09 04:26:55 PM PDT 24 Jul 09 04:27:01 PM PDT 24 120760576 ps
T1273 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2418557981 Jul 09 04:27:07 PM PDT 24 Jul 09 04:27:14 PM PDT 24 33034658 ps
T1274 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2831992529 Jul 09 04:22:54 PM PDT 24 Jul 09 04:22:55 PM PDT 24 110306145 ps
T1275 /workspace/coverage/cover_reg_top/15.uart_tl_errors.4132537152 Jul 09 04:28:10 PM PDT 24 Jul 09 04:28:14 PM PDT 24 447531259 ps
T1276 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1911120103 Jul 09 04:28:07 PM PDT 24 Jul 09 04:28:09 PM PDT 24 189221878 ps
T1277 /workspace/coverage/cover_reg_top/7.uart_intr_test.3434946570 Jul 09 04:24:44 PM PDT 24 Jul 09 04:24:45 PM PDT 24 49937634 ps
T1278 /workspace/coverage/cover_reg_top/43.uart_intr_test.3862226937 Jul 09 04:28:13 PM PDT 24 Jul 09 04:28:18 PM PDT 24 39207021 ps
T1279 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2236588670 Jul 09 04:26:51 PM PDT 24 Jul 09 04:26:53 PM PDT 24 16038003 ps
T1280 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1985656867 Jul 09 04:28:33 PM PDT 24 Jul 09 04:28:41 PM PDT 24 145053011 ps
T1281 /workspace/coverage/cover_reg_top/44.uart_intr_test.668382767 Jul 09 04:28:18 PM PDT 24 Jul 09 04:28:21 PM PDT 24 53409366 ps
T1282 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2057264747 Jul 09 04:24:22 PM PDT 24 Jul 09 04:24:23 PM PDT 24 231046847 ps
T1283 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2277417951 Jul 09 04:27:57 PM PDT 24 Jul 09 04:28:00 PM PDT 24 35029164 ps
T1284 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1465626104 Jul 09 04:26:54 PM PDT 24 Jul 09 04:27:01 PM PDT 24 123196853 ps
T75 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3022472903 Jul 09 04:28:19 PM PDT 24 Jul 09 04:28:22 PM PDT 24 15342525 ps
T1285 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1548256011 Jul 09 04:28:08 PM PDT 24 Jul 09 04:28:10 PM PDT 24 78212491 ps
T1286 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3890769106 Jul 09 04:28:08 PM PDT 24 Jul 09 04:28:11 PM PDT 24 72308108 ps
T1287 /workspace/coverage/cover_reg_top/29.uart_intr_test.752406623 Jul 09 04:28:27 PM PDT 24 Jul 09 04:28:30 PM PDT 24 67947101 ps
T1288 /workspace/coverage/cover_reg_top/40.uart_intr_test.1274896035 Jul 09 04:29:03 PM PDT 24 Jul 09 04:29:15 PM PDT 24 49850916 ps
T1289 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2420870539 Jul 09 04:27:05 PM PDT 24 Jul 09 04:27:11 PM PDT 24 15745734 ps
T1290 /workspace/coverage/cover_reg_top/4.uart_intr_test.752268961 Jul 09 04:25:29 PM PDT 24 Jul 09 04:25:30 PM PDT 24 42083660 ps
T1291 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.863828478 Jul 09 04:28:13 PM PDT 24 Jul 09 04:28:17 PM PDT 24 63608378 ps
T1292 /workspace/coverage/cover_reg_top/15.uart_intr_test.220050274 Jul 09 04:28:12 PM PDT 24 Jul 09 04:28:17 PM PDT 24 34813638 ps
T1293 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3555072649 Jul 09 04:26:50 PM PDT 24 Jul 09 04:26:52 PM PDT 24 49595335 ps
T1294 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2506020823 Jul 09 04:24:36 PM PDT 24 Jul 09 04:24:37 PM PDT 24 25763495 ps
T1295 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.264881058 Jul 09 04:26:54 PM PDT 24 Jul 09 04:27:00 PM PDT 24 108664786 ps
T1296 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3920675799 Jul 09 04:22:33 PM PDT 24 Jul 09 04:22:35 PM PDT 24 73022116 ps
T1297 /workspace/coverage/cover_reg_top/8.uart_intr_test.984475982 Jul 09 04:25:27 PM PDT 24 Jul 09 04:25:28 PM PDT 24 15266568 ps
T1298 /workspace/coverage/cover_reg_top/27.uart_intr_test.3119176652 Jul 09 04:28:16 PM PDT 24 Jul 09 04:28:20 PM PDT 24 60409394 ps
T1299 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2869308137 Jul 09 04:28:02 PM PDT 24 Jul 09 04:28:03 PM PDT 24 31352330 ps
T1300 /workspace/coverage/cover_reg_top/34.uart_intr_test.4238268497 Jul 09 04:28:24 PM PDT 24 Jul 09 04:28:28 PM PDT 24 42689993 ps
T129 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4088416509 Jul 09 04:28:26 PM PDT 24 Jul 09 04:28:30 PM PDT 24 60149496 ps
T1301 /workspace/coverage/cover_reg_top/14.uart_intr_test.3716761777 Jul 09 04:28:19 PM PDT 24 Jul 09 04:28:22 PM PDT 24 18654922 ps
T1302 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2113531238 Jul 09 04:24:01 PM PDT 24 Jul 09 04:24:04 PM PDT 24 249991454 ps
T1303 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2491448875 Jul 09 04:26:44 PM PDT 24 Jul 09 04:26:48 PM PDT 24 137718084 ps
T1304 /workspace/coverage/cover_reg_top/3.uart_tl_errors.290777174 Jul 09 04:27:07 PM PDT 24 Jul 09 04:27:16 PM PDT 24 446508009 ps
T93 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2899158489 Jul 09 04:28:51 PM PDT 24 Jul 09 04:29:06 PM PDT 24 82461084 ps
T1305 /workspace/coverage/cover_reg_top/9.uart_intr_test.3814397596 Jul 09 04:25:20 PM PDT 24 Jul 09 04:25:21 PM PDT 24 16271911 ps
T1306 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1699428594 Jul 09 04:21:53 PM PDT 24 Jul 09 04:21:55 PM PDT 24 437750119 ps
T1307 /workspace/coverage/cover_reg_top/49.uart_intr_test.2115485150 Jul 09 04:28:12 PM PDT 24 Jul 09 04:28:20 PM PDT 24 13762479 ps
T1308 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.328966075 Jul 09 04:27:54 PM PDT 24 Jul 09 04:27:57 PM PDT 24 82170875 ps
T1309 /workspace/coverage/cover_reg_top/22.uart_intr_test.1435490783 Jul 09 04:28:08 PM PDT 24 Jul 09 04:28:10 PM PDT 24 128416402 ps
T1310 /workspace/coverage/cover_reg_top/37.uart_intr_test.1855883772 Jul 09 04:28:30 PM PDT 24 Jul 09 04:28:44 PM PDT 24 25679634 ps
T1311 /workspace/coverage/cover_reg_top/6.uart_intr_test.1461320919 Jul 09 04:26:52 PM PDT 24 Jul 09 04:26:55 PM PDT 24 15012676 ps
T1312 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.849515473 Jul 09 04:21:42 PM PDT 24 Jul 09 04:21:44 PM PDT 24 85240852 ps
T1313 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2299182866 Jul 09 04:23:38 PM PDT 24 Jul 09 04:23:39 PM PDT 24 18203978 ps
T1314 /workspace/coverage/cover_reg_top/32.uart_intr_test.2842802701 Jul 09 04:28:12 PM PDT 24 Jul 09 04:28:15 PM PDT 24 41662707 ps

Test location /workspace/coverage/default/21.uart_stress_all.3224470402
Short name T8
Test name
Test status
Simulation time 449195352756 ps
CPU time 161.06 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:34:12 PM PDT 24
Peak memory 199784 kb
Host smart-60758bb3-6e13-4e91-86f3-0e74d3ea5c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224470402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3224470402
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2113020834
Short name T33
Test name
Test status
Simulation time 1004948337060 ps
CPU time 867.53 seconds
Started Jul 09 04:30:22 PM PDT 24
Finished Jul 09 04:44:51 PM PDT 24
Peak memory 224548 kb
Host smart-260f6700-22e5-4ed0-867e-a7d8340694ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113020834 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2113020834
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.807839617
Short name T15
Test name
Test status
Simulation time 200937331168 ps
CPU time 636.19 seconds
Started Jul 09 04:32:42 PM PDT 24
Finished Jul 09 04:43:19 PM PDT 24
Peak memory 216476 kb
Host smart-4152d905-5529-4143-94e0-f75f83533c37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807839617 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.807839617
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.4204585672
Short name T36
Test name
Test status
Simulation time 307169115958 ps
CPU time 769.05 seconds
Started Jul 09 04:31:20 PM PDT 24
Finished Jul 09 04:44:27 PM PDT 24
Peak memory 224672 kb
Host smart-1d68af48-395f-43a1-9928-61ce8acb7351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204585672 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.4204585672
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.547386192
Short name T253
Test name
Test status
Simulation time 211206857307 ps
CPU time 1029.3 seconds
Started Jul 09 04:31:30 PM PDT 24
Finished Jul 09 04:48:52 PM PDT 24
Peak memory 199676 kb
Host smart-ec07d89a-f52e-4d42-bc87-43e7407ee9a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547386192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.547386192
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all.2386748164
Short name T133
Test name
Test status
Simulation time 284524480549 ps
CPU time 359.33 seconds
Started Jul 09 04:30:41 PM PDT 24
Finished Jul 09 04:36:42 PM PDT 24
Peak memory 199724 kb
Host smart-b1c44ad3-2ba8-46c2-ba07-08bc474bddaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386748164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2386748164
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2009497655
Short name T38
Test name
Test status
Simulation time 321844846963 ps
CPU time 852.45 seconds
Started Jul 09 04:31:55 PM PDT 24
Finished Jul 09 04:46:11 PM PDT 24
Peak memory 224756 kb
Host smart-d6ee6e8e-cfac-4d87-ac7a-19ec69af37af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009497655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2009497655
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.294670385
Short name T102
Test name
Test status
Simulation time 221929898 ps
CPU time 0.9 seconds
Started Jul 09 04:23:35 PM PDT 24
Finished Jul 09 04:23:37 PM PDT 24
Peak memory 218640 kb
Host smart-a396d81b-7da2-4934-8d4b-d087cbf37575
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294670385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.294670385
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.440518221
Short name T34
Test name
Test status
Simulation time 238402669929 ps
CPU time 711.46 seconds
Started Jul 09 04:32:44 PM PDT 24
Finished Jul 09 04:44:36 PM PDT 24
Peak memory 230000 kb
Host smart-7db9e927-0165-43c8-a307-247627089705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440518221 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.440518221
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.421404566
Short name T327
Test name
Test status
Simulation time 14242072 ps
CPU time 0.53 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:31:24 PM PDT 24
Peak memory 195096 kb
Host smart-99b14690-ce08-4734-924d-ffdd6f3ab5ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421404566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.421404566
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.4009880329
Short name T26
Test name
Test status
Simulation time 829941962234 ps
CPU time 789.79 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:43:58 PM PDT 24
Peak memory 216308 kb
Host smart-87994c99-783a-4637-9abc-3ec8703550ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009880329 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.4009880329
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1000221716
Short name T58
Test name
Test status
Simulation time 431841713026 ps
CPU time 1147.31 seconds
Started Jul 09 04:32:23 PM PDT 24
Finished Jul 09 04:51:36 PM PDT 24
Peak memory 224736 kb
Host smart-e521a7ca-94a0-409a-9903-4bb3ffa624a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000221716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1000221716
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2487298101
Short name T45
Test name
Test status
Simulation time 127633055761 ps
CPU time 174.51 seconds
Started Jul 09 04:32:19 PM PDT 24
Finished Jul 09 04:35:19 PM PDT 24
Peak memory 199748 kb
Host smart-a75c05e3-78c9-428d-a037-7b48d83b1034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487298101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2487298101
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2279861501
Short name T42
Test name
Test status
Simulation time 163477530199 ps
CPU time 206.23 seconds
Started Jul 09 04:32:12 PM PDT 24
Finished Jul 09 04:35:40 PM PDT 24
Peak memory 199776 kb
Host smart-b16546bc-7b2e-4641-96de-ed8ece93226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279861501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2279861501
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3438019794
Short name T94
Test name
Test status
Simulation time 358959468 ps
CPU time 1.26 seconds
Started Jul 09 04:28:05 PM PDT 24
Finished Jul 09 04:28:08 PM PDT 24
Peak memory 199912 kb
Host smart-7359d77e-69fd-4584-b6cc-6d9928b54fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438019794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3438019794
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2550433324
Short name T113
Test name
Test status
Simulation time 89609553801 ps
CPU time 165.55 seconds
Started Jul 09 04:31:50 PM PDT 24
Finished Jul 09 04:34:40 PM PDT 24
Peak memory 199816 kb
Host smart-6deb289b-a50d-40d1-8d7e-f2371af94a0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550433324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2550433324
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1785577538
Short name T67
Test name
Test status
Simulation time 19351308 ps
CPU time 0.54 seconds
Started Jul 09 04:28:19 PM PDT 24
Finished Jul 09 04:28:23 PM PDT 24
Peak memory 196020 kb
Host smart-31abebbc-93eb-4fa5-b84a-4d0be8d3aa62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785577538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1785577538
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2682096458
Short name T126
Test name
Test status
Simulation time 182694273017 ps
CPU time 1065.4 seconds
Started Jul 09 04:30:39 PM PDT 24
Finished Jul 09 04:48:27 PM PDT 24
Peak memory 224608 kb
Host smart-5bc325c3-fdb0-4fa0-afb4-966aea3081fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682096458 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2682096458
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.448102684
Short name T157
Test name
Test status
Simulation time 45063805662 ps
CPU time 43.19 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:34:10 PM PDT 24
Peak memory 199716 kb
Host smart-b914f743-6714-44f5-9a7c-3398d86af77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448102684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.448102684
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.4033414746
Short name T125
Test name
Test status
Simulation time 169028777768 ps
CPU time 124.39 seconds
Started Jul 09 04:24:05 PM PDT 24
Finished Jul 09 04:26:10 PM PDT 24
Peak memory 199800 kb
Host smart-d4d04048-29b4-4a1d-93d8-17cad1a63ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033414746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.4033414746
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3473579734
Short name T41
Test name
Test status
Simulation time 14092424806 ps
CPU time 26.74 seconds
Started Jul 09 04:33:31 PM PDT 24
Finished Jul 09 04:33:58 PM PDT 24
Peak memory 199876 kb
Host smart-1aa68e8f-abb6-48ed-b025-97c411bf2f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473579734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3473579734
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1840823800
Short name T109
Test name
Test status
Simulation time 325157266526 ps
CPU time 1025.03 seconds
Started Jul 09 04:32:46 PM PDT 24
Finished Jul 09 04:49:52 PM PDT 24
Peak memory 224648 kb
Host smart-0d764496-8b5a-4186-9932-d7976eebd481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840823800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1840823800
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1404691952
Short name T288
Test name
Test status
Simulation time 136383665454 ps
CPU time 90.07 seconds
Started Jul 09 04:32:56 PM PDT 24
Finished Jul 09 04:34:27 PM PDT 24
Peak memory 199764 kb
Host smart-9514c0c5-f618-4253-92fc-7c5fee43af36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404691952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1404691952
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.286504702
Short name T116
Test name
Test status
Simulation time 162900644697 ps
CPU time 66.98 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:32:43 PM PDT 24
Peak memory 199820 kb
Host smart-bb888ff0-a18a-4a8f-8a1d-36b9bdcdcd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286504702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.286504702
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1581091189
Short name T153
Test name
Test status
Simulation time 153918516755 ps
CPU time 67.05 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:34:12 PM PDT 24
Peak memory 199744 kb
Host smart-d17f0309-e3bf-455c-9fd8-17077bed9e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581091189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1581091189
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.371908127
Short name T89
Test name
Test status
Simulation time 75914674 ps
CPU time 0.9 seconds
Started Jul 09 04:25:37 PM PDT 24
Finished Jul 09 04:25:38 PM PDT 24
Peak memory 199356 kb
Host smart-9990bd5a-5bb2-4776-923b-00e0088f3f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371908127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.371908127
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.204255110
Short name T243
Test name
Test status
Simulation time 95876371739 ps
CPU time 33.77 seconds
Started Jul 09 04:32:59 PM PDT 24
Finished Jul 09 04:33:34 PM PDT 24
Peak memory 199772 kb
Host smart-f66c6cc1-7019-4240-94a6-728db107384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204255110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.204255110
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1710382593
Short name T163
Test name
Test status
Simulation time 115002816605 ps
CPU time 434.96 seconds
Started Jul 09 04:31:13 PM PDT 24
Finished Jul 09 04:38:47 PM PDT 24
Peak memory 215464 kb
Host smart-1d7f84b8-c31c-4175-a630-32e8623c8009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710382593 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1710382593
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3311775014
Short name T44
Test name
Test status
Simulation time 30136397590 ps
CPU time 55.14 seconds
Started Jul 09 04:33:32 PM PDT 24
Finished Jul 09 04:34:29 PM PDT 24
Peak memory 199804 kb
Host smart-e5b36467-545a-43e3-b99f-6b57de59b5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311775014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3311775014
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3553250055
Short name T1079
Test name
Test status
Simulation time 306324338989 ps
CPU time 385.82 seconds
Started Jul 09 04:32:56 PM PDT 24
Finished Jul 09 04:39:23 PM PDT 24
Peak memory 216280 kb
Host smart-2299832d-0f39-453d-9a1e-3933d627bdea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553250055 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3553250055
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.222965398
Short name T98
Test name
Test status
Simulation time 200490858 ps
CPU time 0.94 seconds
Started Jul 09 04:28:22 PM PDT 24
Finished Jul 09 04:28:25 PM PDT 24
Peak memory 199848 kb
Host smart-d27df6fe-c015-4644-8183-5d31fc2feb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222965398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.222965398
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/29.uart_stress_all.3323380747
Short name T18
Test name
Test status
Simulation time 193621576379 ps
CPU time 113.52 seconds
Started Jul 09 04:31:42 PM PDT 24
Finished Jul 09 04:33:43 PM PDT 24
Peak memory 199756 kb
Host smart-3231ec34-de91-47ac-98bf-89034f5202a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323380747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3323380747
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2692038633
Short name T192
Test name
Test status
Simulation time 171629819046 ps
CPU time 39.08 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:33:45 PM PDT 24
Peak memory 199816 kb
Host smart-5ec98f79-e43c-4d3a-b4d0-c38ca7db331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692038633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2692038633
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3754207165
Short name T489
Test name
Test status
Simulation time 89664332545 ps
CPU time 99.46 seconds
Started Jul 09 04:31:35 PM PDT 24
Finished Jul 09 04:33:24 PM PDT 24
Peak memory 199780 kb
Host smart-ac03d58e-d72a-4be0-8242-56901b93d6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754207165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3754207165
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2405644233
Short name T206
Test name
Test status
Simulation time 42149061113 ps
CPU time 35.42 seconds
Started Jul 09 04:32:43 PM PDT 24
Finished Jul 09 04:33:19 PM PDT 24
Peak memory 199676 kb
Host smart-dd475cc5-63c2-4830-8c62-6f852f1624fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405644233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2405644233
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1339973173
Short name T261
Test name
Test status
Simulation time 81303939438 ps
CPU time 38.36 seconds
Started Jul 09 04:30:58 PM PDT 24
Finished Jul 09 04:31:50 PM PDT 24
Peak memory 199728 kb
Host smart-2f1a9834-2657-4c13-8718-0295e042b2d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339973173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1339973173
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.339000598
Short name T200
Test name
Test status
Simulation time 32274853262 ps
CPU time 21.87 seconds
Started Jul 09 04:33:09 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 199764 kb
Host smart-f6351362-229d-4ea6-8e28-5f8ec28f4610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339000598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.339000598
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.397259158
Short name T238
Test name
Test status
Simulation time 13537213343 ps
CPU time 15.94 seconds
Started Jul 09 04:33:29 PM PDT 24
Finished Jul 09 04:33:46 PM PDT 24
Peak memory 199944 kb
Host smart-fb4c073d-8535-4b6d-bac0-b76dc2190bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397259158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.397259158
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_full.4246748409
Short name T414
Test name
Test status
Simulation time 129867768173 ps
CPU time 269 seconds
Started Jul 09 04:30:51 PM PDT 24
Finished Jul 09 04:35:25 PM PDT 24
Peak memory 199768 kb
Host smart-b6b23327-01af-4204-8596-e3f3d8d841dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246748409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4246748409
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3484928141
Short name T237
Test name
Test status
Simulation time 101934881358 ps
CPU time 147.56 seconds
Started Jul 09 04:27:19 PM PDT 24
Finished Jul 09 04:29:50 PM PDT 24
Peak memory 199620 kb
Host smart-7e61d2e2-cec2-4f4e-8cd4-ba95ce975d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484928141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3484928141
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.383731068
Short name T310
Test name
Test status
Simulation time 186226278582 ps
CPU time 104.71 seconds
Started Jul 09 04:30:56 PM PDT 24
Finished Jul 09 04:32:52 PM PDT 24
Peak memory 208148 kb
Host smart-d2c988e4-bf0b-4a65-9568-cd84ae12b55b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383731068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.383731068
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.168339632
Short name T233
Test name
Test status
Simulation time 19981579814 ps
CPU time 34.27 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:33:38 PM PDT 24
Peak memory 199744 kb
Host smart-90f9bb9e-e516-4518-a341-de32dabdbc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168339632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.168339632
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.105343333
Short name T228
Test name
Test status
Simulation time 7003326479 ps
CPU time 11.55 seconds
Started Jul 09 04:33:08 PM PDT 24
Finished Jul 09 04:33:20 PM PDT 24
Peak memory 199564 kb
Host smart-be9477a2-b33c-4849-90aa-0e87527b1512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105343333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.105343333
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1252773856
Short name T135
Test name
Test status
Simulation time 171542160336 ps
CPU time 251.6 seconds
Started Jul 09 04:33:13 PM PDT 24
Finished Jul 09 04:37:26 PM PDT 24
Peak memory 199744 kb
Host smart-f147139c-db1f-4329-9e60-2e4be3d90d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252773856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1252773856
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.3822518074
Short name T191
Test name
Test status
Simulation time 189671982391 ps
CPU time 199.74 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:33:49 PM PDT 24
Peak memory 199688 kb
Host smart-598e03f9-5c75-4561-b6fb-75bac07dac77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822518074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3822518074
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3273261754
Short name T260
Test name
Test status
Simulation time 17403769584 ps
CPU time 14.58 seconds
Started Jul 09 04:32:41 PM PDT 24
Finished Jul 09 04:32:56 PM PDT 24
Peak memory 199828 kb
Host smart-8d58bd7a-82bd-4fcb-b17f-19d79f061566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273261754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3273261754
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.752009312
Short name T37
Test name
Test status
Simulation time 92408332308 ps
CPU time 638.19 seconds
Started Jul 09 04:33:00 PM PDT 24
Finished Jul 09 04:43:39 PM PDT 24
Peak memory 225108 kb
Host smart-79b28c81-679f-4489-87dd-5ca9f4997e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752009312 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.752009312
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3132645057
Short name T232
Test name
Test status
Simulation time 253217159415 ps
CPU time 490.05 seconds
Started Jul 09 04:32:55 PM PDT 24
Finished Jul 09 04:41:06 PM PDT 24
Peak memory 216496 kb
Host smart-87a944af-6b11-45c9-93f2-898640d16602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132645057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3132645057
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2120177073
Short name T128
Test name
Test status
Simulation time 166226640 ps
CPU time 0.92 seconds
Started Jul 09 04:28:33 PM PDT 24
Finished Jul 09 04:28:41 PM PDT 24
Peak memory 199572 kb
Host smart-d4fa710b-7726-44b1-a7d0-c734f658aa35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120177073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2120177073
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3355978518
Short name T498
Test name
Test status
Simulation time 73142545978 ps
CPU time 103.63 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:33:06 PM PDT 24
Peak memory 200056 kb
Host smart-e136f53e-b380-4d9c-a1c3-00d8a0adefae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355978518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3355978518
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.4205238750
Short name T150
Test name
Test status
Simulation time 27744459780 ps
CPU time 34.73 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:33:37 PM PDT 24
Peak memory 199756 kb
Host smart-3e17a925-cee7-4805-81a9-3a96205196a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205238750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.4205238750
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2635651959
Short name T218
Test name
Test status
Simulation time 8333761460 ps
CPU time 3.93 seconds
Started Jul 09 04:33:11 PM PDT 24
Finished Jul 09 04:33:16 PM PDT 24
Peak memory 199648 kb
Host smart-606b079b-b12e-4ff6-ad95-283323a526e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635651959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2635651959
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.950074018
Short name T245
Test name
Test status
Simulation time 40903248445 ps
CPU time 27.43 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:33:35 PM PDT 24
Peak memory 199824 kb
Host smart-5f43f1a7-42f5-4e62-9263-21ce083d9112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950074018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.950074018
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.501905851
Short name T178
Test name
Test status
Simulation time 139981798059 ps
CPU time 40.71 seconds
Started Jul 09 04:33:52 PM PDT 24
Finished Jul 09 04:34:35 PM PDT 24
Peak memory 199736 kb
Host smart-3f593f30-6158-47f7-8754-061fe1d84694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501905851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.501905851
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3501997890
Short name T1077
Test name
Test status
Simulation time 12466125344 ps
CPU time 33.2 seconds
Started Jul 09 04:33:07 PM PDT 24
Finished Jul 09 04:33:41 PM PDT 24
Peak memory 199780 kb
Host smart-d90e3a5e-86bd-4a78-b13b-ee7ec98e26e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501997890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3501997890
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.45938220
Short name T224
Test name
Test status
Simulation time 23310639508 ps
CPU time 21.31 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:31:45 PM PDT 24
Peak memory 199804 kb
Host smart-797f21e6-faf0-4de0-a1d7-81d9ee02cc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45938220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.45938220
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3192052497
Short name T242
Test name
Test status
Simulation time 40070164470 ps
CPU time 32.8 seconds
Started Jul 09 04:33:08 PM PDT 24
Finished Jul 09 04:33:41 PM PDT 24
Peak memory 199596 kb
Host smart-e4eb13ee-1f00-4378-ac3d-7dcdeb884dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192052497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3192052497
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2581635081
Short name T211
Test name
Test status
Simulation time 87693892110 ps
CPU time 160.62 seconds
Started Jul 09 04:33:07 PM PDT 24
Finished Jul 09 04:35:49 PM PDT 24
Peak memory 199672 kb
Host smart-6fcc564b-98a1-4a4e-a320-c5a22ea4da48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581635081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2581635081
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.223542948
Short name T202
Test name
Test status
Simulation time 199564612756 ps
CPU time 63.15 seconds
Started Jul 09 04:33:13 PM PDT 24
Finished Jul 09 04:34:17 PM PDT 24
Peak memory 199768 kb
Host smart-76d0c046-0c24-49da-9ab0-7666602729dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223542948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.223542948
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1062659738
Short name T997
Test name
Test status
Simulation time 132332226546 ps
CPU time 175.79 seconds
Started Jul 09 04:33:14 PM PDT 24
Finished Jul 09 04:36:11 PM PDT 24
Peak memory 199812 kb
Host smart-b01ecf68-626b-4795-a8a2-7826570115fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062659738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1062659738
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2366052282
Short name T219
Test name
Test status
Simulation time 298395902140 ps
CPU time 69.3 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:34:25 PM PDT 24
Peak memory 199748 kb
Host smart-b8de8fce-00b3-49c0-8eaf-bc677469ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366052282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2366052282
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4132379918
Short name T186
Test name
Test status
Simulation time 13793619169 ps
CPU time 23.77 seconds
Started Jul 09 04:33:23 PM PDT 24
Finished Jul 09 04:33:48 PM PDT 24
Peak memory 199800 kb
Host smart-385adfa2-ad9e-4271-9da9-f78f7fe2a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132379918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4132379918
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3571266584
Short name T145
Test name
Test status
Simulation time 102810305739 ps
CPU time 53.18 seconds
Started Jul 09 04:33:24 PM PDT 24
Finished Jul 09 04:34:18 PM PDT 24
Peak memory 199776 kb
Host smart-53a72f72-13d6-4adc-b1fc-dc79e5238369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571266584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3571266584
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2587714114
Short name T141
Test name
Test status
Simulation time 24258686604 ps
CPU time 20.36 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:31:51 PM PDT 24
Peak memory 199692 kb
Host smart-fc2cacc5-7662-43a9-9ca9-1a4756052295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587714114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2587714114
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1915382129
Short name T239
Test name
Test status
Simulation time 34007071007 ps
CPU time 11.88 seconds
Started Jul 09 04:33:33 PM PDT 24
Finished Jul 09 04:33:47 PM PDT 24
Peak memory 199720 kb
Host smart-f8371396-caae-49d6-84d8-522b2557b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915382129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1915382129
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.76077456
Short name T222
Test name
Test status
Simulation time 59627221705 ps
CPU time 12.04 seconds
Started Jul 09 04:33:33 PM PDT 24
Finished Jul 09 04:33:46 PM PDT 24
Peak memory 199824 kb
Host smart-ef535e29-273a-4e58-9a8b-432cf89b7cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76077456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.76077456
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1161938813
Short name T246
Test name
Test status
Simulation time 63953177783 ps
CPU time 39.29 seconds
Started Jul 09 04:33:39 PM PDT 24
Finished Jul 09 04:34:20 PM PDT 24
Peak memory 199812 kb
Host smart-d8591c6b-cdae-45d6-9ebe-28bf7b31cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161938813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1161938813
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all.3718307324
Short name T226
Test name
Test status
Simulation time 297960443075 ps
CPU time 317.8 seconds
Started Jul 09 04:32:16 PM PDT 24
Finished Jul 09 04:37:37 PM PDT 24
Peak memory 199800 kb
Host smart-0030e8d3-1b73-4fc7-a721-fe35ad3f79a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718307324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3718307324
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all.969531818
Short name T223
Test name
Test status
Simulation time 203122686461 ps
CPU time 199.69 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:36:07 PM PDT 24
Peak memory 200180 kb
Host smart-23624a97-1fce-472f-a14e-bd149810a02b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969531818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.969531818
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3397571028
Short name T149
Test name
Test status
Simulation time 68425708115 ps
CPU time 117.75 seconds
Started Jul 09 04:32:52 PM PDT 24
Finished Jul 09 04:34:51 PM PDT 24
Peak memory 199792 kb
Host smart-00b9047d-f17c-4c09-b780-bc4d797874f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397571028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3397571028
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.373761966
Short name T155
Test name
Test status
Simulation time 333383421527 ps
CPU time 30.22 seconds
Started Jul 09 04:32:51 PM PDT 24
Finished Jul 09 04:33:22 PM PDT 24
Peak memory 199540 kb
Host smart-092a106e-b97d-4531-8ac7-a83988dae744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373761966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.373761966
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.936484471
Short name T1254
Test name
Test status
Simulation time 59219569 ps
CPU time 0.72 seconds
Started Jul 09 04:26:53 PM PDT 24
Finished Jul 09 04:26:58 PM PDT 24
Peak memory 196936 kb
Host smart-5b689c94-68be-4eb4-8e99-23cc116545aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936484471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.936484471
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4095577841
Short name T1197
Test name
Test status
Simulation time 134114171 ps
CPU time 1.29 seconds
Started Jul 09 04:26:43 PM PDT 24
Finished Jul 09 04:26:47 PM PDT 24
Peak memory 198012 kb
Host smart-86d6b383-aa64-4dbc-a51a-5842dedbc4d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095577841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4095577841
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.268272614
Short name T1233
Test name
Test status
Simulation time 16500168 ps
CPU time 0.6 seconds
Started Jul 09 04:26:57 PM PDT 24
Finished Jul 09 04:27:04 PM PDT 24
Peak memory 196028 kb
Host smart-c21e09c0-a7c8-44c5-ab66-afd6933dbd75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268272614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.268272614
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.730649400
Short name T1194
Test name
Test status
Simulation time 32923638 ps
CPU time 0.79 seconds
Started Jul 09 04:27:10 PM PDT 24
Finished Jul 09 04:27:17 PM PDT 24
Peak memory 200056 kb
Host smart-881021c2-891a-4b52-a65a-4686b33bf91e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730649400 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.730649400
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.4236338895
Short name T1234
Test name
Test status
Simulation time 14844187 ps
CPU time 0.56 seconds
Started Jul 09 04:26:43 PM PDT 24
Finished Jul 09 04:26:47 PM PDT 24
Peak memory 195764 kb
Host smart-6c0a9e3f-77fb-4e2a-a35c-7e10aed67627
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236338895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4236338895
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2555776399
Short name T1267
Test name
Test status
Simulation time 44472744 ps
CPU time 0.55 seconds
Started Jul 09 04:26:57 PM PDT 24
Finished Jul 09 04:27:03 PM PDT 24
Peak memory 194976 kb
Host smart-8005e6a3-9f1c-4a45-809f-1ec58715174b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555776399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2555776399
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1430381530
Short name T84
Test name
Test status
Simulation time 33147747 ps
CPU time 0.75 seconds
Started Jul 09 04:26:42 PM PDT 24
Finished Jul 09 04:26:46 PM PDT 24
Peak memory 197236 kb
Host smart-32f6f3d6-b0af-4c16-abca-1dff90af95df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430381530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1430381530
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3616424738
Short name T1204
Test name
Test status
Simulation time 47485151 ps
CPU time 1.16 seconds
Started Jul 09 04:26:43 PM PDT 24
Finished Jul 09 04:26:46 PM PDT 24
Peak memory 199716 kb
Host smart-5889bb26-2a83-4484-8bd5-171788f42d17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616424738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3616424738
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2759146948
Short name T1232
Test name
Test status
Simulation time 72408907 ps
CPU time 1.25 seconds
Started Jul 09 04:21:40 PM PDT 24
Finished Jul 09 04:21:42 PM PDT 24
Peak memory 199844 kb
Host smart-0264140d-6087-4563-b4c9-32abc18a0d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759146948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2759146948
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2236588670
Short name T1279
Test name
Test status
Simulation time 16038003 ps
CPU time 0.64 seconds
Started Jul 09 04:26:51 PM PDT 24
Finished Jul 09 04:26:53 PM PDT 24
Peak memory 194024 kb
Host smart-2b9f225a-0404-49db-9d99-d14fd83ba699
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236588670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2236588670
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1465626104
Short name T1284
Test name
Test status
Simulation time 123196853 ps
CPU time 1.32 seconds
Started Jul 09 04:26:54 PM PDT 24
Finished Jul 09 04:27:01 PM PDT 24
Peak memory 197988 kb
Host smart-a71c4afc-1479-4765-b257-47f9549d0240
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465626104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1465626104
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3330495132
Short name T1272
Test name
Test status
Simulation time 120760576 ps
CPU time 0.55 seconds
Started Jul 09 04:26:55 PM PDT 24
Finished Jul 09 04:27:01 PM PDT 24
Peak memory 195716 kb
Host smart-200bb8ce-2765-40ce-a0f4-9ab6af64d674
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330495132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3330495132
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.309136009
Short name T1231
Test name
Test status
Simulation time 49520645 ps
CPU time 1.3 seconds
Started Jul 09 04:27:05 PM PDT 24
Finished Jul 09 04:27:12 PM PDT 24
Peak memory 200668 kb
Host smart-a4094c93-febe-44e9-9e57-d5efbc8b6a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309136009 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.309136009
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.742222861
Short name T1248
Test name
Test status
Simulation time 20342762 ps
CPU time 0.62 seconds
Started Jul 09 04:27:07 PM PDT 24
Finished Jul 09 04:27:14 PM PDT 24
Peak memory 195996 kb
Host smart-21bf57e2-f606-4dd6-9afc-d69dc355f0cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742222861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.742222861
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4110030331
Short name T1253
Test name
Test status
Simulation time 12371589 ps
CPU time 0.57 seconds
Started Jul 09 04:27:06 PM PDT 24
Finished Jul 09 04:27:12 PM PDT 24
Peak memory 195000 kb
Host smart-61ff2d68-9b5d-4741-ab9c-09441a1c6a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110030331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4110030331
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.328966075
Short name T1308
Test name
Test status
Simulation time 82170875 ps
CPU time 0.7 seconds
Started Jul 09 04:27:54 PM PDT 24
Finished Jul 09 04:27:57 PM PDT 24
Peak memory 197612 kb
Host smart-79d8a09b-5313-4126-9177-d1045b97d14a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328966075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.328966075
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3988840342
Short name T1262
Test name
Test status
Simulation time 19335527 ps
CPU time 0.87 seconds
Started Jul 09 04:26:51 PM PDT 24
Finished Jul 09 04:26:53 PM PDT 24
Peak memory 198076 kb
Host smart-06965590-edfa-46b2-a667-0d32063fc658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988840342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3988840342
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1985656867
Short name T1280
Test name
Test status
Simulation time 145053011 ps
CPU time 0.97 seconds
Started Jul 09 04:28:33 PM PDT 24
Finished Jul 09 04:28:41 PM PDT 24
Peak memory 200444 kb
Host smart-ab4e164d-a954-4cb4-82fc-2492187b5a0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985656867 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1985656867
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2831992529
Short name T1274
Test name
Test status
Simulation time 110306145 ps
CPU time 0.61 seconds
Started Jul 09 04:22:54 PM PDT 24
Finished Jul 09 04:22:55 PM PDT 24
Peak memory 196004 kb
Host smart-ae58c200-443b-429f-9c14-a55e0616c6a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831992529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2831992529
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1366550197
Short name T1228
Test name
Test status
Simulation time 171102332 ps
CPU time 0.55 seconds
Started Jul 09 04:27:24 PM PDT 24
Finished Jul 09 04:27:29 PM PDT 24
Peak memory 194992 kb
Host smart-e18f63fa-fc8f-46a7-9a8e-c54f743747e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366550197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1366550197
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.4196151324
Short name T1210
Test name
Test status
Simulation time 50796732 ps
CPU time 0.72 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:15 PM PDT 24
Peak memory 198292 kb
Host smart-968245fd-6862-40e6-b656-b5ba3587a179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196151324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.4196151324
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3920675799
Short name T1296
Test name
Test status
Simulation time 73022116 ps
CPU time 1.64 seconds
Started Jul 09 04:22:33 PM PDT 24
Finished Jul 09 04:22:35 PM PDT 24
Peak memory 200724 kb
Host smart-f2f645b9-7e36-4231-b7a2-d8b7b0b6928e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920675799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3920675799
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2734933534
Short name T92
Test name
Test status
Simulation time 177149974 ps
CPU time 1.31 seconds
Started Jul 09 04:27:46 PM PDT 24
Finished Jul 09 04:27:48 PM PDT 24
Peak memory 199936 kb
Host smart-fc728ae1-74bc-4bf7-84aa-90a39f67d40b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734933534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2734933534
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.843363960
Short name T1202
Test name
Test status
Simulation time 72434467 ps
CPU time 0.97 seconds
Started Jul 09 04:27:57 PM PDT 24
Finished Jul 09 04:28:00 PM PDT 24
Peak memory 200456 kb
Host smart-5510a331-97a3-4190-b1e8-9d770cf851af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843363960 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.843363960
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.4139540805
Short name T1222
Test name
Test status
Simulation time 22976411 ps
CPU time 0.57 seconds
Started Jul 09 04:28:40 PM PDT 24
Finished Jul 09 04:28:53 PM PDT 24
Peak memory 196028 kb
Host smart-b6d458e9-592a-4248-a4a2-b00582e8b709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139540805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.4139540805
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4172858422
Short name T1270
Test name
Test status
Simulation time 27133008 ps
CPU time 0.55 seconds
Started Jul 09 04:28:37 PM PDT 24
Finished Jul 09 04:28:49 PM PDT 24
Peak memory 194924 kb
Host smart-79505fd8-344d-4876-a1c9-51d2863edf76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172858422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4172858422
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.863828478
Short name T1291
Test name
Test status
Simulation time 63608378 ps
CPU time 0.64 seconds
Started Jul 09 04:28:13 PM PDT 24
Finished Jul 09 04:28:17 PM PDT 24
Peak memory 196204 kb
Host smart-555976de-a88e-4a94-8a67-6c42f0b664ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863828478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.863828478
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2277417951
Short name T1283
Test name
Test status
Simulation time 35029164 ps
CPU time 1.71 seconds
Started Jul 09 04:27:57 PM PDT 24
Finished Jul 09 04:28:00 PM PDT 24
Peak memory 200656 kb
Host smart-55e985f8-7e54-444e-b416-3d59129fa42d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277417951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2277417951
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2899158489
Short name T93
Test name
Test status
Simulation time 82461084 ps
CPU time 1.24 seconds
Started Jul 09 04:28:51 PM PDT 24
Finished Jul 09 04:29:06 PM PDT 24
Peak memory 199980 kb
Host smart-959cc291-8452-40bb-90e6-bd17ee77a061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899158489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2899158489
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2943970314
Short name T1235
Test name
Test status
Simulation time 48901887 ps
CPU time 1.22 seconds
Started Jul 09 04:28:24 PM PDT 24
Finished Jul 09 04:28:28 PM PDT 24
Peak memory 201060 kb
Host smart-f67b8b01-8a11-4d50-93f2-5c7bb5eb9751
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943970314 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2943970314
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3022472903
Short name T75
Test name
Test status
Simulation time 15342525 ps
CPU time 0.58 seconds
Started Jul 09 04:28:19 PM PDT 24
Finished Jul 09 04:28:22 PM PDT 24
Peak memory 196096 kb
Host smart-ab3295c5-0051-4d0a-9db1-9a249f4d7411
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022472903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3022472903
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1695327914
Short name T1265
Test name
Test status
Simulation time 43917823 ps
CPU time 0.56 seconds
Started Jul 09 04:28:15 PM PDT 24
Finished Jul 09 04:28:19 PM PDT 24
Peak memory 195084 kb
Host smart-5db16dc0-d127-4258-bf96-a416e6501e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695327914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1695327914
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4274650740
Short name T1242
Test name
Test status
Simulation time 93189803 ps
CPU time 0.72 seconds
Started Jul 09 04:27:56 PM PDT 24
Finished Jul 09 04:27:59 PM PDT 24
Peak memory 197592 kb
Host smart-23aa67d6-2937-4d65-8161-8ade73d686a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274650740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.4274650740
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2683683343
Short name T1198
Test name
Test status
Simulation time 44162636 ps
CPU time 1.1 seconds
Started Jul 09 04:28:10 PM PDT 24
Finished Jul 09 04:28:13 PM PDT 24
Peak memory 200624 kb
Host smart-5e5fa8ea-3bd7-4138-ae2d-000cfe97b0fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683683343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2683683343
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1548256011
Short name T1285
Test name
Test status
Simulation time 78212491 ps
CPU time 1.17 seconds
Started Jul 09 04:28:08 PM PDT 24
Finished Jul 09 04:28:10 PM PDT 24
Peak memory 199920 kb
Host smart-ddc79aca-20e2-4483-a050-3d0e88297b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548256011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1548256011
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3918876113
Short name T1239
Test name
Test status
Simulation time 33329367 ps
CPU time 0.84 seconds
Started Jul 09 04:28:04 PM PDT 24
Finished Jul 09 04:28:05 PM PDT 24
Peak memory 200392 kb
Host smart-89bf4e87-71cf-44f5-a340-085e78c23d30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918876113 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3918876113
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1111357960
Short name T82
Test name
Test status
Simulation time 15225240 ps
CPU time 0.61 seconds
Started Jul 09 04:28:03 PM PDT 24
Finished Jul 09 04:28:04 PM PDT 24
Peak memory 195988 kb
Host smart-a67f5215-c142-45dd-bc4a-856019b93d26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111357960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1111357960
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.375713263
Short name T1199
Test name
Test status
Simulation time 16199679 ps
CPU time 0.55 seconds
Started Jul 09 04:28:11 PM PDT 24
Finished Jul 09 04:28:14 PM PDT 24
Peak memory 195100 kb
Host smart-09d81744-38e3-4af4-8b39-19f8da1a814c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375713263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.375713263
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2487705759
Short name T85
Test name
Test status
Simulation time 99095687 ps
CPU time 0.71 seconds
Started Jul 09 04:28:09 PM PDT 24
Finished Jul 09 04:28:11 PM PDT 24
Peak memory 196592 kb
Host smart-e1496204-347a-470f-a5e1-3460e49fe093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487705759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2487705759
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.430373301
Short name T1236
Test name
Test status
Simulation time 40171946 ps
CPU time 1.8 seconds
Started Jul 09 04:28:24 PM PDT 24
Finished Jul 09 04:28:29 PM PDT 24
Peak memory 200672 kb
Host smart-a57f6b27-aa11-483c-86e9-90ee6ea32fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430373301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.430373301
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3832638878
Short name T1209
Test name
Test status
Simulation time 196915685 ps
CPU time 0.71 seconds
Started Jul 09 04:28:16 PM PDT 24
Finished Jul 09 04:28:21 PM PDT 24
Peak memory 199564 kb
Host smart-ee7a5f4e-ee53-4be1-8671-92b5ccfd430f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832638878 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3832638878
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3716761777
Short name T1301
Test name
Test status
Simulation time 18654922 ps
CPU time 0.56 seconds
Started Jul 09 04:28:19 PM PDT 24
Finished Jul 09 04:28:22 PM PDT 24
Peak memory 194900 kb
Host smart-59e53027-e304-4376-a84b-41348b3d3c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716761777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3716761777
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1641809189
Short name T1250
Test name
Test status
Simulation time 16513727 ps
CPU time 0.7 seconds
Started Jul 09 04:28:19 PM PDT 24
Finished Jul 09 04:28:22 PM PDT 24
Peak memory 197604 kb
Host smart-3b9b6f78-f50a-4482-a03e-9affa07cd256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641809189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1641809189
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2496549237
Short name T1252
Test name
Test status
Simulation time 535444810 ps
CPU time 2.4 seconds
Started Jul 09 04:28:16 PM PDT 24
Finished Jul 09 04:28:22 PM PDT 24
Peak memory 200664 kb
Host smart-30ff6a17-e262-47e3-81cb-2a8450604bf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496549237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2496549237
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2744395050
Short name T91
Test name
Test status
Simulation time 180246185 ps
CPU time 0.92 seconds
Started Jul 09 04:28:29 PM PDT 24
Finished Jul 09 04:28:34 PM PDT 24
Peak memory 199688 kb
Host smart-33d6c7a6-c766-4d27-8833-a548452aaf10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744395050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2744395050
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2442438091
Short name T1269
Test name
Test status
Simulation time 104693227 ps
CPU time 0.72 seconds
Started Jul 09 04:28:07 PM PDT 24
Finished Jul 09 04:28:09 PM PDT 24
Peak memory 199340 kb
Host smart-f9de70e2-239c-4f89-bc68-9e0d9ba57659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442438091 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2442438091
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3447130713
Short name T72
Test name
Test status
Simulation time 14138315 ps
CPU time 0.56 seconds
Started Jul 09 04:28:28 PM PDT 24
Finished Jul 09 04:28:32 PM PDT 24
Peak memory 196092 kb
Host smart-50fb441f-c9bc-44ab-a85f-70321f3debca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447130713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3447130713
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.220050274
Short name T1292
Test name
Test status
Simulation time 34813638 ps
CPU time 0.55 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:17 PM PDT 24
Peak memory 194924 kb
Host smart-f907eafe-7615-4d63-bbf0-cd05831f3570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220050274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.220050274
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2954231242
Short name T83
Test name
Test status
Simulation time 53115025 ps
CPU time 0.73 seconds
Started Jul 09 04:28:19 PM PDT 24
Finished Jul 09 04:28:22 PM PDT 24
Peak memory 197532 kb
Host smart-e97fb437-7197-41c6-9092-475b26c00c5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954231242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2954231242
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4132537152
Short name T1275
Test name
Test status
Simulation time 447531259 ps
CPU time 1.97 seconds
Started Jul 09 04:28:10 PM PDT 24
Finished Jul 09 04:28:14 PM PDT 24
Peak memory 201036 kb
Host smart-68add309-8248-48cb-a65e-035653862d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132537152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4132537152
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3890769106
Short name T1286
Test name
Test status
Simulation time 72308108 ps
CPU time 1.07 seconds
Started Jul 09 04:28:08 PM PDT 24
Finished Jul 09 04:28:11 PM PDT 24
Peak memory 200688 kb
Host smart-1c196295-fd24-40b9-80f4-51ad5b0dea5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890769106 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3890769106
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1426638736
Short name T1264
Test name
Test status
Simulation time 47196098 ps
CPU time 0.64 seconds
Started Jul 09 04:28:08 PM PDT 24
Finished Jul 09 04:28:10 PM PDT 24
Peak memory 196052 kb
Host smart-de5d7f4f-80d0-4f2f-b754-6c101901cc00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426638736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1426638736
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2353842770
Short name T1268
Test name
Test status
Simulation time 16167119 ps
CPU time 0.59 seconds
Started Jul 09 04:28:08 PM PDT 24
Finished Jul 09 04:28:10 PM PDT 24
Peak memory 195036 kb
Host smart-e28251fa-1cc9-4716-930e-9075c4420c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353842770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2353842770
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.497484642
Short name T80
Test name
Test status
Simulation time 18596379 ps
CPU time 0.68 seconds
Started Jul 09 04:28:15 PM PDT 24
Finished Jul 09 04:28:19 PM PDT 24
Peak memory 197612 kb
Host smart-ff849d8c-336a-4185-ab17-d81a95b5e331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497484642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.497484642
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3774603249
Short name T1230
Test name
Test status
Simulation time 414929010 ps
CPU time 1.92 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:17 PM PDT 24
Peak memory 200648 kb
Host smart-f39bc9ad-4b05-4df2-a334-75c2a783f336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774603249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3774603249
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.453652804
Short name T1255
Test name
Test status
Simulation time 42708091 ps
CPU time 0.89 seconds
Started Jul 09 04:29:02 PM PDT 24
Finished Jul 09 04:29:14 PM PDT 24
Peak memory 200396 kb
Host smart-ed16e37b-3f7c-4e7b-bd87-a202c6421f2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453652804 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.453652804
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2629658413
Short name T1192
Test name
Test status
Simulation time 43785798 ps
CPU time 0.58 seconds
Started Jul 09 04:28:15 PM PDT 24
Finished Jul 09 04:28:19 PM PDT 24
Peak memory 196396 kb
Host smart-b800a2a4-262c-4c4b-b825-9298e84a6b2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629658413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2629658413
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3375517748
Short name T1201
Test name
Test status
Simulation time 16415490 ps
CPU time 0.54 seconds
Started Jul 09 04:28:13 PM PDT 24
Finished Jul 09 04:28:19 PM PDT 24
Peak memory 194800 kb
Host smart-f8cd84a2-d1bb-4a94-9dc9-b066e0dfdcaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375517748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3375517748
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1568682163
Short name T1221
Test name
Test status
Simulation time 79573699 ps
CPU time 0.62 seconds
Started Jul 09 04:28:31 PM PDT 24
Finished Jul 09 04:28:36 PM PDT 24
Peak memory 195152 kb
Host smart-eb9cada2-c030-4f20-9e29-bb42dadb5e36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568682163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1568682163
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1911120103
Short name T1276
Test name
Test status
Simulation time 189221878 ps
CPU time 1.09 seconds
Started Jul 09 04:28:07 PM PDT 24
Finished Jul 09 04:28:09 PM PDT 24
Peak memory 200644 kb
Host smart-54b9c169-04f4-4896-b26f-00bccf65b891
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911120103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1911120103
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4088416509
Short name T129
Test name
Test status
Simulation time 60149496 ps
CPU time 0.89 seconds
Started Jul 09 04:28:26 PM PDT 24
Finished Jul 09 04:28:30 PM PDT 24
Peak memory 199520 kb
Host smart-1087de16-e34a-4fb2-842b-282a472e0f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088416509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4088416509
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.806306172
Short name T1224
Test name
Test status
Simulation time 30696743 ps
CPU time 0.87 seconds
Started Jul 09 04:28:15 PM PDT 24
Finished Jul 09 04:28:19 PM PDT 24
Peak memory 200464 kb
Host smart-a6c55f1b-ba58-4461-a451-02339e23df52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806306172 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.806306172
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3053428360
Short name T73
Test name
Test status
Simulation time 43993015 ps
CPU time 0.6 seconds
Started Jul 09 04:28:41 PM PDT 24
Finished Jul 09 04:29:00 PM PDT 24
Peak memory 196232 kb
Host smart-15a787be-8577-4a0d-8525-89b2875b45eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053428360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3053428360
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4226342807
Short name T1263
Test name
Test status
Simulation time 53046352 ps
CPU time 0.53 seconds
Started Jul 09 04:28:11 PM PDT 24
Finished Jul 09 04:28:19 PM PDT 24
Peak memory 195036 kb
Host smart-78b9a5cf-a625-49ea-81c8-4f5abb0aa649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226342807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4226342807
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3105758888
Short name T1219
Test name
Test status
Simulation time 16036592 ps
CPU time 0.62 seconds
Started Jul 09 04:28:16 PM PDT 24
Finished Jul 09 04:28:20 PM PDT 24
Peak memory 196032 kb
Host smart-abca9051-3617-45b9-ad2a-70864987b689
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105758888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3105758888
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.4143618178
Short name T1208
Test name
Test status
Simulation time 234893945 ps
CPU time 1.18 seconds
Started Jul 09 04:28:27 PM PDT 24
Finished Jul 09 04:28:31 PM PDT 24
Peak memory 200668 kb
Host smart-ff8490d6-848b-4f19-9805-b94ab06dc7d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143618178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4143618178
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3800284593
Short name T97
Test name
Test status
Simulation time 82920298 ps
CPU time 0.89 seconds
Started Jul 09 04:28:13 PM PDT 24
Finished Jul 09 04:28:18 PM PDT 24
Peak memory 199424 kb
Host smart-ea23eb2a-44ab-4665-a2fa-46e8e1e0f6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800284593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3800284593
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.378748542
Short name T1193
Test name
Test status
Simulation time 128800708 ps
CPU time 0.72 seconds
Started Jul 09 04:28:11 PM PDT 24
Finished Jul 09 04:28:17 PM PDT 24
Peak memory 199592 kb
Host smart-3d581161-f420-42ef-9a0d-af2f4d153c44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378748542 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.378748542
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.337586248
Short name T87
Test name
Test status
Simulation time 21944370 ps
CPU time 0.63 seconds
Started Jul 09 04:28:06 PM PDT 24
Finished Jul 09 04:28:08 PM PDT 24
Peak memory 196012 kb
Host smart-e2108979-c458-4fa8-9501-d6144a7a0593
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337586248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.337586248
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1948422689
Short name T1247
Test name
Test status
Simulation time 11646345 ps
CPU time 0.56 seconds
Started Jul 09 04:29:00 PM PDT 24
Finished Jul 09 04:29:13 PM PDT 24
Peak memory 194984 kb
Host smart-be7e213e-4536-4b5c-a5d0-0f96ded18077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948422689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1948422689
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2853798203
Short name T1260
Test name
Test status
Simulation time 23389960 ps
CPU time 0.63 seconds
Started Jul 09 04:28:54 PM PDT 24
Finished Jul 09 04:29:08 PM PDT 24
Peak memory 196136 kb
Host smart-d022b782-2123-402b-a06d-9ad69b8e1e08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853798203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2853798203
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.581425756
Short name T1217
Test name
Test status
Simulation time 189018000 ps
CPU time 1.39 seconds
Started Jul 09 04:28:19 PM PDT 24
Finished Jul 09 04:28:24 PM PDT 24
Peak memory 200632 kb
Host smart-c3e4eda3-5544-4984-8141-46019700f7e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581425756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.581425756
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3888078048
Short name T99
Test name
Test status
Simulation time 76744372 ps
CPU time 0.9 seconds
Started Jul 09 04:28:08 PM PDT 24
Finished Jul 09 04:28:10 PM PDT 24
Peak memory 199420 kb
Host smart-ca530532-43ad-4fd1-a2e2-c2130b337ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888078048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3888078048
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2775394315
Short name T1195
Test name
Test status
Simulation time 59724054 ps
CPU time 0.66 seconds
Started Jul 09 04:22:45 PM PDT 24
Finished Jul 09 04:22:46 PM PDT 24
Peak memory 195700 kb
Host smart-56045bd8-27ea-4e6a-ad98-9ca5aacba947
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775394315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2775394315
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2491448875
Short name T1303
Test name
Test status
Simulation time 137718084 ps
CPU time 1.56 seconds
Started Jul 09 04:26:44 PM PDT 24
Finished Jul 09 04:26:48 PM PDT 24
Peak memory 197032 kb
Host smart-de1f3162-c610-4dee-a889-cc39f6c47d0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491448875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2491448875
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1450651842
Short name T77
Test name
Test status
Simulation time 16443374 ps
CPU time 0.59 seconds
Started Jul 09 04:27:07 PM PDT 24
Finished Jul 09 04:27:14 PM PDT 24
Peak memory 195988 kb
Host smart-82c24bed-9ba3-4667-8036-a7c49dc2e79f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450651842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1450651842
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3555072649
Short name T1293
Test name
Test status
Simulation time 49595335 ps
CPU time 0.67 seconds
Started Jul 09 04:26:50 PM PDT 24
Finished Jul 09 04:26:52 PM PDT 24
Peak memory 197184 kb
Host smart-d4274ac1-dc90-4b61-aec3-a5237f0afc33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555072649 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3555072649
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2418557981
Short name T1273
Test name
Test status
Simulation time 33034658 ps
CPU time 0.58 seconds
Started Jul 09 04:27:07 PM PDT 24
Finished Jul 09 04:27:14 PM PDT 24
Peak memory 195992 kb
Host smart-8deba831-a235-49bc-92c8-1dfe2fd22bef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418557981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2418557981
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.422835414
Short name T1183
Test name
Test status
Simulation time 18567008 ps
CPU time 0.57 seconds
Started Jul 09 04:24:15 PM PDT 24
Finished Jul 09 04:24:17 PM PDT 24
Peak memory 195004 kb
Host smart-4ddd45e6-c3a1-4402-a48d-c531d311e076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422835414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.422835414
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1717977177
Short name T86
Test name
Test status
Simulation time 20427530 ps
CPU time 0.74 seconds
Started Jul 09 04:23:18 PM PDT 24
Finished Jul 09 04:23:19 PM PDT 24
Peak memory 196472 kb
Host smart-f526e102-579e-47ec-aa4c-b098b440500c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717977177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1717977177
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.741831221
Short name T1246
Test name
Test status
Simulation time 56755073 ps
CPU time 1.14 seconds
Started Jul 09 04:27:07 PM PDT 24
Finished Jul 09 04:27:15 PM PDT 24
Peak memory 199704 kb
Host smart-c3046c5d-1572-4051-a890-94534f5ceef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741831221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.741831221
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3320498256
Short name T96
Test name
Test status
Simulation time 165543233 ps
CPU time 0.89 seconds
Started Jul 09 04:26:44 PM PDT 24
Finished Jul 09 04:26:48 PM PDT 24
Peak memory 198960 kb
Host smart-3e896d7d-bf9b-48ff-b89a-164c6653a8ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320498256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3320498256
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2163055070
Short name T1196
Test name
Test status
Simulation time 22573414 ps
CPU time 0.56 seconds
Started Jul 09 04:28:10 PM PDT 24
Finished Jul 09 04:28:12 PM PDT 24
Peak memory 194920 kb
Host smart-86978d87-b4f6-48d4-861f-68d348f016c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163055070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2163055070
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.376469012
Short name T1261
Test name
Test status
Simulation time 107456408 ps
CPU time 0.56 seconds
Started Jul 09 04:28:51 PM PDT 24
Finished Jul 09 04:29:06 PM PDT 24
Peak memory 195008 kb
Host smart-1185f10d-d4d9-43af-bf83-54c0769622c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376469012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.376469012
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1435490783
Short name T1309
Test name
Test status
Simulation time 128416402 ps
CPU time 0.56 seconds
Started Jul 09 04:28:08 PM PDT 24
Finished Jul 09 04:28:10 PM PDT 24
Peak memory 195020 kb
Host smart-5da29a90-2b93-46c2-b380-9dc796ff36d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435490783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1435490783
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3218786422
Short name T1259
Test name
Test status
Simulation time 45186821 ps
CPU time 0.53 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:15 PM PDT 24
Peak memory 195000 kb
Host smart-663bd1ff-1e84-4f52-9cd9-c184f4371264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218786422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3218786422
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2201929656
Short name T1186
Test name
Test status
Simulation time 16542174 ps
CPU time 0.56 seconds
Started Jul 09 04:28:55 PM PDT 24
Finished Jul 09 04:29:13 PM PDT 24
Peak memory 194964 kb
Host smart-f3a23409-98f8-430c-9311-0bbd770b6a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201929656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2201929656
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1993661690
Short name T1190
Test name
Test status
Simulation time 13696263 ps
CPU time 0.58 seconds
Started Jul 09 04:28:58 PM PDT 24
Finished Jul 09 04:29:10 PM PDT 24
Peak memory 194968 kb
Host smart-1ab952f8-ed75-4377-99ca-0ae54a123522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993661690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1993661690
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3233892082
Short name T1225
Test name
Test status
Simulation time 14859200 ps
CPU time 0.57 seconds
Started Jul 09 04:28:16 PM PDT 24
Finished Jul 09 04:28:19 PM PDT 24
Peak memory 194868 kb
Host smart-11f4f39e-dba7-40f1-89e3-d70a32191c34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233892082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3233892082
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3119176652
Short name T1298
Test name
Test status
Simulation time 60409394 ps
CPU time 0.58 seconds
Started Jul 09 04:28:16 PM PDT 24
Finished Jul 09 04:28:20 PM PDT 24
Peak memory 195012 kb
Host smart-315f4ed7-a23c-493d-b44c-65b7e465c0aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119176652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3119176652
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1982438319
Short name T1213
Test name
Test status
Simulation time 27270852 ps
CPU time 0.59 seconds
Started Jul 09 04:28:11 PM PDT 24
Finished Jul 09 04:28:14 PM PDT 24
Peak memory 195028 kb
Host smart-fd85716d-2431-4406-b9f2-566a92f32953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982438319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1982438319
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.752406623
Short name T1287
Test name
Test status
Simulation time 67947101 ps
CPU time 0.54 seconds
Started Jul 09 04:28:27 PM PDT 24
Finished Jul 09 04:28:30 PM PDT 24
Peak memory 195016 kb
Host smart-1281697c-b94c-4bc6-9b9f-ac6e85a4514e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752406623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.752406623
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2516206414
Short name T1251
Test name
Test status
Simulation time 311974897 ps
CPU time 0.79 seconds
Started Jul 09 04:21:40 PM PDT 24
Finished Jul 09 04:21:41 PM PDT 24
Peak memory 196928 kb
Host smart-b49290ed-f090-4dce-9f41-e7de7c832d6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516206414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2516206414
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3310203719
Short name T1185
Test name
Test status
Simulation time 144851135 ps
CPU time 1.32 seconds
Started Jul 09 04:27:20 PM PDT 24
Finished Jul 09 04:27:25 PM PDT 24
Peak memory 198408 kb
Host smart-ab2abf6d-af87-41b9-9cf1-61d799618d44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310203719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3310203719
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2551662999
Short name T1258
Test name
Test status
Simulation time 11917723 ps
CPU time 0.54 seconds
Started Jul 09 04:26:50 PM PDT 24
Finished Jul 09 04:26:52 PM PDT 24
Peak memory 195588 kb
Host smart-477dc105-d0a4-45f2-a3a6-3a689c8ad0cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551662999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2551662999
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3524030809
Short name T1203
Test name
Test status
Simulation time 17274921 ps
CPU time 0.81 seconds
Started Jul 09 04:21:44 PM PDT 24
Finished Jul 09 04:21:45 PM PDT 24
Peak memory 200400 kb
Host smart-b1eb8a8d-73d8-46c6-8b63-430f03b5a36d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524030809 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3524030809
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2735076238
Short name T78
Test name
Test status
Simulation time 55213462 ps
CPU time 0.6 seconds
Started Jul 09 04:27:01 PM PDT 24
Finished Jul 09 04:27:07 PM PDT 24
Peak memory 196288 kb
Host smart-04a3f8ba-459f-4295-9917-892e39eb9545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735076238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2735076238
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2885518587
Short name T1211
Test name
Test status
Simulation time 57580223 ps
CPU time 0.63 seconds
Started Jul 09 04:23:08 PM PDT 24
Finished Jul 09 04:23:09 PM PDT 24
Peak memory 195000 kb
Host smart-dc6f03dd-9732-4374-8d04-e1d4640d7216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885518587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2885518587
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2659742112
Short name T1243
Test name
Test status
Simulation time 33507938 ps
CPU time 0.73 seconds
Started Jul 09 04:21:42 PM PDT 24
Finished Jul 09 04:21:44 PM PDT 24
Peak memory 197244 kb
Host smart-e677f494-4703-40f0-86df-7090815cddc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659742112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2659742112
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.290777174
Short name T1304
Test name
Test status
Simulation time 446508009 ps
CPU time 2.1 seconds
Started Jul 09 04:27:07 PM PDT 24
Finished Jul 09 04:27:16 PM PDT 24
Peak memory 200628 kb
Host smart-7157930b-ccea-42d2-8350-335ad00cea54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290777174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.290777174
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1615379082
Short name T1256
Test name
Test status
Simulation time 54662654 ps
CPU time 1.05 seconds
Started Jul 09 04:26:59 PM PDT 24
Finished Jul 09 04:27:06 PM PDT 24
Peak memory 199792 kb
Host smart-bb863ff0-4f7f-42fd-ae37-d9be9cdd001f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615379082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1615379082
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.124161811
Short name T1271
Test name
Test status
Simulation time 24218882 ps
CPU time 0.57 seconds
Started Jul 09 04:28:20 PM PDT 24
Finished Jul 09 04:28:23 PM PDT 24
Peak memory 195000 kb
Host smart-786b4021-9e97-43b5-b917-db91139eb8d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124161811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.124161811
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3927946695
Short name T1215
Test name
Test status
Simulation time 20776205 ps
CPU time 0.54 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:15 PM PDT 24
Peak memory 194996 kb
Host smart-23d87603-41d5-4209-b6f3-32fcd2cc1ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927946695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3927946695
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2842802701
Short name T1314
Test name
Test status
Simulation time 41662707 ps
CPU time 0.54 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:15 PM PDT 24
Peak memory 195000 kb
Host smart-735bed9d-6f2d-4017-ac39-4c4c4dbee75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842802701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2842802701
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.803020165
Short name T1241
Test name
Test status
Simulation time 36623385 ps
CPU time 0.53 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:15 PM PDT 24
Peak memory 194964 kb
Host smart-679ecf39-b2ed-4550-8816-6a03601d06ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803020165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.803020165
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4238268497
Short name T1300
Test name
Test status
Simulation time 42689993 ps
CPU time 0.53 seconds
Started Jul 09 04:28:24 PM PDT 24
Finished Jul 09 04:28:28 PM PDT 24
Peak memory 194936 kb
Host smart-6fa1f173-17af-4fab-a49c-e00288d32736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238268497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4238268497
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.297775293
Short name T1205
Test name
Test status
Simulation time 27555351 ps
CPU time 0.53 seconds
Started Jul 09 04:28:20 PM PDT 24
Finished Jul 09 04:28:23 PM PDT 24
Peak memory 195052 kb
Host smart-aeace48f-9b15-4fab-8732-bf24fc7b73bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297775293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.297775293
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2003992653
Short name T1257
Test name
Test status
Simulation time 25830264 ps
CPU time 0.54 seconds
Started Jul 09 04:28:09 PM PDT 24
Finished Jul 09 04:28:11 PM PDT 24
Peak memory 194968 kb
Host smart-dfe53594-5077-436b-bf24-d27b6b74d2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003992653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2003992653
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1855883772
Short name T1310
Test name
Test status
Simulation time 25679634 ps
CPU time 0.54 seconds
Started Jul 09 04:28:30 PM PDT 24
Finished Jul 09 04:28:44 PM PDT 24
Peak memory 195000 kb
Host smart-faeb5ecb-1bc3-445a-a978-f7549cbaaa78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855883772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1855883772
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2288196522
Short name T1189
Test name
Test status
Simulation time 12196214 ps
CPU time 0.56 seconds
Started Jul 09 04:28:16 PM PDT 24
Finished Jul 09 04:28:20 PM PDT 24
Peak memory 194804 kb
Host smart-2e079ed7-9ed0-4be8-b6f0-9d48cf1061cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288196522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2288196522
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.378320925
Short name T1220
Test name
Test status
Simulation time 45335406 ps
CPU time 0.56 seconds
Started Jul 09 04:28:10 PM PDT 24
Finished Jul 09 04:28:13 PM PDT 24
Peak memory 194988 kb
Host smart-6f297165-3a99-4c5a-9f39-ed0072436a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378320925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.378320925
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3980609483
Short name T74
Test name
Test status
Simulation time 74784831 ps
CPU time 0.64 seconds
Started Jul 09 04:27:22 PM PDT 24
Finished Jul 09 04:27:27 PM PDT 24
Peak memory 196032 kb
Host smart-bf150f02-da72-47f4-bf1f-7e512ec84022
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980609483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3980609483
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2291913466
Short name T1226
Test name
Test status
Simulation time 117408956 ps
CPU time 1.52 seconds
Started Jul 09 04:26:40 PM PDT 24
Finished Jul 09 04:26:45 PM PDT 24
Peak memory 196712 kb
Host smart-b0e9c42a-ea78-439d-b921-36c7cdc1f77d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291913466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2291913466
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2109304084
Short name T71
Test name
Test status
Simulation time 19031663 ps
CPU time 0.58 seconds
Started Jul 09 04:27:22 PM PDT 24
Finished Jul 09 04:27:27 PM PDT 24
Peak memory 196032 kb
Host smart-b5abb725-81c1-4773-b858-8cfed84821d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109304084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2109304084
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.67494826
Short name T1187
Test name
Test status
Simulation time 79106661 ps
CPU time 1.1 seconds
Started Jul 09 04:24:49 PM PDT 24
Finished Jul 09 04:24:51 PM PDT 24
Peak memory 200560 kb
Host smart-eaf3e3e8-5113-4679-b398-2d116e3c46e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67494826 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.67494826
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2506020823
Short name T1294
Test name
Test status
Simulation time 25763495 ps
CPU time 0.61 seconds
Started Jul 09 04:24:36 PM PDT 24
Finished Jul 09 04:24:37 PM PDT 24
Peak memory 196052 kb
Host smart-d4c3cae2-abc9-401b-82e4-8463bbf8fb64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506020823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2506020823
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.752268961
Short name T1290
Test name
Test status
Simulation time 42083660 ps
CPU time 0.56 seconds
Started Jul 09 04:25:29 PM PDT 24
Finished Jul 09 04:25:30 PM PDT 24
Peak memory 194944 kb
Host smart-6d613792-ee81-4042-81ba-f36dbe2b0857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752268961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.752268961
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2420870539
Short name T1289
Test name
Test status
Simulation time 15745734 ps
CPU time 0.65 seconds
Started Jul 09 04:27:05 PM PDT 24
Finished Jul 09 04:27:11 PM PDT 24
Peak memory 194184 kb
Host smart-61e78565-1b2f-4c54-9c4d-883fb9d76939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420870539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2420870539
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1433717845
Short name T1200
Test name
Test status
Simulation time 18641332 ps
CPU time 1.07 seconds
Started Jul 09 04:22:41 PM PDT 24
Finished Jul 09 04:22:43 PM PDT 24
Peak memory 200776 kb
Host smart-72132e07-5c9c-478f-b4ba-325675eb5c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433717845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1433717845
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2011334564
Short name T1245
Test name
Test status
Simulation time 615987670 ps
CPU time 1.25 seconds
Started Jul 09 04:27:20 PM PDT 24
Finished Jul 09 04:27:25 PM PDT 24
Peak memory 199904 kb
Host smart-34ee624c-93c6-4ddc-a0e3-1c27219dabde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011334564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2011334564
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1274896035
Short name T1288
Test name
Test status
Simulation time 49850916 ps
CPU time 0.57 seconds
Started Jul 09 04:29:03 PM PDT 24
Finished Jul 09 04:29:15 PM PDT 24
Peak memory 195032 kb
Host smart-863f98c4-c4e1-4880-a433-294797f5be0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274896035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1274896035
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2448780991
Short name T1206
Test name
Test status
Simulation time 16416647 ps
CPU time 0.57 seconds
Started Jul 09 04:28:13 PM PDT 24
Finished Jul 09 04:28:16 PM PDT 24
Peak memory 194988 kb
Host smart-bc97ebbc-7dc2-43b2-bd74-8a3b073d9ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448780991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2448780991
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1446882979
Short name T1237
Test name
Test status
Simulation time 27162323 ps
CPU time 0.56 seconds
Started Jul 09 04:28:27 PM PDT 24
Finished Jul 09 04:28:30 PM PDT 24
Peak memory 195076 kb
Host smart-ff116b7c-87f0-4206-85d4-8e3bee8013c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446882979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1446882979
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3862226937
Short name T1278
Test name
Test status
Simulation time 39207021 ps
CPU time 0.56 seconds
Started Jul 09 04:28:13 PM PDT 24
Finished Jul 09 04:28:18 PM PDT 24
Peak memory 194956 kb
Host smart-9c345160-f293-46d5-8efa-a6476ec9b114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862226937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3862226937
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.668382767
Short name T1281
Test name
Test status
Simulation time 53409366 ps
CPU time 0.55 seconds
Started Jul 09 04:28:18 PM PDT 24
Finished Jul 09 04:28:21 PM PDT 24
Peak memory 195008 kb
Host smart-96fd0cfb-d412-4094-8528-2987e8623edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668382767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.668382767
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3513046145
Short name T1216
Test name
Test status
Simulation time 15696534 ps
CPU time 0.57 seconds
Started Jul 09 04:28:18 PM PDT 24
Finished Jul 09 04:28:22 PM PDT 24
Peak memory 195012 kb
Host smart-95a8e377-7cec-4949-9855-8e37a7eb7533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513046145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3513046145
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.4051143561
Short name T1188
Test name
Test status
Simulation time 65332857 ps
CPU time 0.55 seconds
Started Jul 09 04:28:31 PM PDT 24
Finished Jul 09 04:28:36 PM PDT 24
Peak memory 194956 kb
Host smart-a3e88940-6f79-4745-b2d9-de0a1b40c727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051143561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4051143561
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.129584250
Short name T1218
Test name
Test status
Simulation time 67579260 ps
CPU time 0.56 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:15 PM PDT 24
Peak memory 195016 kb
Host smart-ebaf420d-3d4a-4dc7-adfa-0c6ad74f59fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129584250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.129584250
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.4004702814
Short name T1212
Test name
Test status
Simulation time 21397677 ps
CPU time 0.54 seconds
Started Jul 09 04:29:03 PM PDT 24
Finished Jul 09 04:29:15 PM PDT 24
Peak memory 194900 kb
Host smart-0e2fd97f-4224-453d-9538-3c6d274182dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004702814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4004702814
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2115485150
Short name T1307
Test name
Test status
Simulation time 13762479 ps
CPU time 0.63 seconds
Started Jul 09 04:28:12 PM PDT 24
Finished Jul 09 04:28:20 PM PDT 24
Peak memory 195368 kb
Host smart-a31ab6c2-451d-4c85-90f7-7f075718fa14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115485150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2115485150
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1598399277
Short name T1244
Test name
Test status
Simulation time 26928005 ps
CPU time 0.79 seconds
Started Jul 09 04:25:54 PM PDT 24
Finished Jul 09 04:25:56 PM PDT 24
Peak memory 199204 kb
Host smart-56360eb9-32bd-4f55-b48b-647495e43914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598399277 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1598399277
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1629435496
Short name T70
Test name
Test status
Simulation time 15854206 ps
CPU time 0.64 seconds
Started Jul 09 04:25:35 PM PDT 24
Finished Jul 09 04:25:36 PM PDT 24
Peak memory 196232 kb
Host smart-ffdbf29c-4bf8-4d07-803c-b2c41f7f7fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629435496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1629435496
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2960324108
Short name T1229
Test name
Test status
Simulation time 40037523 ps
CPU time 0.57 seconds
Started Jul 09 04:27:09 PM PDT 24
Finished Jul 09 04:27:16 PM PDT 24
Peak memory 194976 kb
Host smart-e4b18a4f-9817-4019-9455-a230f068a1d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960324108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2960324108
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2232942914
Short name T1207
Test name
Test status
Simulation time 27600968 ps
CPU time 0.63 seconds
Started Jul 09 04:27:05 PM PDT 24
Finished Jul 09 04:27:11 PM PDT 24
Peak memory 195384 kb
Host smart-ca0e4aab-d975-46e4-a690-5c9571793573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232942914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2232942914
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1558063274
Short name T1191
Test name
Test status
Simulation time 147761132 ps
CPU time 2.06 seconds
Started Jul 09 04:25:06 PM PDT 24
Finished Jul 09 04:25:09 PM PDT 24
Peak memory 200780 kb
Host smart-6f4741ef-026d-48b2-9062-5c9c14cc2129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558063274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1558063274
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2057264747
Short name T1282
Test name
Test status
Simulation time 231046847 ps
CPU time 0.93 seconds
Started Jul 09 04:24:22 PM PDT 24
Finished Jul 09 04:24:23 PM PDT 24
Peak memory 199564 kb
Host smart-c988e009-5ca2-4f38-883d-bafa2bb643d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057264747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2057264747
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.818999487
Short name T1238
Test name
Test status
Simulation time 62663203 ps
CPU time 0.65 seconds
Started Jul 09 04:24:50 PM PDT 24
Finished Jul 09 04:24:51 PM PDT 24
Peak memory 198420 kb
Host smart-316851db-bc40-42ff-9c9f-7541e5884229
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818999487 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.818999487
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4187394780
Short name T79
Test name
Test status
Simulation time 21086299 ps
CPU time 0.61 seconds
Started Jul 09 04:22:38 PM PDT 24
Finished Jul 09 04:22:39 PM PDT 24
Peak memory 196408 kb
Host smart-4c8b44dd-0f91-4c73-8c0f-e180f3d0917d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187394780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4187394780
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1461320919
Short name T1311
Test name
Test status
Simulation time 15012676 ps
CPU time 0.57 seconds
Started Jul 09 04:26:52 PM PDT 24
Finished Jul 09 04:26:55 PM PDT 24
Peak memory 194936 kb
Host smart-5b543bd4-8e62-49b1-8677-55a9f9879643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461320919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1461320919
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4186929700
Short name T81
Test name
Test status
Simulation time 20377348 ps
CPU time 0.59 seconds
Started Jul 09 04:26:51 PM PDT 24
Finished Jul 09 04:26:53 PM PDT 24
Peak memory 196112 kb
Host smart-ce6b51dd-b45c-4006-9761-815f126334a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186929700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.4186929700
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2830315669
Short name T1227
Test name
Test status
Simulation time 312715614 ps
CPU time 1.74 seconds
Started Jul 09 04:26:39 PM PDT 24
Finished Jul 09 04:26:43 PM PDT 24
Peak memory 200200 kb
Host smart-6a3d7edd-c153-4ae0-954a-4747e3871512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830315669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2830315669
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1699428594
Short name T1306
Test name
Test status
Simulation time 437750119 ps
CPU time 0.99 seconds
Started Jul 09 04:21:53 PM PDT 24
Finished Jul 09 04:21:55 PM PDT 24
Peak memory 199396 kb
Host smart-3644115f-41bf-42aa-9821-c675a868385e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699428594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1699428594
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2436862294
Short name T1223
Test name
Test status
Simulation time 148326198 ps
CPU time 1.26 seconds
Started Jul 09 04:27:21 PM PDT 24
Finished Jul 09 04:27:26 PM PDT 24
Peak memory 200640 kb
Host smart-92b132b1-893e-40c7-be04-79b5f05058a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436862294 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2436862294
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4250550401
Short name T68
Test name
Test status
Simulation time 35287830 ps
CPU time 0.59 seconds
Started Jul 09 04:27:21 PM PDT 24
Finished Jul 09 04:27:25 PM PDT 24
Peak memory 196000 kb
Host smart-10619552-0efc-4033-9e54-aaabac315dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250550401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4250550401
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3434946570
Short name T1277
Test name
Test status
Simulation time 49937634 ps
CPU time 0.59 seconds
Started Jul 09 04:24:44 PM PDT 24
Finished Jul 09 04:24:45 PM PDT 24
Peak memory 194996 kb
Host smart-bbcda52e-6ede-40f0-bdcf-3a96688a96ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434946570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3434946570
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1960058694
Short name T1240
Test name
Test status
Simulation time 57302155 ps
CPU time 0.79 seconds
Started Jul 09 04:25:36 PM PDT 24
Finished Jul 09 04:25:38 PM PDT 24
Peak memory 197520 kb
Host smart-29d871b7-1177-4c03-b9b0-f6d79373c5f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960058694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1960058694
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2120542536
Short name T1249
Test name
Test status
Simulation time 52729399 ps
CPU time 1.27 seconds
Started Jul 09 04:24:29 PM PDT 24
Finished Jul 09 04:24:30 PM PDT 24
Peak memory 200412 kb
Host smart-1b77a03b-2b3d-44ee-b3b8-812c18254cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120542536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2120542536
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3319647913
Short name T95
Test name
Test status
Simulation time 53362684 ps
CPU time 0.94 seconds
Started Jul 09 04:25:25 PM PDT 24
Finished Jul 09 04:25:26 PM PDT 24
Peak memory 199672 kb
Host smart-1f9944d2-607c-48cb-aba4-ca6db09324bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319647913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3319647913
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2515311240
Short name T1184
Test name
Test status
Simulation time 17541623 ps
CPU time 0.63 seconds
Started Jul 09 04:27:54 PM PDT 24
Finished Jul 09 04:27:56 PM PDT 24
Peak memory 198248 kb
Host smart-3a77426e-7e31-4012-9076-842c5ad9cff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515311240 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2515311240
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3439891545
Short name T69
Test name
Test status
Simulation time 11551170 ps
CPU time 0.58 seconds
Started Jul 09 04:24:42 PM PDT 24
Finished Jul 09 04:24:43 PM PDT 24
Peak memory 196032 kb
Host smart-6bf33e66-cfe1-4fc2-887a-c1319b9bb941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439891545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3439891545
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.984475982
Short name T1297
Test name
Test status
Simulation time 15266568 ps
CPU time 0.54 seconds
Started Jul 09 04:25:27 PM PDT 24
Finished Jul 09 04:25:28 PM PDT 24
Peak memory 195028 kb
Host smart-79ea892d-fccd-4f35-8e62-892ed5e8f770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984475982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.984475982
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2299182866
Short name T1313
Test name
Test status
Simulation time 18203978 ps
CPU time 0.65 seconds
Started Jul 09 04:23:38 PM PDT 24
Finished Jul 09 04:23:39 PM PDT 24
Peak memory 195328 kb
Host smart-9bdabc7a-c9bc-473d-950c-9020a439b181
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299182866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2299182866
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2113531238
Short name T1302
Test name
Test status
Simulation time 249991454 ps
CPU time 2.76 seconds
Started Jul 09 04:24:01 PM PDT 24
Finished Jul 09 04:24:04 PM PDT 24
Peak memory 200636 kb
Host smart-0782b9dd-c182-4d24-84d9-1666326f52c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113531238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2113531238
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3248929209
Short name T90
Test name
Test status
Simulation time 275428680 ps
CPU time 1.02 seconds
Started Jul 09 04:23:17 PM PDT 24
Finished Jul 09 04:23:18 PM PDT 24
Peak memory 200084 kb
Host smart-3b9d7d08-ba97-46f9-9379-41eb9fa671cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248929209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3248929209
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.264881058
Short name T1295
Test name
Test status
Simulation time 108664786 ps
CPU time 0.84 seconds
Started Jul 09 04:26:54 PM PDT 24
Finished Jul 09 04:27:00 PM PDT 24
Peak memory 200140 kb
Host smart-4869606f-c47a-4b7f-83b6-dc6dead79688
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264881058 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.264881058
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2869308137
Short name T1299
Test name
Test status
Simulation time 31352330 ps
CPU time 0.6 seconds
Started Jul 09 04:28:02 PM PDT 24
Finished Jul 09 04:28:03 PM PDT 24
Peak memory 196288 kb
Host smart-759a0e6a-b6b2-4fb2-b757-12b5c2f262f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869308137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2869308137
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3814397596
Short name T1305
Test name
Test status
Simulation time 16271911 ps
CPU time 0.59 seconds
Started Jul 09 04:25:20 PM PDT 24
Finished Jul 09 04:25:21 PM PDT 24
Peak memory 195012 kb
Host smart-f031b03c-0557-4a70-9597-74b7e5c2192e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814397596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3814397596
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3262452267
Short name T1214
Test name
Test status
Simulation time 79258329 ps
CPU time 0.62 seconds
Started Jul 09 04:25:15 PM PDT 24
Finished Jul 09 04:25:16 PM PDT 24
Peak memory 196092 kb
Host smart-d9993367-5665-4eda-85f7-50e2805e78cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262452267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3262452267
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.131164224
Short name T1266
Test name
Test status
Simulation time 58904386 ps
CPU time 1.14 seconds
Started Jul 09 04:23:38 PM PDT 24
Finished Jul 09 04:23:39 PM PDT 24
Peak memory 200680 kb
Host smart-9548332a-1cde-4e1b-a4fc-5ee8c1e9cccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131164224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.131164224
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.849515473
Short name T1312
Test name
Test status
Simulation time 85240852 ps
CPU time 1.39 seconds
Started Jul 09 04:21:42 PM PDT 24
Finished Jul 09 04:21:44 PM PDT 24
Peak memory 199892 kb
Host smart-674997d7-6002-4025-b570-e726d5ee1516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849515473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.849515473
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3143456686
Short name T745
Test name
Test status
Simulation time 14135966 ps
CPU time 0.58 seconds
Started Jul 09 04:22:54 PM PDT 24
Finished Jul 09 04:22:55 PM PDT 24
Peak memory 194548 kb
Host smart-da9e7acc-f457-401c-b25e-1e1538e5d40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143456686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3143456686
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2550778377
Short name T748
Test name
Test status
Simulation time 26798093247 ps
CPU time 42.96 seconds
Started Jul 09 04:27:04 PM PDT 24
Finished Jul 09 04:27:53 PM PDT 24
Peak memory 198508 kb
Host smart-8b92a9de-52cd-44e4-98d9-5d6f9a30e422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550778377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2550778377
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.4283790455
Short name T1002
Test name
Test status
Simulation time 50431108558 ps
CPU time 19.14 seconds
Started Jul 09 04:26:55 PM PDT 24
Finished Jul 09 04:27:20 PM PDT 24
Peak memory 198276 kb
Host smart-716265a6-33cc-455a-8341-131d78438704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283790455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4283790455
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3262490108
Short name T1006
Test name
Test status
Simulation time 8776024645 ps
CPU time 15.19 seconds
Started Jul 09 04:27:00 PM PDT 24
Finished Jul 09 04:27:21 PM PDT 24
Peak memory 199772 kb
Host smart-bd7310b6-c76b-4ecb-9916-6e76d613ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262490108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3262490108
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1128396305
Short name T673
Test name
Test status
Simulation time 27485448087 ps
CPU time 18.75 seconds
Started Jul 09 04:23:17 PM PDT 24
Finished Jul 09 04:23:36 PM PDT 24
Peak memory 198192 kb
Host smart-d04335d6-8032-4375-b40a-18369d86304e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128396305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1128396305
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1876560481
Short name T883
Test name
Test status
Simulation time 89912707829 ps
CPU time 646.08 seconds
Started Jul 09 04:22:24 PM PDT 24
Finished Jul 09 04:33:11 PM PDT 24
Peak memory 199764 kb
Host smart-63f653b3-4dec-474a-9334-5b148df80ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876560481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1876560481
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4010218075
Short name T1029
Test name
Test status
Simulation time 11416715586 ps
CPU time 6.85 seconds
Started Jul 09 04:28:15 PM PDT 24
Finished Jul 09 04:28:25 PM PDT 24
Peak memory 199460 kb
Host smart-aa095c1d-db7a-4fd3-a783-5ff5b32d17f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010218075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4010218075
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2102419524
Short name T807
Test name
Test status
Simulation time 24549529663 ps
CPU time 18.77 seconds
Started Jul 09 04:26:43 PM PDT 24
Finished Jul 09 04:27:04 PM PDT 24
Peak memory 198656 kb
Host smart-f1571436-c14f-42dd-9920-6bdaf40a1846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102419524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2102419524
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3609863200
Short name T581
Test name
Test status
Simulation time 24864820865 ps
CPU time 1291.83 seconds
Started Jul 09 04:23:35 PM PDT 24
Finished Jul 09 04:45:08 PM PDT 24
Peak memory 200100 kb
Host smart-45d874db-9548-448e-90cf-6e58c66441c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609863200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3609863200
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2602063166
Short name T968
Test name
Test status
Simulation time 6113073638 ps
CPU time 14.17 seconds
Started Jul 09 04:25:01 PM PDT 24
Finished Jul 09 04:25:15 PM PDT 24
Peak memory 197944 kb
Host smart-00af073c-fa31-45d4-8b5d-cb1364eed88d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602063166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2602063166
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.381757836
Short name T605
Test name
Test status
Simulation time 127146522043 ps
CPU time 15.59 seconds
Started Jul 09 04:27:08 PM PDT 24
Finished Jul 09 04:27:30 PM PDT 24
Peak memory 199532 kb
Host smart-261b8f74-02e2-4034-b2b7-05e814b2abad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381757836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.381757836
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.734525530
Short name T789
Test name
Test status
Simulation time 3860810027 ps
CPU time 3.08 seconds
Started Jul 09 04:26:43 PM PDT 24
Finished Jul 09 04:26:49 PM PDT 24
Peak memory 195468 kb
Host smart-fa1a6943-6708-4910-baef-38bc3b7ef61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734525530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.734525530
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1837156196
Short name T354
Test name
Test status
Simulation time 6058686320 ps
CPU time 11.95 seconds
Started Jul 09 04:27:10 PM PDT 24
Finished Jul 09 04:27:28 PM PDT 24
Peak memory 199520 kb
Host smart-7d37db04-bde6-4683-ad94-86af50261b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837156196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1837156196
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1143718964
Short name T65
Test name
Test status
Simulation time 187600457398 ps
CPU time 446.38 seconds
Started Jul 09 04:28:23 PM PDT 24
Finished Jul 09 04:35:51 PM PDT 24
Peak memory 216264 kb
Host smart-c465054b-b245-4cf9-b9dd-20c568d7afe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143718964 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1143718964
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1873948784
Short name T700
Test name
Test status
Simulation time 1113948522 ps
CPU time 2.74 seconds
Started Jul 09 04:23:55 PM PDT 24
Finished Jul 09 04:23:58 PM PDT 24
Peak memory 198824 kb
Host smart-c7f9fc47-ffe9-4db8-9255-457910c0b0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873948784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1873948784
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.921351228
Short name T658
Test name
Test status
Simulation time 77109404817 ps
CPU time 23.11 seconds
Started Jul 09 04:27:09 PM PDT 24
Finished Jul 09 04:27:39 PM PDT 24
Peak memory 199512 kb
Host smart-334ea925-fc25-49ba-96a1-cad4f031f0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921351228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.921351228
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2662115222
Short name T338
Test name
Test status
Simulation time 33886363 ps
CPU time 0.55 seconds
Started Jul 09 04:30:18 PM PDT 24
Finished Jul 09 04:30:19 PM PDT 24
Peak memory 194540 kb
Host smart-3892efac-c3c6-46bc-914b-711e6096582b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662115222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2662115222
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3755563039
Short name T176
Test name
Test status
Simulation time 37190545636 ps
CPU time 18.97 seconds
Started Jul 09 04:24:31 PM PDT 24
Finished Jul 09 04:24:51 PM PDT 24
Peak memory 199808 kb
Host smart-f3112535-0d9f-4412-afae-00c9e3036040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755563039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3755563039
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.4064217347
Short name T432
Test name
Test status
Simulation time 128251248154 ps
CPU time 113.04 seconds
Started Jul 09 04:27:20 PM PDT 24
Finished Jul 09 04:29:17 PM PDT 24
Peak memory 199800 kb
Host smart-b64e62e0-9c0a-4897-90f5-cc835895cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064217347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.4064217347
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.2901894968
Short name T21
Test name
Test status
Simulation time 51321281760 ps
CPU time 86.98 seconds
Started Jul 09 04:27:12 PM PDT 24
Finished Jul 09 04:28:44 PM PDT 24
Peak memory 199652 kb
Host smart-41b8d80a-aa27-4458-b2ec-eefb1bee17df
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901894968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2901894968
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.952116910
Short name T1162
Test name
Test status
Simulation time 93652162695 ps
CPU time 146.24 seconds
Started Jul 09 04:30:13 PM PDT 24
Finished Jul 09 04:32:41 PM PDT 24
Peak memory 199720 kb
Host smart-ba0f75a0-c5e8-4b81-b7e0-16d38e4cbd3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952116910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.952116910
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2423327807
Short name T1016
Test name
Test status
Simulation time 10706828185 ps
CPU time 10.71 seconds
Started Jul 09 04:26:40 PM PDT 24
Finished Jul 09 04:26:54 PM PDT 24
Peak memory 199084 kb
Host smart-09adb98d-082c-4a19-bf4a-a5520c0ffc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423327807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2423327807
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.312838501
Short name T1019
Test name
Test status
Simulation time 26990316834 ps
CPU time 23.36 seconds
Started Jul 09 04:22:29 PM PDT 24
Finished Jul 09 04:22:53 PM PDT 24
Peak memory 199144 kb
Host smart-d78ce3e0-ab30-4514-a62e-9388a3349bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312838501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.312838501
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1570629042
Short name T889
Test name
Test status
Simulation time 12430364562 ps
CPU time 235.79 seconds
Started Jul 09 04:30:23 PM PDT 24
Finished Jul 09 04:34:22 PM PDT 24
Peak memory 199780 kb
Host smart-837fd19f-394e-4383-9eb2-9eae7422a0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570629042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1570629042
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.871090592
Short name T956
Test name
Test status
Simulation time 5601955158 ps
CPU time 13.08 seconds
Started Jul 09 04:25:23 PM PDT 24
Finished Jul 09 04:25:37 PM PDT 24
Peak memory 199076 kb
Host smart-df7b1bef-4471-4a96-8d86-969b3b29ed7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871090592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.871090592
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.318206063
Short name T1056
Test name
Test status
Simulation time 61690453545 ps
CPU time 28.38 seconds
Started Jul 09 04:26:38 PM PDT 24
Finished Jul 09 04:27:08 PM PDT 24
Peak memory 199140 kb
Host smart-b1dc9719-786d-461c-b2e0-96c11e9b78eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318206063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.318206063
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4018966227
Short name T550
Test name
Test status
Simulation time 1843121731 ps
CPU time 2.08 seconds
Started Jul 09 04:26:38 PM PDT 24
Finished Jul 09 04:26:42 PM PDT 24
Peak memory 194936 kb
Host smart-5c15ad91-a013-4d3c-acb5-99fcc84fc975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018966227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4018966227
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.332213782
Short name T29
Test name
Test status
Simulation time 91605809 ps
CPU time 0.84 seconds
Started Jul 09 04:30:15 PM PDT 24
Finished Jul 09 04:30:23 PM PDT 24
Peak memory 218052 kb
Host smart-ddd116e1-637a-4690-be18-4eb742c57478
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332213782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.332213782
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3872667530
Short name T600
Test name
Test status
Simulation time 5468925415 ps
CPU time 26.02 seconds
Started Jul 09 04:24:01 PM PDT 24
Finished Jul 09 04:24:27 PM PDT 24
Peak memory 199928 kb
Host smart-40a3b6e1-90f6-46b9-b772-96745f592174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872667530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3872667530
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2027314979
Short name T1149
Test name
Test status
Simulation time 294803442026 ps
CPU time 1200.62 seconds
Started Jul 09 04:30:14 PM PDT 24
Finished Jul 09 04:50:16 PM PDT 24
Peak memory 208220 kb
Host smart-452e1e16-0774-4423-be8d-a833b08f049e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027314979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2027314979
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.892797725
Short name T110
Test name
Test status
Simulation time 26318491831 ps
CPU time 278.44 seconds
Started Jul 09 04:30:14 PM PDT 24
Finished Jul 09 04:34:54 PM PDT 24
Peak memory 216212 kb
Host smart-f3139aa4-4917-4f9c-a5d7-36485b8067c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892797725 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.892797725
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3654712894
Short name T874
Test name
Test status
Simulation time 1045602021 ps
CPU time 3.19 seconds
Started Jul 09 04:27:21 PM PDT 24
Finished Jul 09 04:27:29 PM PDT 24
Peak memory 198100 kb
Host smart-3be82bef-89b1-468f-b492-a68addf1ed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654712894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3654712894
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3206242119
Short name T503
Test name
Test status
Simulation time 57322346335 ps
CPU time 78.41 seconds
Started Jul 09 04:25:58 PM PDT 24
Finished Jul 09 04:27:17 PM PDT 24
Peak memory 200204 kb
Host smart-5251970e-0954-42ce-9be6-d09533ad3419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206242119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3206242119
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1076444347
Short name T502
Test name
Test status
Simulation time 14988596 ps
CPU time 0.58 seconds
Started Jul 09 04:30:54 PM PDT 24
Finished Jul 09 04:31:01 PM PDT 24
Peak memory 195488 kb
Host smart-ecad8323-fc93-45d9-867d-7aaf20213878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076444347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1076444347
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2956862377
Short name T426
Test name
Test status
Simulation time 122814825256 ps
CPU time 181.52 seconds
Started Jul 09 04:30:37 PM PDT 24
Finished Jul 09 04:33:41 PM PDT 24
Peak memory 199756 kb
Host smart-5431fbb4-d5c5-4d3e-8611-f3a11be60f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956862377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2956862377
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.341874265
Short name T976
Test name
Test status
Simulation time 176655737069 ps
CPU time 23.52 seconds
Started Jul 09 04:30:50 PM PDT 24
Finished Jul 09 04:31:17 PM PDT 24
Peak memory 198152 kb
Host smart-2ab785eb-4721-4e22-b8ba-b9a30b461102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341874265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.341874265
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2598469627
Short name T435
Test name
Test status
Simulation time 272893793104 ps
CPU time 103.28 seconds
Started Jul 09 04:30:42 PM PDT 24
Finished Jul 09 04:32:27 PM PDT 24
Peak memory 199556 kb
Host smart-9ac8db0d-980e-4ff1-b40a-a365429b8abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598469627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2598469627
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.876258786
Short name T843
Test name
Test status
Simulation time 9825967055 ps
CPU time 2.79 seconds
Started Jul 09 04:30:51 PM PDT 24
Finished Jul 09 04:30:57 PM PDT 24
Peak memory 198716 kb
Host smart-1bd6cea8-79cb-49a5-9173-f5fc4432a256
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876258786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.876258786
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2070597872
Short name T838
Test name
Test status
Simulation time 98374107884 ps
CPU time 354.57 seconds
Started Jul 09 04:30:49 PM PDT 24
Finished Jul 09 04:36:45 PM PDT 24
Peak memory 199848 kb
Host smart-7a1f321e-99de-462b-a2ae-9b36cf9cf263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070597872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2070597872
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.350744388
Short name T980
Test name
Test status
Simulation time 2009876234 ps
CPU time 3.59 seconds
Started Jul 09 04:30:42 PM PDT 24
Finished Jul 09 04:30:47 PM PDT 24
Peak memory 196200 kb
Host smart-8be53d27-a528-475c-b462-35040b40d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350744388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.350744388
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1066647456
Short name T602
Test name
Test status
Simulation time 81787806091 ps
CPU time 89.11 seconds
Started Jul 09 04:30:50 PM PDT 24
Finished Jul 09 04:32:21 PM PDT 24
Peak memory 199980 kb
Host smart-28e47f15-05d9-4e7e-8eca-27e4a4ec09aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066647456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1066647456
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.4015812028
Short name T1052
Test name
Test status
Simulation time 17135582450 ps
CPU time 886.05 seconds
Started Jul 09 04:30:56 PM PDT 24
Finished Jul 09 04:45:53 PM PDT 24
Peak memory 199668 kb
Host smart-93909f34-73e9-41ef-a4d4-1565cb7d6522
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015812028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4015812028
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.322636886
Short name T1165
Test name
Test status
Simulation time 7052096406 ps
CPU time 7.75 seconds
Started Jul 09 04:31:01 PM PDT 24
Finished Jul 09 04:31:24 PM PDT 24
Peak memory 197596 kb
Host smart-af6c0f11-01a5-4c5d-a249-088f070afe56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=322636886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.322636886
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.269634327
Short name T1098
Test name
Test status
Simulation time 47333491632 ps
CPU time 22.33 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:31:11 PM PDT 24
Peak memory 199720 kb
Host smart-b780bfda-7bd2-48df-bb76-cc62fb3814b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269634327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.269634327
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.11523909
Short name T346
Test name
Test status
Simulation time 2529664650 ps
CPU time 1.12 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:30:57 PM PDT 24
Peak memory 196368 kb
Host smart-7e97599e-c37e-4d2f-80d4-17d642f0c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11523909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.11523909
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3176561632
Short name T7
Test name
Test status
Simulation time 465621969 ps
CPU time 3.58 seconds
Started Jul 09 04:30:41 PM PDT 24
Finished Jul 09 04:30:46 PM PDT 24
Peak memory 198652 kb
Host smart-c17cf825-85b7-485b-aec0-b515327fc6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176561632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3176561632
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1926987837
Short name T209
Test name
Test status
Simulation time 392171752464 ps
CPU time 97.17 seconds
Started Jul 09 04:30:49 PM PDT 24
Finished Jul 09 04:32:28 PM PDT 24
Peak memory 199728 kb
Host smart-43b39332-45c5-4736-b95c-552a8c0237ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926987837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1926987837
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.412471759
Short name T306
Test name
Test status
Simulation time 391793625286 ps
CPU time 925.94 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:46:15 PM PDT 24
Peak memory 216348 kb
Host smart-584902b5-8d09-4d84-b0db-9b2c7f4a550e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412471759 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.412471759
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4243260716
Short name T352
Test name
Test status
Simulation time 773242061 ps
CPU time 2.47 seconds
Started Jul 09 04:30:51 PM PDT 24
Finished Jul 09 04:30:57 PM PDT 24
Peak memory 199008 kb
Host smart-69afdf51-287e-4e38-a469-8a65df985bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243260716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4243260716
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2025322371
Short name T593
Test name
Test status
Simulation time 7698831261 ps
CPU time 3.49 seconds
Started Jul 09 04:30:49 PM PDT 24
Finished Jul 09 04:30:54 PM PDT 24
Peak memory 196944 kb
Host smart-23e915e1-1489-43c8-a541-227606732e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025322371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2025322371
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.160503720
Short name T365
Test name
Test status
Simulation time 11243030393 ps
CPU time 24.12 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:33:27 PM PDT 24
Peak memory 199772 kb
Host smart-89625c55-681f-47df-afe8-d8460f835840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160503720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.160503720
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2241332314
Short name T558
Test name
Test status
Simulation time 131529629743 ps
CPU time 22.71 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:33:26 PM PDT 24
Peak memory 199828 kb
Host smart-631a0cd8-1255-4a8a-a573-1517d26827a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241332314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2241332314
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.529573881
Short name T713
Test name
Test status
Simulation time 360664873934 ps
CPU time 291.98 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:37:54 PM PDT 24
Peak memory 199684 kb
Host smart-99e48c50-4e8a-4bf7-b256-82cc1e42c6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529573881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.529573881
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.596153167
Short name T899
Test name
Test status
Simulation time 45876493490 ps
CPU time 15.93 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:33:19 PM PDT 24
Peak memory 199224 kb
Host smart-ebeda168-e6f2-4e17-88b0-622d198a4424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596153167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.596153167
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3749465482
Short name T207
Test name
Test status
Simulation time 105413887052 ps
CPU time 203.29 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:36:28 PM PDT 24
Peak memory 199788 kb
Host smart-8d50285c-24f3-441c-9cf7-c9f595963588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749465482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3749465482
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.255932462
Short name T834
Test name
Test status
Simulation time 7495222423 ps
CPU time 5.7 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:33:12 PM PDT 24
Peak memory 199400 kb
Host smart-fa29c46b-671b-4d9b-8948-d71aad758751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255932462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.255932462
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2840233433
Short name T952
Test name
Test status
Simulation time 101809006791 ps
CPU time 36.52 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:33:39 PM PDT 24
Peak memory 199772 kb
Host smart-95afcf99-26ec-4189-9a30-5262d7267bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840233433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2840233433
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1801052169
Short name T479
Test name
Test status
Simulation time 99926019304 ps
CPU time 132.22 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 199460 kb
Host smart-996e6d28-bafa-45bf-9f1a-1988253a783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801052169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1801052169
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3525119207
Short name T751
Test name
Test status
Simulation time 123359333657 ps
CPU time 43.27 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:33:50 PM PDT 24
Peak memory 199808 kb
Host smart-c477c676-7fed-4a16-8897-30cdddf9196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525119207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3525119207
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1054774550
Short name T420
Test name
Test status
Simulation time 258793869351 ps
CPU time 50.23 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:33:54 PM PDT 24
Peak memory 199772 kb
Host smart-a4f4ddbc-a087-4322-b77a-9da530df5184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054774550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1054774550
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.1014993845
Short name T721
Test name
Test status
Simulation time 29268635 ps
CPU time 0.54 seconds
Started Jul 09 04:30:53 PM PDT 24
Finished Jul 09 04:30:59 PM PDT 24
Peak memory 194872 kb
Host smart-7a95312c-fcbb-4a76-9648-93da5eaaf558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014993845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1014993845
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3393931946
Short name T120
Test name
Test status
Simulation time 74556297805 ps
CPU time 55 seconds
Started Jul 09 04:31:00 PM PDT 24
Finished Jul 09 04:32:09 PM PDT 24
Peak memory 199792 kb
Host smart-dd1f0b42-50aa-46d3-a0c9-c80feb1c1fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393931946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3393931946
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.75010580
Short name T822
Test name
Test status
Simulation time 84989009555 ps
CPU time 40.02 seconds
Started Jul 09 04:30:51 PM PDT 24
Finished Jul 09 04:31:36 PM PDT 24
Peak memory 199796 kb
Host smart-7e0b1d3b-95ed-423a-9b8c-adb91b9a5132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75010580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.75010580
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.691438898
Short name T231
Test name
Test status
Simulation time 77058985010 ps
CPU time 16.7 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:31:14 PM PDT 24
Peak memory 199776 kb
Host smart-96887d60-25e1-4f26-a7fd-9b873ec319b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691438898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.691438898
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3264937499
Short name T548
Test name
Test status
Simulation time 44387611355 ps
CPU time 24.85 seconds
Started Jul 09 04:30:45 PM PDT 24
Finished Jul 09 04:31:11 PM PDT 24
Peak memory 199760 kb
Host smart-83a5da63-1026-46de-b539-b1865e21e5c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264937499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3264937499
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3366570923
Short name T531
Test name
Test status
Simulation time 59305526516 ps
CPU time 485.26 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:39:29 PM PDT 24
Peak memory 199884 kb
Host smart-221d09a5-4582-4192-a06c-992fb7eb9bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366570923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3366570923
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2162553123
Short name T25
Test name
Test status
Simulation time 7421706853 ps
CPU time 14.79 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:31:40 PM PDT 24
Peak memory 199756 kb
Host smart-26a494a4-b64e-45da-9916-a1d1ac8cfa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162553123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2162553123
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.3850838724
Short name T400
Test name
Test status
Simulation time 15941197715 ps
CPU time 483.68 seconds
Started Jul 09 04:30:48 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 199808 kb
Host smart-5586de7b-43ca-4a7f-8176-ee0063b8b77d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850838724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3850838724
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.449682358
Short name T456
Test name
Test status
Simulation time 3064911086 ps
CPU time 11.67 seconds
Started Jul 09 04:30:39 PM PDT 24
Finished Jul 09 04:30:53 PM PDT 24
Peak memory 197936 kb
Host smart-86070373-96f0-45b1-a037-964e7104fe7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449682358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.449682358
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2753108048
Short name T13
Test name
Test status
Simulation time 104762060656 ps
CPU time 40.11 seconds
Started Jul 09 04:30:54 PM PDT 24
Finished Jul 09 04:31:41 PM PDT 24
Peak memory 199712 kb
Host smart-e2e08660-1c3b-4b54-8315-50d96899870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753108048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2753108048
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3090044174
Short name T1117
Test name
Test status
Simulation time 4249042006 ps
CPU time 7.35 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:35 PM PDT 24
Peak memory 196296 kb
Host smart-11cd4324-33b0-4b3b-a040-93671de61fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090044174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3090044174
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1483055229
Short name T649
Test name
Test status
Simulation time 87011100 ps
CPU time 1.01 seconds
Started Jul 09 04:30:48 PM PDT 24
Finished Jul 09 04:30:50 PM PDT 24
Peak memory 199232 kb
Host smart-156bf728-62a5-40a2-bc42-5c0a12704a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483055229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1483055229
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2860776384
Short name T127
Test name
Test status
Simulation time 195904315144 ps
CPU time 559.1 seconds
Started Jul 09 04:30:54 PM PDT 24
Finished Jul 09 04:40:19 PM PDT 24
Peak memory 229024 kb
Host smart-4b081165-7082-4ef8-9b10-f5ae547e125f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860776384 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2860776384
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.651866196
Short name T286
Test name
Test status
Simulation time 755014086 ps
CPU time 2.29 seconds
Started Jul 09 04:30:51 PM PDT 24
Finished Jul 09 04:30:56 PM PDT 24
Peak memory 198692 kb
Host smart-ef4fff46-9f93-4087-82c8-2a3945656be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651866196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.651866196
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2276900673
Short name T525
Test name
Test status
Simulation time 74290014455 ps
CPU time 110.84 seconds
Started Jul 09 04:30:58 PM PDT 24
Finished Jul 09 04:32:59 PM PDT 24
Peak memory 199740 kb
Host smart-c03e0aee-4fa7-4194-bd61-b387e8ad3ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276900673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2276900673
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2008711719
Short name T168
Test name
Test status
Simulation time 34415463766 ps
CPU time 58.14 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:34:02 PM PDT 24
Peak memory 199772 kb
Host smart-88cc0ed2-c488-4092-ad7c-1f00e588d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008711719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2008711719
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.4077303356
Short name T973
Test name
Test status
Simulation time 109716359729 ps
CPU time 182.4 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:36:05 PM PDT 24
Peak memory 199800 kb
Host smart-b32857ad-54d9-453a-aaba-e345ac18b670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077303356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.4077303356
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3441422541
Short name T499
Test name
Test status
Simulation time 53287141088 ps
CPU time 78.67 seconds
Started Jul 09 04:33:00 PM PDT 24
Finished Jul 09 04:34:19 PM PDT 24
Peak memory 199536 kb
Host smart-3f5d4b13-7e15-4502-a650-26dc4ecd312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441422541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3441422541
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1910812752
Short name T1169
Test name
Test status
Simulation time 65457287687 ps
CPU time 50.29 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:33:56 PM PDT 24
Peak memory 199832 kb
Host smart-e6ce717f-1d7c-4fed-8454-2c0effa5faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910812752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1910812752
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2465080794
Short name T1076
Test name
Test status
Simulation time 36779139283 ps
CPU time 56.34 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:34:02 PM PDT 24
Peak memory 199816 kb
Host smart-bf1a66d6-b09a-49f0-a2a3-46877702cc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465080794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2465080794
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1726291898
Short name T1130
Test name
Test status
Simulation time 41278323840 ps
CPU time 72.72 seconds
Started Jul 09 04:33:01 PM PDT 24
Finished Jul 09 04:34:14 PM PDT 24
Peak memory 199684 kb
Host smart-fc86394c-2de9-4af0-aa2a-9dbc65bf937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726291898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1726291898
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.664855777
Short name T870
Test name
Test status
Simulation time 205693337791 ps
CPU time 83.39 seconds
Started Jul 09 04:33:01 PM PDT 24
Finished Jul 09 04:34:25 PM PDT 24
Peak memory 199836 kb
Host smart-1e54a874-827d-48d5-b7fd-010ab75595c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664855777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.664855777
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2751957692
Short name T796
Test name
Test status
Simulation time 13379231 ps
CPU time 0.55 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:32:12 PM PDT 24
Peak memory 195360 kb
Host smart-957465a5-53e7-4e31-b047-438a17acb7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751957692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2751957692
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3538779190
Short name T132
Test name
Test status
Simulation time 90053121427 ps
CPU time 32.52 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:32:00 PM PDT 24
Peak memory 199776 kb
Host smart-02a508b7-0979-4ef0-a291-ebd843f753cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538779190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3538779190
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.5721740
Short name T159
Test name
Test status
Simulation time 139776118859 ps
CPU time 50.44 seconds
Started Jul 09 04:31:02 PM PDT 24
Finished Jul 09 04:32:08 PM PDT 24
Peak memory 199292 kb
Host smart-83f6cee1-9832-468a-856d-c1d0521736c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5721740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.5721740
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2527489009
Short name T236
Test name
Test status
Simulation time 26293154239 ps
CPU time 40.53 seconds
Started Jul 09 04:30:50 PM PDT 24
Finished Jul 09 04:31:34 PM PDT 24
Peak memory 199804 kb
Host smart-eb661446-0da1-4405-9530-345a27969e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527489009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2527489009
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1416609078
Short name T596
Test name
Test status
Simulation time 12559346506 ps
CPU time 5.61 seconds
Started Jul 09 04:30:51 PM PDT 24
Finished Jul 09 04:31:01 PM PDT 24
Peak memory 199308 kb
Host smart-46fa655f-8755-44a3-b319-c4d665c187c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416609078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1416609078
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3350189869
Short name T685
Test name
Test status
Simulation time 160970045667 ps
CPU time 722 seconds
Started Jul 09 04:31:07 PM PDT 24
Finished Jul 09 04:43:27 PM PDT 24
Peak memory 199640 kb
Host smart-eae1f2fb-4073-496c-951e-78c2d12e80eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350189869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3350189869
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1683684041
Short name T375
Test name
Test status
Simulation time 1376719887 ps
CPU time 2.55 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:31:26 PM PDT 24
Peak memory 195848 kb
Host smart-5614b0e5-bec4-443d-a72d-efa1a552cc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683684041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1683684041
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1578344170
Short name T529
Test name
Test status
Simulation time 141726950652 ps
CPU time 66.45 seconds
Started Jul 09 04:30:58 PM PDT 24
Finished Jul 09 04:32:15 PM PDT 24
Peak memory 207912 kb
Host smart-fac8a47f-2441-4d16-aa38-607a06d0a3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578344170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1578344170
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3303858182
Short name T1093
Test name
Test status
Simulation time 14444053597 ps
CPU time 222.22 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 199748 kb
Host smart-ffea593d-6283-4703-8e84-001259c9e1ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3303858182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3303858182
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.535038728
Short name T679
Test name
Test status
Simulation time 1785747170 ps
CPU time 8.28 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:31:32 PM PDT 24
Peak memory 197832 kb
Host smart-2b29d56a-bdae-42c3-8818-6f4f14be08f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535038728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.535038728
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.282277854
Short name T804
Test name
Test status
Simulation time 50110400095 ps
CPU time 24.33 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:31:49 PM PDT 24
Peak memory 199844 kb
Host smart-73b854bb-330b-4fe5-bd36-812702c17de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282277854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.282277854
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2582044324
Short name T297
Test name
Test status
Simulation time 5554833800 ps
CPU time 4.57 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:31:35 PM PDT 24
Peak memory 196036 kb
Host smart-571b4a0b-0260-4fe2-be52-54b4f06aa918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582044324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2582044324
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2342825927
Short name T481
Test name
Test status
Simulation time 101924194 ps
CPU time 0.85 seconds
Started Jul 09 04:31:02 PM PDT 24
Finished Jul 09 04:31:20 PM PDT 24
Peak memory 196960 kb
Host smart-94bcd9bb-f07c-40ca-8fe9-52b64a877b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342825927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2342825927
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1111871914
Short name T115
Test name
Test status
Simulation time 26560819623 ps
CPU time 186.28 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:35:19 PM PDT 24
Peak memory 199704 kb
Host smart-41350e3c-263e-4103-b268-1dc2b72d9cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111871914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1111871914
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.145317630
Short name T451
Test name
Test status
Simulation time 127175209533 ps
CPU time 294.66 seconds
Started Jul 09 04:30:54 PM PDT 24
Finished Jul 09 04:35:56 PM PDT 24
Peak memory 216400 kb
Host smart-322de7fa-b080-4ee5-a39f-906fa58416fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145317630 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.145317630
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2481050613
Short name T788
Test name
Test status
Simulation time 502589462 ps
CPU time 1.81 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:32:13 PM PDT 24
Peak memory 199644 kb
Host smart-fcd275b4-df9c-4f9e-83c1-22509eeecdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481050613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2481050613
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1468402536
Short name T486
Test name
Test status
Simulation time 58277221495 ps
CPU time 41.89 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:31:56 PM PDT 24
Peak memory 199752 kb
Host smart-59691551-26a7-465d-ac34-2b2e825147bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468402536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1468402536
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2720219887
Short name T515
Test name
Test status
Simulation time 127566964555 ps
CPU time 232.74 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:36:59 PM PDT 24
Peak memory 199792 kb
Host smart-7217c5c3-6b36-4f05-a2d4-3b84bf1ab7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720219887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2720219887
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1045553872
Short name T773
Test name
Test status
Simulation time 111990664710 ps
CPU time 84.45 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:34:29 PM PDT 24
Peak memory 199756 kb
Host smart-4f343470-8802-4fbf-bf09-39ba6ff016d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045553872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1045553872
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3573519703
Short name T227
Test name
Test status
Simulation time 81220199188 ps
CPU time 123.97 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:35:09 PM PDT 24
Peak memory 199864 kb
Host smart-061469d9-3d57-49a1-8da0-53d7b84ec2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573519703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3573519703
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1932619942
Short name T445
Test name
Test status
Simulation time 82664242218 ps
CPU time 239.91 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:37:06 PM PDT 24
Peak memory 199676 kb
Host smart-40f8a064-dc46-4481-9f7c-c67c3b1a14ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932619942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1932619942
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2478904812
Short name T616
Test name
Test status
Simulation time 79092389375 ps
CPU time 74.9 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:34:20 PM PDT 24
Peak memory 199800 kb
Host smart-3f75f8f8-6c8f-4aa1-865e-e21305e0f035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478904812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2478904812
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2954520572
Short name T459
Test name
Test status
Simulation time 66629698660 ps
CPU time 103.53 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:34:51 PM PDT 24
Peak memory 199688 kb
Host smart-7f99c696-dad0-465e-a32a-b35da5a54732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954520572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2954520572
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1494257195
Short name T10
Test name
Test status
Simulation time 77341741576 ps
CPU time 50.86 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:33:58 PM PDT 24
Peak memory 199792 kb
Host smart-1faeb874-8b2e-4f87-8d13-0b5fcac9baae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494257195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1494257195
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1639773166
Short name T410
Test name
Test status
Simulation time 175481192230 ps
CPU time 148.06 seconds
Started Jul 09 04:30:58 PM PDT 24
Finished Jul 09 04:33:37 PM PDT 24
Peak memory 199816 kb
Host smart-7a94622e-9ac3-4dea-8353-65d53b4c6a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639773166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1639773166
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3849239742
Short name T1045
Test name
Test status
Simulation time 31023503026 ps
CPU time 69.84 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:33:21 PM PDT 24
Peak memory 199656 kb
Host smart-a10ddcc6-c4e4-4f7e-a705-20fde9d5b742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849239742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3849239742
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3414118211
Short name T731
Test name
Test status
Simulation time 47995468264 ps
CPU time 97.01 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:33:01 PM PDT 24
Peak memory 199632 kb
Host smart-01800f3c-4314-4825-8bea-8d40bf9c7c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414118211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3414118211
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3352511696
Short name T871
Test name
Test status
Simulation time 33891708420 ps
CPU time 50.68 seconds
Started Jul 09 04:30:57 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 199744 kb
Host smart-99b7f925-d8f6-4256-9311-a25784b7a7ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352511696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3352511696
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3082494873
Short name T795
Test name
Test status
Simulation time 61331108459 ps
CPU time 192.64 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:34:41 PM PDT 24
Peak memory 199712 kb
Host smart-5b576e58-a439-4f6f-a4fc-a2d94b6db2a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082494873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3082494873
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.757342787
Short name T935
Test name
Test status
Simulation time 11158990111 ps
CPU time 6.59 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:32:19 PM PDT 24
Peak memory 199660 kb
Host smart-b529bedb-e57d-417c-9cb4-2db69c9dd5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757342787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.757342787
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.779191948
Short name T645
Test name
Test status
Simulation time 61185028292 ps
CPU time 27.18 seconds
Started Jul 09 04:30:57 PM PDT 24
Finished Jul 09 04:31:35 PM PDT 24
Peak memory 199640 kb
Host smart-1f02fc7e-3474-4a23-9294-db31cac83ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779191948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.779191948
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3154966281
Short name T638
Test name
Test status
Simulation time 19054584173 ps
CPU time 535.81 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:40:20 PM PDT 24
Peak memory 199796 kb
Host smart-6478964b-7d61-41ff-9457-1f22128dfe41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3154966281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3154966281
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.662728899
Short name T948
Test name
Test status
Simulation time 7441873280 ps
CPU time 14.41 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:31:37 PM PDT 24
Peak memory 198824 kb
Host smart-b5b9d396-c48d-4e39-8682-0e040ea675c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662728899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.662728899
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2178544727
Short name T538
Test name
Test status
Simulation time 4245087447 ps
CPU time 3.17 seconds
Started Jul 09 04:30:57 PM PDT 24
Finished Jul 09 04:31:11 PM PDT 24
Peak memory 196200 kb
Host smart-0dd649e7-2456-4f62-a3a5-63361239d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178544727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2178544727
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.565843877
Short name T258
Test name
Test status
Simulation time 294067231 ps
CPU time 1.4 seconds
Started Jul 09 04:30:44 PM PDT 24
Finished Jul 09 04:30:47 PM PDT 24
Peak memory 197980 kb
Host smart-739f584b-7c9f-4331-9fd3-1a9c244d0f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565843877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.565843877
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.753556445
Short name T555
Test name
Test status
Simulation time 116041186091 ps
CPU time 289.82 seconds
Started Jul 09 04:30:56 PM PDT 24
Finished Jul 09 04:35:55 PM PDT 24
Peak memory 199916 kb
Host smart-b06720cb-bce1-44ff-b6a5-cba052399ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753556445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.753556445
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2393095480
Short name T606
Test name
Test status
Simulation time 16636208265 ps
CPU time 180.08 seconds
Started Jul 09 04:32:09 PM PDT 24
Finished Jul 09 04:35:11 PM PDT 24
Peak memory 215748 kb
Host smart-85c565fd-2a7c-4c4f-aa85-6f2a027ca972
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393095480 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2393095480
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3314318552
Short name T981
Test name
Test status
Simulation time 916350900 ps
CPU time 2.84 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:31:16 PM PDT 24
Peak memory 197696 kb
Host smart-8f99736b-2fe9-4b5d-8a2f-1a3ff23fac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314318552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3314318552
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1257450461
Short name T1128
Test name
Test status
Simulation time 15750739007 ps
CPU time 24.09 seconds
Started Jul 09 04:31:02 PM PDT 24
Finished Jul 09 04:31:43 PM PDT 24
Peak memory 199828 kb
Host smart-21c97ed5-9108-4bfd-b52c-ca2ec55142ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257450461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1257450461
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1572743748
Short name T387
Test name
Test status
Simulation time 68304847648 ps
CPU time 145.94 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:35:31 PM PDT 24
Peak memory 199772 kb
Host smart-cdeda5c1-09c7-427e-946c-5a5d53af4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572743748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1572743748
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.957916755
Short name T1062
Test name
Test status
Simulation time 256878887265 ps
CPU time 32.53 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:33:36 PM PDT 24
Peak memory 200096 kb
Host smart-87ce91ac-d884-4669-bd48-28a22ee50bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957916755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.957916755
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3766617838
Short name T190
Test name
Test status
Simulation time 134591118417 ps
CPU time 24.11 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:33:30 PM PDT 24
Peak memory 199752 kb
Host smart-790d78b7-f7b8-441d-be1e-9246dda2fcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766617838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3766617838
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1880561109
Short name T331
Test name
Test status
Simulation time 17842367935 ps
CPU time 13.53 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:33:18 PM PDT 24
Peak memory 199804 kb
Host smart-bc8b7b78-29ad-4b0e-930d-484d0e31451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880561109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1880561109
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.787257882
Short name T283
Test name
Test status
Simulation time 100351343040 ps
CPU time 44.9 seconds
Started Jul 09 04:33:07 PM PDT 24
Finished Jul 09 04:33:53 PM PDT 24
Peak memory 199744 kb
Host smart-e3254ed8-05e3-4fdf-b950-79b834fb8c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787257882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.787257882
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2225819527
Short name T891
Test name
Test status
Simulation time 17201719996 ps
CPU time 27.75 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:33:35 PM PDT 24
Peak memory 198780 kb
Host smart-71d6ca7f-f629-488a-8586-c2fd75af7651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225819527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2225819527
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3672057567
Short name T811
Test name
Test status
Simulation time 151558996607 ps
CPU time 138.67 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:35:26 PM PDT 24
Peak memory 199780 kb
Host smart-643336ff-3503-4499-af4d-e1e10c31fcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672057567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3672057567
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1716567973
Short name T594
Test name
Test status
Simulation time 13246834 ps
CPU time 0.56 seconds
Started Jul 09 04:30:55 PM PDT 24
Finished Jul 09 04:31:04 PM PDT 24
Peak memory 195024 kb
Host smart-b7d973cf-4605-4924-a2de-78ceee42cfb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716567973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1716567973
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3069957415
Short name T123
Test name
Test status
Simulation time 160876271528 ps
CPU time 79.23 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:32:41 PM PDT 24
Peak memory 199748 kb
Host smart-61008354-edb6-4f8b-980e-ca5160cffe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069957415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3069957415
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1914128101
Short name T783
Test name
Test status
Simulation time 54910010195 ps
CPU time 15.15 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:31:28 PM PDT 24
Peak memory 199792 kb
Host smart-490db745-8997-49dc-9f11-f8e0436036fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914128101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1914128101
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.680747323
Short name T340
Test name
Test status
Simulation time 99135714326 ps
CPU time 630.63 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:41:57 PM PDT 24
Peak memory 199756 kb
Host smart-83fc18db-9d86-4f1b-8808-1e5bfd8929b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=680747323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.680747323
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1318491973
Short name T640
Test name
Test status
Simulation time 5452771727 ps
CPU time 11.13 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:32:22 PM PDT 24
Peak memory 199668 kb
Host smart-bbc176bd-9827-487c-b5f5-d7b14d669b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318491973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1318491973
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3917145005
Short name T104
Test name
Test status
Simulation time 270436656908 ps
CPU time 30.49 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:31:54 PM PDT 24
Peak memory 208196 kb
Host smart-3dd10bad-fdd2-4bae-ba5c-67e914d61a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917145005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3917145005
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.102679869
Short name T586
Test name
Test status
Simulation time 27032668306 ps
CPU time 1414.22 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:54:59 PM PDT 24
Peak memory 199764 kb
Host smart-0fd59489-cf1f-4090-84d8-3730b3e4ea01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102679869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.102679869
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1706266462
Short name T859
Test name
Test status
Simulation time 5566924501 ps
CPU time 45.22 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 198640 kb
Host smart-153e4d5a-21bd-4ead-bad4-a9a72202b37b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706266462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1706266462
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2836208761
Short name T470
Test name
Test status
Simulation time 70285966876 ps
CPU time 40.75 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:32:11 PM PDT 24
Peak memory 199768 kb
Host smart-3829a891-56b8-4357-ac74-766395720d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836208761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2836208761
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1835873341
Short name T1141
Test name
Test status
Simulation time 5242146774 ps
CPU time 1.37 seconds
Started Jul 09 04:31:54 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 195180 kb
Host smart-3a8d6a0a-b373-482f-93a7-e14e28190985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835873341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1835873341
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2753359196
Short name T522
Test name
Test status
Simulation time 121952743 ps
CPU time 0.78 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:31:25 PM PDT 24
Peak memory 196976 kb
Host smart-b758d1fa-9f58-4036-921a-804f42e39c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753359196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2753359196
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3820900585
Short name T730
Test name
Test status
Simulation time 72079707467 ps
CPU time 745.63 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:43:49 PM PDT 24
Peak memory 199672 kb
Host smart-df5571fb-5b85-4474-b070-256ca23d3cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820900585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3820900585
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1615381842
Short name T59
Test name
Test status
Simulation time 79146447711 ps
CPU time 1031.23 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:48:39 PM PDT 24
Peak memory 216620 kb
Host smart-8541820e-ea30-470f-970a-968a36fb106d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615381842 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1615381842
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3003353219
Short name T1157
Test name
Test status
Simulation time 2251369161 ps
CPU time 2.67 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:31:00 PM PDT 24
Peak memory 198740 kb
Host smart-27ca8890-e010-4b06-9b41-212e908e3a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003353219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3003353219
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3606011878
Short name T588
Test name
Test status
Simulation time 31252898230 ps
CPU time 43.96 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:31:42 PM PDT 24
Peak memory 199816 kb
Host smart-d32c8145-1e92-46e9-ab47-d79187afadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606011878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3606011878
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3207829655
Short name T180
Test name
Test status
Simulation time 91431253685 ps
CPU time 39.69 seconds
Started Jul 09 04:33:07 PM PDT 24
Finished Jul 09 04:33:48 PM PDT 24
Peak memory 199812 kb
Host smart-3752933d-1681-406a-992c-3685d4e1579b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207829655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3207829655
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2535747833
Short name T494
Test name
Test status
Simulation time 127541113963 ps
CPU time 203.4 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:36:29 PM PDT 24
Peak memory 199832 kb
Host smart-0c73d91b-72bc-4bf7-8741-5412c6a8aefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535747833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2535747833
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.350607612
Short name T1080
Test name
Test status
Simulation time 16106839797 ps
CPU time 25.33 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:33:33 PM PDT 24
Peak memory 199812 kb
Host smart-bf91bd95-8c7c-41d9-bea5-4e3b76fdc7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350607612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.350607612
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1425999281
Short name T872
Test name
Test status
Simulation time 191415484549 ps
CPU time 29.74 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:33:37 PM PDT 24
Peak memory 199788 kb
Host smart-8f2c0d9e-45ed-486e-8c2f-74c0a47702d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425999281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1425999281
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3013570808
Short name T851
Test name
Test status
Simulation time 141090797457 ps
CPU time 78.6 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:34:25 PM PDT 24
Peak memory 199872 kb
Host smart-fccf7a04-1773-40d9-a768-0a6a979a1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013570808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3013570808
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.791467036
Short name T801
Test name
Test status
Simulation time 106020521074 ps
CPU time 108.61 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:34:56 PM PDT 24
Peak memory 199832 kb
Host smart-39c607f7-df1b-4fbc-a875-cda6f46f8d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791467036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.791467036
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3359118474
Short name T154
Test name
Test status
Simulation time 60938258069 ps
CPU time 24.05 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 199756 kb
Host smart-aafd4db2-4d2f-4cc5-b2c1-19e9461f91a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359118474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3359118474
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1440169468
Short name T136
Test name
Test status
Simulation time 262516687501 ps
CPU time 32.69 seconds
Started Jul 09 04:33:07 PM PDT 24
Finished Jul 09 04:33:41 PM PDT 24
Peak memory 199736 kb
Host smart-6cb81efe-33d4-4e3a-8a2c-5a61bec342f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440169468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1440169468
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.890314571
Short name T398
Test name
Test status
Simulation time 118773235752 ps
CPU time 48.14 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:33:56 PM PDT 24
Peak memory 199800 kb
Host smart-af193b49-2f95-4a0d-8317-555dc3af0be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890314571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.890314571
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1848918410
Short name T333
Test name
Test status
Simulation time 82375133 ps
CPU time 0.56 seconds
Started Jul 09 04:31:03 PM PDT 24
Finished Jul 09 04:31:22 PM PDT 24
Peak memory 195404 kb
Host smart-60ac33ea-d089-4415-b13f-7fb8321926aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848918410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1848918410
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.189920604
Short name T902
Test name
Test status
Simulation time 127160064470 ps
CPU time 281.43 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:36:05 PM PDT 24
Peak memory 199760 kb
Host smart-daa508d5-129c-4868-a8b4-73f69f1a3080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189920604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.189920604
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3863931283
Short name T392
Test name
Test status
Simulation time 14572530551 ps
CPU time 11.85 seconds
Started Jul 09 04:31:02 PM PDT 24
Finished Jul 09 04:31:30 PM PDT 24
Peak memory 198280 kb
Host smart-303435c3-95b7-47bc-bf31-a1502c3fe3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863931283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3863931283
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2876451228
Short name T321
Test name
Test status
Simulation time 77546723358 ps
CPU time 102.09 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:33:09 PM PDT 24
Peak memory 199732 kb
Host smart-7d7104ae-789a-45bd-b5f1-2fa9a442cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876451228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2876451228
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.4264261161
Short name T706
Test name
Test status
Simulation time 20086702132 ps
CPU time 8.88 seconds
Started Jul 09 04:31:02 PM PDT 24
Finished Jul 09 04:31:27 PM PDT 24
Peak memory 199192 kb
Host smart-4fd520d9-2da6-43fd-b894-68fff4d55553
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264261161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4264261161
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.922349574
Short name T754
Test name
Test status
Simulation time 235641596474 ps
CPU time 335.7 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:37:49 PM PDT 24
Peak memory 199736 kb
Host smart-d07a11d8-aafa-43ba-b4a9-b58ad99746e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922349574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.922349574
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1679767864
Short name T512
Test name
Test status
Simulation time 5232392495 ps
CPU time 10.1 seconds
Started Jul 09 04:30:55 PM PDT 24
Finished Jul 09 04:31:14 PM PDT 24
Peak memory 198804 kb
Host smart-b762eb98-0c74-4149-8502-ec89ab0f74e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679767864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1679767864
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.589511279
Short name T879
Test name
Test status
Simulation time 15069571288 ps
CPU time 20.43 seconds
Started Jul 09 04:30:53 PM PDT 24
Finished Jul 09 04:31:20 PM PDT 24
Peak memory 199940 kb
Host smart-0dce8f79-0e62-4980-84d7-b0dfceb25ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589511279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.589511279
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2393167373
Short name T573
Test name
Test status
Simulation time 19450118412 ps
CPU time 758.43 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:43:51 PM PDT 24
Peak memory 199732 kb
Host smart-500afc7a-1db7-412c-8bf1-54c2b983430c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393167373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2393167373
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1341302110
Short name T47
Test name
Test status
Simulation time 2734512098 ps
CPU time 9.7 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:31:32 PM PDT 24
Peak memory 197856 kb
Host smart-2d1531fe-a244-4a8a-8385-160cd0808b7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341302110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1341302110
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.329042538
Short name T162
Test name
Test status
Simulation time 56094151883 ps
CPU time 59.21 seconds
Started Jul 09 04:30:58 PM PDT 24
Finished Jul 09 04:32:10 PM PDT 24
Peak memory 199668 kb
Host smart-38a7adfb-8c7e-4115-9525-4bfc54b43292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329042538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.329042538
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2237549545
Short name T404
Test name
Test status
Simulation time 3683372595 ps
CPU time 1.5 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:31:25 PM PDT 24
Peak memory 196168 kb
Host smart-dce1aac5-75a8-48ec-9188-1c80edd6a8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237549545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2237549545
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.234616976
Short name T501
Test name
Test status
Simulation time 852450559 ps
CPU time 2.92 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:31:16 PM PDT 24
Peak memory 199604 kb
Host smart-9ef75819-3b99-4b56-ac37-93b8848c8f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234616976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.234616976
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1675499095
Short name T881
Test name
Test status
Simulation time 554668096047 ps
CPU time 449.31 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:39:00 PM PDT 24
Peak memory 216192 kb
Host smart-9dd94cce-2bb6-4522-a83c-0b88d327c524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675499095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1675499095
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3364375861
Short name T729
Test name
Test status
Simulation time 53761600756 ps
CPU time 159.02 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:34:52 PM PDT 24
Peak memory 212328 kb
Host smart-dcd42b75-29fc-403b-a2b8-d1a9eee2668e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364375861 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3364375861
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3403146484
Short name T396
Test name
Test status
Simulation time 840041923 ps
CPU time 2.34 seconds
Started Jul 09 04:30:57 PM PDT 24
Finished Jul 09 04:31:11 PM PDT 24
Peak memory 198104 kb
Host smart-8215b32c-87a4-46a6-8e96-23dd8812b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403146484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3403146484
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1137173581
Short name T254
Test name
Test status
Simulation time 93293267658 ps
CPU time 157.17 seconds
Started Jul 09 04:30:50 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 199784 kb
Host smart-4cbfad77-1c09-49ac-8440-7d83bf3079c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137173581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1137173581
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3160189890
Short name T184
Test name
Test status
Simulation time 103240472474 ps
CPU time 263.34 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:37:30 PM PDT 24
Peak memory 199592 kb
Host smart-da17be3c-44a7-49d7-a340-7f52625b0ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160189890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3160189890
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3208850015
Short name T458
Test name
Test status
Simulation time 15369620716 ps
CPU time 14.63 seconds
Started Jul 09 04:33:06 PM PDT 24
Finished Jul 09 04:33:22 PM PDT 24
Peak memory 199776 kb
Host smart-6898fa17-f71f-4c3c-9283-98c8a5acf1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208850015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3208850015
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1516789202
Short name T1142
Test name
Test status
Simulation time 145278759921 ps
CPU time 24.63 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 199808 kb
Host smart-fa63849f-9d85-45b0-b07c-10659eedf4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516789202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1516789202
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3314001233
Short name T14
Test name
Test status
Simulation time 85242531637 ps
CPU time 26.39 seconds
Started Jul 09 04:33:07 PM PDT 24
Finished Jul 09 04:33:34 PM PDT 24
Peak memory 199488 kb
Host smart-52c5840d-8425-4999-9b26-c0dfc5695788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314001233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3314001233
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.869857027
Short name T244
Test name
Test status
Simulation time 21731978363 ps
CPU time 18.93 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:33:26 PM PDT 24
Peak memory 199740 kb
Host smart-1317033d-1615-477b-8fd8-9a5dcf60f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869857027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.869857027
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.54582465
Short name T622
Test name
Test status
Simulation time 38691995886 ps
CPU time 16.03 seconds
Started Jul 09 04:33:11 PM PDT 24
Finished Jul 09 04:33:28 PM PDT 24
Peak memory 199920 kb
Host smart-1ab5d57f-9426-40ec-a558-7523b855d4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54582465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.54582465
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1695287438
Short name T166
Test name
Test status
Simulation time 59979859871 ps
CPU time 35.51 seconds
Started Jul 09 04:33:05 PM PDT 24
Finished Jul 09 04:33:42 PM PDT 24
Peak memory 199828 kb
Host smart-0fd68e01-bd9d-4016-99b8-ada0ce295ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695287438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1695287438
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1285537817
Short name T344
Test name
Test status
Simulation time 53386523 ps
CPU time 0.54 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:31:23 PM PDT 24
Peak memory 195408 kb
Host smart-1ed16f32-d7d0-47fe-811f-2567e5a70cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285537817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1285537817
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.236213567
Short name T374
Test name
Test status
Simulation time 19135660378 ps
CPU time 31.22 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:31:53 PM PDT 24
Peak memory 199816 kb
Host smart-e07b977c-d68a-497c-a177-79b118d14b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236213567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.236213567
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2728581189
Short name T741
Test name
Test status
Simulation time 17121550662 ps
CPU time 23.01 seconds
Started Jul 09 04:31:07 PM PDT 24
Finished Jul 09 04:31:48 PM PDT 24
Peak memory 199812 kb
Host smart-f7e28c9f-5d4c-4019-88d2-184ac10403a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728581189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2728581189
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1060640581
Short name T857
Test name
Test status
Simulation time 116336409998 ps
CPU time 47.69 seconds
Started Jul 09 04:31:03 PM PDT 24
Finished Jul 09 04:32:08 PM PDT 24
Peak memory 199524 kb
Host smart-f77b55a6-07dc-4dd0-b20b-9dbb80d21bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060640581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1060640581
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.4055545406
Short name T1035
Test name
Test status
Simulation time 45867538522 ps
CPU time 17.56 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:31:48 PM PDT 24
Peak memory 199728 kb
Host smart-63cd5a85-b90f-4f11-9464-576c0667421c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055545406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.4055545406
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2087020564
Short name T562
Test name
Test status
Simulation time 168712165014 ps
CPU time 1657.04 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:58:50 PM PDT 24
Peak memory 199708 kb
Host smart-03634676-7cd9-452b-b93c-b98ca96a6e3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087020564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2087020564
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1712629059
Short name T362
Test name
Test status
Simulation time 5735643926 ps
CPU time 5.98 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:33 PM PDT 24
Peak memory 199484 kb
Host smart-f87763b9-d006-4c95-a289-86a8d3b62123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712629059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1712629059
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4245736639
Short name T528
Test name
Test status
Simulation time 43507612741 ps
CPU time 36.97 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:32:06 PM PDT 24
Peak memory 198684 kb
Host smart-1a98e0da-c62e-4074-87de-99fb4e2a9697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245736639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4245736639
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.648608887
Short name T694
Test name
Test status
Simulation time 19114801559 ps
CPU time 50.12 seconds
Started Jul 09 04:30:55 PM PDT 24
Finished Jul 09 04:31:54 PM PDT 24
Peak memory 199636 kb
Host smart-44192ee8-549a-4dc9-a231-1df4eb20c0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648608887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.648608887
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3040068313
Short name T709
Test name
Test status
Simulation time 1606490287 ps
CPU time 2 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:31:15 PM PDT 24
Peak memory 197852 kb
Host smart-e494c62d-7aa6-4336-ac96-cf3f12ac903f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040068313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3040068313
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.555827213
Short name T422
Test name
Test status
Simulation time 59832273671 ps
CPU time 54.96 seconds
Started Jul 09 04:31:00 PM PDT 24
Finished Jul 09 04:32:09 PM PDT 24
Peak memory 199636 kb
Host smart-9fd41713-4c56-4aeb-b716-f13334553f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555827213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.555827213
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4115243116
Short name T725
Test name
Test status
Simulation time 42507218331 ps
CPU time 68.68 seconds
Started Jul 09 04:31:03 PM PDT 24
Finished Jul 09 04:32:29 PM PDT 24
Peak memory 195572 kb
Host smart-67a8e815-1eb5-4c79-81cf-40dcbc591487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115243116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4115243116
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3263907542
Short name T372
Test name
Test status
Simulation time 696999023 ps
CPU time 1.89 seconds
Started Jul 09 04:30:55 PM PDT 24
Finished Jul 09 04:31:04 PM PDT 24
Peak memory 199540 kb
Host smart-a25687d0-5e18-4fa6-b4f0-86b8243fb429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263907542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3263907542
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2376065380
Short name T661
Test name
Test status
Simulation time 135341399776 ps
CPU time 102.67 seconds
Started Jul 09 04:30:56 PM PDT 24
Finished Jul 09 04:32:48 PM PDT 24
Peak memory 198704 kb
Host smart-167042aa-87d0-4919-b6b1-5e0c365c6480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376065380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2376065380
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3070565182
Short name T64
Test name
Test status
Simulation time 436191251781 ps
CPU time 702.55 seconds
Started Jul 09 04:31:03 PM PDT 24
Finished Jul 09 04:43:03 PM PDT 24
Peak memory 224648 kb
Host smart-02128180-775a-46e8-9814-e669be1a3cdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070565182 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3070565182
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.283253625
Short name T272
Test name
Test status
Simulation time 12047078439 ps
CPU time 53.96 seconds
Started Jul 09 04:31:13 PM PDT 24
Finished Jul 09 04:32:26 PM PDT 24
Peak memory 199608 kb
Host smart-5da7856c-1f11-4210-9603-897628d81370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283253625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.283253625
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.115996365
Short name T933
Test name
Test status
Simulation time 62347055321 ps
CPU time 26.04 seconds
Started Jul 09 04:31:03 PM PDT 24
Finished Jul 09 04:31:46 PM PDT 24
Peak memory 199708 kb
Host smart-de64df8f-dddb-4936-bb91-4399078b7c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115996365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.115996365
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.139974117
Short name T373
Test name
Test status
Simulation time 49733123296 ps
CPU time 38.3 seconds
Started Jul 09 04:33:13 PM PDT 24
Finished Jul 09 04:33:52 PM PDT 24
Peak memory 199732 kb
Host smart-85296b39-60f2-480e-9daf-13a1765aa81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139974117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.139974117
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2291258391
Short name T922
Test name
Test status
Simulation time 93501503398 ps
CPU time 63.02 seconds
Started Jul 09 04:33:12 PM PDT 24
Finished Jul 09 04:34:16 PM PDT 24
Peak memory 199536 kb
Host smart-8f3b475f-08af-41ca-a2d3-3044607a5e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291258391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2291258391
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.917548067
Short name T592
Test name
Test status
Simulation time 17905691587 ps
CPU time 29.13 seconds
Started Jul 09 04:33:13 PM PDT 24
Finished Jul 09 04:33:43 PM PDT 24
Peak memory 199716 kb
Host smart-566a7fe0-11df-4756-ac6f-49863c8b8068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917548067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.917548067
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3750126702
Short name T183
Test name
Test status
Simulation time 16134294773 ps
CPU time 26.2 seconds
Started Jul 09 04:33:10 PM PDT 24
Finished Jul 09 04:33:37 PM PDT 24
Peak memory 199752 kb
Host smart-2257cebc-4d65-47b3-881e-14ac5d214ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750126702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3750126702
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3147714198
Short name T636
Test name
Test status
Simulation time 163221855413 ps
CPU time 28.42 seconds
Started Jul 09 04:33:12 PM PDT 24
Finished Jul 09 04:33:41 PM PDT 24
Peak memory 198908 kb
Host smart-6e35bebe-f14d-44b1-a871-00698bab497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147714198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3147714198
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3743245739
Short name T1094
Test name
Test status
Simulation time 63290467722 ps
CPU time 30.84 seconds
Started Jul 09 04:33:11 PM PDT 24
Finished Jul 09 04:33:42 PM PDT 24
Peak memory 200180 kb
Host smart-3d570fef-3e4a-47c3-9992-8b140dc43e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743245739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3743245739
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2797839960
Short name T852
Test name
Test status
Simulation time 13782627049 ps
CPU time 22.7 seconds
Started Jul 09 04:33:11 PM PDT 24
Finished Jul 09 04:33:35 PM PDT 24
Peak memory 199776 kb
Host smart-08d8d714-0a58-4cfa-ab2a-c214e090bc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797839960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2797839960
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2693451075
Short name T909
Test name
Test status
Simulation time 135866890475 ps
CPU time 97.14 seconds
Started Jul 09 04:33:12 PM PDT 24
Finished Jul 09 04:34:50 PM PDT 24
Peak memory 199680 kb
Host smart-9da98c18-1948-4399-b457-a9b302bd8545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693451075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2693451075
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2930789647
Short name T629
Test name
Test status
Simulation time 32551130918 ps
CPU time 51.67 seconds
Started Jul 09 04:33:14 PM PDT 24
Finished Jul 09 04:34:06 PM PDT 24
Peak memory 199748 kb
Host smart-6c03323e-bec3-4739-af0d-07c07363f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930789647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2930789647
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2713693836
Short name T545
Test name
Test status
Simulation time 44777363 ps
CPU time 0.55 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:31:30 PM PDT 24
Peak memory 195140 kb
Host smart-4514f78b-d798-4746-9570-2a55453239be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713693836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2713693836
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1787089806
Short name T790
Test name
Test status
Simulation time 34921746169 ps
CPU time 31.8 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:32:01 PM PDT 24
Peak memory 199784 kb
Host smart-e8a5b2d6-9b8f-466e-af00-dffab19f6b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787089806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1787089806
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.225466888
Short name T530
Test name
Test status
Simulation time 112462349398 ps
CPU time 126.88 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:33:34 PM PDT 24
Peak memory 199872 kb
Host smart-9540e3c0-0db2-448d-aed9-3ff8d29b25f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225466888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.225466888
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1005715128
Short name T1000
Test name
Test status
Simulation time 26109654637 ps
CPU time 41.08 seconds
Started Jul 09 04:30:54 PM PDT 24
Finished Jul 09 04:31:43 PM PDT 24
Peak memory 199692 kb
Host smart-c3821465-3361-43fc-810a-2d7e885a6bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005715128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1005715128
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.101482683
Short name T312
Test name
Test status
Simulation time 42237240446 ps
CPU time 62.81 seconds
Started Jul 09 04:31:03 PM PDT 24
Finished Jul 09 04:32:23 PM PDT 24
Peak memory 199724 kb
Host smart-494ee13a-b0d1-418a-9537-1670c59f5d6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101482683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.101482683
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1129914009
Short name T926
Test name
Test status
Simulation time 74502262254 ps
CPU time 129.11 seconds
Started Jul 09 04:30:58 PM PDT 24
Finished Jul 09 04:33:18 PM PDT 24
Peak memory 199736 kb
Host smart-ac0456c0-d03a-4e72-8920-1647ff15b65e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129914009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1129914009
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2320346107
Short name T341
Test name
Test status
Simulation time 9060860491 ps
CPU time 24.82 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:31:55 PM PDT 24
Peak memory 199620 kb
Host smart-63e0bd2d-788d-4a04-b1cf-cd679d72144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320346107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2320346107
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.4192647571
Short name T524
Test name
Test status
Simulation time 36672850065 ps
CPU time 59.74 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:33:13 PM PDT 24
Peak memory 199828 kb
Host smart-e98e6085-7f11-4692-b212-ec259b55550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192647571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.4192647571
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2787108182
Short name T901
Test name
Test status
Simulation time 25097141734 ps
CPU time 1423.07 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:55:17 PM PDT 24
Peak memory 199732 kb
Host smart-d2f3b37c-511c-4f2f-baa7-1c4da3a80dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787108182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2787108182
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2720950572
Short name T416
Test name
Test status
Simulation time 5378894646 ps
CPU time 11.4 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:31:34 PM PDT 24
Peak memory 197976 kb
Host smart-a672a278-09e9-400e-a59a-4ac033dfc9a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720950572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2720950572
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2566261683
Short name T1022
Test name
Test status
Simulation time 48707152364 ps
CPU time 33.52 seconds
Started Jul 09 04:30:58 PM PDT 24
Finished Jul 09 04:31:44 PM PDT 24
Peak memory 199868 kb
Host smart-32d38591-3a70-44bb-aec4-1742e4ebade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566261683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2566261683
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1422243825
Short name T991
Test name
Test status
Simulation time 51621389868 ps
CPU time 72.72 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:32:46 PM PDT 24
Peak memory 195584 kb
Host smart-ee78f584-4b4c-41f6-bc45-a53726432ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422243825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1422243825
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.225356699
Short name T379
Test name
Test status
Simulation time 292815493 ps
CPU time 1.71 seconds
Started Jul 09 04:30:54 PM PDT 24
Finished Jul 09 04:31:04 PM PDT 24
Peak memory 199280 kb
Host smart-53336a31-f149-4e7d-9b5c-f55e9f56594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225356699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.225356699
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1017681770
Short name T318
Test name
Test status
Simulation time 99552477513 ps
CPU time 118.54 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 208108 kb
Host smart-239241d6-9b9c-4172-9b70-277a7c331716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017681770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1017681770
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1877796060
Short name T907
Test name
Test status
Simulation time 103943300988 ps
CPU time 539.33 seconds
Started Jul 09 04:31:01 PM PDT 24
Finished Jul 09 04:40:15 PM PDT 24
Peak memory 216504 kb
Host smart-b6007f27-70bc-45a9-8dd7-f011a754b1eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877796060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1877796060
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.854461939
Short name T992
Test name
Test status
Simulation time 7971647010 ps
CPU time 7.83 seconds
Started Jul 09 04:31:07 PM PDT 24
Finished Jul 09 04:31:33 PM PDT 24
Peak memory 199608 kb
Host smart-4decc4c6-4ab0-4530-9d06-bb3937b4f2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854461939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.854461939
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3464837124
Short name T518
Test name
Test status
Simulation time 60853304044 ps
CPU time 104.26 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:32:41 PM PDT 24
Peak memory 199664 kb
Host smart-ba922a09-ab78-4590-89b5-edfaa61b1255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464837124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3464837124
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.317703784
Short name T1158
Test name
Test status
Simulation time 10425242927 ps
CPU time 9.32 seconds
Started Jul 09 04:33:10 PM PDT 24
Finished Jul 09 04:33:20 PM PDT 24
Peak memory 199464 kb
Host smart-16c90465-bc03-45e0-a715-40e3d01e80ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317703784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.317703784
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3529985991
Short name T739
Test name
Test status
Simulation time 27327243048 ps
CPU time 38.64 seconds
Started Jul 09 04:33:11 PM PDT 24
Finished Jul 09 04:33:50 PM PDT 24
Peak memory 199808 kb
Host smart-b3e44b4d-e02a-441d-a411-11d49082bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529985991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3529985991
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1341641989
Short name T825
Test name
Test status
Simulation time 105410342698 ps
CPU time 63.27 seconds
Started Jul 09 04:33:10 PM PDT 24
Finished Jul 09 04:34:14 PM PDT 24
Peak memory 199760 kb
Host smart-f2ffc9c2-67c1-4c56-a913-41d2a8c20e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341641989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1341641989
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3121434333
Short name T597
Test name
Test status
Simulation time 2743002872 ps
CPU time 5.39 seconds
Started Jul 09 04:33:14 PM PDT 24
Finished Jul 09 04:33:20 PM PDT 24
Peak memory 199700 kb
Host smart-fcf93bf1-9483-446d-841a-7762c36c5b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121434333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3121434333
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2337935632
Short name T156
Test name
Test status
Simulation time 45472753830 ps
CPU time 18.3 seconds
Started Jul 09 04:33:10 PM PDT 24
Finished Jul 09 04:33:29 PM PDT 24
Peak memory 199800 kb
Host smart-f48da041-5812-4da0-ae63-c8bbf37e56d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337935632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2337935632
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1964346182
Short name T688
Test name
Test status
Simulation time 48205434684 ps
CPU time 16.84 seconds
Started Jul 09 04:33:11 PM PDT 24
Finished Jul 09 04:33:29 PM PDT 24
Peak memory 199652 kb
Host smart-69a7f2b4-691b-4780-9806-979dca166f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964346182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1964346182
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2883528398
Short name T12
Test name
Test status
Simulation time 89848197741 ps
CPU time 10.22 seconds
Started Jul 09 04:33:09 PM PDT 24
Finished Jul 09 04:33:20 PM PDT 24
Peak memory 199772 kb
Host smart-caf8ec8d-192e-4b9b-b335-0ae5b386d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883528398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2883528398
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3066050480
Short name T234
Test name
Test status
Simulation time 148506939206 ps
CPU time 93.18 seconds
Started Jul 09 04:33:11 PM PDT 24
Finished Jul 09 04:34:45 PM PDT 24
Peak memory 199828 kb
Host smart-86a6c743-b328-46ca-965e-2855ea69bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066050480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3066050480
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.73324245
Short name T381
Test name
Test status
Simulation time 283588372696 ps
CPU time 25.66 seconds
Started Jul 09 04:33:09 PM PDT 24
Finished Jul 09 04:33:35 PM PDT 24
Peak memory 199768 kb
Host smart-03893446-e398-4bef-9155-23c039ea22fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73324245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.73324245
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.892515909
Short name T1113
Test name
Test status
Simulation time 79392629100 ps
CPU time 60.48 seconds
Started Jul 09 04:33:11 PM PDT 24
Finished Jul 09 04:34:13 PM PDT 24
Peak memory 199832 kb
Host smart-e53ebe87-7691-41e1-91e6-dc9db40bc3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892515909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.892515909
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3814984602
Short name T329
Test name
Test status
Simulation time 34866786 ps
CPU time 0.55 seconds
Started Jul 09 04:30:58 PM PDT 24
Finished Jul 09 04:31:12 PM PDT 24
Peak memory 194712 kb
Host smart-d69bd172-4989-45a5-acd0-9d47f9e1a903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814984602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3814984602
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1263491355
Short name T519
Test name
Test status
Simulation time 169658466561 ps
CPU time 33.69 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:31:47 PM PDT 24
Peak memory 199692 kb
Host smart-33e1cc2b-1723-4dfa-9192-30ab2335c8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263491355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1263491355
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3159321423
Short name T727
Test name
Test status
Simulation time 160659978383 ps
CPU time 64.4 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:32:28 PM PDT 24
Peak memory 199816 kb
Host smart-afe65e63-b725-4a8e-b68b-e2db79d487b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159321423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3159321423
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1845804566
Short name T969
Test name
Test status
Simulation time 22997650407 ps
CPU time 16.42 seconds
Started Jul 09 04:31:13 PM PDT 24
Finished Jul 09 04:31:48 PM PDT 24
Peak memory 199748 kb
Host smart-d8945eac-d6f9-4c66-946b-47d82ceffc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845804566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1845804566
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1176298391
Short name T348
Test name
Test status
Simulation time 24442804806 ps
CPU time 33.56 seconds
Started Jul 09 04:31:13 PM PDT 24
Finished Jul 09 04:32:06 PM PDT 24
Peak memory 197748 kb
Host smart-f21ab6f3-ff4d-4e9c-9605-90bf94e4bd75
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176298391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1176298391
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3205643646
Short name T609
Test name
Test status
Simulation time 175559146539 ps
CPU time 172.91 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:34:16 PM PDT 24
Peak memory 199732 kb
Host smart-c5086260-8752-4282-8e7b-a09d9d5ad851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205643646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3205643646
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3743334777
Short name T506
Test name
Test status
Simulation time 2418977068 ps
CPU time 4.88 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:32 PM PDT 24
Peak memory 199076 kb
Host smart-ff222e46-d59e-4751-aea3-d7eea313a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743334777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3743334777
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1065630289
Short name T1166
Test name
Test status
Simulation time 172019176105 ps
CPU time 99.92 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:32:53 PM PDT 24
Peak memory 208096 kb
Host smart-701a57bf-a64a-4453-9bc6-3820fe5378ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065630289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1065630289
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.366731247
Short name T428
Test name
Test status
Simulation time 10143754132 ps
CPU time 148.47 seconds
Started Jul 09 04:31:00 PM PDT 24
Finished Jul 09 04:33:44 PM PDT 24
Peak memory 199740 kb
Host smart-7cac692b-c75e-408a-a955-5daa7d6958d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366731247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.366731247
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2258749350
Short name T427
Test name
Test status
Simulation time 2005324110 ps
CPU time 8.99 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:31:33 PM PDT 24
Peak memory 197948 kb
Host smart-35fb80bc-88b1-4277-89f6-be7170261d32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2258749350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2258749350
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3203866323
Short name T275
Test name
Test status
Simulation time 191706658373 ps
CPU time 370.89 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:37:44 PM PDT 24
Peak memory 199708 kb
Host smart-9a03fbf5-e568-4160-84f4-50ddc80a8f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203866323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3203866323
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1478950048
Short name T296
Test name
Test status
Simulation time 41837531182 ps
CPU time 27.26 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:32:01 PM PDT 24
Peak memory 196252 kb
Host smart-5d4134b8-432d-460b-8083-100dac63edce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478950048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1478950048
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2594447336
Short name T978
Test name
Test status
Simulation time 451284184 ps
CPU time 1.85 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:29 PM PDT 24
Peak memory 198208 kb
Host smart-50381dcd-e334-40c0-a0b6-efab5618e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594447336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2594447336
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3781578495
Short name T406
Test name
Test status
Simulation time 214952414758 ps
CPU time 72.47 seconds
Started Jul 09 04:31:13 PM PDT 24
Finished Jul 09 04:32:45 PM PDT 24
Peak memory 215508 kb
Host smart-151c3b12-f787-4954-8ead-c63e16d12f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781578495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3781578495
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2988133348
Short name T854
Test name
Test status
Simulation time 147077678113 ps
CPU time 559.43 seconds
Started Jul 09 04:31:07 PM PDT 24
Finished Jul 09 04:40:44 PM PDT 24
Peak memory 224668 kb
Host smart-4a0f268c-181e-4fbc-8fd7-ea69c7750025
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988133348 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2988133348
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1094755966
Short name T429
Test name
Test status
Simulation time 367869002 ps
CPU time 1.35 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:31:24 PM PDT 24
Peak memory 198052 kb
Host smart-b654f340-e193-43b4-9f56-b9d1e3e17c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094755966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1094755966
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2332451352
Short name T314
Test name
Test status
Simulation time 68252319074 ps
CPU time 130.79 seconds
Started Jul 09 04:31:17 PM PDT 24
Finished Jul 09 04:33:46 PM PDT 24
Peak memory 199752 kb
Host smart-a11c30fc-e42f-4cbf-aec3-74c681b4318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332451352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2332451352
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3576908666
Short name T303
Test name
Test status
Simulation time 80057259827 ps
CPU time 57.3 seconds
Started Jul 09 04:33:12 PM PDT 24
Finished Jul 09 04:34:10 PM PDT 24
Peak memory 199612 kb
Host smart-5de530b4-d470-4964-84ef-234c83c2c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576908666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3576908666
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2796265525
Short name T199
Test name
Test status
Simulation time 46965744351 ps
CPU time 82.33 seconds
Started Jul 09 04:33:09 PM PDT 24
Finished Jul 09 04:34:32 PM PDT 24
Peak memory 199712 kb
Host smart-225bedd5-a647-4462-8de8-aec4c530fba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796265525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2796265525
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2631449475
Short name T961
Test name
Test status
Simulation time 12186339345 ps
CPU time 19.66 seconds
Started Jul 09 04:33:12 PM PDT 24
Finished Jul 09 04:33:33 PM PDT 24
Peak memory 199544 kb
Host smart-eb4f54f9-6ea1-4f8f-b889-2b15545c9d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631449475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2631449475
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2572707494
Short name T205
Test name
Test status
Simulation time 219049848904 ps
CPU time 187.66 seconds
Started Jul 09 04:33:12 PM PDT 24
Finished Jul 09 04:36:20 PM PDT 24
Peak memory 199688 kb
Host smart-276d58e3-7936-4368-b5e0-2ba601c18b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572707494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2572707494
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.825915395
Short name T417
Test name
Test status
Simulation time 25886476037 ps
CPU time 42.52 seconds
Started Jul 09 04:33:10 PM PDT 24
Finished Jul 09 04:33:53 PM PDT 24
Peak memory 199708 kb
Host smart-e83ad634-391c-4202-9a95-4e7d646af869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825915395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.825915395
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1879091355
Short name T689
Test name
Test status
Simulation time 56382145733 ps
CPU time 79.75 seconds
Started Jul 09 04:33:10 PM PDT 24
Finished Jul 09 04:34:31 PM PDT 24
Peak memory 199840 kb
Host smart-3a1497d1-c1c7-4c59-9837-1c67e6a700ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879091355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1879091355
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.90895202
Short name T251
Test name
Test status
Simulation time 206265512602 ps
CPU time 534.61 seconds
Started Jul 09 04:33:12 PM PDT 24
Finished Jul 09 04:42:08 PM PDT 24
Peak memory 199768 kb
Host smart-de4778b8-0b08-4c57-9776-6448cb9b3481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90895202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.90895202
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2655052514
Short name T439
Test name
Test status
Simulation time 121033179522 ps
CPU time 189.28 seconds
Started Jul 09 04:33:16 PM PDT 24
Finished Jul 09 04:36:26 PM PDT 24
Peak memory 199800 kb
Host smart-b0e3f88b-5b5f-40a8-99bb-0022b64f82c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655052514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2655052514
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1916006324
Short name T336
Test name
Test status
Simulation time 28820113 ps
CPU time 0.53 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:31:37 PM PDT 24
Peak memory 195196 kb
Host smart-7fe24595-628b-47b6-89e2-f0dcb8a728f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916006324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1916006324
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1094425114
Short name T996
Test name
Test status
Simulation time 38040283545 ps
CPU time 14.83 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:42 PM PDT 24
Peak memory 199736 kb
Host smart-f13324bd-9964-4161-a078-3d1ffd3e7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094425114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1094425114
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1892747203
Short name T51
Test name
Test status
Simulation time 7041759326 ps
CPU time 10.88 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:31:41 PM PDT 24
Peak memory 199728 kb
Host smart-64c0c882-84b8-4859-b720-56d57da09b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892747203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1892747203
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1226376685
Short name T769
Test name
Test status
Simulation time 57636070108 ps
CPU time 25.94 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:32:02 PM PDT 24
Peak memory 199632 kb
Host smart-3633c01f-1830-41f7-acee-2bc320379f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226376685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1226376685
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.169666953
Short name T862
Test name
Test status
Simulation time 90800584162 ps
CPU time 73.18 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:32:38 PM PDT 24
Peak memory 198964 kb
Host smart-2f8bc5f9-4531-4084-b0ce-8f7c7ea70278
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169666953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.169666953
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3552118956
Short name T736
Test name
Test status
Simulation time 309983500893 ps
CPU time 546.27 seconds
Started Jul 09 04:31:00 PM PDT 24
Finished Jul 09 04:40:22 PM PDT 24
Peak memory 199784 kb
Host smart-3a35ffbe-deb2-405f-b0b5-e8e973d63355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552118956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3552118956
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3235829729
Short name T772
Test name
Test status
Simulation time 3451463453 ps
CPU time 5.55 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:31:40 PM PDT 24
Peak memory 199364 kb
Host smart-d57c531a-b9a5-4f2c-941d-2110510c24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235829729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3235829729
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.762564592
Short name T391
Test name
Test status
Simulation time 147935777014 ps
CPU time 50.05 seconds
Started Jul 09 04:31:19 PM PDT 24
Finished Jul 09 04:32:27 PM PDT 24
Peak memory 200004 kb
Host smart-5c863941-3d49-423e-b872-cceb519c39cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762564592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.762564592
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1784911417
Short name T895
Test name
Test status
Simulation time 10579231901 ps
CPU time 163.89 seconds
Started Jul 09 04:31:07 PM PDT 24
Finished Jul 09 04:34:10 PM PDT 24
Peak memory 199612 kb
Host smart-8716e3a0-e981-4757-9ae4-21d807fc8547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784911417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1784911417
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2239249676
Short name T653
Test name
Test status
Simulation time 3085832989 ps
CPU time 25.73 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:53 PM PDT 24
Peak memory 198388 kb
Host smart-d27df51b-40de-4077-a1d6-44084f214491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239249676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2239249676
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.4109704755
Short name T802
Test name
Test status
Simulation time 65313126077 ps
CPU time 34.72 seconds
Started Jul 09 04:31:07 PM PDT 24
Finished Jul 09 04:32:00 PM PDT 24
Peak memory 200184 kb
Host smart-90d75ab3-9ce3-4e04-95af-39babb3bea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109704755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4109704755
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3534126766
Short name T1
Test name
Test status
Simulation time 42696457170 ps
CPU time 55.67 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:32:26 PM PDT 24
Peak memory 195780 kb
Host smart-38975cc0-d998-4b79-9c59-383b0c6dc8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534126766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3534126766
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1724564986
Short name T753
Test name
Test status
Simulation time 301664715 ps
CPU time 1.21 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:31:32 PM PDT 24
Peak memory 198920 kb
Host smart-eb9a2908-6a62-48d0-9564-0907dfa29a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724564986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1724564986
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1983208044
Short name T733
Test name
Test status
Simulation time 132901723416 ps
CPU time 450.95 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 199752 kb
Host smart-ddf3be58-8ec8-47d2-a0a7-7d0253da5606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983208044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1983208044
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2304988138
Short name T1177
Test name
Test status
Simulation time 1026902381 ps
CPU time 2.89 seconds
Started Jul 09 04:31:31 PM PDT 24
Finished Jul 09 04:31:46 PM PDT 24
Peak memory 198596 kb
Host smart-5ff8fe75-9245-4a7a-822c-cbc72c2f6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304988138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2304988138
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2665670540
Short name T359
Test name
Test status
Simulation time 6244488500 ps
CPU time 8.99 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:31:45 PM PDT 24
Peak memory 198492 kb
Host smart-161a8da4-833c-46f5-9520-163eb0506279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665670540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2665670540
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1993647163
Short name T309
Test name
Test status
Simulation time 51498455402 ps
CPU time 45.13 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:34:01 PM PDT 24
Peak memory 200120 kb
Host smart-8017e826-4d68-4e25-a6ba-e12ab1411a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993647163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1993647163
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1552311098
Short name T229
Test name
Test status
Simulation time 10274571245 ps
CPU time 16.88 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:33:33 PM PDT 24
Peak memory 199244 kb
Host smart-88744665-d8b5-41fb-8351-73e14f25e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552311098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1552311098
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.337592676
Short name T294
Test name
Test status
Simulation time 137821115044 ps
CPU time 71.4 seconds
Started Jul 09 04:33:16 PM PDT 24
Finished Jul 09 04:34:28 PM PDT 24
Peak memory 199680 kb
Host smart-be494540-5cc1-495f-bed3-ea2da1368b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337592676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.337592676
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1142004692
Short name T130
Test name
Test status
Simulation time 33568715838 ps
CPU time 60.11 seconds
Started Jul 09 04:33:16 PM PDT 24
Finished Jul 09 04:34:17 PM PDT 24
Peak memory 199916 kb
Host smart-f991f568-b70b-4a13-b001-cac72e1a24ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142004692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1142004692
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3011378906
Short name T208
Test name
Test status
Simulation time 48209691545 ps
CPU time 66.63 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:34:23 PM PDT 24
Peak memory 199768 kb
Host smart-cf9f7bbb-aff9-443a-8dcf-1ddbb351e17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011378906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3011378906
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2533874010
Short name T140
Test name
Test status
Simulation time 39037675316 ps
CPU time 35.04 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:33:52 PM PDT 24
Peak memory 199772 kb
Host smart-d88e6bd7-47e8-42b0-bd37-3c829d73bbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533874010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2533874010
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1468168177
Short name T1161
Test name
Test status
Simulation time 85071959536 ps
CPU time 19.18 seconds
Started Jul 09 04:33:16 PM PDT 24
Finished Jul 09 04:33:36 PM PDT 24
Peak memory 199736 kb
Host smart-79a81c91-6ad0-46ff-ad1b-de6ee46aa5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468168177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1468168177
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4280258811
Short name T1139
Test name
Test status
Simulation time 218116404051 ps
CPU time 138.6 seconds
Started Jul 09 04:33:17 PM PDT 24
Finished Jul 09 04:35:37 PM PDT 24
Peak memory 199752 kb
Host smart-abbdd959-85ad-4091-be0e-ed401f9e2ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280258811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4280258811
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.416402565
Short name T841
Test name
Test status
Simulation time 9279484214 ps
CPU time 22.04 seconds
Started Jul 09 04:33:17 PM PDT 24
Finished Jul 09 04:33:40 PM PDT 24
Peak memory 199884 kb
Host smart-63943940-b89b-4429-85b0-2f26d5dd6d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416402565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.416402565
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3243790165
Short name T916
Test name
Test status
Simulation time 20697362 ps
CPU time 0.55 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:30:30 PM PDT 24
Peak memory 195416 kb
Host smart-4e26a6a6-f202-4700-95a5-99ef247dd8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243790165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3243790165
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.356677977
Short name T507
Test name
Test status
Simulation time 225033506866 ps
CPU time 75.92 seconds
Started Jul 09 04:30:14 PM PDT 24
Finished Jul 09 04:31:37 PM PDT 24
Peak memory 199756 kb
Host smart-20bd3b5e-77a3-43b1-bdd0-de26b4b78cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356677977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.356677977
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3745925488
Short name T888
Test name
Test status
Simulation time 113475157894 ps
CPU time 175.51 seconds
Started Jul 09 04:30:21 PM PDT 24
Finished Jul 09 04:33:19 PM PDT 24
Peak memory 199768 kb
Host smart-8c584ddc-792b-44a4-ab19-460e569bd121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745925488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3745925488
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2433535653
Short name T230
Test name
Test status
Simulation time 108566963886 ps
CPU time 26.62 seconds
Started Jul 09 04:30:16 PM PDT 24
Finished Jul 09 04:30:43 PM PDT 24
Peak memory 199736 kb
Host smart-4c6d468c-446f-45dd-bf56-2769610f2e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433535653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2433535653
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3201730971
Short name T22
Test name
Test status
Simulation time 17733238572 ps
CPU time 8.77 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:30:38 PM PDT 24
Peak memory 199476 kb
Host smart-1ec57fc0-ebbe-4917-920d-014a919cbd05
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201730971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3201730971
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1068385175
Short name T837
Test name
Test status
Simulation time 165726631175 ps
CPU time 330.31 seconds
Started Jul 09 04:30:20 PM PDT 24
Finished Jul 09 04:35:52 PM PDT 24
Peak memory 199744 kb
Host smart-b6a56040-a4a4-463e-9c50-a8ecfa17aecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1068385175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1068385175
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2086072156
Short name T654
Test name
Test status
Simulation time 2879342250 ps
CPU time 5.04 seconds
Started Jul 09 04:30:19 PM PDT 24
Finished Jul 09 04:30:26 PM PDT 24
Peak memory 198652 kb
Host smart-853a5733-3e50-4fce-81b3-225e3dfad931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086072156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2086072156
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1700804262
Short name T505
Test name
Test status
Simulation time 64725298471 ps
CPU time 51.15 seconds
Started Jul 09 04:30:23 PM PDT 24
Finished Jul 09 04:31:17 PM PDT 24
Peak memory 199216 kb
Host smart-b10dc986-07c5-451b-b0a0-dd0b85ec93af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700804262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1700804262
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.308138848
Short name T1134
Test name
Test status
Simulation time 25012712366 ps
CPU time 159.39 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:33:07 PM PDT 24
Peak memory 199808 kb
Host smart-0e85aff9-1fba-46ba-a386-47d96bf9cbff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308138848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.308138848
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.881176296
Short name T504
Test name
Test status
Simulation time 2331584665 ps
CPU time 9.51 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:30:37 PM PDT 24
Peak memory 197720 kb
Host smart-f4e9e93e-9cc9-4ba6-8c7d-6d2566d80843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881176296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.881176296
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1577404135
Short name T923
Test name
Test status
Simulation time 64170248949 ps
CPU time 24.94 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:30:55 PM PDT 24
Peak memory 199484 kb
Host smart-cd6d845f-2d6f-4511-a2d2-ca066a2854ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577404135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1577404135
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3766939211
Short name T289
Test name
Test status
Simulation time 2873854832 ps
CPU time 1.48 seconds
Started Jul 09 04:30:21 PM PDT 24
Finished Jul 09 04:30:24 PM PDT 24
Peak memory 195564 kb
Host smart-e0e4ec50-901c-4d14-8c77-de2e407148fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766939211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3766939211
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.4139706104
Short name T30
Test name
Test status
Simulation time 58607800 ps
CPU time 0.77 seconds
Started Jul 09 04:30:19 PM PDT 24
Finished Jul 09 04:30:22 PM PDT 24
Peak memory 218136 kb
Host smart-1727087f-6afd-4e93-96a2-130d54805d4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139706104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4139706104
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3029954190
Short name T929
Test name
Test status
Simulation time 103698640 ps
CPU time 0.93 seconds
Started Jul 09 04:30:16 PM PDT 24
Finished Jul 09 04:30:18 PM PDT 24
Peak memory 197000 kb
Host smart-125c1a63-7479-4fb9-aa66-31342ceadd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029954190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3029954190
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3571379793
Short name T582
Test name
Test status
Simulation time 17302163883 ps
CPU time 155.08 seconds
Started Jul 09 04:30:23 PM PDT 24
Finished Jul 09 04:33:02 PM PDT 24
Peak memory 215528 kb
Host smart-d5522d5e-1675-45b8-90be-93ebfca4cc3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571379793 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3571379793
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1255359163
Short name T347
Test name
Test status
Simulation time 7178210556 ps
CPU time 7.73 seconds
Started Jul 09 04:30:19 PM PDT 24
Finished Jul 09 04:30:29 PM PDT 24
Peak memory 199736 kb
Host smart-75fe053b-58d4-4857-b29c-71ee05bb364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255359163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1255359163
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.906509321
Short name T698
Test name
Test status
Simulation time 21095488388 ps
CPU time 32.06 seconds
Started Jul 09 04:30:27 PM PDT 24
Finished Jul 09 04:31:04 PM PDT 24
Peak memory 199808 kb
Host smart-613ee359-9bb4-4f56-9ee4-014493178b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906509321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.906509321
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3868013322
Short name T643
Test name
Test status
Simulation time 14610458 ps
CPU time 0.55 seconds
Started Jul 09 04:31:41 PM PDT 24
Finished Jul 09 04:31:49 PM PDT 24
Peak memory 195428 kb
Host smart-c75135ee-7eb3-49b0-8e3c-b6c2c353d8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868013322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3868013322
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.883880044
Short name T826
Test name
Test status
Simulation time 120863578517 ps
CPU time 78.82 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:32:51 PM PDT 24
Peak memory 199712 kb
Host smart-b26ecd5b-7241-42e6-8019-595d4fb2035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883880044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.883880044
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3413191921
Short name T164
Test name
Test status
Simulation time 229959036233 ps
CPU time 117.02 seconds
Started Jul 09 04:31:13 PM PDT 24
Finished Jul 09 04:33:29 PM PDT 24
Peak memory 199788 kb
Host smart-e1bb585b-d643-45e5-a1d7-24beeb2f1dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413191921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3413191921
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.234307632
Short name T1034
Test name
Test status
Simulation time 91250950458 ps
CPU time 79.02 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:32:46 PM PDT 24
Peak memory 200160 kb
Host smart-7dc044cf-a14c-4247-8232-5e978c0da581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234307632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.234307632
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.636151499
Short name T269
Test name
Test status
Simulation time 14544503447 ps
CPU time 12.15 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:31:36 PM PDT 24
Peak memory 199740 kb
Host smart-9d0fe3b4-2e2f-4843-b5ba-893e26e2ff60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636151499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.636151499
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.720910158
Short name T1115
Test name
Test status
Simulation time 112117299357 ps
CPU time 342.57 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:37:10 PM PDT 24
Peak memory 199744 kb
Host smart-0c084496-a8a0-4b85-b04d-2ba113b81239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=720910158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.720910158
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1615153535
Short name T712
Test name
Test status
Simulation time 9708744243 ps
CPU time 18.86 seconds
Started Jul 09 04:31:23 PM PDT 24
Finished Jul 09 04:31:58 PM PDT 24
Peak memory 198348 kb
Host smart-115c5b95-340a-4965-94aa-21899b086a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615153535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1615153535
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2358606711
Short name T259
Test name
Test status
Simulation time 132488016108 ps
CPU time 94.91 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:33:01 PM PDT 24
Peak memory 199556 kb
Host smart-78a39d1c-3642-490b-b8c1-769ecd1bbb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358606711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2358606711
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.285343134
Short name T696
Test name
Test status
Simulation time 3356633983 ps
CPU time 92.49 seconds
Started Jul 09 04:30:57 PM PDT 24
Finished Jul 09 04:32:40 PM PDT 24
Peak memory 199720 kb
Host smart-6508dcdb-ad71-446f-b5f7-6ee2a87f06a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285343134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.285343134
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1656932581
Short name T1072
Test name
Test status
Simulation time 3166906675 ps
CPU time 5.29 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:31:34 PM PDT 24
Peak memory 197768 kb
Host smart-19a1d5c3-5de0-47d8-8e0a-6f8c1fd0311a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656932581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1656932581
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.161738420
Short name T924
Test name
Test status
Simulation time 192871053145 ps
CPU time 309.89 seconds
Started Jul 09 04:30:57 PM PDT 24
Finished Jul 09 04:36:18 PM PDT 24
Peak memory 199776 kb
Host smart-9bc14a4c-db8c-4912-b6fc-3e0b255153ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161738420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.161738420
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3247677576
Short name T1180
Test name
Test status
Simulation time 48687351333 ps
CPU time 69.92 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:32:32 PM PDT 24
Peak memory 195484 kb
Host smart-44120d4b-3acc-4591-a70c-4f618449fb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247677576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3247677576
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1214032334
Short name T54
Test name
Test status
Simulation time 502108417 ps
CPU time 1.5 seconds
Started Jul 09 04:31:03 PM PDT 24
Finished Jul 09 04:31:22 PM PDT 24
Peak memory 198856 kb
Host smart-134e5441-8d20-4d24-9a0f-eb5e252283b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214032334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1214032334
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3503627910
Short name T447
Test name
Test status
Simulation time 157569690731 ps
CPU time 457.48 seconds
Started Jul 09 04:31:38 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 199740 kb
Host smart-cb88ea6d-7dc4-4e81-b148-728bfb56d8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503627910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3503627910
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1566171363
Short name T566
Test name
Test status
Simulation time 1450173694 ps
CPU time 2.12 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:31:38 PM PDT 24
Peak memory 198080 kb
Host smart-b56f21ac-5c82-43a5-96d4-838234441418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566171363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1566171363
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1697823715
Short name T299
Test name
Test status
Simulation time 215726599567 ps
CPU time 88.83 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:32:51 PM PDT 24
Peak memory 199796 kb
Host smart-cd100a40-f6d7-47aa-b947-7d32496e27cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697823715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1697823715
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1014025451
Short name T463
Test name
Test status
Simulation time 40896819830 ps
CPU time 14.17 seconds
Started Jul 09 04:33:16 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 199760 kb
Host smart-f20515da-14ea-4174-818d-80d7af1c6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014025451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1014025451
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2906192210
Short name T356
Test name
Test status
Simulation time 103194482555 ps
CPU time 156.91 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:35:53 PM PDT 24
Peak memory 199768 kb
Host smart-94c2b25d-c4da-497d-b004-59fd320d3e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906192210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2906192210
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2170409066
Short name T4
Test name
Test status
Simulation time 40300194332 ps
CPU time 41.88 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:33:57 PM PDT 24
Peak memory 199720 kb
Host smart-2b1a6f4d-2b79-4196-bc6e-d6f6834a2ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170409066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2170409066
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1886734198
Short name T255
Test name
Test status
Simulation time 54202534971 ps
CPU time 48.19 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:34:04 PM PDT 24
Peak memory 199720 kb
Host smart-fe088b81-4b28-4cf1-b6f5-eeeaf782c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886734198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1886734198
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2075285712
Short name T669
Test name
Test status
Simulation time 217279265529 ps
CPU time 106.56 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:35:03 PM PDT 24
Peak memory 199828 kb
Host smart-af54b45a-447d-4373-821f-92d3e1132382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075285712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2075285712
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1655531435
Short name T830
Test name
Test status
Simulation time 101660829592 ps
CPU time 125.76 seconds
Started Jul 09 04:33:17 PM PDT 24
Finished Jul 09 04:35:23 PM PDT 24
Peak memory 199540 kb
Host smart-e05b2c79-8a62-47f3-b92f-02baa1cf488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655531435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1655531435
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2125628710
Short name T1078
Test name
Test status
Simulation time 104681699234 ps
CPU time 142.82 seconds
Started Jul 09 04:33:17 PM PDT 24
Finished Jul 09 04:35:40 PM PDT 24
Peak memory 199756 kb
Host smart-bba0f8f1-de6b-4c56-b091-9609f548ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125628710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2125628710
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.283581904
Short name T117
Test name
Test status
Simulation time 69408155205 ps
CPU time 89.4 seconds
Started Jul 09 04:33:15 PM PDT 24
Finished Jul 09 04:34:45 PM PDT 24
Peak memory 199812 kb
Host smart-f4704953-f96f-46a5-8b5e-f2f9a49392c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283581904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.283581904
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2326119983
Short name T920
Test name
Test status
Simulation time 127759826141 ps
CPU time 17.25 seconds
Started Jul 09 04:33:14 PM PDT 24
Finished Jul 09 04:33:32 PM PDT 24
Peak memory 199812 kb
Host smart-39aa7532-f2ba-4367-943f-3ea0f6808ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326119983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2326119983
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3615678742
Short name T376
Test name
Test status
Simulation time 38604116 ps
CPU time 0.54 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:31:35 PM PDT 24
Peak memory 194648 kb
Host smart-2debf30d-c2ad-4c68-8994-41e17861cbd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615678742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3615678742
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2792236553
Short name T1107
Test name
Test status
Simulation time 218099419681 ps
CPU time 75.05 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:32:41 PM PDT 24
Peak memory 199776 kb
Host smart-bfc4fb52-5b0d-4486-a534-e1d6c789f298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792236553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2792236553
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3826034811
Short name T1087
Test name
Test status
Simulation time 14595596915 ps
CPU time 23.28 seconds
Started Jul 09 04:31:41 PM PDT 24
Finished Jul 09 04:32:12 PM PDT 24
Peak memory 199832 kb
Host smart-02823fb1-64f2-43cd-bea2-ba0c7e471a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826034811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3826034811
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2793577855
Short name T914
Test name
Test status
Simulation time 134365661293 ps
CPU time 267.24 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:35:53 PM PDT 24
Peak memory 199824 kb
Host smart-536397b1-fa72-4ad8-bd85-ad24b147ba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793577855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2793577855
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2099354362
Short name T577
Test name
Test status
Simulation time 61271307163 ps
CPU time 98.76 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:33:05 PM PDT 24
Peak memory 199268 kb
Host smart-bc46e047-9e44-487f-b19d-2e83500950a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099354362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2099354362
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3892580987
Short name T1086
Test name
Test status
Simulation time 111927022552 ps
CPU time 493.9 seconds
Started Jul 09 04:32:29 PM PDT 24
Finished Jul 09 04:40:47 PM PDT 24
Peak memory 199660 kb
Host smart-84daa97c-6bd3-4d9a-a1b7-b45d4d89b089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892580987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3892580987
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2472361292
Short name T584
Test name
Test status
Simulation time 8343878220 ps
CPU time 17.81 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:45 PM PDT 24
Peak memory 199788 kb
Host smart-10cf4573-2b16-4073-b62c-89542f557618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472361292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2472361292
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1116862704
Short name T257
Test name
Test status
Simulation time 45526657666 ps
CPU time 62.38 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:32:36 PM PDT 24
Peak memory 199444 kb
Host smart-45dc062e-84ea-459b-b6da-6ca6ec72153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116862704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1116862704
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2474151451
Short name T744
Test name
Test status
Simulation time 18147151608 ps
CPU time 216.28 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:35:05 PM PDT 24
Peak memory 199788 kb
Host smart-ef3f51f9-2886-4e09-bdd1-321a8d18cc5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2474151451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2474151451
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2309012479
Short name T462
Test name
Test status
Simulation time 6331599519 ps
CPU time 49.29 seconds
Started Jul 09 04:31:02 PM PDT 24
Finished Jul 09 04:32:08 PM PDT 24
Peak memory 199208 kb
Host smart-d350d9f9-f95b-4769-a3ea-7bfd97191d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309012479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2309012479
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1786712013
Short name T134
Test name
Test status
Simulation time 41455053450 ps
CPU time 28.75 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:31:58 PM PDT 24
Peak memory 199584 kb
Host smart-6e614ee0-1a2f-477c-803c-f460647d16ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786712013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1786712013
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2107198819
Short name T578
Test name
Test status
Simulation time 4456678033 ps
CPU time 7.61 seconds
Started Jul 09 04:31:07 PM PDT 24
Finished Jul 09 04:31:33 PM PDT 24
Peak memory 196008 kb
Host smart-287088d7-f2db-4904-b6be-dc190f627982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107198819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2107198819
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1918343670
Short name T384
Test name
Test status
Simulation time 286438614 ps
CPU time 1.66 seconds
Started Jul 09 04:31:23 PM PDT 24
Finished Jul 09 04:31:41 PM PDT 24
Peak memory 198292 kb
Host smart-c10b2da1-20ee-480d-a63e-b28714d5ab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918343670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1918343670
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1682655392
Short name T962
Test name
Test status
Simulation time 23990699349 ps
CPU time 160.15 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:33:53 PM PDT 24
Peak memory 216316 kb
Host smart-89b8ebfb-86d9-4939-a8b3-367d36e96dec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682655392 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1682655392
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1869100816
Short name T55
Test name
Test status
Simulation time 3035582278 ps
CPU time 2.44 seconds
Started Jul 09 04:31:13 PM PDT 24
Finished Jul 09 04:31:33 PM PDT 24
Peak memory 198268 kb
Host smart-d75daf89-9a09-481f-903a-3be0eb61ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869100816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1869100816
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2464672145
Short name T900
Test name
Test status
Simulation time 26554916680 ps
CPU time 10.98 seconds
Started Jul 09 04:31:36 PM PDT 24
Finished Jul 09 04:31:56 PM PDT 24
Peak memory 199804 kb
Host smart-5f31232b-d5c7-496d-bcea-4bac7dd98ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464672145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2464672145
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1028726949
Short name T496
Test name
Test status
Simulation time 74249924207 ps
CPU time 28.04 seconds
Started Jul 09 04:33:17 PM PDT 24
Finished Jul 09 04:33:46 PM PDT 24
Peak memory 199788 kb
Host smart-7e816367-282b-4153-9f91-b7f0f92636c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028726949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1028726949
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.836613880
Short name T203
Test name
Test status
Simulation time 54268200381 ps
CPU time 7.27 seconds
Started Jul 09 04:33:14 PM PDT 24
Finished Jul 09 04:33:22 PM PDT 24
Peak memory 199496 kb
Host smart-f7b1d084-aa9f-4b46-8801-31846a99dc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836613880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.836613880
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2946963822
Short name T781
Test name
Test status
Simulation time 152035944237 ps
CPU time 92.86 seconds
Started Jul 09 04:33:21 PM PDT 24
Finished Jul 09 04:34:54 PM PDT 24
Peak memory 199800 kb
Host smart-7cfacf26-e125-4a2e-b225-ce5bffb332a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946963822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2946963822
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1244719918
Short name T1122
Test name
Test status
Simulation time 14539927871 ps
CPU time 23.5 seconds
Started Jul 09 04:33:23 PM PDT 24
Finished Jul 09 04:33:47 PM PDT 24
Peak memory 199624 kb
Host smart-f89e3e5e-8e99-4b31-a836-2b6ec9f3863b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244719918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1244719918
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.304291029
Short name T144
Test name
Test status
Simulation time 155938416775 ps
CPU time 229.03 seconds
Started Jul 09 04:33:22 PM PDT 24
Finished Jul 09 04:37:11 PM PDT 24
Peak memory 199760 kb
Host smart-656913ef-0b9f-4108-9b53-665bd61f9dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304291029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.304291029
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.4254226447
Short name T471
Test name
Test status
Simulation time 29684307732 ps
CPU time 11.21 seconds
Started Jul 09 04:33:21 PM PDT 24
Finished Jul 09 04:33:33 PM PDT 24
Peak memory 199832 kb
Host smart-3a7ee7bb-b0cf-42b6-924c-359d53111d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254226447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.4254226447
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2214232529
Short name T173
Test name
Test status
Simulation time 118917442588 ps
CPU time 46.04 seconds
Started Jul 09 04:33:20 PM PDT 24
Finished Jul 09 04:34:07 PM PDT 24
Peak memory 199832 kb
Host smart-b10d9e79-db38-4c92-b1c7-375532bc691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214232529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2214232529
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.929750550
Short name T591
Test name
Test status
Simulation time 38495580075 ps
CPU time 9.78 seconds
Started Jul 09 04:33:19 PM PDT 24
Finished Jul 09 04:33:29 PM PDT 24
Peak memory 199552 kb
Host smart-3b005d0c-4b28-4466-bbaf-95b79211c450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929750550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.929750550
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4200644133
Short name T1092
Test name
Test status
Simulation time 40470748340 ps
CPU time 56.3 seconds
Started Jul 09 04:33:21 PM PDT 24
Finished Jul 09 04:34:18 PM PDT 24
Peak memory 199836 kb
Host smart-8cf70612-78ac-4250-951f-3da390162776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200644133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4200644133
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4190565704
Short name T777
Test name
Test status
Simulation time 38154069005 ps
CPU time 53.31 seconds
Started Jul 09 04:33:19 PM PDT 24
Finished Jul 09 04:34:13 PM PDT 24
Peak memory 199608 kb
Host smart-a877f504-ab8c-434e-a437-cf909cd214ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190565704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4190565704
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2292134779
Short name T535
Test name
Test status
Simulation time 14987326 ps
CPU time 0.53 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:32:33 PM PDT 24
Peak memory 195352 kb
Host smart-45f9b95e-88d2-492f-81ce-0732ecebd5cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292134779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2292134779
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.571521658
Short name T861
Test name
Test status
Simulation time 53533248737 ps
CPU time 22.22 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:31:46 PM PDT 24
Peak memory 199704 kb
Host smart-1d27e0ce-244d-460c-8ece-37eaa3f8585d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571521658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.571521658
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.458554419
Short name T300
Test name
Test status
Simulation time 220472306509 ps
CPU time 182.66 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:34:36 PM PDT 24
Peak memory 199780 kb
Host smart-66b91bb6-5fc6-4e58-b413-7ff799782d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458554419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.458554419
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1295092886
Short name T317
Test name
Test status
Simulation time 139798906464 ps
CPU time 55.52 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:33:28 PM PDT 24
Peak memory 199664 kb
Host smart-474cddb5-ddc9-4851-8099-ec76149604f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295092886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1295092886
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2331096996
Short name T513
Test name
Test status
Simulation time 32294650804 ps
CPU time 51.43 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:32:15 PM PDT 24
Peak memory 199708 kb
Host smart-bdc10143-1d3b-461b-a7d2-d5b429858918
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331096996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2331096996
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2571860618
Short name T542
Test name
Test status
Simulation time 102563943466 ps
CPU time 819.6 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:45:02 PM PDT 24
Peak memory 199664 kb
Host smart-21c63207-3a41-4b61-b021-854f83cea1f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2571860618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2571860618
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3626207889
Short name T6
Test name
Test status
Simulation time 7216730298 ps
CPU time 5.11 seconds
Started Jul 09 04:32:29 PM PDT 24
Finished Jul 09 04:32:38 PM PDT 24
Peak memory 199064 kb
Host smart-1e84384b-a7f1-432b-bd42-9c01997ce1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626207889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3626207889
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2015317640
Short name T853
Test name
Test status
Simulation time 9641267741 ps
CPU time 15.37 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:32:48 PM PDT 24
Peak memory 195988 kb
Host smart-a47cec46-a82a-4add-a3ad-3427df4b6901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015317640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2015317640
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.222329430
Short name T784
Test name
Test status
Simulation time 21237360971 ps
CPU time 538.52 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:40:32 PM PDT 24
Peak memory 199676 kb
Host smart-468461ad-d231-4a6a-baea-9af208d3d07c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222329430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.222329430
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1678092756
Short name T349
Test name
Test status
Simulation time 4305126452 ps
CPU time 19.21 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:32:52 PM PDT 24
Peak memory 198016 kb
Host smart-81e9e67c-e2a4-4113-b320-fcf242d1f6ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678092756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1678092756
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1321095752
Short name T146
Test name
Test status
Simulation time 297688222542 ps
CPU time 34.18 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:32:02 PM PDT 24
Peak memory 199836 kb
Host smart-ea6d03c4-30ba-46c8-be7a-7c3752d76fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321095752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1321095752
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3964930357
Short name T760
Test name
Test status
Simulation time 5027284954 ps
CPU time 7.85 seconds
Started Jul 09 04:31:04 PM PDT 24
Finished Jul 09 04:31:30 PM PDT 24
Peak memory 196224 kb
Host smart-a0de0242-ae93-476c-869f-005ab6b9ec14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964930357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3964930357
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.735405795
Short name T1018
Test name
Test status
Simulation time 623841312 ps
CPU time 3.26 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:31:32 PM PDT 24
Peak memory 199416 kb
Host smart-bb287b15-2273-46a9-948a-63dae12d1a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735405795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.735405795
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4115794226
Short name T570
Test name
Test status
Simulation time 190090549869 ps
CPU time 31.7 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:33:04 PM PDT 24
Peak memory 199496 kb
Host smart-4dffae1a-c8bd-4a09-933e-b5ea80d5c543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115794226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4115794226
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3078490308
Short name T1012
Test name
Test status
Simulation time 182634184478 ps
CPU time 1117.05 seconds
Started Jul 09 04:31:07 PM PDT 24
Finished Jul 09 04:50:02 PM PDT 24
Peak memory 226204 kb
Host smart-96796bcb-4715-4270-86b8-06623cc45152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078490308 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3078490308
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4129406299
Short name T660
Test name
Test status
Simulation time 994375842 ps
CPU time 2.58 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:31:31 PM PDT 24
Peak memory 198248 kb
Host smart-2198f22a-6cb6-4fe4-b2d2-11232e455589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129406299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4129406299
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4220742226
Short name T263
Test name
Test status
Simulation time 119898893171 ps
CPU time 152.25 seconds
Started Jul 09 04:32:29 PM PDT 24
Finished Jul 09 04:35:05 PM PDT 24
Peak memory 199616 kb
Host smart-97162d01-5b69-42ec-92d3-ba0c60e0acd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220742226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4220742226
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1027181431
Short name T478
Test name
Test status
Simulation time 9794606787 ps
CPU time 17.46 seconds
Started Jul 09 04:33:23 PM PDT 24
Finished Jul 09 04:33:41 PM PDT 24
Peak memory 199724 kb
Host smart-1a26a237-008a-4ceb-92c6-56a2b08376cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027181431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1027181431
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1947058222
Short name T1088
Test name
Test status
Simulation time 152712471752 ps
CPU time 37.37 seconds
Started Jul 09 04:33:20 PM PDT 24
Finished Jul 09 04:33:58 PM PDT 24
Peak memory 199800 kb
Host smart-06129565-e023-4493-830a-aa29eb19c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947058222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1947058222
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1952001493
Short name T1057
Test name
Test status
Simulation time 124457220497 ps
CPU time 98.85 seconds
Started Jul 09 04:33:19 PM PDT 24
Finished Jul 09 04:34:58 PM PDT 24
Peak memory 199728 kb
Host smart-52860a6e-6d53-4df1-9196-e168db554a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952001493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1952001493
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3923333603
Short name T894
Test name
Test status
Simulation time 114845233744 ps
CPU time 59.5 seconds
Started Jul 09 04:33:19 PM PDT 24
Finished Jul 09 04:34:20 PM PDT 24
Peak memory 199640 kb
Host smart-707451bc-ab02-4729-9d50-254711bc5810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923333603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3923333603
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1076766191
Short name T1082
Test name
Test status
Simulation time 171434360136 ps
CPU time 460.32 seconds
Started Jul 09 04:33:20 PM PDT 24
Finished Jul 09 04:41:01 PM PDT 24
Peak memory 199776 kb
Host smart-ed360f40-b829-4edc-ad56-e1f3a29a7298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076766191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1076766191
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1012564621
Short name T662
Test name
Test status
Simulation time 189334908563 ps
CPU time 53.15 seconds
Started Jul 09 04:33:21 PM PDT 24
Finished Jul 09 04:34:14 PM PDT 24
Peak memory 199504 kb
Host smart-52533476-96ef-46a0-81c8-6df99125943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012564621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1012564621
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3770384724
Short name T1046
Test name
Test status
Simulation time 151613489615 ps
CPU time 243.64 seconds
Started Jul 09 04:33:20 PM PDT 24
Finished Jul 09 04:37:24 PM PDT 24
Peak memory 199772 kb
Host smart-ed5924b2-4241-45f3-b93b-146c8ec7ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770384724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3770384724
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3339938037
Short name T828
Test name
Test status
Simulation time 130887824725 ps
CPU time 135.46 seconds
Started Jul 09 04:33:21 PM PDT 24
Finished Jul 09 04:35:37 PM PDT 24
Peak memory 199732 kb
Host smart-41ad55d5-31df-4162-9337-958e2d4318f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339938037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3339938037
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3561649735
Short name T608
Test name
Test status
Simulation time 25305413850 ps
CPU time 10.28 seconds
Started Jul 09 04:33:21 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 198692 kb
Host smart-ec605964-27f1-4df3-83e2-7770a81b702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561649735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3561649735
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.4251574428
Short name T1104
Test name
Test status
Simulation time 151670467880 ps
CPU time 237.05 seconds
Started Jul 09 04:33:24 PM PDT 24
Finished Jul 09 04:37:22 PM PDT 24
Peak memory 199776 kb
Host smart-9da9eca4-35ac-4fbe-b4cb-fb9996dab236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251574428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.4251574428
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1494129729
Short name T1067
Test name
Test status
Simulation time 13168446 ps
CPU time 0.56 seconds
Started Jul 09 04:31:17 PM PDT 24
Finished Jul 09 04:31:36 PM PDT 24
Peak memory 195408 kb
Host smart-582a95bf-abf5-469b-8517-6fd1a4eece49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494129729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1494129729
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3013643717
Short name T495
Test name
Test status
Simulation time 63063588615 ps
CPU time 24.4 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:31:51 PM PDT 24
Peak memory 199904 kb
Host smart-06591927-a470-475e-a495-b6cd22cae0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013643717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3013643717
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_intr.1487714572
Short name T875
Test name
Test status
Simulation time 21208319434 ps
CPU time 8.03 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:31:41 PM PDT 24
Peak memory 197800 kb
Host smart-95218ded-3616-4b56-9b7a-df24aa36c18e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487714572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1487714572
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.97192013
Short name T39
Test name
Test status
Simulation time 82945003038 ps
CPU time 200.63 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:34:51 PM PDT 24
Peak memory 199724 kb
Host smart-4688533b-9416-46c2-907e-f58ef7022a5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97192013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.97192013
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3982942234
Short name T364
Test name
Test status
Simulation time 2942626306 ps
CPU time 2.35 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:31:31 PM PDT 24
Peak memory 199244 kb
Host smart-7d6167ce-75df-402a-a5b9-a6ea0fc15e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982942234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3982942234
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.4156847717
Short name T666
Test name
Test status
Simulation time 30802282329 ps
CPU time 53.04 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:32:22 PM PDT 24
Peak memory 197644 kb
Host smart-a67976ac-d41b-491c-9a57-44ef6efa2abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156847717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4156847717
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2834135659
Short name T434
Test name
Test status
Simulation time 16440332860 ps
CPU time 195.7 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:34:40 PM PDT 24
Peak memory 199700 kb
Host smart-6c230d2b-5628-438c-a918-f90b5d29f07b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2834135659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2834135659
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3817419961
Short name T325
Test name
Test status
Simulation time 5861065219 ps
CPU time 49.23 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:32:18 PM PDT 24
Peak memory 197992 kb
Host smart-feede845-0fb8-47b0-9401-a73721de6f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817419961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3817419961
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1702292342
Short name T147
Test name
Test status
Simulation time 62967914556 ps
CPU time 23.79 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:31:53 PM PDT 24
Peak memory 199528 kb
Host smart-e157810a-97ad-47e3-b83b-e2b0b6f557a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702292342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1702292342
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2880740004
Short name T111
Test name
Test status
Simulation time 4904508104 ps
CPU time 7.47 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:31:37 PM PDT 24
Peak memory 196232 kb
Host smart-0f07c089-b49d-4f9d-8a65-f57ebc54a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880740004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2880740004
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4118635597
Short name T369
Test name
Test status
Simulation time 642994626 ps
CPU time 2.17 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:32:16 PM PDT 24
Peak memory 198784 kb
Host smart-5b1d2997-3408-4604-b782-26b8f46495ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118635597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4118635597
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1075464155
Short name T913
Test name
Test status
Simulation time 235174342051 ps
CPU time 86.05 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:33:01 PM PDT 24
Peak memory 199776 kb
Host smart-e8784581-15d0-4c9b-872a-0d6e07e766a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075464155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1075464155
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1323628648
Short name T738
Test name
Test status
Simulation time 55836662246 ps
CPU time 199 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:34:45 PM PDT 24
Peak memory 216340 kb
Host smart-cee49e94-b724-467b-b84d-7608e4bb2a29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323628648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1323628648
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1641573423
Short name T355
Test name
Test status
Simulation time 1329048062 ps
CPU time 4.17 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:31:30 PM PDT 24
Peak memory 199564 kb
Host smart-6f6f4936-6fb7-4b14-aa0f-a95e74b52d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641573423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1641573423
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3168286507
Short name T764
Test name
Test status
Simulation time 197301321444 ps
CPU time 85 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:32:52 PM PDT 24
Peak memory 199836 kb
Host smart-b75effdc-c289-4fdd-a8e3-2cc5a2d0ff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168286507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3168286507
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1588085957
Short name T1125
Test name
Test status
Simulation time 168901099380 ps
CPU time 33.09 seconds
Started Jul 09 04:33:19 PM PDT 24
Finished Jul 09 04:33:53 PM PDT 24
Peak memory 199800 kb
Host smart-7c529ed3-02e5-4859-bee5-714f899f2015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588085957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1588085957
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1260977815
Short name T1041
Test name
Test status
Simulation time 23373554557 ps
CPU time 37.07 seconds
Started Jul 09 04:33:19 PM PDT 24
Finished Jul 09 04:33:57 PM PDT 24
Peak memory 199860 kb
Host smart-1cfe1170-28f7-4780-ad71-8d20e2b592fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260977815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1260977815
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1023578467
Short name T906
Test name
Test status
Simulation time 74271673356 ps
CPU time 112.42 seconds
Started Jul 09 04:33:23 PM PDT 24
Finished Jul 09 04:35:17 PM PDT 24
Peak memory 199736 kb
Host smart-c3098b15-0ed2-4ff9-b96b-f4c163d2e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023578467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1023578467
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3387392063
Short name T984
Test name
Test status
Simulation time 13705369828 ps
CPU time 22.82 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:33:50 PM PDT 24
Peak memory 199780 kb
Host smart-5b8792ea-a019-4f51-8a3e-f63292da486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387392063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3387392063
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1571426923
Short name T820
Test name
Test status
Simulation time 274813311683 ps
CPU time 304.89 seconds
Started Jul 09 04:33:23 PM PDT 24
Finished Jul 09 04:38:29 PM PDT 24
Peak memory 199776 kb
Host smart-6a5ea078-0a8e-4fb4-b5c3-fdc8739e3be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571426923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1571426923
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.779225368
Short name T845
Test name
Test status
Simulation time 77163413060 ps
CPU time 124.64 seconds
Started Jul 09 04:33:25 PM PDT 24
Finished Jul 09 04:35:30 PM PDT 24
Peak memory 199928 kb
Host smart-31948ed1-6943-426a-af8b-84c4691baf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779225368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.779225368
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.706121617
Short name T158
Test name
Test status
Simulation time 66988906843 ps
CPU time 17.45 seconds
Started Jul 09 04:33:25 PM PDT 24
Finished Jul 09 04:33:43 PM PDT 24
Peak memory 199748 kb
Host smart-f5c9d524-fb27-4c44-ac7d-dddb15e09d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706121617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.706121617
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4131262273
Short name T569
Test name
Test status
Simulation time 186514341165 ps
CPU time 84.47 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:34:53 PM PDT 24
Peak memory 199792 kb
Host smart-891ec02e-91ee-43a5-ae01-4b6f617a26f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131262273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4131262273
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1113473071
Short name T536
Test name
Test status
Simulation time 17103892 ps
CPU time 0.54 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:28 PM PDT 24
Peak memory 194056 kb
Host smart-b41c83ef-3cfa-4944-8f6d-fdb8000ca36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113473071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1113473071
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3880241989
Short name T40
Test name
Test status
Simulation time 69535748063 ps
CPU time 48.02 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:32:19 PM PDT 24
Peak memory 199844 kb
Host smart-e2038d76-3c44-4507-b8d0-427b05e66771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880241989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3880241989
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3658991637
Short name T865
Test name
Test status
Simulation time 39312644368 ps
CPU time 18.62 seconds
Started Jul 09 04:31:21 PM PDT 24
Finished Jul 09 04:31:57 PM PDT 24
Peak memory 199692 kb
Host smart-9adf2c7b-cc59-41d6-9469-0eea5ad09fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658991637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3658991637
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.646720915
Short name T755
Test name
Test status
Simulation time 112248589960 ps
CPU time 180.83 seconds
Started Jul 09 04:31:06 PM PDT 24
Finished Jul 09 04:34:25 PM PDT 24
Peak memory 199756 kb
Host smart-7854f917-3dd2-407a-b6a7-2678ce55c062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646720915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.646720915
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3489215878
Short name T293
Test name
Test status
Simulation time 64859505197 ps
CPU time 84.35 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:32:59 PM PDT 24
Peak memory 199792 kb
Host smart-cc0741ca-889c-46af-92e5-9aa740af555f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489215878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3489215878
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2134325999
Short name T692
Test name
Test status
Simulation time 72214242234 ps
CPU time 144.83 seconds
Started Jul 09 04:31:23 PM PDT 24
Finished Jul 09 04:34:04 PM PDT 24
Peak memory 199708 kb
Host smart-a2ea4d62-cd4c-4eaf-bfa5-e58d6833aa3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134325999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2134325999
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1725202921
Short name T817
Test name
Test status
Simulation time 9267249378 ps
CPU time 6.4 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:31:39 PM PDT 24
Peak memory 199588 kb
Host smart-d7b34785-539e-4489-9e00-ae70fd3e1893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725202921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1725202921
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2001566444
Short name T295
Test name
Test status
Simulation time 117911669635 ps
CPU time 37.54 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:33:10 PM PDT 24
Peak memory 199668 kb
Host smart-401dffa1-91f3-48d3-b651-701d87d78dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001566444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2001566444
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.303772997
Short name T702
Test name
Test status
Simulation time 10829813886 ps
CPU time 514.27 seconds
Started Jul 09 04:31:08 PM PDT 24
Finished Jul 09 04:40:00 PM PDT 24
Peak memory 199872 kb
Host smart-447b90c5-708d-4c4c-9dd5-06064aaf82b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303772997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.303772997
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.4120481107
Short name T607
Test name
Test status
Simulation time 1496229280 ps
CPU time 1.14 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:28 PM PDT 24
Peak memory 195408 kb
Host smart-61dbefa5-8ba3-4f27-be20-71a7aec7cac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120481107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.4120481107
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1971640467
Short name T815
Test name
Test status
Simulation time 63612150099 ps
CPU time 14.32 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:31:44 PM PDT 24
Peak memory 199604 kb
Host smart-01affc89-ac31-4c69-9ee2-9857ec4fbadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971640467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1971640467
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3449794737
Short name T766
Test name
Test status
Simulation time 5371610713 ps
CPU time 8.54 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:31:32 PM PDT 24
Peak memory 196260 kb
Host smart-b5c8db97-36db-4dc7-b992-202d3e600f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449794737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3449794737
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.520138127
Short name T876
Test name
Test status
Simulation time 648948444 ps
CPU time 2.59 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:31:35 PM PDT 24
Peak memory 198712 kb
Host smart-83232c00-7c03-4dc5-adc5-362dbb1f948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520138127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.520138127
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3842207074
Short name T477
Test name
Test status
Simulation time 401136690935 ps
CPU time 1341.6 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:53:57 PM PDT 24
Peak memory 199600 kb
Host smart-f71f35d9-f38b-4651-b9c1-2b746baa18ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842207074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3842207074
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3892854146
Short name T1068
Test name
Test status
Simulation time 94701711171 ps
CPU time 1041.66 seconds
Started Jul 09 04:31:17 PM PDT 24
Finished Jul 09 04:48:57 PM PDT 24
Peak memory 216468 kb
Host smart-e2f9d706-7a00-48ad-bf80-64e49b22c3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892854146 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3892854146
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3923448679
Short name T388
Test name
Test status
Simulation time 978991082 ps
CPU time 1.93 seconds
Started Jul 09 04:32:29 PM PDT 24
Finished Jul 09 04:32:35 PM PDT 24
Peak memory 198080 kb
Host smart-6a2a54e6-5a39-4954-869a-064771242525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923448679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3923448679
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1354600059
Short name T53
Test name
Test status
Simulation time 31878095334 ps
CPU time 41.21 seconds
Started Jul 09 04:31:10 PM PDT 24
Finished Jul 09 04:32:10 PM PDT 24
Peak memory 199836 kb
Host smart-71f697ab-6e6c-41aa-9859-53967ccb1cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354600059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1354600059
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2030469904
Short name T840
Test name
Test status
Simulation time 102310424156 ps
CPU time 231.33 seconds
Started Jul 09 04:33:28 PM PDT 24
Finished Jul 09 04:37:21 PM PDT 24
Peak memory 199776 kb
Host smart-b36adbed-d610-4c12-af72-ec2e255de601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030469904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2030469904
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2294950186
Short name T897
Test name
Test status
Simulation time 161705060970 ps
CPU time 266.09 seconds
Started Jul 09 04:33:23 PM PDT 24
Finished Jul 09 04:37:50 PM PDT 24
Peak memory 199736 kb
Host smart-ba9d0a38-b4c5-42b1-b96a-f2624bf1c7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294950186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2294950186
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.781183266
Short name T977
Test name
Test status
Simulation time 5893893116 ps
CPU time 14.53 seconds
Started Jul 09 04:33:25 PM PDT 24
Finished Jul 09 04:33:40 PM PDT 24
Peak memory 199816 kb
Host smart-1c8b496a-cf7a-4312-b7f4-e82237a839d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781183266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.781183266
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2039039727
Short name T189
Test name
Test status
Simulation time 59943933371 ps
CPU time 98.37 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:35:06 PM PDT 24
Peak memory 199772 kb
Host smart-cf996187-64fa-46dd-9e8d-9a45ffc08b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039039727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2039039727
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4159868177
Short name T850
Test name
Test status
Simulation time 29331065646 ps
CPU time 21.37 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:33:50 PM PDT 24
Peak memory 199820 kb
Host smart-07c5a82f-c277-4841-908a-96b18c809acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159868177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4159868177
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1110513543
Short name T960
Test name
Test status
Simulation time 95420880611 ps
CPU time 45.27 seconds
Started Jul 09 04:33:26 PM PDT 24
Finished Jul 09 04:34:12 PM PDT 24
Peak memory 199924 kb
Host smart-474af2f8-fd5e-47b6-9a81-141bb740329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110513543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1110513543
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3905741153
Short name T724
Test name
Test status
Simulation time 114492189408 ps
CPU time 176.32 seconds
Started Jul 09 04:33:28 PM PDT 24
Finished Jul 09 04:36:26 PM PDT 24
Peak memory 199884 kb
Host smart-87326a43-f63e-4ad7-a439-cd06752e40b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905741153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3905741153
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1182260062
Short name T397
Test name
Test status
Simulation time 81545692872 ps
CPU time 67.94 seconds
Started Jul 09 04:33:25 PM PDT 24
Finished Jul 09 04:34:34 PM PDT 24
Peak memory 199776 kb
Host smart-54463d67-70e8-4fe4-b9c1-5030b828a30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182260062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1182260062
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.456499303
Short name T1033
Test name
Test status
Simulation time 11100828 ps
CPU time 0.55 seconds
Started Jul 09 04:31:24 PM PDT 24
Finished Jul 09 04:31:40 PM PDT 24
Peak memory 195096 kb
Host smart-d108511e-a5ca-4e5d-a12b-e1f93d6b4742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456499303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.456499303
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1452892016
Short name T1048
Test name
Test status
Simulation time 25078101042 ps
CPU time 35.42 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:32:05 PM PDT 24
Peak memory 199752 kb
Host smart-381f4659-dd39-4ae7-ae8e-887ee00b1c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452892016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1452892016
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2090645456
Short name T1085
Test name
Test status
Simulation time 199978852889 ps
CPU time 56.96 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:32:27 PM PDT 24
Peak memory 199712 kb
Host smart-afe7150e-1b05-4643-adf9-dfabcb7917a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090645456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2090645456
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2288802332
Short name T403
Test name
Test status
Simulation time 71755904700 ps
CPU time 23.42 seconds
Started Jul 09 04:31:13 PM PDT 24
Finished Jul 09 04:31:56 PM PDT 24
Peak memory 199748 kb
Host smart-b82456e7-2a7c-431e-842b-61f2faa5955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288802332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2288802332
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.717177194
Short name T756
Test name
Test status
Simulation time 150515042897 ps
CPU time 123.31 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:33:36 PM PDT 24
Peak memory 199660 kb
Host smart-cbfa8b46-2f6a-49c2-94ad-d2c4ea375834
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717177194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.717177194
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.497422289
Short name T1101
Test name
Test status
Simulation time 97551323548 ps
CPU time 136.19 seconds
Started Jul 09 04:31:19 PM PDT 24
Finished Jul 09 04:33:52 PM PDT 24
Peak memory 199640 kb
Host smart-f4ac1c07-c16c-4518-a626-d0b060f3c6f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497422289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.497422289
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1589485918
Short name T619
Test name
Test status
Simulation time 2222610430 ps
CPU time 2.59 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:31:36 PM PDT 24
Peak memory 199448 kb
Host smart-faa8945e-f030-41d5-a599-7b5412bfb919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589485918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1589485918
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2585122532
Short name T746
Test name
Test status
Simulation time 14052215891 ps
CPU time 25.92 seconds
Started Jul 09 04:31:09 PM PDT 24
Finished Jul 09 04:31:53 PM PDT 24
Peak memory 200012 kb
Host smart-f68f84ba-7dbf-481e-9f6e-dabb923dad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585122532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2585122532
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.685753043
Short name T966
Test name
Test status
Simulation time 12751005231 ps
CPU time 144.25 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:34:01 PM PDT 24
Peak memory 199816 kb
Host smart-4e199bef-8e35-4027-ae70-2f8463736142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685753043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.685753043
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3243685124
Short name T603
Test name
Test status
Simulation time 5431014708 ps
CPU time 15.52 seconds
Started Jul 09 04:31:30 PM PDT 24
Finished Jul 09 04:31:58 PM PDT 24
Peak memory 198048 kb
Host smart-90d1b890-722c-461d-bb22-7571e572a9c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243685124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3243685124
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.992269994
Short name T378
Test name
Test status
Simulation time 10300976127 ps
CPU time 16.79 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:31:46 PM PDT 24
Peak memory 199740 kb
Host smart-3672ed64-47cb-4c22-8868-347bebc8baf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992269994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.992269994
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.251173546
Short name T441
Test name
Test status
Simulation time 40553776390 ps
CPU time 16.98 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:31:53 PM PDT 24
Peak memory 196264 kb
Host smart-769da369-08d0-45b5-948c-d388782e59fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251173546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.251173546
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1436746029
Short name T473
Test name
Test status
Simulation time 483801420 ps
CPU time 1.43 seconds
Started Jul 09 04:31:31 PM PDT 24
Finished Jul 09 04:31:44 PM PDT 24
Peak memory 198080 kb
Host smart-92e27ad9-4109-4852-9626-da6ba8c906ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436746029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1436746029
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1490534683
Short name T945
Test name
Test status
Simulation time 391966102442 ps
CPU time 884.08 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:46:18 PM PDT 24
Peak memory 199652 kb
Host smart-0567a281-fd44-4a2d-9d9f-7a09ca5e1522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490534683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1490534683
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.898482952
Short name T938
Test name
Test status
Simulation time 103226594596 ps
CPU time 1996.46 seconds
Started Jul 09 04:31:24 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 232992 kb
Host smart-81f23db2-ab31-4895-848e-3e65511cb6af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898482952 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.898482952
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2419660972
Short name T270
Test name
Test status
Simulation time 709848717 ps
CPU time 2.17 seconds
Started Jul 09 04:31:21 PM PDT 24
Finished Jul 09 04:31:40 PM PDT 24
Peak memory 198620 kb
Host smart-0cbca3a4-c198-41fa-a615-9443b28feb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419660972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2419660972
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1730980176
Short name T1143
Test name
Test status
Simulation time 44417676035 ps
CPU time 41.96 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:32:13 PM PDT 24
Peak memory 199724 kb
Host smart-768c7cfd-4d30-41c4-896b-21dd12b47ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730980176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1730980176
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2753310920
Short name T212
Test name
Test status
Simulation time 37796151428 ps
CPU time 50.62 seconds
Started Jul 09 04:33:26 PM PDT 24
Finished Jul 09 04:34:17 PM PDT 24
Peak memory 199744 kb
Host smart-6106ddd2-b810-436e-adfd-58c2fa2b3533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753310920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2753310920
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.711977808
Short name T187
Test name
Test status
Simulation time 26276098830 ps
CPU time 23.78 seconds
Started Jul 09 04:33:25 PM PDT 24
Finished Jul 09 04:33:49 PM PDT 24
Peak memory 199724 kb
Host smart-87a4d04c-db20-4c9c-9f5f-9dc9d4f210ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711977808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.711977808
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1236976760
Short name T793
Test name
Test status
Simulation time 55185516293 ps
CPU time 16.5 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:33:44 PM PDT 24
Peak memory 199816 kb
Host smart-1a3f2cb6-69ce-49ee-b36d-866a96cbd19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236976760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1236976760
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.469923651
Short name T313
Test name
Test status
Simulation time 172685733097 ps
CPU time 99.57 seconds
Started Jul 09 04:33:26 PM PDT 24
Finished Jul 09 04:35:06 PM PDT 24
Peak memory 199804 kb
Host smart-7e629e76-f844-43a0-a99c-c6b28956081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469923651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.469923651
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.4011919241
Short name T143
Test name
Test status
Simulation time 20078956751 ps
CPU time 36.13 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:34:05 PM PDT 24
Peak memory 199768 kb
Host smart-f6f91e46-2b0a-49e0-a5b0-a048c74c8fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011919241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.4011919241
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1848911164
Short name T119
Test name
Test status
Simulation time 34037203082 ps
CPU time 53.93 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:34:22 PM PDT 24
Peak memory 199752 kb
Host smart-b2fccea5-6a32-44a3-9b2c-2b46754e078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848911164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1848911164
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3824919430
Short name T770
Test name
Test status
Simulation time 134165104187 ps
CPU time 104.29 seconds
Started Jul 09 04:33:32 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 199736 kb
Host smart-54b4ea2d-f078-482e-90a3-638cebc14607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824919430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3824919430
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3346306953
Short name T196
Test name
Test status
Simulation time 58893175756 ps
CPU time 56.02 seconds
Started Jul 09 04:33:30 PM PDT 24
Finished Jul 09 04:34:27 PM PDT 24
Peak memory 200120 kb
Host smart-89f6f5d2-f3cc-4ac6-a3c1-d30460871bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346306953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3346306953
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.4172977878
Short name T780
Test name
Test status
Simulation time 95640524350 ps
CPU time 43.34 seconds
Started Jul 09 04:33:29 PM PDT 24
Finished Jul 09 04:34:14 PM PDT 24
Peak memory 199632 kb
Host smart-da13b1c8-98e8-4cd4-8144-00872239f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172977878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.4172977878
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.936281080
Short name T583
Test name
Test status
Simulation time 223222773600 ps
CPU time 151.78 seconds
Started Jul 09 04:33:32 PM PDT 24
Finished Jul 09 04:36:05 PM PDT 24
Peak memory 199796 kb
Host smart-e025b845-04f9-432e-bb52-cf9c9903870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936281080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.936281080
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3660272085
Short name T490
Test name
Test status
Simulation time 12982663 ps
CPU time 0.56 seconds
Started Jul 09 04:31:27 PM PDT 24
Finished Jul 09 04:31:42 PM PDT 24
Peak memory 195488 kb
Host smart-24fa1297-d6b1-4514-8b9e-f727f92d5faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660272085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3660272085
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2788397435
Short name T277
Test name
Test status
Simulation time 308003681862 ps
CPU time 63.18 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:32:38 PM PDT 24
Peak memory 199760 kb
Host smart-515e0874-dbf2-43c9-8578-843117a0dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788397435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2788397435
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.221477700
Short name T460
Test name
Test status
Simulation time 84129950144 ps
CPU time 49.75 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:32:24 PM PDT 24
Peak memory 199880 kb
Host smart-551fd7fc-9479-428c-8eb1-50c821a7d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221477700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.221477700
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_intr.1078436080
Short name T949
Test name
Test status
Simulation time 173180445151 ps
CPU time 54.82 seconds
Started Jul 09 04:31:23 PM PDT 24
Finished Jul 09 04:32:34 PM PDT 24
Peak memory 199800 kb
Host smart-c24cd2a5-dce8-4567-9d24-a571f4515570
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078436080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1078436080
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2089862338
Short name T650
Test name
Test status
Simulation time 69409964079 ps
CPU time 590.7 seconds
Started Jul 09 04:31:23 PM PDT 24
Finished Jul 09 04:41:30 PM PDT 24
Peak memory 199644 kb
Host smart-f4990d63-146d-42ac-a904-1230ce84de89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089862338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2089862338
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1079635765
Short name T995
Test name
Test status
Simulation time 9752371934 ps
CPU time 19.85 seconds
Started Jul 09 04:31:22 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 199552 kb
Host smart-7336c00b-aad3-4ec9-8e44-98a91b1b4eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079635765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1079635765
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1846720273
Short name T454
Test name
Test status
Simulation time 9601112923 ps
CPU time 14.04 seconds
Started Jul 09 04:31:14 PM PDT 24
Finished Jul 09 04:31:47 PM PDT 24
Peak memory 199644 kb
Host smart-b49f170d-f6e0-45ba-a222-0cc67cd9516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846720273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1846720273
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1706858920
Short name T302
Test name
Test status
Simulation time 6283743950 ps
CPU time 293.85 seconds
Started Jul 09 04:31:25 PM PDT 24
Finished Jul 09 04:36:34 PM PDT 24
Peak memory 199792 kb
Host smart-92f3fdf4-ab13-45bd-8231-b5c861faa30f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706858920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1706858920
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1399231830
Short name T1172
Test name
Test status
Simulation time 2248303187 ps
CPU time 1.94 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:31:37 PM PDT 24
Peak memory 197832 kb
Host smart-f6fd263d-f8b8-4c47-85cf-e59cb360e78d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399231830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1399231830
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2872371648
Short name T49
Test name
Test status
Simulation time 22381679592 ps
CPU time 24.93 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:31:56 PM PDT 24
Peak memory 199828 kb
Host smart-bb1a2d6b-4e09-4188-8e39-e754f9a7e01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872371648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2872371648
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3752819124
Short name T791
Test name
Test status
Simulation time 34806758479 ps
CPU time 13.47 seconds
Started Jul 09 04:31:22 PM PDT 24
Finished Jul 09 04:31:52 PM PDT 24
Peak memory 196216 kb
Host smart-9eac6129-8a0e-4aca-bb5c-f9a43fd7e939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752819124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3752819124
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.959145542
Short name T1103
Test name
Test status
Simulation time 6041463686 ps
CPU time 24.1 seconds
Started Jul 09 04:31:19 PM PDT 24
Finished Jul 09 04:32:01 PM PDT 24
Peak memory 199828 kb
Host smart-bda9b4ac-79e5-4b07-b3fd-bdf91535b3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959145542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.959145542
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1857499844
Short name T928
Test name
Test status
Simulation time 75539905569 ps
CPU time 479.13 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 199736 kb
Host smart-ea1066ef-6e77-416f-9189-1fc57aad507c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857499844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1857499844
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2202306527
Short name T691
Test name
Test status
Simulation time 95643353153 ps
CPU time 263.78 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:35:57 PM PDT 24
Peak memory 208652 kb
Host smart-1cda7e7c-7475-4528-aea5-b85549d6db51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202306527 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2202306527
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1420882356
Short name T675
Test name
Test status
Simulation time 7010705639 ps
CPU time 23.58 seconds
Started Jul 09 04:31:38 PM PDT 24
Finished Jul 09 04:32:10 PM PDT 24
Peak memory 199812 kb
Host smart-169825f0-40f2-431b-a491-7199d656e05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420882356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1420882356
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2629536429
Short name T343
Test name
Test status
Simulation time 74341600508 ps
CPU time 120.49 seconds
Started Jul 09 04:31:11 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 199788 kb
Host smart-099d65ec-fbcd-4bfd-b606-ef83dc5dc1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629536429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2629536429
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.597910307
Short name T1131
Test name
Test status
Simulation time 22261193051 ps
CPU time 9.6 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:33:37 PM PDT 24
Peak memory 199552 kb
Host smart-082a758f-3a9f-4f88-b9ad-0ef52958d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597910307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.597910307
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2660308914
Short name T464
Test name
Test status
Simulation time 69730166378 ps
CPU time 14.36 seconds
Started Jul 09 04:33:28 PM PDT 24
Finished Jul 09 04:33:44 PM PDT 24
Peak memory 199524 kb
Host smart-caeb749e-5eab-426b-a5e2-007ffa192f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660308914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2660308914
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.602563651
Short name T723
Test name
Test status
Simulation time 40884759930 ps
CPU time 21.62 seconds
Started Jul 09 04:33:29 PM PDT 24
Finished Jul 09 04:33:52 PM PDT 24
Peak memory 199792 kb
Host smart-012dabb5-104d-4c6b-aa14-08021c849a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602563651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.602563651
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3362421000
Short name T917
Test name
Test status
Simulation time 186429056859 ps
CPU time 64.26 seconds
Started Jul 09 04:33:31 PM PDT 24
Finished Jul 09 04:34:36 PM PDT 24
Peak memory 199916 kb
Host smart-bb9c3bc7-5292-4d9f-8bd2-c84f26a9211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362421000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3362421000
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1777008813
Short name T615
Test name
Test status
Simulation time 35302093521 ps
CPU time 48.1 seconds
Started Jul 09 04:33:37 PM PDT 24
Finished Jul 09 04:34:26 PM PDT 24
Peak memory 199788 kb
Host smart-fa24e8bb-9845-494f-a923-9dc8185761b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777008813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1777008813
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2879971528
Short name T350
Test name
Test status
Simulation time 155127668345 ps
CPU time 27.76 seconds
Started Jul 09 04:33:27 PM PDT 24
Finished Jul 09 04:33:56 PM PDT 24
Peak memory 199704 kb
Host smart-ee5201d7-c939-410a-9293-e6752aa03c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879971528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2879971528
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2974435729
Short name T556
Test name
Test status
Simulation time 27867086809 ps
CPU time 21.24 seconds
Started Jul 09 04:33:34 PM PDT 24
Finished Jul 09 04:33:56 PM PDT 24
Peak memory 199736 kb
Host smart-f59a3e52-9296-421c-a749-959d6bf45d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974435729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2974435729
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.483108007
Short name T1170
Test name
Test status
Simulation time 42079262772 ps
CPU time 13.31 seconds
Started Jul 09 04:33:28 PM PDT 24
Finished Jul 09 04:33:42 PM PDT 24
Peak memory 199600 kb
Host smart-1843c164-44a8-4818-9899-5a2869ba600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483108007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.483108007
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3454827543
Short name T394
Test name
Test status
Simulation time 105106650934 ps
CPU time 44.54 seconds
Started Jul 09 04:33:29 PM PDT 24
Finished Jul 09 04:34:15 PM PDT 24
Peak memory 199700 kb
Host smart-cd2764ae-67b5-4f87-81da-ae9e99de67a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454827543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3454827543
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1757923618
Short name T549
Test name
Test status
Simulation time 129022474100 ps
CPU time 194.54 seconds
Started Jul 09 04:33:28 PM PDT 24
Finished Jul 09 04:36:43 PM PDT 24
Peak memory 199776 kb
Host smart-71f54580-ec5c-4c01-bb55-8db6f4f1c553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757923618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1757923618
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1396117981
Short name T443
Test name
Test status
Simulation time 14259214 ps
CPU time 0.55 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:31:34 PM PDT 24
Peak memory 195220 kb
Host smart-62fa75c8-0568-424a-8623-2b55e77e8a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396117981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1396117981
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3856467447
Short name T941
Test name
Test status
Simulation time 60969657432 ps
CPU time 48.85 seconds
Started Jul 09 04:31:33 PM PDT 24
Finished Jul 09 04:32:33 PM PDT 24
Peak memory 199676 kb
Host smart-ab43f95e-c5b9-466f-9c37-9a20280271b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856467447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3856467447
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1997351161
Short name T1007
Test name
Test status
Simulation time 105200522402 ps
CPU time 86.37 seconds
Started Jul 09 04:31:24 PM PDT 24
Finished Jul 09 04:33:06 PM PDT 24
Peak memory 199776 kb
Host smart-a7d044e0-0c0e-4a14-9e4f-6f85024293a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997351161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1997351161
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2336093251
Short name T539
Test name
Test status
Simulation time 103427508965 ps
CPU time 144.04 seconds
Started Jul 09 04:31:38 PM PDT 24
Finished Jul 09 04:34:10 PM PDT 24
Peak memory 199792 kb
Host smart-76835e8d-2881-4868-948e-999ef23afa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336093251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2336093251
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2486149530
Short name T564
Test name
Test status
Simulation time 28836400610 ps
CPU time 17.13 seconds
Started Jul 09 04:31:15 PM PDT 24
Finished Jul 09 04:31:50 PM PDT 24
Peak memory 199640 kb
Host smart-147c7a25-c67f-49e3-88aa-77e932d1dffc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486149530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2486149530
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2009154846
Short name T943
Test name
Test status
Simulation time 34311861157 ps
CPU time 108.2 seconds
Started Jul 09 04:31:16 PM PDT 24
Finished Jul 09 04:33:23 PM PDT 24
Peak memory 199804 kb
Host smart-da786048-d61e-48d4-b092-c203e8c36baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009154846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2009154846
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2121010617
Short name T839
Test name
Test status
Simulation time 5533886282 ps
CPU time 3.4 seconds
Started Jul 09 04:31:38 PM PDT 24
Finished Jul 09 04:31:50 PM PDT 24
Peak memory 198764 kb
Host smart-0d174f55-eabb-4e50-b576-3a390cd4eb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121010617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2121010617
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1676591263
Short name T915
Test name
Test status
Simulation time 160956428182 ps
CPU time 70.9 seconds
Started Jul 09 04:31:40 PM PDT 24
Finished Jul 09 04:32:59 PM PDT 24
Peak memory 199228 kb
Host smart-adb3d6ef-b8f0-4bc0-ba08-6a0cba2531ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676591263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1676591263
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3160582741
Short name T1040
Test name
Test status
Simulation time 9621176290 ps
CPU time 122.98 seconds
Started Jul 09 04:31:29 PM PDT 24
Finished Jul 09 04:33:45 PM PDT 24
Peak memory 199776 kb
Host smart-a363c933-8fd6-45e5-93b6-b691c64303d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160582741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3160582741
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4229547682
Short name T1168
Test name
Test status
Simulation time 4025107431 ps
CPU time 8.43 seconds
Started Jul 09 04:31:21 PM PDT 24
Finished Jul 09 04:31:46 PM PDT 24
Peak memory 198120 kb
Host smart-c5a620fa-39bf-4992-8d2e-6da408f59c8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229547682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4229547682
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.853508584
Short name T137
Test name
Test status
Simulation time 319921003801 ps
CPU time 46.71 seconds
Started Jul 09 04:31:37 PM PDT 24
Finished Jul 09 04:32:32 PM PDT 24
Peak memory 199796 kb
Host smart-67dea2a7-f305-41cc-9278-ead15769975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853508584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.853508584
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2238757204
Short name T1106
Test name
Test status
Simulation time 4062591791 ps
CPU time 1.57 seconds
Started Jul 09 04:31:25 PM PDT 24
Finished Jul 09 04:31:42 PM PDT 24
Peak memory 196600 kb
Host smart-602bcbf0-7c30-4155-96e9-3dc1f5f53783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238757204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2238757204
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1123033944
Short name T342
Test name
Test status
Simulation time 660051679 ps
CPU time 2.41 seconds
Started Jul 09 04:31:12 PM PDT 24
Finished Jul 09 04:31:33 PM PDT 24
Peak memory 198244 kb
Host smart-3fce0329-4a55-43c3-a09f-f9bc82fb1d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123033944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1123033944
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.325300818
Short name T655
Test name
Test status
Simulation time 232092120131 ps
CPU time 112.57 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:33:39 PM PDT 24
Peak memory 216072 kb
Host smart-51bd9da1-b263-4e92-9810-802e771dfc5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325300818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.325300818
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3203403192
Short name T175
Test name
Test status
Simulation time 228747655933 ps
CPU time 1130.97 seconds
Started Jul 09 04:31:31 PM PDT 24
Finished Jul 09 04:50:34 PM PDT 24
Peak memory 224696 kb
Host smart-8d915c68-ac1d-428a-b9da-b9092f65cc11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203403192 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3203403192
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.723462360
Short name T467
Test name
Test status
Simulation time 6421992013 ps
CPU time 23.36 seconds
Started Jul 09 04:31:37 PM PDT 24
Finished Jul 09 04:32:09 PM PDT 24
Peak memory 199044 kb
Host smart-2858b643-b18b-4276-b2db-0e4974777482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723462360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.723462360
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3859993466
Short name T693
Test name
Test status
Simulation time 36903900930 ps
CPU time 57.5 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:32:34 PM PDT 24
Peak memory 199688 kb
Host smart-40806134-2b1f-4c27-ba41-da9f58acafcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859993466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3859993466
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3051837659
Short name T247
Test name
Test status
Simulation time 156162806010 ps
CPU time 23.1 seconds
Started Jul 09 04:33:33 PM PDT 24
Finished Jul 09 04:33:58 PM PDT 24
Peak memory 199736 kb
Host smart-bf47ca15-f172-42cb-94d2-18c93b868f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051837659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3051837659
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.355511132
Short name T809
Test name
Test status
Simulation time 58434354294 ps
CPU time 50.2 seconds
Started Jul 09 04:33:37 PM PDT 24
Finished Jul 09 04:34:28 PM PDT 24
Peak memory 199816 kb
Host smart-b9eadcb4-ed00-4133-bfcb-17a5861bb661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355511132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.355511132
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3220723648
Short name T1005
Test name
Test status
Simulation time 14425846108 ps
CPU time 21.48 seconds
Started Jul 09 04:33:29 PM PDT 24
Finished Jul 09 04:33:51 PM PDT 24
Peak memory 199832 kb
Host smart-e0d0d683-dac0-454f-bb38-2bc175ad262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220723648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3220723648
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2866644362
Short name T185
Test name
Test status
Simulation time 15425764746 ps
CPU time 34.09 seconds
Started Jul 09 04:33:31 PM PDT 24
Finished Jul 09 04:34:06 PM PDT 24
Peak memory 199856 kb
Host smart-7c50ca79-949f-4be0-a73c-2e16ba2f51a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866644362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2866644362
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2973546952
Short name T1032
Test name
Test status
Simulation time 22963640449 ps
CPU time 47.17 seconds
Started Jul 09 04:33:39 PM PDT 24
Finished Jul 09 04:34:27 PM PDT 24
Peak memory 199780 kb
Host smart-a52bf517-765c-4dbc-8ab3-3982289df9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973546952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2973546952
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.530790177
Short name T618
Test name
Test status
Simulation time 89059740826 ps
CPU time 38.73 seconds
Started Jul 09 04:33:33 PM PDT 24
Finished Jul 09 04:34:12 PM PDT 24
Peak memory 199740 kb
Host smart-e96d310a-12cb-4cdc-9cb4-b62fc2725d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530790177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.530790177
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1339565337
Short name T877
Test name
Test status
Simulation time 18161355919 ps
CPU time 28.62 seconds
Started Jul 09 04:33:33 PM PDT 24
Finished Jul 09 04:34:03 PM PDT 24
Peak memory 199696 kb
Host smart-770db84f-75b9-423c-ba2a-d4227e432068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339565337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1339565337
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1429484373
Short name T517
Test name
Test status
Simulation time 12226334546 ps
CPU time 19.09 seconds
Started Jul 09 04:33:34 PM PDT 24
Finished Jul 09 04:33:55 PM PDT 24
Peak memory 199696 kb
Host smart-1e99d456-031b-4d1e-a72a-6c0b9286eb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429484373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1429484373
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2512087879
Short name T204
Test name
Test status
Simulation time 115614653666 ps
CPU time 188.9 seconds
Started Jul 09 04:33:34 PM PDT 24
Finished Jul 09 04:36:44 PM PDT 24
Peak memory 199744 kb
Host smart-8f7ac467-7798-48be-b5be-abc62743c14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512087879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2512087879
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1746508119
Short name T100
Test name
Test status
Simulation time 223623947 ps
CPU time 0.59 seconds
Started Jul 09 04:31:36 PM PDT 24
Finished Jul 09 04:31:45 PM PDT 24
Peak memory 195100 kb
Host smart-4cffb4b9-c8fe-431f-ad4d-d8f2ca834606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746508119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1746508119
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.77106639
Short name T728
Test name
Test status
Simulation time 171251026733 ps
CPU time 242.21 seconds
Started Jul 09 04:31:18 PM PDT 24
Finished Jul 09 04:35:38 PM PDT 24
Peak memory 199876 kb
Host smart-6afa5ebd-1cc6-4ec6-b1ce-f398005f497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77106639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.77106639
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1797846651
Short name T667
Test name
Test status
Simulation time 192801749589 ps
CPU time 18.47 seconds
Started Jul 09 04:31:23 PM PDT 24
Finished Jul 09 04:31:58 PM PDT 24
Peak memory 198952 kb
Host smart-9fd6259a-ae78-4078-b3b9-90b9c91c6fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797846651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1797846651
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.456014803
Short name T735
Test name
Test status
Simulation time 78702724803 ps
CPU time 458.8 seconds
Started Jul 09 04:31:22 PM PDT 24
Finished Jul 09 04:39:18 PM PDT 24
Peak memory 199716 kb
Host smart-69120e30-f046-4675-b44d-6297f24eff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456014803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.456014803
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1370508070
Short name T268
Test name
Test status
Simulation time 112771092478 ps
CPU time 368.04 seconds
Started Jul 09 04:31:35 PM PDT 24
Finished Jul 09 04:37:53 PM PDT 24
Peak memory 199764 kb
Host smart-f4b75f77-4742-4235-9924-eeca5326627d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370508070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1370508070
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2981247179
Short name T1102
Test name
Test status
Simulation time 171400660445 ps
CPU time 648.06 seconds
Started Jul 09 04:31:40 PM PDT 24
Finished Jul 09 04:42:36 PM PDT 24
Peak memory 199796 kb
Host smart-164d311c-7a9b-4cdb-b792-aafc7d602581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981247179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2981247179
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.141576652
Short name T345
Test name
Test status
Simulation time 8227983593 ps
CPU time 18.7 seconds
Started Jul 09 04:31:44 PM PDT 24
Finished Jul 09 04:32:10 PM PDT 24
Peak memory 199216 kb
Host smart-04d6b161-0043-41e4-b3d4-4b1f5790448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141576652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.141576652
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.760154548
Short name T1112
Test name
Test status
Simulation time 92344239675 ps
CPU time 45.36 seconds
Started Jul 09 04:31:21 PM PDT 24
Finished Jul 09 04:32:23 PM PDT 24
Peak memory 199384 kb
Host smart-db222eb0-7274-438e-8a83-22efaffaac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760154548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.760154548
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1992691049
Short name T1129
Test name
Test status
Simulation time 15895096030 ps
CPU time 49.69 seconds
Started Jul 09 04:31:22 PM PDT 24
Finished Jul 09 04:32:28 PM PDT 24
Peak memory 199756 kb
Host smart-e34341b6-f454-452d-a16f-f161f5478fe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992691049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1992691049
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.4090212439
Short name T547
Test name
Test status
Simulation time 6338892066 ps
CPU time 49.2 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:32:36 PM PDT 24
Peak memory 199812 kb
Host smart-94d33a93-2755-431f-b5f4-37990efa44e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090212439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.4090212439
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2059439280
Short name T118
Test name
Test status
Simulation time 91266541036 ps
CPU time 35.89 seconds
Started Jul 09 04:31:27 PM PDT 24
Finished Jul 09 04:32:17 PM PDT 24
Peak memory 199584 kb
Host smart-b07c3f61-f8e5-4e47-b7de-c3bb64388121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059439280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2059439280
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3448402511
Short name T1050
Test name
Test status
Simulation time 2960386918 ps
CPU time 1.57 seconds
Started Jul 09 04:31:40 PM PDT 24
Finished Jul 09 04:31:49 PM PDT 24
Peak memory 195752 kb
Host smart-56d1244c-2789-45ce-810c-173f3e3c98ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448402511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3448402511
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3066456537
Short name T831
Test name
Test status
Simulation time 873814760 ps
CPU time 2.19 seconds
Started Jul 09 04:31:43 PM PDT 24
Finished Jul 09 04:31:53 PM PDT 24
Peak memory 198716 kb
Host smart-3e638819-fbf7-410a-9f6c-74f1d026571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066456537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3066456537
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1320861434
Short name T771
Test name
Test status
Simulation time 278382651509 ps
CPU time 122.6 seconds
Started Jul 09 04:31:21 PM PDT 24
Finished Jul 09 04:33:41 PM PDT 24
Peak memory 199724 kb
Host smart-e19968fb-f62a-49e6-a000-c57aa00b77b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320861434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1320861434
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.4031493206
Short name T774
Test name
Test status
Simulation time 3311685730 ps
CPU time 2.34 seconds
Started Jul 09 04:31:23 PM PDT 24
Finished Jul 09 04:31:41 PM PDT 24
Peak memory 199144 kb
Host smart-460e57d0-8d73-4880-8557-02a409c06f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031493206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4031493206
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3135776641
Short name T1174
Test name
Test status
Simulation time 55947207832 ps
CPU time 9.59 seconds
Started Jul 09 04:31:36 PM PDT 24
Finished Jul 09 04:31:55 PM PDT 24
Peak memory 199744 kb
Host smart-9015b952-d805-4779-ab41-ec0e63de7b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135776641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3135776641
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1519454859
Short name T252
Test name
Test status
Simulation time 103585914456 ps
CPU time 33.15 seconds
Started Jul 09 04:33:34 PM PDT 24
Finished Jul 09 04:34:08 PM PDT 24
Peak memory 199292 kb
Host smart-f34e5b50-eff0-4821-8e98-5ecae937f98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519454859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1519454859
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2962801223
Short name T216
Test name
Test status
Simulation time 248823434669 ps
CPU time 51.69 seconds
Started Jul 09 04:33:38 PM PDT 24
Finished Jul 09 04:34:31 PM PDT 24
Peak memory 199852 kb
Host smart-ad4a283d-217e-40f0-8ee2-171e20dc3121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962801223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2962801223
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2880003086
Short name T1167
Test name
Test status
Simulation time 56110418728 ps
CPU time 39.28 seconds
Started Jul 09 04:33:32 PM PDT 24
Finished Jul 09 04:34:12 PM PDT 24
Peak memory 199832 kb
Host smart-b5284818-d740-4029-a2a6-effb49aedc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880003086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2880003086
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2005994296
Short name T1031
Test name
Test status
Simulation time 38743855469 ps
CPU time 19.74 seconds
Started Jul 09 04:33:33 PM PDT 24
Finished Jul 09 04:33:54 PM PDT 24
Peak memory 199652 kb
Host smart-212835cb-1abe-4aab-8c2c-a9f4fa33c6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005994296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2005994296
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.974891081
Short name T1114
Test name
Test status
Simulation time 170282710759 ps
CPU time 93.25 seconds
Started Jul 09 04:33:38 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 199892 kb
Host smart-429ce1c9-6e56-43c7-a4c4-0791a0905d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974891081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.974891081
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3286141414
Short name T1008
Test name
Test status
Simulation time 60939473794 ps
CPU time 49.69 seconds
Started Jul 09 04:33:39 PM PDT 24
Finished Jul 09 04:34:30 PM PDT 24
Peak memory 199796 kb
Host smart-1620b53d-ef38-400b-8f3f-b33bf89413b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286141414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3286141414
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.800228792
Short name T198
Test name
Test status
Simulation time 9613206416 ps
CPU time 6.88 seconds
Started Jul 09 04:33:32 PM PDT 24
Finished Jul 09 04:33:40 PM PDT 24
Peak memory 199772 kb
Host smart-8a87aa4f-755a-46e6-a6e1-72cce0ff5be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800228792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.800228792
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2864597253
Short name T634
Test name
Test status
Simulation time 32038302622 ps
CPU time 22.52 seconds
Started Jul 09 04:33:34 PM PDT 24
Finished Jul 09 04:33:58 PM PDT 24
Peak memory 199632 kb
Host smart-0b50654a-e25b-451d-9b37-18c6dc4a2d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864597253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2864597253
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.367586517
Short name T195
Test name
Test status
Simulation time 15530847277 ps
CPU time 23.43 seconds
Started Jul 09 04:33:38 PM PDT 24
Finished Jul 09 04:34:03 PM PDT 24
Peak memory 199848 kb
Host smart-51fd9b2d-a28e-494d-a026-639f7683605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367586517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.367586517
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1185250370
Short name T1146
Test name
Test status
Simulation time 105053385 ps
CPU time 0.53 seconds
Started Jul 09 04:31:41 PM PDT 24
Finished Jul 09 04:31:49 PM PDT 24
Peak memory 195120 kb
Host smart-9a6134a0-ccd9-4c85-a3a8-22c9145f51ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185250370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1185250370
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1941258549
Short name T695
Test name
Test status
Simulation time 42791450661 ps
CPU time 23.01 seconds
Started Jul 09 04:31:22 PM PDT 24
Finished Jul 09 04:32:02 PM PDT 24
Peak memory 199776 kb
Host smart-8023a486-7936-428e-baee-4b436c933849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941258549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1941258549
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1188279490
Short name T1156
Test name
Test status
Simulation time 45347013532 ps
CPU time 71.28 seconds
Started Jul 09 04:31:41 PM PDT 24
Finished Jul 09 04:33:00 PM PDT 24
Peak memory 199768 kb
Host smart-7b2db80d-7db7-4e2c-9d1f-db87966b9513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188279490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1188279490
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2369741337
Short name T833
Test name
Test status
Simulation time 30522557607 ps
CPU time 51.34 seconds
Started Jul 09 04:31:21 PM PDT 24
Finished Jul 09 04:32:29 PM PDT 24
Peak memory 199728 kb
Host smart-0d44bc66-bf1e-4f6b-824d-2ae2c5e7d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369741337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2369741337
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1673258547
Short name T366
Test name
Test status
Simulation time 70607160461 ps
CPU time 138.66 seconds
Started Jul 09 04:31:22 PM PDT 24
Finished Jul 09 04:33:57 PM PDT 24
Peak memory 199620 kb
Host smart-b2877d2d-23b7-4009-885e-a3d32a25b31f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673258547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1673258547
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.4180047805
Short name T974
Test name
Test status
Simulation time 106361797655 ps
CPU time 415.29 seconds
Started Jul 09 04:31:27 PM PDT 24
Finished Jul 09 04:38:36 PM PDT 24
Peak memory 199720 kb
Host smart-36d614dd-657b-4fbd-bb35-96cd8de37d94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180047805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.4180047805
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1661307312
Short name T572
Test name
Test status
Simulation time 9240084946 ps
CPU time 18.04 seconds
Started Jul 09 04:31:44 PM PDT 24
Finished Jul 09 04:32:09 PM PDT 24
Peak memory 199724 kb
Host smart-4f93b4b8-607d-4954-b1cf-1b56215ed4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661307312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1661307312
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1156423391
Short name T360
Test name
Test status
Simulation time 34500196255 ps
CPU time 13.6 seconds
Started Jul 09 04:31:33 PM PDT 24
Finished Jul 09 04:31:57 PM PDT 24
Peak memory 199876 kb
Host smart-76ed9009-b121-4136-8718-cf1449db96c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156423391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1156423391
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2385002664
Short name T598
Test name
Test status
Simulation time 2714225008 ps
CPU time 83.5 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:33:11 PM PDT 24
Peak memory 199768 kb
Host smart-d1c93530-fc5b-4c49-b482-68f787111a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385002664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2385002664
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1482685980
Short name T23
Test name
Test status
Simulation time 3053333664 ps
CPU time 21.74 seconds
Started Jul 09 04:31:26 PM PDT 24
Finished Jul 09 04:32:02 PM PDT 24
Peak memory 198284 kb
Host smart-3e27ef57-bf47-4d2a-a694-a0f7aa5a8500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482685980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1482685980
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2599469913
Short name T1001
Test name
Test status
Simulation time 54664482538 ps
CPU time 75.3 seconds
Started Jul 09 04:31:32 PM PDT 24
Finished Jul 09 04:32:59 PM PDT 24
Peak memory 199668 kb
Host smart-c4131978-3f48-4b9f-8bdf-8401a955b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599469913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2599469913
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3136386585
Short name T1024
Test name
Test status
Simulation time 34956123854 ps
CPU time 51.35 seconds
Started Jul 09 04:31:24 PM PDT 24
Finished Jul 09 04:32:31 PM PDT 24
Peak memory 195592 kb
Host smart-b140152f-2262-4313-bf81-f5af869e68fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136386585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3136386585
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1800145375
Short name T265
Test name
Test status
Simulation time 92701186 ps
CPU time 0.71 seconds
Started Jul 09 04:31:23 PM PDT 24
Finished Jul 09 04:31:40 PM PDT 24
Peak memory 196440 kb
Host smart-3425aa1f-e8a3-454c-a1e3-392cf00f52eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800145375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1800145375
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2413729193
Short name T1054
Test name
Test status
Simulation time 486637223790 ps
CPU time 1324.8 seconds
Started Jul 09 04:31:28 PM PDT 24
Finished Jul 09 04:53:47 PM PDT 24
Peak memory 224520 kb
Host smart-cd31e962-ed60-4257-8662-93de36b156a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413729193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2413729193
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2883237803
Short name T383
Test name
Test status
Simulation time 6396917894 ps
CPU time 20.62 seconds
Started Jul 09 04:31:26 PM PDT 24
Finished Jul 09 04:32:01 PM PDT 24
Peak memory 199764 kb
Host smart-15dcc867-2457-4e51-ac4a-8ee2693f0e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883237803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2883237803
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2690434121
Short name T800
Test name
Test status
Simulation time 12215324040 ps
CPU time 18.89 seconds
Started Jul 09 04:31:21 PM PDT 24
Finished Jul 09 04:31:57 PM PDT 24
Peak memory 199700 kb
Host smart-2ae8f9d0-009d-4cdb-82a9-d42bfaa6261a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690434121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2690434121
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1972677761
Short name T718
Test name
Test status
Simulation time 195421142742 ps
CPU time 98.3 seconds
Started Jul 09 04:33:34 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 199708 kb
Host smart-db2f603d-cd2e-4aef-ba0a-2d78d766f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972677761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1972677761
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3983049980
Short name T315
Test name
Test status
Simulation time 22321624003 ps
CPU time 36.54 seconds
Started Jul 09 04:33:33 PM PDT 24
Finished Jul 09 04:34:11 PM PDT 24
Peak memory 200104 kb
Host smart-0f662dcd-d291-450f-803e-3087a57d5603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983049980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3983049980
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2762751988
Short name T998
Test name
Test status
Simulation time 14324363975 ps
CPU time 15.47 seconds
Started Jul 09 04:33:33 PM PDT 24
Finished Jul 09 04:33:50 PM PDT 24
Peak memory 199872 kb
Host smart-bfedbf8e-91fb-444e-99e3-6d8294237847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762751988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2762751988
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.421384282
Short name T483
Test name
Test status
Simulation time 33450242572 ps
CPU time 51.81 seconds
Started Jul 09 04:33:40 PM PDT 24
Finished Jul 09 04:34:33 PM PDT 24
Peak memory 199796 kb
Host smart-b899106d-c884-4bdd-8836-acff2bff237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421384282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.421384282
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.145584875
Short name T805
Test name
Test status
Simulation time 75212248581 ps
CPU time 65.17 seconds
Started Jul 09 04:33:32 PM PDT 24
Finished Jul 09 04:34:38 PM PDT 24
Peak memory 199696 kb
Host smart-a57f3841-808a-4b7a-b003-a71824d70be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145584875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.145584875
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1992047064
Short name T823
Test name
Test status
Simulation time 6080725588 ps
CPU time 9.47 seconds
Started Jul 09 04:33:32 PM PDT 24
Finished Jul 09 04:33:42 PM PDT 24
Peak memory 199724 kb
Host smart-abef9ea5-a380-4515-93d3-ab249c02e126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992047064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1992047064
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.231479279
Short name T625
Test name
Test status
Simulation time 147767854340 ps
CPU time 58.19 seconds
Started Jul 09 04:33:39 PM PDT 24
Finished Jul 09 04:34:38 PM PDT 24
Peak memory 199760 kb
Host smart-f294047f-d4c7-464d-914a-2671417f70eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231479279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.231479279
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.208510939
Short name T903
Test name
Test status
Simulation time 13692438 ps
CPU time 0.53 seconds
Started Jul 09 04:30:28 PM PDT 24
Finished Jul 09 04:30:33 PM PDT 24
Peak memory 194100 kb
Host smart-37aa4d38-6914-47ce-9f3a-1e110e11e633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208510939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.208510939
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2968260705
Short name T632
Test name
Test status
Simulation time 55646492612 ps
CPU time 76.23 seconds
Started Jul 09 04:30:50 PM PDT 24
Finished Jul 09 04:32:09 PM PDT 24
Peak memory 200168 kb
Host smart-82f0f699-6a8d-4b56-bbd9-8418bf951047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968260705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2968260705
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1222041136
Short name T965
Test name
Test status
Simulation time 39538974055 ps
CPU time 65.94 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:31:35 PM PDT 24
Peak memory 199704 kb
Host smart-b7b973e7-0756-4bff-8724-7aa1bdcea976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222041136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1222041136
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2328743327
Short name T742
Test name
Test status
Simulation time 63756585773 ps
CPU time 97.79 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:32:05 PM PDT 24
Peak memory 199700 kb
Host smart-11ee3d47-ebe5-4590-bf76-94dd96b028b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328743327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2328743327
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1525228268
Short name T697
Test name
Test status
Simulation time 41201980724 ps
CPU time 51.34 seconds
Started Jul 09 04:30:20 PM PDT 24
Finished Jul 09 04:31:13 PM PDT 24
Peak memory 197768 kb
Host smart-fdd9ba68-dc63-4328-9ef3-2c4404695000
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525228268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1525228268
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1734983461
Short name T48
Test name
Test status
Simulation time 78142757477 ps
CPU time 483.87 seconds
Started Jul 09 04:30:22 PM PDT 24
Finished Jul 09 04:38:28 PM PDT 24
Peak memory 199824 kb
Host smart-7aa5598c-d133-4a10-ba96-66bbf494df66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734983461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1734983461
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2701179129
Short name T425
Test name
Test status
Simulation time 9954547258 ps
CPU time 19.61 seconds
Started Jul 09 04:30:22 PM PDT 24
Finished Jul 09 04:30:44 PM PDT 24
Peak memory 199752 kb
Host smart-ecdeb1b9-6778-42cb-8324-f4268037b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701179129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2701179129
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.40411187
Short name T749
Test name
Test status
Simulation time 57428879526 ps
CPU time 125.83 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:32:34 PM PDT 24
Peak memory 199404 kb
Host smart-8ec2e123-e000-4d8a-afbc-bbc88e4bfa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40411187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.40411187
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3029667922
Short name T714
Test name
Test status
Simulation time 20917849574 ps
CPU time 939.26 seconds
Started Jul 09 04:30:21 PM PDT 24
Finished Jul 09 04:46:02 PM PDT 24
Peak memory 199732 kb
Host smart-3f1bad15-6070-43e4-b827-7f8c338673a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029667922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3029667922
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.4161550448
Short name T644
Test name
Test status
Simulation time 2972698344 ps
CPU time 8.68 seconds
Started Jul 09 04:30:19 PM PDT 24
Finished Jul 09 04:30:30 PM PDT 24
Peak memory 197980 kb
Host smart-e4abff12-8d90-43ca-8aee-595988750a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161550448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.4161550448
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3832027745
Short name T665
Test name
Test status
Simulation time 84472943769 ps
CPU time 24.38 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:30:54 PM PDT 24
Peak memory 199728 kb
Host smart-8e1bbe35-98c5-46ce-8708-db93b71c37b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832027745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3832027745
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2803365544
Short name T112
Test name
Test status
Simulation time 4708840023 ps
CPU time 1.67 seconds
Started Jul 09 04:30:30 PM PDT 24
Finished Jul 09 04:30:35 PM PDT 24
Peak memory 196024 kb
Host smart-908c069a-9048-40a9-be9a-6d328bc502fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803365544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2803365544
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2685606192
Short name T31
Test name
Test status
Simulation time 46723447 ps
CPU time 0.79 seconds
Started Jul 09 04:30:22 PM PDT 24
Finished Jul 09 04:30:24 PM PDT 24
Peak memory 218048 kb
Host smart-e1ccf56f-a388-4fd7-918d-95bc00b20b5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685606192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2685606192
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.4072785705
Short name T873
Test name
Test status
Simulation time 841012026 ps
CPU time 3.63 seconds
Started Jul 09 04:30:20 PM PDT 24
Finished Jul 09 04:30:25 PM PDT 24
Peak memory 199496 kb
Host smart-eb56af57-eb7b-47e3-accd-c1e5d63f154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072785705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4072785705
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3109118271
Short name T241
Test name
Test status
Simulation time 276729167109 ps
CPU time 289.32 seconds
Started Jul 09 04:30:23 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 199716 kb
Host smart-a60afa17-8a50-425a-9ad1-2057b7077af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109118271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3109118271
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4275779953
Short name T440
Test name
Test status
Simulation time 1970045189 ps
CPU time 1.89 seconds
Started Jul 09 04:30:19 PM PDT 24
Finished Jul 09 04:30:23 PM PDT 24
Peak memory 199552 kb
Host smart-f92dfb2f-ede5-436b-b409-710ba6fd2e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275779953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4275779953
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.720276317
Short name T563
Test name
Test status
Simulation time 73609240046 ps
CPU time 38.77 seconds
Started Jul 09 04:30:38 PM PDT 24
Finished Jul 09 04:31:19 PM PDT 24
Peak memory 199804 kb
Host smart-64e835dd-936b-4861-9144-a5391aeab4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720276317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.720276317
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2336876418
Short name T101
Test name
Test status
Simulation time 31194873 ps
CPU time 0.54 seconds
Started Jul 09 04:31:43 PM PDT 24
Finished Jul 09 04:31:51 PM PDT 24
Peak memory 194084 kb
Host smart-7ab17e1f-7ca2-4f17-b313-903d863b8573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336876418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2336876418
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.940181194
Short name T1123
Test name
Test status
Simulation time 76134406559 ps
CPU time 46.39 seconds
Started Jul 09 04:31:27 PM PDT 24
Finished Jul 09 04:32:27 PM PDT 24
Peak memory 199748 kb
Host smart-8191d6d1-5342-4bc1-88a1-b1988f93e62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940181194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.940181194
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2311648559
Short name T285
Test name
Test status
Simulation time 19669374747 ps
CPU time 25.49 seconds
Started Jul 09 04:31:25 PM PDT 24
Finished Jul 09 04:32:06 PM PDT 24
Peak memory 199788 kb
Host smart-0357d95c-8f98-42f1-a20f-829d0fcb3efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311648559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2311648559
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.2068497274
Short name T827
Test name
Test status
Simulation time 44570809271 ps
CPU time 18.81 seconds
Started Jul 09 04:31:29 PM PDT 24
Finished Jul 09 04:32:01 PM PDT 24
Peak memory 199732 kb
Host smart-0ed54ca2-1c3f-4951-9bd1-48408192a775
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068497274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2068497274
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3751878718
Short name T704
Test name
Test status
Simulation time 51139133515 ps
CPU time 107.45 seconds
Started Jul 09 04:31:30 PM PDT 24
Finished Jul 09 04:33:30 PM PDT 24
Peak memory 199696 kb
Host smart-29d08f9a-a682-43ba-a4ea-3e2b05971492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751878718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3751878718
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3026351815
Short name T1154
Test name
Test status
Simulation time 10508867813 ps
CPU time 6.59 seconds
Started Jul 09 04:31:45 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 199420 kb
Host smart-0599675d-6683-4656-9a90-73fd4ea075dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026351815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3026351815
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.97252238
Short name T469
Test name
Test status
Simulation time 50944635611 ps
CPU time 73.31 seconds
Started Jul 09 04:31:33 PM PDT 24
Finished Jul 09 04:32:57 PM PDT 24
Peak memory 199012 kb
Host smart-8e4e4565-bf79-4200-939d-8fd58ba57201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97252238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.97252238
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3589402693
Short name T975
Test name
Test status
Simulation time 11641655152 ps
CPU time 598.79 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:41:46 PM PDT 24
Peak memory 199760 kb
Host smart-c8f298e9-98e0-476e-a632-5ff75452f487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589402693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3589402693
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4222202340
Short name T808
Test name
Test status
Simulation time 5398228935 ps
CPU time 48.96 seconds
Started Jul 09 04:31:32 PM PDT 24
Finished Jul 09 04:32:33 PM PDT 24
Peak memory 198208 kb
Host smart-1db8cb2e-6a8b-4ffb-9afe-8a2fd70c722d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222202340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4222202340
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2990245356
Short name T639
Test name
Test status
Simulation time 51411533491 ps
CPU time 74.21 seconds
Started Jul 09 04:31:42 PM PDT 24
Finished Jul 09 04:33:04 PM PDT 24
Peak memory 199820 kb
Host smart-e9aa6b67-31c8-4d2a-9b44-02bca1553476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990245356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2990245356
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3724689968
Short name T932
Test name
Test status
Simulation time 35145480920 ps
CPU time 47.43 seconds
Started Jul 09 04:31:31 PM PDT 24
Finished Jul 09 04:32:30 PM PDT 24
Peak memory 196464 kb
Host smart-8430cc7b-1f2c-4d90-90d9-401f19b805ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724689968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3724689968
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.156447150
Short name T720
Test name
Test status
Simulation time 665525157 ps
CPU time 3.16 seconds
Started Jul 09 04:31:31 PM PDT 24
Finished Jul 09 04:31:46 PM PDT 24
Peak memory 199308 kb
Host smart-8a9a382a-54b6-4d7a-bab2-4c2765d9bccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156447150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.156447150
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3260530656
Short name T122
Test name
Test status
Simulation time 138214852007 ps
CPU time 779.72 seconds
Started Jul 09 04:31:41 PM PDT 24
Finished Jul 09 04:44:49 PM PDT 24
Peak memory 216280 kb
Host smart-a4caa3ea-7115-4066-b849-fb18b0d0e291
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260530656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3260530656
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1231887532
Short name T614
Test name
Test status
Simulation time 1569308852 ps
CPU time 2.28 seconds
Started Jul 09 04:31:29 PM PDT 24
Finished Jul 09 04:31:45 PM PDT 24
Peak memory 198516 kb
Host smart-0fc35733-fd7b-4cdb-b67e-86dce3881207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231887532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1231887532
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.531780930
Short name T921
Test name
Test status
Simulation time 111239911266 ps
CPU time 235.21 seconds
Started Jul 09 04:31:37 PM PDT 24
Finished Jul 09 04:35:41 PM PDT 24
Peak memory 199832 kb
Host smart-d10e83c6-3c19-4c0a-995b-59a66116570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531780930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.531780930
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.729590402
Short name T385
Test name
Test status
Simulation time 41337821 ps
CPU time 0.54 seconds
Started Jul 09 04:31:36 PM PDT 24
Finished Jul 09 04:31:46 PM PDT 24
Peak memory 195096 kb
Host smart-a89b7247-cecd-422b-aa63-3e6c1d46937b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729590402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.729590402
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.563916808
Short name T278
Test name
Test status
Simulation time 66365390820 ps
CPU time 61.45 seconds
Started Jul 09 04:31:29 PM PDT 24
Finished Jul 09 04:32:44 PM PDT 24
Peak memory 199740 kb
Host smart-fcbcd592-52d1-42a5-b78a-25c0a95b4b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563916808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.563916808
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.665609889
Short name T553
Test name
Test status
Simulation time 188928953664 ps
CPU time 102.88 seconds
Started Jul 09 04:31:42 PM PDT 24
Finished Jul 09 04:33:32 PM PDT 24
Peak memory 199892 kb
Host smart-1a48919b-d3c9-4a5a-aa1b-b833d02114be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665609889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.665609889
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1644138328
Short name T221
Test name
Test status
Simulation time 119013384800 ps
CPU time 75.84 seconds
Started Jul 09 04:31:37 PM PDT 24
Finished Jul 09 04:33:02 PM PDT 24
Peak memory 199812 kb
Host smart-309b654b-85f1-4b8a-9453-ae39f65f8717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644138328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1644138328
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2962943265
Short name T377
Test name
Test status
Simulation time 8264816298 ps
CPU time 7.1 seconds
Started Jul 09 04:31:43 PM PDT 24
Finished Jul 09 04:31:58 PM PDT 24
Peak memory 196720 kb
Host smart-ab125f6d-8d86-4d28-ab20-ae626c0c3e51
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962943265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2962943265
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2193140767
Short name T798
Test name
Test status
Simulation time 134631607921 ps
CPU time 1214.7 seconds
Started Jul 09 04:31:41 PM PDT 24
Finished Jul 09 04:52:04 PM PDT 24
Peak memory 199732 kb
Host smart-92b3b90c-14c7-4131-a47c-4e16d1bf0a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193140767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2193140767
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2175794585
Short name T1051
Test name
Test status
Simulation time 1821913233 ps
CPU time 1.2 seconds
Started Jul 09 04:31:45 PM PDT 24
Finished Jul 09 04:31:54 PM PDT 24
Peak memory 195740 kb
Host smart-fa21e6bb-65fb-4f8d-87d8-98306f8e27dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175794585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2175794585
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3693069381
Short name T316
Test name
Test status
Simulation time 1347191251 ps
CPU time 2.49 seconds
Started Jul 09 04:31:37 PM PDT 24
Finished Jul 09 04:31:48 PM PDT 24
Peak memory 199668 kb
Host smart-397db917-f0ec-4ba1-b9f8-b8965c73f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693069381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3693069381
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3899199728
Short name T663
Test name
Test status
Simulation time 26771616376 ps
CPU time 67.71 seconds
Started Jul 09 04:31:35 PM PDT 24
Finished Jul 09 04:32:52 PM PDT 24
Peak memory 199812 kb
Host smart-63d4c9de-0dfe-417c-875a-6715f7daa06a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899199728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3899199728
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2418273704
Short name T339
Test name
Test status
Simulation time 4720818172 ps
CPU time 44.71 seconds
Started Jul 09 04:31:43 PM PDT 24
Finished Jul 09 04:32:35 PM PDT 24
Peak memory 199408 kb
Host smart-3d6d36da-3060-45a5-a3fe-2179260e1be3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418273704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2418273704
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.56577354
Short name T520
Test name
Test status
Simulation time 32117792385 ps
CPU time 44.57 seconds
Started Jul 09 04:31:35 PM PDT 24
Finished Jul 09 04:32:29 PM PDT 24
Peak memory 199760 kb
Host smart-4dd28b86-4cd9-4103-9604-0b0206f65cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56577354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.56577354
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2732198826
Short name T11
Test name
Test status
Simulation time 5562882637 ps
CPU time 9.15 seconds
Started Jul 09 04:31:43 PM PDT 24
Finished Jul 09 04:32:00 PM PDT 24
Peak memory 195868 kb
Host smart-bd356f2a-697e-4b4a-8e44-65a7927ff757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732198826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2732198826
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3685719884
Short name T846
Test name
Test status
Simulation time 319553367 ps
CPU time 1.06 seconds
Started Jul 09 04:31:51 PM PDT 24
Finished Jul 09 04:31:57 PM PDT 24
Peak memory 198044 kb
Host smart-4329b5d7-0a7a-4875-86d6-1e8b4855cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685719884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3685719884
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2147101704
Short name T1070
Test name
Test status
Simulation time 20276270666 ps
CPU time 9.18 seconds
Started Jul 09 04:31:43 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 199720 kb
Host smart-f4f08e0a-15af-408d-83d7-442efbdefab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147101704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2147101704
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1486337122
Short name T1010
Test name
Test status
Simulation time 107921081543 ps
CPU time 720.39 seconds
Started Jul 09 04:31:47 PM PDT 24
Finished Jul 09 04:43:54 PM PDT 24
Peak memory 228800 kb
Host smart-0e645043-87ba-4727-acb0-4ba1e5588487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486337122 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1486337122
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1385222638
Short name T627
Test name
Test status
Simulation time 619912002 ps
CPU time 2.77 seconds
Started Jul 09 04:31:34 PM PDT 24
Finished Jul 09 04:31:47 PM PDT 24
Peak memory 199092 kb
Host smart-e5249bde-7c65-46b0-9ac2-88fcc2bbb853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385222638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1385222638
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3504810818
Short name T1049
Test name
Test status
Simulation time 26266652731 ps
CPU time 9.83 seconds
Started Jul 09 04:31:44 PM PDT 24
Finished Jul 09 04:32:01 PM PDT 24
Peak memory 199792 kb
Host smart-78029c32-9734-4473-9eb3-d02ad5c3227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504810818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3504810818
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1667635455
Short name T27
Test name
Test status
Simulation time 12970188 ps
CPU time 0.55 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:31:48 PM PDT 24
Peak memory 194068 kb
Host smart-8892cbb2-8cb8-466e-bee2-e4989eb854e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667635455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1667635455
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1611980241
Short name T635
Test name
Test status
Simulation time 49316087421 ps
CPU time 83.56 seconds
Started Jul 09 04:31:47 PM PDT 24
Finished Jul 09 04:33:17 PM PDT 24
Peak memory 199792 kb
Host smart-f07f22da-6c95-4122-b069-3f7706297423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611980241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1611980241
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.4274865366
Short name T844
Test name
Test status
Simulation time 126525694986 ps
CPU time 145.91 seconds
Started Jul 09 04:31:42 PM PDT 24
Finished Jul 09 04:34:15 PM PDT 24
Peak memory 199796 kb
Host smart-669c752d-57dc-4fd3-9cc8-fe554f89d79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274865366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4274865366
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2464824364
Short name T161
Test name
Test status
Simulation time 183869854919 ps
CPU time 287.37 seconds
Started Jul 09 04:31:41 PM PDT 24
Finished Jul 09 04:36:36 PM PDT 24
Peak memory 199704 kb
Host smart-4c4df352-0976-4cdf-bbdf-8ec949531cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464824364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2464824364
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1515215337
Short name T358
Test name
Test status
Simulation time 131710477892 ps
CPU time 52.1 seconds
Started Jul 09 04:31:54 PM PDT 24
Finished Jul 09 04:32:49 PM PDT 24
Peak memory 196972 kb
Host smart-2ff8481e-3e81-42c7-98ae-fc502008d763
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515215337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1515215337
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.162650046
Short name T604
Test name
Test status
Simulation time 105896794320 ps
CPU time 756.86 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:44:24 PM PDT 24
Peak memory 199884 kb
Host smart-909c8c88-f8f5-49f7-8a2c-42d94f6ea5ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162650046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.162650046
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3872996297
Short name T613
Test name
Test status
Simulation time 7484834004 ps
CPU time 13.47 seconds
Started Jul 09 04:31:40 PM PDT 24
Finished Jul 09 04:32:01 PM PDT 24
Peak memory 198672 kb
Host smart-6c9c6c5e-4f79-477b-8382-962486746ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872996297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3872996297
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3811985118
Short name T821
Test name
Test status
Simulation time 73752593525 ps
CPU time 14.77 seconds
Started Jul 09 04:31:41 PM PDT 24
Finished Jul 09 04:32:04 PM PDT 24
Peak memory 199308 kb
Host smart-c5c3cb1d-080c-4a36-b061-316aa4287555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811985118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3811985118
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3447341000
Short name T418
Test name
Test status
Simulation time 14368289759 ps
CPU time 757.17 seconds
Started Jul 09 04:31:49 PM PDT 24
Finished Jul 09 04:44:32 PM PDT 24
Peak memory 199748 kb
Host smart-070ee47f-26e1-4e68-b92a-4c553cdf1101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447341000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3447341000
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2574170441
Short name T946
Test name
Test status
Simulation time 4758936835 ps
CPU time 9.89 seconds
Started Jul 09 04:31:42 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 197940 kb
Host smart-da16ed74-05a6-4eee-a2c2-74da3e462145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574170441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2574170441
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3993702337
Short name T19
Test name
Test status
Simulation time 45281797551 ps
CPU time 68.19 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:32:55 PM PDT 24
Peak memory 199804 kb
Host smart-9f69eda5-0905-4517-ab20-dac90e41bb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993702337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3993702337
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.245413537
Short name T540
Test name
Test status
Simulation time 28438118782 ps
CPU time 39.35 seconds
Started Jul 09 04:31:45 PM PDT 24
Finished Jul 09 04:32:32 PM PDT 24
Peak memory 195912 kb
Host smart-c7914eb1-53c4-4e3d-868e-0e782fe1abce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245413537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.245413537
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.996968096
Short name T450
Test name
Test status
Simulation time 5386839471 ps
CPU time 8.94 seconds
Started Jul 09 04:31:44 PM PDT 24
Finished Jul 09 04:32:00 PM PDT 24
Peak memory 199144 kb
Host smart-b259b18a-ac95-495d-b333-bbf3a7c172ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996968096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.996968096
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1137725532
Short name T651
Test name
Test status
Simulation time 402451678636 ps
CPU time 164.5 seconds
Started Jul 09 04:31:39 PM PDT 24
Finished Jul 09 04:34:31 PM PDT 24
Peak memory 199772 kb
Host smart-bdd2b577-964c-43b3-923e-6ea512a027f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137725532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1137725532
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.776307285
Short name T1013
Test name
Test status
Simulation time 27903504757 ps
CPU time 208.12 seconds
Started Jul 09 04:31:40 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 215716 kb
Host smart-0aa7be1b-fafc-4a71-8c97-96cfd542642e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776307285 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.776307285
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4080955924
Short name T1095
Test name
Test status
Simulation time 624065479 ps
CPU time 2.1 seconds
Started Jul 09 04:31:49 PM PDT 24
Finished Jul 09 04:31:56 PM PDT 24
Peak memory 199592 kb
Host smart-f64a574f-9c98-4146-8bde-8a3d87b69473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080955924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4080955924
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2269215057
Short name T409
Test name
Test status
Simulation time 72475324260 ps
CPU time 42.67 seconds
Started Jul 09 04:31:34 PM PDT 24
Finished Jul 09 04:32:27 PM PDT 24
Peak memory 199896 kb
Host smart-4bac9c24-134d-49c7-ace8-3bd20ef082e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269215057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2269215057
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.446522679
Short name T719
Test name
Test status
Simulation time 51230993 ps
CPU time 0.54 seconds
Started Jul 09 04:31:55 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 195032 kb
Host smart-9b38986a-bbce-4a0f-b8c1-f88b4fca8730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446522679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.446522679
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.4241041669
Short name T806
Test name
Test status
Simulation time 255949651840 ps
CPU time 58.95 seconds
Started Jul 09 04:31:45 PM PDT 24
Finished Jul 09 04:32:51 PM PDT 24
Peak memory 199896 kb
Host smart-725c693b-ec14-4704-8f68-61f1cc89dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241041669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4241041669
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.978884819
Short name T743
Test name
Test status
Simulation time 31845498553 ps
CPU time 14.95 seconds
Started Jul 09 04:31:44 PM PDT 24
Finished Jul 09 04:32:07 PM PDT 24
Peak memory 199856 kb
Host smart-4895a603-8408-4b07-afa1-2b70286e145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978884819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.978884819
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.739960940
Short name T220
Test name
Test status
Simulation time 42824354701 ps
CPU time 66.82 seconds
Started Jul 09 04:31:56 PM PDT 24
Finished Jul 09 04:33:06 PM PDT 24
Peak memory 199788 kb
Host smart-02f6164b-f3e1-476f-b46b-3c452cade11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739960940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.739960940
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1334756169
Short name T1164
Test name
Test status
Simulation time 22979565592 ps
CPU time 18.72 seconds
Started Jul 09 04:31:51 PM PDT 24
Finished Jul 09 04:32:14 PM PDT 24
Peak memory 197628 kb
Host smart-9c2127db-ae36-43e0-ae7b-0936ef939bdf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334756169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1334756169
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_loopback.3367423539
Short name T1120
Test name
Test status
Simulation time 160917915 ps
CPU time 0.84 seconds
Started Jul 09 04:31:54 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 197728 kb
Host smart-785f192a-f7b2-4d86-a646-2b93c5885574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367423539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3367423539
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2341453676
Short name T482
Test name
Test status
Simulation time 71424532580 ps
CPU time 186.89 seconds
Started Jul 09 04:31:45 PM PDT 24
Finished Jul 09 04:34:59 PM PDT 24
Peak memory 200052 kb
Host smart-4862cfcd-6a77-4e3b-81db-c8ad25979429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341453676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2341453676
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.4086639618
Short name T810
Test name
Test status
Simulation time 12913139160 ps
CPU time 277.5 seconds
Started Jul 09 04:31:56 PM PDT 24
Finished Jul 09 04:36:37 PM PDT 24
Peak memory 199756 kb
Host smart-8e8edefe-316c-4b1d-a93e-b290e3ebcc6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086639618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.4086639618
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1719006946
Short name T674
Test name
Test status
Simulation time 6238402495 ps
CPU time 55.76 seconds
Started Jul 09 04:31:44 PM PDT 24
Finished Jul 09 04:32:47 PM PDT 24
Peak memory 198016 kb
Host smart-098284c3-c3f3-4bdc-8351-1e3b44d6094f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719006946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1719006946
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2021441057
Short name T262
Test name
Test status
Simulation time 21885608738 ps
CPU time 33.59 seconds
Started Jul 09 04:31:44 PM PDT 24
Finished Jul 09 04:32:25 PM PDT 24
Peak memory 199708 kb
Host smart-685f52e1-4792-4d29-a866-237423378141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021441057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2021441057
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.673464608
Short name T762
Test name
Test status
Simulation time 35133364681 ps
CPU time 46.9 seconds
Started Jul 09 04:31:45 PM PDT 24
Finished Jul 09 04:32:39 PM PDT 24
Peak memory 196176 kb
Host smart-fffee880-ada5-4ffb-89d7-ae7df3f299f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673464608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.673464608
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3052150371
Short name T1097
Test name
Test status
Simulation time 727296365 ps
CPU time 2.06 seconds
Started Jul 09 04:31:44 PM PDT 24
Finished Jul 09 04:31:53 PM PDT 24
Peak memory 198700 kb
Host smart-a0fc1751-e692-4ed8-b5f6-5861e85a1e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052150371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3052150371
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3578097333
Short name T867
Test name
Test status
Simulation time 183169642085 ps
CPU time 325.45 seconds
Started Jul 09 04:31:53 PM PDT 24
Finished Jul 09 04:37:22 PM PDT 24
Peak memory 199764 kb
Host smart-3993ea72-a660-4999-9d2d-5d9acb6274ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578097333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3578097333
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.561904171
Short name T574
Test name
Test status
Simulation time 1711551448 ps
CPU time 3.68 seconds
Started Jul 09 04:31:51 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 198592 kb
Host smart-11e182ff-9d3b-48f4-8359-6de989e2a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561904171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.561904171
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.969105724
Short name T1003
Test name
Test status
Simulation time 86745958577 ps
CPU time 68.63 seconds
Started Jul 09 04:31:48 PM PDT 24
Finished Jul 09 04:33:03 PM PDT 24
Peak memory 199732 kb
Host smart-bfe4f914-37eb-404c-92f8-accae872c888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969105724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.969105724
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1045018452
Short name T1147
Test name
Test status
Simulation time 22522826 ps
CPU time 0.57 seconds
Started Jul 09 04:31:54 PM PDT 24
Finished Jul 09 04:31:58 PM PDT 24
Peak memory 195408 kb
Host smart-b601e5de-42c0-4c8f-91d0-6368d3a9bcea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045018452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1045018452
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1455103974
Short name T266
Test name
Test status
Simulation time 214575389553 ps
CPU time 350.06 seconds
Started Jul 09 04:31:49 PM PDT 24
Finished Jul 09 04:37:45 PM PDT 24
Peak memory 199756 kb
Host smart-3f784778-04b0-4f4b-b870-1ac9ae965bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455103974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1455103974
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2880322106
Short name T554
Test name
Test status
Simulation time 74941142497 ps
CPU time 114.29 seconds
Started Jul 09 04:31:51 PM PDT 24
Finished Jul 09 04:33:50 PM PDT 24
Peak memory 199760 kb
Host smart-328da052-547e-46b2-a81c-cc363120247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880322106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2880322106
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.4204076983
Short name T131
Test name
Test status
Simulation time 72897576765 ps
CPU time 111.78 seconds
Started Jul 09 04:31:55 PM PDT 24
Finished Jul 09 04:33:51 PM PDT 24
Peak memory 199768 kb
Host smart-db9f208c-b6dd-4f8d-88a0-d0c76c1208bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204076983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.4204076983
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.4189081360
Short name T1109
Test name
Test status
Simulation time 64455615520 ps
CPU time 68.91 seconds
Started Jul 09 04:31:52 PM PDT 24
Finished Jul 09 04:33:05 PM PDT 24
Peak memory 199820 kb
Host smart-a68c8af7-607e-442c-8264-047a4905c1be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189081360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4189081360
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2026471286
Short name T1011
Test name
Test status
Simulation time 188892748104 ps
CPU time 472.08 seconds
Started Jul 09 04:31:56 PM PDT 24
Finished Jul 09 04:39:52 PM PDT 24
Peak memory 199724 kb
Host smart-f3bb9696-f5bd-4f3a-9e00-34683e4b36de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026471286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2026471286
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4013481067
Short name T1178
Test name
Test status
Simulation time 6568351988 ps
CPU time 12.87 seconds
Started Jul 09 04:31:55 PM PDT 24
Finished Jul 09 04:32:12 PM PDT 24
Peak memory 198744 kb
Host smart-a1bad1ed-c3db-4d10-a2b0-443451dad84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013481067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4013481067
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3601098016
Short name T799
Test name
Test status
Simulation time 68059878979 ps
CPU time 33.67 seconds
Started Jul 09 04:31:52 PM PDT 24
Finished Jul 09 04:32:30 PM PDT 24
Peak memory 199348 kb
Host smart-ca990996-e8de-40a6-b644-43ca11c0e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601098016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3601098016
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.637161132
Short name T722
Test name
Test status
Simulation time 13224278980 ps
CPU time 757.93 seconds
Started Jul 09 04:31:58 PM PDT 24
Finished Jul 09 04:44:40 PM PDT 24
Peak memory 199760 kb
Host smart-4526e4a3-5589-4adb-b1d2-bb818eef43ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637161132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.637161132
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3288030506
Short name T1020
Test name
Test status
Simulation time 4553669432 ps
CPU time 10.46 seconds
Started Jul 09 04:31:50 PM PDT 24
Finished Jul 09 04:32:05 PM PDT 24
Peak memory 198140 kb
Host smart-891dfa2d-4e13-480b-bb4b-5f48203ddde0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288030506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3288030506
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1933807670
Short name T172
Test name
Test status
Simulation time 166281705480 ps
CPU time 66.06 seconds
Started Jul 09 04:31:58 PM PDT 24
Finished Jul 09 04:33:08 PM PDT 24
Peak memory 199748 kb
Host smart-cf8c234d-2e90-45dc-b98f-7c0ee6b8a6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933807670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1933807670
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3385998887
Short name T430
Test name
Test status
Simulation time 3737696507 ps
CPU time 6.05 seconds
Started Jul 09 04:31:51 PM PDT 24
Finished Jul 09 04:32:01 PM PDT 24
Peak memory 196028 kb
Host smart-7d5d5b6b-78d6-43ca-9979-f54068818059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385998887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3385998887
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2684482960
Short name T927
Test name
Test status
Simulation time 6283594748 ps
CPU time 9.45 seconds
Started Jul 09 04:31:57 PM PDT 24
Finished Jul 09 04:32:10 PM PDT 24
Peak memory 199764 kb
Host smart-4b74d73f-743b-45cf-ae8f-67911e9560d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684482960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2684482960
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2989498840
Short name T1116
Test name
Test status
Simulation time 134190151882 ps
CPU time 52.29 seconds
Started Jul 09 04:31:55 PM PDT 24
Finished Jul 09 04:32:50 PM PDT 24
Peak memory 199784 kb
Host smart-d21252db-9a2f-40e9-bda6-4ce9e25ceaa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989498840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2989498840
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.806148957
Short name T66
Test name
Test status
Simulation time 180694519780 ps
CPU time 549.16 seconds
Started Jul 09 04:31:53 PM PDT 24
Finished Jul 09 04:41:06 PM PDT 24
Peak memory 216204 kb
Host smart-3d3028fa-193a-46f7-a063-3a9834fd7182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806148957 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.806148957
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.997070821
Short name T786
Test name
Test status
Simulation time 1091461713 ps
CPU time 2.06 seconds
Started Jul 09 04:31:53 PM PDT 24
Finished Jul 09 04:31:59 PM PDT 24
Peak memory 198380 kb
Host smart-18254b0d-a976-452e-97dd-93d8b7e236a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997070821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.997070821
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.354753144
Short name T983
Test name
Test status
Simulation time 15818696637 ps
CPU time 13.65 seconds
Started Jul 09 04:31:52 PM PDT 24
Finished Jul 09 04:32:09 PM PDT 24
Peak memory 199764 kb
Host smart-663beadd-b238-45b9-a704-c61e72b50d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354753144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.354753144
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2885058770
Short name T930
Test name
Test status
Simulation time 13315623 ps
CPU time 0.59 seconds
Started Jul 09 04:31:59 PM PDT 24
Finished Jul 09 04:32:03 PM PDT 24
Peak memory 194516 kb
Host smart-b3187168-c1c1-4153-9ad6-3338afaa5e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885058770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2885058770
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2391029605
Short name T1171
Test name
Test status
Simulation time 38892302716 ps
CPU time 68.04 seconds
Started Jul 09 04:31:57 PM PDT 24
Finished Jul 09 04:33:09 PM PDT 24
Peak memory 199736 kb
Host smart-6247f333-3699-4a41-8d2c-93f6be10aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391029605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2391029605
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1574360142
Short name T1081
Test name
Test status
Simulation time 58017079332 ps
CPU time 25.41 seconds
Started Jul 09 04:31:54 PM PDT 24
Finished Jul 09 04:32:23 PM PDT 24
Peak memory 199848 kb
Host smart-a8dfe825-67b7-46f8-b97f-d5f1dc0a3ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574360142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1574360142
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3844967479
Short name T819
Test name
Test status
Simulation time 89340704070 ps
CPU time 146.25 seconds
Started Jul 09 04:31:53 PM PDT 24
Finished Jul 09 04:34:23 PM PDT 24
Peak memory 199524 kb
Host smart-c7d4d528-fb9b-4c10-93a8-012ffa3ff9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844967479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3844967479
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1861310049
Short name T617
Test name
Test status
Simulation time 12654728000 ps
CPU time 5.34 seconds
Started Jul 09 04:31:55 PM PDT 24
Finished Jul 09 04:32:04 PM PDT 24
Peak memory 198692 kb
Host smart-231dc44a-2dbf-4ba9-be39-578bedc3d76d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861310049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1861310049
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2175285109
Short name T794
Test name
Test status
Simulation time 147308505045 ps
CPU time 1017.83 seconds
Started Jul 09 04:32:01 PM PDT 24
Finished Jul 09 04:49:02 PM PDT 24
Peak memory 199748 kb
Host smart-18fad5ee-7386-49a8-ae5b-9d024dbf1cbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175285109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2175285109
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3404230281
Short name T452
Test name
Test status
Simulation time 13038013259 ps
CPU time 14.04 seconds
Started Jul 09 04:31:59 PM PDT 24
Finished Jul 09 04:32:17 PM PDT 24
Peak memory 199844 kb
Host smart-8565e3f9-cf84-4c6f-adeb-ec270c998899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404230281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3404230281
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.4118545560
Short name T985
Test name
Test status
Simulation time 224731245290 ps
CPU time 107.69 seconds
Started Jul 09 04:31:55 PM PDT 24
Finished Jul 09 04:33:47 PM PDT 24
Peak memory 200168 kb
Host smart-119550e6-ffeb-4f45-81bb-b728a19802e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118545560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.4118545560
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.895353996
Short name T510
Test name
Test status
Simulation time 13603000852 ps
CPU time 162.24 seconds
Started Jul 09 04:32:00 PM PDT 24
Finished Jul 09 04:34:45 PM PDT 24
Peak memory 199888 kb
Host smart-35b3c1ce-baf3-4fc8-bdf9-c1a246aa787e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895353996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.895353996
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1170115480
Short name T335
Test name
Test status
Simulation time 6232333103 ps
CPU time 53.06 seconds
Started Jul 09 04:31:53 PM PDT 24
Finished Jul 09 04:32:49 PM PDT 24
Peak memory 198568 kb
Host smart-73d57272-70ed-4388-abb2-86aba3b9047f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170115480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1170115480
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.941129524
Short name T987
Test name
Test status
Simulation time 125157281687 ps
CPU time 55.96 seconds
Started Jul 09 04:31:54 PM PDT 24
Finished Jul 09 04:32:53 PM PDT 24
Peak memory 199756 kb
Host smart-350e434c-47e0-46e5-8bb1-8c561dce2ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941129524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.941129524
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3372467201
Short name T1133
Test name
Test status
Simulation time 5741198300 ps
CPU time 4.96 seconds
Started Jul 09 04:31:54 PM PDT 24
Finished Jul 09 04:32:03 PM PDT 24
Peak memory 195940 kb
Host smart-fc9b0353-e170-4303-8f43-efa089169279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372467201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3372467201
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3573869560
Short name T624
Test name
Test status
Simulation time 720978327 ps
CPU time 2.52 seconds
Started Jul 09 04:31:57 PM PDT 24
Finished Jul 09 04:32:04 PM PDT 24
Peak memory 199492 kb
Host smart-8829572b-2486-4fed-a391-fc6bc64d1216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573869560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3573869560
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.364464300
Short name T1059
Test name
Test status
Simulation time 10651352260 ps
CPU time 27.04 seconds
Started Jul 09 04:32:05 PM PDT 24
Finished Jul 09 04:32:33 PM PDT 24
Peak memory 199932 kb
Host smart-2275c4eb-4d1e-4165-86c1-3a958c1fb908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364464300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.364464300
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3275497791
Short name T816
Test name
Test status
Simulation time 269602650571 ps
CPU time 923.54 seconds
Started Jul 09 04:32:00 PM PDT 24
Finished Jul 09 04:47:26 PM PDT 24
Peak memory 216280 kb
Host smart-f5f7cf5f-19ec-4c83-863e-24529095ff7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275497791 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3275497791
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2799382190
Short name T576
Test name
Test status
Simulation time 6753054883 ps
CPU time 8.59 seconds
Started Jul 09 04:31:59 PM PDT 24
Finished Jul 09 04:32:11 PM PDT 24
Peak memory 199656 kb
Host smart-a3cef599-2500-4e3a-b142-332d79f521bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799382190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2799382190
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.789149282
Short name T707
Test name
Test status
Simulation time 184561356988 ps
CPU time 44.72 seconds
Started Jul 09 04:31:55 PM PDT 24
Finished Jul 09 04:32:43 PM PDT 24
Peak memory 199760 kb
Host smart-dd63bdd1-1b8a-4c5e-a161-4906c4e0a7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789149282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.789149282
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.4213523998
Short name T571
Test name
Test status
Simulation time 22700334 ps
CPU time 0.54 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:32:12 PM PDT 24
Peak memory 195400 kb
Host smart-8fab6425-e73e-4e2a-a3eb-753cdb875c7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213523998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.4213523998
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.4101326941
Short name T461
Test name
Test status
Simulation time 180820099070 ps
CPU time 291.04 seconds
Started Jul 09 04:32:02 PM PDT 24
Finished Jul 09 04:36:55 PM PDT 24
Peak memory 199784 kb
Host smart-a0b57f22-b7e2-4842-9429-dc0a0748bd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101326941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.4101326941
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2995310169
Short name T287
Test name
Test status
Simulation time 122065591915 ps
CPU time 80.5 seconds
Started Jul 09 04:32:01 PM PDT 24
Finished Jul 09 04:33:24 PM PDT 24
Peak memory 199552 kb
Host smart-0ddb7d6c-ec11-4ca9-a795-1e9bfca08d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995310169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2995310169
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.114065044
Short name T947
Test name
Test status
Simulation time 85977017052 ps
CPU time 35.24 seconds
Started Jul 09 04:32:00 PM PDT 24
Finished Jul 09 04:32:38 PM PDT 24
Peak memory 199748 kb
Host smart-ffb18022-91d1-4f0e-a545-cee50fd70fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114065044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.114065044
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1588323385
Short name T1135
Test name
Test status
Simulation time 25847285023 ps
CPU time 8.61 seconds
Started Jul 09 04:32:00 PM PDT 24
Finished Jul 09 04:32:11 PM PDT 24
Peak memory 198424 kb
Host smart-5388a27e-de7e-40e9-8bcf-d8a2af649c34
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588323385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1588323385
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.677379302
Short name T630
Test name
Test status
Simulation time 45808366893 ps
CPU time 278.37 seconds
Started Jul 09 04:32:06 PM PDT 24
Finished Jul 09 04:36:46 PM PDT 24
Peak memory 199716 kb
Host smart-118730ab-c33e-433c-8004-08ec3458929e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677379302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.677379302
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.477088673
Short name T589
Test name
Test status
Simulation time 24735151 ps
CPU time 0.57 seconds
Started Jul 09 04:32:01 PM PDT 24
Finished Jul 09 04:32:04 PM PDT 24
Peak memory 195692 kb
Host smart-5895034a-5d71-413c-b703-dd6db2948d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477088673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.477088673
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1494931558
Short name T1145
Test name
Test status
Simulation time 46648063016 ps
CPU time 19.99 seconds
Started Jul 09 04:31:59 PM PDT 24
Finished Jul 09 04:32:22 PM PDT 24
Peak memory 198204 kb
Host smart-11f91af1-d510-4130-9857-11b99e1c80f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494931558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1494931558
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3047541480
Short name T951
Test name
Test status
Simulation time 14636832632 ps
CPU time 356.14 seconds
Started Jul 09 04:32:01 PM PDT 24
Finished Jul 09 04:37:59 PM PDT 24
Peak memory 199824 kb
Host smart-4e76f7c0-9d20-4d86-8764-5fdd49a5f5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047541480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3047541480
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3454585161
Short name T380
Test name
Test status
Simulation time 5549121539 ps
CPU time 45.69 seconds
Started Jul 09 04:31:59 PM PDT 24
Finished Jul 09 04:32:49 PM PDT 24
Peak memory 197840 kb
Host smart-329a4f27-9799-45b9-8655-e3f1d66c8e28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454585161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3454585161
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2980445262
Short name T628
Test name
Test status
Simulation time 157591378024 ps
CPU time 347.91 seconds
Started Jul 09 04:32:01 PM PDT 24
Finished Jul 09 04:37:51 PM PDT 24
Peak memory 199844 kb
Host smart-3bdafefb-4a87-4cef-a236-5a149ed5847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980445262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2980445262
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2264203650
Short name T1047
Test name
Test status
Simulation time 3902485595 ps
CPU time 1.27 seconds
Started Jul 09 04:31:58 PM PDT 24
Finished Jul 09 04:32:03 PM PDT 24
Peak memory 196420 kb
Host smart-fddbfc9a-92ea-4c23-b8f5-a5645cb5f351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264203650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2264203650
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1182444095
Short name T9
Test name
Test status
Simulation time 6330155089 ps
CPU time 25.11 seconds
Started Jul 09 04:32:05 PM PDT 24
Finished Jul 09 04:32:32 PM PDT 24
Peak memory 199208 kb
Host smart-0ac588b1-3ba8-4862-be9b-f4f997da17a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182444095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1182444095
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3607828484
Short name T1124
Test name
Test status
Simulation time 317075168248 ps
CPU time 384.85 seconds
Started Jul 09 04:32:03 PM PDT 24
Finished Jul 09 04:38:30 PM PDT 24
Peak memory 199860 kb
Host smart-0a0807b7-9696-460d-b4f4-88d1027e7f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607828484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3607828484
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.4088943052
Short name T532
Test name
Test status
Simulation time 425782025072 ps
CPU time 1011.27 seconds
Started Jul 09 04:32:07 PM PDT 24
Finished Jul 09 04:48:59 PM PDT 24
Peak memory 225260 kb
Host smart-37d337b9-4455-444b-ae6d-a1ced9b30ea7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088943052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.4088943052
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2308568008
Short name T963
Test name
Test status
Simulation time 13775019815 ps
CPU time 23.92 seconds
Started Jul 09 04:31:58 PM PDT 24
Finished Jul 09 04:32:26 PM PDT 24
Peak memory 199876 kb
Host smart-4d38e59d-dfbc-4959-a4f9-3cd0a359147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308568008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2308568008
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.609042501
Short name T612
Test name
Test status
Simulation time 29447982286 ps
CPU time 13.46 seconds
Started Jul 09 04:31:59 PM PDT 24
Finished Jul 09 04:32:16 PM PDT 24
Peak memory 198556 kb
Host smart-5be3ac6b-e31c-4869-a5ce-df6a01747650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609042501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.609042501
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1439775335
Short name T328
Test name
Test status
Simulation time 11030902 ps
CPU time 0.56 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:32:13 PM PDT 24
Peak memory 195352 kb
Host smart-586313c0-30e0-4d28-9528-9686f1b3d1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439775335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1439775335
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.804473003
Short name T267
Test name
Test status
Simulation time 195416925298 ps
CPU time 54.32 seconds
Started Jul 09 04:32:08 PM PDT 24
Finished Jul 09 04:33:04 PM PDT 24
Peak memory 199724 kb
Host smart-4c8b5be4-223b-4580-9658-eda5e6c348da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804473003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.804473003
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.478436042
Short name T457
Test name
Test status
Simulation time 130936991129 ps
CPU time 22.77 seconds
Started Jul 09 04:32:04 PM PDT 24
Finished Jul 09 04:32:28 PM PDT 24
Peak memory 199772 kb
Host smart-aa7853b3-fc34-44f6-9957-a2e92a4ca4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478436042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.478436042
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1659789509
Short name T551
Test name
Test status
Simulation time 37960964878 ps
CPU time 28.75 seconds
Started Jul 09 04:32:04 PM PDT 24
Finished Jul 09 04:32:34 PM PDT 24
Peak memory 199756 kb
Host smart-842b849e-3180-489a-8998-25478eab98fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659789509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1659789509
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.423575962
Short name T652
Test name
Test status
Simulation time 13440471684 ps
CPU time 24.73 seconds
Started Jul 09 04:32:05 PM PDT 24
Finished Jul 09 04:32:31 PM PDT 24
Peak memory 199764 kb
Host smart-6e52bc8f-bf13-4417-b107-c03699d27066
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423575962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.423575962
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2187389423
Short name T863
Test name
Test status
Simulation time 52841537222 ps
CPU time 61.34 seconds
Started Jul 09 04:32:06 PM PDT 24
Finished Jul 09 04:33:08 PM PDT 24
Peak memory 199816 kb
Host smart-fa43e205-dd51-4bfe-8fc5-de036e8c0f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187389423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2187389423
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1910002346
Short name T726
Test name
Test status
Simulation time 2863784174 ps
CPU time 3.34 seconds
Started Jul 09 04:32:07 PM PDT 24
Finished Jul 09 04:32:11 PM PDT 24
Peak memory 195476 kb
Host smart-6a4561c2-78df-4658-823d-8717c1f61c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910002346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1910002346
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2551269255
Short name T105
Test name
Test status
Simulation time 20229685012 ps
CPU time 32.25 seconds
Started Jul 09 04:32:07 PM PDT 24
Finished Jul 09 04:32:39 PM PDT 24
Peak memory 198448 kb
Host smart-87655a69-021c-45b5-b7dc-31a793bdbdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551269255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2551269255
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1127457141
Short name T292
Test name
Test status
Simulation time 15096056474 ps
CPU time 349.19 seconds
Started Jul 09 04:32:03 PM PDT 24
Finished Jul 09 04:37:54 PM PDT 24
Peak memory 199712 kb
Host smart-eedf3786-f787-4616-8bd4-0bba39cd9433
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127457141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1127457141
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.4178122462
Short name T829
Test name
Test status
Simulation time 6944237929 ps
CPU time 15.4 seconds
Started Jul 09 04:32:05 PM PDT 24
Finished Jul 09 04:32:21 PM PDT 24
Peak memory 199100 kb
Host smart-b2ee22cd-1b25-4d81-909f-8b9e779c2501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178122462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.4178122462
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3749076362
Short name T567
Test name
Test status
Simulation time 51997559190 ps
CPU time 36.04 seconds
Started Jul 09 04:32:07 PM PDT 24
Finished Jul 09 04:32:43 PM PDT 24
Peak memory 199624 kb
Host smart-d89d8292-6cd2-42da-9f5e-3953ea7704a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749076362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3749076362
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3392659722
Short name T633
Test name
Test status
Simulation time 5384721627 ps
CPU time 1.37 seconds
Started Jul 09 04:32:05 PM PDT 24
Finished Jul 09 04:32:08 PM PDT 24
Peak memory 196236 kb
Host smart-0a6dcfc2-3f8d-43af-9ca6-7f4f44fe4ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392659722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3392659722
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3012468762
Short name T623
Test name
Test status
Simulation time 433544559 ps
CPU time 1.73 seconds
Started Jul 09 04:32:04 PM PDT 24
Finished Jul 09 04:32:07 PM PDT 24
Peak memory 199688 kb
Host smart-12b7ee1d-c1a9-4a97-9345-be6f79f63971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012468762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3012468762
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.4052448021
Short name T449
Test name
Test status
Simulation time 203613170470 ps
CPU time 513.47 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:40:45 PM PDT 24
Peak memory 208196 kb
Host smart-222b6c89-2855-42de-8993-8b1009583bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052448021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4052448021
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2921034299
Short name T642
Test name
Test status
Simulation time 202106445001 ps
CPU time 441.35 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 224748 kb
Host smart-5de6b64c-b951-415c-9ce3-7798de7adc3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921034299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2921034299
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3779159229
Short name T543
Test name
Test status
Simulation time 1219182569 ps
CPU time 3.64 seconds
Started Jul 09 04:32:04 PM PDT 24
Finished Jul 09 04:32:09 PM PDT 24
Peak memory 199380 kb
Host smart-c2fe4c75-d603-434c-a6b1-30f76cfb80d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779159229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3779159229
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3736626880
Short name T1021
Test name
Test status
Simulation time 9518002383 ps
CPU time 72.54 seconds
Started Jul 09 04:32:05 PM PDT 24
Finished Jul 09 04:33:19 PM PDT 24
Peak memory 199840 kb
Host smart-6d5ab8df-28e2-4cb7-91bf-3513d61b7fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736626880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3736626880
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.781123110
Short name T423
Test name
Test status
Simulation time 25654663 ps
CPU time 0.56 seconds
Started Jul 09 04:32:15 PM PDT 24
Finished Jul 09 04:32:17 PM PDT 24
Peak memory 195084 kb
Host smart-a30ef6b1-25e8-4bf8-95ed-b7f8bf1e3763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781123110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.781123110
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3046158596
Short name T1042
Test name
Test status
Simulation time 158096953923 ps
CPU time 114.77 seconds
Started Jul 09 04:32:16 PM PDT 24
Finished Jul 09 04:34:13 PM PDT 24
Peak memory 199748 kb
Host smart-05ec138e-9cb1-44d9-9851-7e400efe7b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046158596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3046158596
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1441283145
Short name T1090
Test name
Test status
Simulation time 88155229689 ps
CPU time 15.02 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:32:27 PM PDT 24
Peak memory 199768 kb
Host smart-af812a9b-a893-4208-a3b5-7b31b98403ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441283145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1441283145
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.322194698
Short name T939
Test name
Test status
Simulation time 54599507724 ps
CPU time 90.41 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:33:43 PM PDT 24
Peak memory 199568 kb
Host smart-b61c2cf8-1a58-4072-b939-5ce04bfd601c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322194698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.322194698
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2687577149
Short name T474
Test name
Test status
Simulation time 34293073369 ps
CPU time 47.2 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:33:02 PM PDT 24
Peak memory 199756 kb
Host smart-6cff3369-632f-4418-96ce-b7486937fdb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687577149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2687577149
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3545617543
Short name T437
Test name
Test status
Simulation time 8478182463 ps
CPU time 8.5 seconds
Started Jul 09 04:32:14 PM PDT 24
Finished Jul 09 04:32:24 PM PDT 24
Peak memory 199772 kb
Host smart-7c1eefea-2aa7-4cad-b570-d2d26669b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545617543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3545617543
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3310747972
Short name T847
Test name
Test status
Simulation time 270494653 ps
CPU time 0.98 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:32:14 PM PDT 24
Peak memory 194288 kb
Host smart-e05397f6-2bbe-4572-8345-d45a22a178ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310747972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3310747972
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2006460335
Short name T931
Test name
Test status
Simulation time 14090168242 ps
CPU time 750.57 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:44:46 PM PDT 24
Peak memory 199868 kb
Host smart-07a6c8d6-f3b1-4245-b1a7-c4de65be8dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006460335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2006460335
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1017248816
Short name T1071
Test name
Test status
Simulation time 2217316248 ps
CPU time 11.28 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:32:24 PM PDT 24
Peak memory 198800 kb
Host smart-d003a34d-7ae3-4c2b-ae6e-26b0e1dec818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017248816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1017248816
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3553783228
Short name T803
Test name
Test status
Simulation time 21902937255 ps
CPU time 30.35 seconds
Started Jul 09 04:32:12 PM PDT 24
Finished Jul 09 04:32:44 PM PDT 24
Peak memory 199824 kb
Host smart-432839ec-53b4-4e46-a660-616a70082f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553783228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3553783228
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.86462812
Short name T734
Test name
Test status
Simulation time 5604143118 ps
CPU time 8.47 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:32:21 PM PDT 24
Peak memory 195884 kb
Host smart-0811d830-8b2e-44a7-983e-fc3eb8a03640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86462812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.86462812
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3990925215
Short name T620
Test name
Test status
Simulation time 469646823 ps
CPU time 1.28 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:32:16 PM PDT 24
Peak memory 198332 kb
Host smart-94ab29f8-dee9-4cb0-91c1-35fa772a886b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990925215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3990925215
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3046543827
Short name T171
Test name
Test status
Simulation time 122322230141 ps
CPU time 58.11 seconds
Started Jul 09 04:32:14 PM PDT 24
Finished Jul 09 04:33:14 PM PDT 24
Peak memory 199680 kb
Host smart-a789d166-1c9e-4c56-a9c6-36e8ef355ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046543827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3046543827
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2096008878
Short name T485
Test name
Test status
Simulation time 13212180171 ps
CPU time 221.55 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:35:56 PM PDT 24
Peak memory 216240 kb
Host smart-e7235486-9048-4454-ae84-337014b3cc63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096008878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2096008878
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2422350008
Short name T20
Test name
Test status
Simulation time 2090935851 ps
CPU time 1.83 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:32:17 PM PDT 24
Peak memory 198604 kb
Host smart-32ed1358-b594-41c8-b4a9-16b07e523942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422350008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2422350008
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2647245003
Short name T322
Test name
Test status
Simulation time 69348513905 ps
CPU time 100.91 seconds
Started Jul 09 04:32:12 PM PDT 24
Finished Jul 09 04:33:55 PM PDT 24
Peak memory 199776 kb
Host smart-6a988b96-40ad-4d34-8f06-49a777dff64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647245003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2647245003
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.579056763
Short name T687
Test name
Test status
Simulation time 18310079 ps
CPU time 0.54 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:32:21 PM PDT 24
Peak memory 195352 kb
Host smart-248be32d-962e-4592-bf09-cfdd444d0929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579056763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.579056763
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1634248205
Short name T401
Test name
Test status
Simulation time 134744359910 ps
CPU time 45.97 seconds
Started Jul 09 04:32:12 PM PDT 24
Finished Jul 09 04:33:00 PM PDT 24
Peak memory 199704 kb
Host smart-3c472973-ad41-424b-b7da-9ea2b58b2f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634248205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1634248205
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3522534541
Short name T363
Test name
Test status
Simulation time 87230863030 ps
CPU time 19.39 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:32:34 PM PDT 24
Peak memory 199716 kb
Host smart-92fd184e-905f-42d9-989a-fb1c7bf5ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522534541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3522534541
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3531149613
Short name T958
Test name
Test status
Simulation time 46160195865 ps
CPU time 67.49 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:33:22 PM PDT 24
Peak memory 199740 kb
Host smart-37dfd015-845d-4be2-bafd-66d5b58b2d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531149613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3531149613
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1354462948
Short name T311
Test name
Test status
Simulation time 49610237705 ps
CPU time 19.04 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:32:31 PM PDT 24
Peak memory 199796 kb
Host smart-4e62d57f-f232-4bc8-a936-33bc0e21b7f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354462948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1354462948
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3357996706
Short name T353
Test name
Test status
Simulation time 91768846482 ps
CPU time 804.91 seconds
Started Jul 09 04:32:12 PM PDT 24
Finished Jul 09 04:45:39 PM PDT 24
Peak memory 199804 kb
Host smart-b1026855-187b-47ab-b86d-e6ff1670d051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3357996706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3357996706
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4118961631
Short name T106
Test name
Test status
Simulation time 321290301 ps
CPU time 0.87 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:32:16 PM PDT 24
Peak memory 197884 kb
Host smart-3dacd048-b7fc-47ad-bc24-65b069727f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118961631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4118961631
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2115498638
Short name T389
Test name
Test status
Simulation time 35268626674 ps
CPU time 15.9 seconds
Started Jul 09 04:32:14 PM PDT 24
Finished Jul 09 04:32:32 PM PDT 24
Peak memory 195136 kb
Host smart-5a08746f-c71b-44fd-b9a7-32f9c7655e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115498638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2115498638
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.575351378
Short name T50
Test name
Test status
Simulation time 6398254536 ps
CPU time 365.57 seconds
Started Jul 09 04:32:14 PM PDT 24
Finished Jul 09 04:38:22 PM PDT 24
Peak memory 199668 kb
Host smart-062ccc5b-f575-4f28-ba5f-b833b80efab5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575351378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.575351378
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.408517358
Short name T1132
Test name
Test status
Simulation time 3473066757 ps
CPU time 14.11 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:32:29 PM PDT 24
Peak memory 198012 kb
Host smart-af9d6435-8c38-429f-a890-6735a0fe041b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408517358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.408517358
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1521444079
Short name T864
Test name
Test status
Simulation time 171543807069 ps
CPU time 29.97 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:32:45 PM PDT 24
Peak memory 199776 kb
Host smart-6ec8fdcd-8ef1-4841-af1c-d64626f32bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521444079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1521444079
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3369473426
Short name T585
Test name
Test status
Simulation time 1814611601 ps
CPU time 2.31 seconds
Started Jul 09 04:32:13 PM PDT 24
Finished Jul 09 04:32:17 PM PDT 24
Peak memory 195396 kb
Host smart-0d8f87fb-aea1-4402-b23f-74a9841f93aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369473426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3369473426
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1076454258
Short name T579
Test name
Test status
Simulation time 245761404 ps
CPU time 1.43 seconds
Started Jul 09 04:32:10 PM PDT 24
Finished Jul 09 04:32:12 PM PDT 24
Peak memory 199760 kb
Host smart-4c21c096-ed4b-4cd8-8400-c13d8b126ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076454258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1076454258
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.4229955593
Short name T121
Test name
Test status
Simulation time 455908919611 ps
CPU time 250.22 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:36:31 PM PDT 24
Peak memory 215420 kb
Host smart-eea98dd8-7d6b-4929-920d-13ec81acf12b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229955593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.4229955593
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.879481129
Short name T671
Test name
Test status
Simulation time 89418223739 ps
CPU time 683.22 seconds
Started Jul 09 04:32:12 PM PDT 24
Finished Jul 09 04:43:37 PM PDT 24
Peak memory 216336 kb
Host smart-a99365e6-116f-4bec-9edf-62afcd77f795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879481129 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.879481129
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1439303987
Short name T599
Test name
Test status
Simulation time 1505575297 ps
CPU time 1.96 seconds
Started Jul 09 04:32:11 PM PDT 24
Finished Jul 09 04:32:14 PM PDT 24
Peak memory 198156 kb
Host smart-5081fb07-f503-47fb-9f26-7565dc99d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439303987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1439303987
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1841401808
Short name T279
Test name
Test status
Simulation time 9940931765 ps
CPU time 4.71 seconds
Started Jul 09 04:32:09 PM PDT 24
Finished Jul 09 04:32:15 PM PDT 24
Peak memory 199804 kb
Host smart-c91abc06-e70a-472b-b9c4-b8f7388a2ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841401808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1841401808
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1226483817
Short name T1066
Test name
Test status
Simulation time 12614883 ps
CPU time 0.58 seconds
Started Jul 09 04:30:31 PM PDT 24
Finished Jul 09 04:30:35 PM PDT 24
Peak memory 194648 kb
Host smart-8cf4105b-8c74-47ec-af35-a16acc8afc46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226483817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1226483817
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3874412979
Short name T179
Test name
Test status
Simulation time 272987843628 ps
CPU time 113.58 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:32:22 PM PDT 24
Peak memory 199756 kb
Host smart-a57ad00b-5c8f-410e-92d3-e9a78892a871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874412979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3874412979
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3062909849
Short name T56
Test name
Test status
Simulation time 27413345338 ps
CPU time 44.12 seconds
Started Jul 09 04:30:23 PM PDT 24
Finished Jul 09 04:31:11 PM PDT 24
Peak memory 199612 kb
Host smart-7d9fa17b-5cf8-4507-91e0-bcf762ed1c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062909849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3062909849
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3800802850
Short name T971
Test name
Test status
Simulation time 29530355954 ps
CPU time 23.08 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:30:52 PM PDT 24
Peak memory 199836 kb
Host smart-e23df1ba-1673-4e38-a20c-330b30c625bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800802850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3800802850
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1945133078
Short name T276
Test name
Test status
Simulation time 54400707331 ps
CPU time 326.11 seconds
Started Jul 09 04:30:30 PM PDT 24
Finished Jul 09 04:35:59 PM PDT 24
Peak memory 199796 kb
Host smart-ba570983-779f-445c-99b0-573938e7cc95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945133078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1945133078
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.403744067
Short name T1074
Test name
Test status
Simulation time 13562959866 ps
CPU time 15.51 seconds
Started Jul 09 04:30:26 PM PDT 24
Finished Jul 09 04:30:46 PM PDT 24
Peak memory 199528 kb
Host smart-97f20ef8-823a-4083-88a2-e864233f1b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403744067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.403744067
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2351256946
Short name T892
Test name
Test status
Simulation time 34325424979 ps
CPU time 48.68 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:31:16 PM PDT 24
Peak memory 199768 kb
Host smart-3ebebf98-d4eb-4d3d-a9e5-bbf4bcf8d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351256946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2351256946
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2390165351
Short name T371
Test name
Test status
Simulation time 18689792873 ps
CPU time 174.5 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:33:22 PM PDT 24
Peak memory 199752 kb
Host smart-c7a8140f-d829-4a55-b918-6c24ab68c0b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390165351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2390165351
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4194583948
Short name T1118
Test name
Test status
Simulation time 5887281929 ps
CPU time 48.52 seconds
Started Jul 09 04:30:21 PM PDT 24
Finished Jul 09 04:31:12 PM PDT 24
Peak memory 199060 kb
Host smart-3932478e-bbd6-49bb-b2c0-479879af0aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194583948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4194583948
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2803406312
Short name T1152
Test name
Test status
Simulation time 52854429706 ps
CPU time 22.87 seconds
Started Jul 09 04:30:22 PM PDT 24
Finished Jul 09 04:30:47 PM PDT 24
Peak memory 199740 kb
Host smart-06282c11-d5e0-4629-8aa3-532191c7f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803406312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2803406312
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2127397016
Short name T290
Test name
Test status
Simulation time 651043241 ps
CPU time 1.59 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:30:29 PM PDT 24
Peak memory 195192 kb
Host smart-2262202d-98ec-40b2-8878-885c8cea33d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127397016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2127397016
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.522426782
Short name T103
Test name
Test status
Simulation time 134957661 ps
CPU time 0.82 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:30:29 PM PDT 24
Peak memory 218108 kb
Host smart-29da26e3-9028-4f59-8f6e-fcff864d8cf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522426782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.522426782
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4036353195
Short name T1126
Test name
Test status
Simulation time 510931567 ps
CPU time 1.55 seconds
Started Jul 09 04:30:22 PM PDT 24
Finished Jul 09 04:30:25 PM PDT 24
Peak memory 198548 kb
Host smart-3ec8bbc7-4de1-4514-87ce-19e65a3a808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036353195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4036353195
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.4248648537
Short name T568
Test name
Test status
Simulation time 509991852344 ps
CPU time 1455.51 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:54:45 PM PDT 24
Peak memory 199724 kb
Host smart-4e8f260b-125d-436a-8363-4900e3f53e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248648537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4248648537
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3359406149
Short name T16
Test name
Test status
Simulation time 77996732902 ps
CPU time 375.46 seconds
Started Jul 09 04:30:26 PM PDT 24
Finished Jul 09 04:36:50 PM PDT 24
Peak memory 216320 kb
Host smart-4ee5e299-aaa6-4ae5-a631-8fc196802195
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359406149 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3359406149
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2573463979
Short name T967
Test name
Test status
Simulation time 6999447845 ps
CPU time 8.54 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:30:38 PM PDT 24
Peak memory 199624 kb
Host smart-136f5168-4264-4bff-a733-f7a4dfd8a138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573463979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2573463979
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3282347634
Short name T610
Test name
Test status
Simulation time 35984299249 ps
CPU time 52.58 seconds
Started Jul 09 04:30:22 PM PDT 24
Finished Jul 09 04:31:17 PM PDT 24
Peak memory 199716 kb
Host smart-7adeee23-5813-41ab-af25-bdbd75218e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282347634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3282347634
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.545192405
Short name T761
Test name
Test status
Simulation time 10897936 ps
CPU time 0.55 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:32:21 PM PDT 24
Peak memory 194160 kb
Host smart-df8f0af0-07dd-4b16-a760-ad4d90f9f39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545192405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.545192405
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.390588829
Short name T393
Test name
Test status
Simulation time 96239306957 ps
CPU time 258.93 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:36:39 PM PDT 24
Peak memory 199772 kb
Host smart-988455bf-73f0-4cb8-8998-8ff3942ae9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390588829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.390588829
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.764139949
Short name T148
Test name
Test status
Simulation time 164471766088 ps
CPU time 199.21 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:35:40 PM PDT 24
Peak memory 199756 kb
Host smart-e9d82a48-7078-4687-88ea-d96fa8b321ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764139949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.764139949
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3002418896
Short name T491
Test name
Test status
Simulation time 22656937638 ps
CPU time 8.98 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:32:30 PM PDT 24
Peak memory 199728 kb
Host smart-c972eef6-dd1f-4613-bb45-95a0ab6d351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002418896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3002418896
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.228826971
Short name T497
Test name
Test status
Simulation time 198978120071 ps
CPU time 187.01 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:35:30 PM PDT 24
Peak memory 199764 kb
Host smart-b733da3d-98ea-42f9-849d-0b5711754438
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228826971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.228826971
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.732154519
Short name T250
Test name
Test status
Simulation time 51381861800 ps
CPU time 206.54 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:35:49 PM PDT 24
Peak memory 199720 kb
Host smart-61268dab-1067-4b89-aae8-162926023fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=732154519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.732154519
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1074186446
Short name T919
Test name
Test status
Simulation time 2871377241 ps
CPU time 2.32 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:32:26 PM PDT 24
Peak memory 196024 kb
Host smart-e37c0ed4-6521-4880-9357-0c00edb808cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074186446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1074186446
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.4017289982
Short name T869
Test name
Test status
Simulation time 13329129579 ps
CPU time 11.43 seconds
Started Jul 09 04:32:16 PM PDT 24
Finished Jul 09 04:32:30 PM PDT 24
Peak memory 196436 kb
Host smart-13d905ce-660c-407f-baeb-561659610835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017289982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.4017289982
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.625094066
Short name T684
Test name
Test status
Simulation time 32801973787 ps
CPU time 873.32 seconds
Started Jul 09 04:32:16 PM PDT 24
Finished Jul 09 04:46:52 PM PDT 24
Peak memory 200160 kb
Host smart-69317857-3a53-42d9-a5ee-f0b2f2526152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625094066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.625094066
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3305727572
Short name T1148
Test name
Test status
Simulation time 3912216799 ps
CPU time 15.85 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:32:38 PM PDT 24
Peak memory 197924 kb
Host smart-0613db38-9432-4bc0-9bbf-cb6979054069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3305727572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3305727572
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.4107919724
Short name T778
Test name
Test status
Simulation time 115936882392 ps
CPU time 82.11 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:33:44 PM PDT 24
Peak memory 199744 kb
Host smart-9ad5ad51-3f2e-47d3-b500-c298b94be7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107919724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4107919724
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1878680114
Short name T767
Test name
Test status
Simulation time 909349112 ps
CPU time 1.34 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:32:22 PM PDT 24
Peak memory 195240 kb
Host smart-a2e1ead6-dd44-4601-883f-5fc8298250c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878680114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1878680114
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3191542054
Short name T368
Test name
Test status
Simulation time 313573721 ps
CPU time 1.1 seconds
Started Jul 09 04:32:20 PM PDT 24
Finished Jul 09 04:32:27 PM PDT 24
Peak memory 198452 kb
Host smart-292385fc-3b5f-49b9-ad38-5901d9374097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191542054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3191542054
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3902911973
Short name T647
Test name
Test status
Simulation time 152938753918 ps
CPU time 266.63 seconds
Started Jul 09 04:32:19 PM PDT 24
Finished Jul 09 04:36:51 PM PDT 24
Peak memory 216436 kb
Host smart-580ee095-8bbb-499c-a9b6-33c0c9a4cb02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902911973 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3902911973
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2331328483
Short name T972
Test name
Test status
Simulation time 11281006217 ps
CPU time 7.11 seconds
Started Jul 09 04:32:19 PM PDT 24
Finished Jul 09 04:32:32 PM PDT 24
Peak memory 199352 kb
Host smart-2b090ceb-5aac-4512-ae7c-566a16e6b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331328483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2331328483
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.354256255
Short name T893
Test name
Test status
Simulation time 175231096903 ps
CPU time 107.52 seconds
Started Jul 09 04:32:19 PM PDT 24
Finished Jul 09 04:34:11 PM PDT 24
Peak memory 199796 kb
Host smart-f9d8b2d0-495f-4f21-9c4d-e0fc29a207af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354256255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.354256255
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.129668305
Short name T732
Test name
Test status
Simulation time 87031938 ps
CPU time 0.53 seconds
Started Jul 09 04:32:16 PM PDT 24
Finished Jul 09 04:32:19 PM PDT 24
Peak memory 195148 kb
Host smart-0d948d95-995e-42a8-b762-245ed6211d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129668305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.129668305
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.802616044
Short name T537
Test name
Test status
Simulation time 50686139934 ps
CPU time 80.56 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:33:43 PM PDT 24
Peak memory 199840 kb
Host smart-8c9cc8ee-5d17-4f11-975e-34020d4b3389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802616044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.802616044
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.404086678
Short name T676
Test name
Test status
Simulation time 68312036417 ps
CPU time 46.7 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:33:10 PM PDT 24
Peak memory 199564 kb
Host smart-0742eab1-a736-41cf-82f4-c4bc1362dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404086678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.404086678
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.740296122
Short name T866
Test name
Test status
Simulation time 37954033508 ps
CPU time 49.02 seconds
Started Jul 09 04:32:16 PM PDT 24
Finished Jul 09 04:33:07 PM PDT 24
Peak memory 199780 kb
Host smart-555e5ba3-c974-4afb-a317-451517b098a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740296122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.740296122
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3351012784
Short name T776
Test name
Test status
Simulation time 112080640069 ps
CPU time 294.46 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:37:17 PM PDT 24
Peak memory 199748 kb
Host smart-ae2ec1b0-a709-494c-b210-3c56939b7e6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351012784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3351012784
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1930852211
Short name T715
Test name
Test status
Simulation time 5066071259 ps
CPU time 9.29 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:32:31 PM PDT 24
Peak memory 199700 kb
Host smart-1cb3a485-8dbf-4433-9d00-b7ba919860ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930852211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1930852211
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.272761711
Short name T274
Test name
Test status
Simulation time 48671540472 ps
CPU time 75.08 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:33:37 PM PDT 24
Peak memory 199940 kb
Host smart-866bf735-e8c5-472f-97ac-03aa1bc14e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272761711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.272761711
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.546176258
Short name T323
Test name
Test status
Simulation time 17378372420 ps
CPU time 350.77 seconds
Started Jul 09 04:32:19 PM PDT 24
Finished Jul 09 04:38:15 PM PDT 24
Peak memory 199680 kb
Host smart-8cb6559d-459c-473e-bbc5-d30dcc9e4bb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546176258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.546176258
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.4195105393
Short name T668
Test name
Test status
Simulation time 6834572762 ps
CPU time 14.99 seconds
Started Jul 09 04:32:16 PM PDT 24
Finished Jul 09 04:32:33 PM PDT 24
Peak memory 199008 kb
Host smart-87942a1a-c37f-45bd-9201-ba2470c94746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195105393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.4195105393
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4265591401
Short name T177
Test name
Test status
Simulation time 230426266941 ps
CPU time 75.65 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:33:39 PM PDT 24
Peak memory 199744 kb
Host smart-34384286-eb21-4554-8ae0-e2b181bd61fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265591401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4265591401
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2321696535
Short name T1038
Test name
Test status
Simulation time 5542741686 ps
CPU time 2.9 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:32:24 PM PDT 24
Peak memory 196300 kb
Host smart-ec8c84f7-e11a-43b0-bdd3-67bfac0c7760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321696535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2321696535
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3218515286
Short name T637
Test name
Test status
Simulation time 6284416121 ps
CPU time 13.21 seconds
Started Jul 09 04:32:15 PM PDT 24
Finished Jul 09 04:32:30 PM PDT 24
Peak memory 199120 kb
Host smart-6f1a3fcd-92ef-4a3a-a8fd-b9c2d0df1469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218515286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3218515286
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2054578779
Short name T217
Test name
Test status
Simulation time 227581914707 ps
CPU time 110.31 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:34:11 PM PDT 24
Peak memory 199796 kb
Host smart-8c882f8f-73da-459b-9368-affaace5e191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054578779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2054578779
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.950765677
Short name T57
Test name
Test status
Simulation time 45082334372 ps
CPU time 284.5 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:37:05 PM PDT 24
Peak memory 216308 kb
Host smart-6c4db969-b096-432e-a62e-a663aea444d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950765677 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.950765677
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2798681573
Short name T705
Test name
Test status
Simulation time 2981816956 ps
CPU time 1.71 seconds
Started Jul 09 04:32:15 PM PDT 24
Finished Jul 09 04:32:19 PM PDT 24
Peak memory 199104 kb
Host smart-8b10c7bc-bd4d-42ef-9377-3dc860adaa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798681573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2798681573
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1584086274
Short name T611
Test name
Test status
Simulation time 65993978329 ps
CPU time 116.96 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:34:18 PM PDT 24
Peak memory 199828 kb
Host smart-3a60a785-cb7c-412f-9efd-10c8a715314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584086274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1584086274
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4157783022
Short name T757
Test name
Test status
Simulation time 13421731 ps
CPU time 0.6 seconds
Started Jul 09 04:32:20 PM PDT 24
Finished Jul 09 04:32:26 PM PDT 24
Peak memory 194600 kb
Host smart-d4079f98-30d6-4615-abb6-a08e004593a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157783022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4157783022
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1292020909
Short name T763
Test name
Test status
Simulation time 142853290361 ps
CPU time 246.83 seconds
Started Jul 09 04:32:17 PM PDT 24
Finished Jul 09 04:36:28 PM PDT 24
Peak memory 199808 kb
Host smart-80b11b6e-83e5-4f61-bec7-b4832f7c93a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292020909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1292020909
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1998117833
Short name T88
Test name
Test status
Simulation time 11846192206 ps
CPU time 16.55 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:32:39 PM PDT 24
Peak memory 199712 kb
Host smart-224f1214-753d-491d-9920-9cab6e367b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998117833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1998117833
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.955559709
Short name T197
Test name
Test status
Simulation time 107789981610 ps
CPU time 42.62 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:33:10 PM PDT 24
Peak memory 199724 kb
Host smart-a03c7d28-0e35-4e0e-97c6-ccfb1c066f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955559709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.955559709
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3639283881
Short name T408
Test name
Test status
Simulation time 7500401626 ps
CPU time 3.6 seconds
Started Jul 09 04:32:19 PM PDT 24
Finished Jul 09 04:32:29 PM PDT 24
Peak memory 196536 kb
Host smart-1d640404-1390-424c-963f-f1029d82a861
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639283881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3639283881
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2790544059
Short name T448
Test name
Test status
Simulation time 169041989738 ps
CPU time 461.65 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:40:10 PM PDT 24
Peak memory 199792 kb
Host smart-e4e8c6bf-a8ef-4256-8671-70853f9701b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790544059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2790544059
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1151149847
Short name T455
Test name
Test status
Simulation time 11022382883 ps
CPU time 6.33 seconds
Started Jul 09 04:32:23 PM PDT 24
Finished Jul 09 04:32:35 PM PDT 24
Peak memory 198272 kb
Host smart-29d554c3-46ee-45e3-b3ca-3bb15d4e60d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151149847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1151149847
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.571465554
Short name T782
Test name
Test status
Simulation time 158081877106 ps
CPU time 27.18 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:32:54 PM PDT 24
Peak memory 207920 kb
Host smart-9c7e5aed-a8e6-4898-8f1c-18ce4dc063f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571465554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.571465554
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1622879309
Short name T797
Test name
Test status
Simulation time 8056882400 ps
CPU time 79.83 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:33:47 PM PDT 24
Peak memory 199764 kb
Host smart-01a62ff4-f51d-49c6-bbc4-9fa82dab35c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622879309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1622879309
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.99334004
Short name T677
Test name
Test status
Simulation time 3445857626 ps
CPU time 25.5 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:32:53 PM PDT 24
Peak memory 197896 kb
Host smart-934c4b2c-875e-4f1a-b0b1-2d2dd7797d28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99334004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.99334004
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2855318781
Short name T493
Test name
Test status
Simulation time 47953989167 ps
CPU time 39.83 seconds
Started Jul 09 04:32:20 PM PDT 24
Finished Jul 09 04:33:05 PM PDT 24
Peak memory 199772 kb
Host smart-4b3d2f40-0ca9-4fd5-b4d8-c8bf05f11cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855318781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2855318781
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.577799322
Short name T559
Test name
Test status
Simulation time 2700578721 ps
CPU time 1.61 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:32:30 PM PDT 24
Peak memory 195476 kb
Host smart-c15d6728-8b88-4b82-97ff-106a88c91c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577799322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.577799322
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3306942023
Short name T1036
Test name
Test status
Simulation time 678371099 ps
CPU time 1.25 seconds
Started Jul 09 04:32:15 PM PDT 24
Finished Jul 09 04:32:18 PM PDT 24
Peak memory 199652 kb
Host smart-95b2a153-ebad-46ca-915e-487b29b0d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306942023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3306942023
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1985500369
Short name T885
Test name
Test status
Simulation time 416749784673 ps
CPU time 716.51 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:44:25 PM PDT 24
Peak memory 199800 kb
Host smart-b498567d-58c4-4976-8e43-31e2176cc943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985500369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1985500369
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.379362723
Short name T812
Test name
Test status
Simulation time 30917896750 ps
CPU time 528.84 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:41:16 PM PDT 24
Peak memory 216320 kb
Host smart-87702b90-f3fa-47f1-bcad-b1c262c983db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379362723 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.379362723
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3429601295
Short name T1100
Test name
Test status
Simulation time 3835964841 ps
CPU time 1.92 seconds
Started Jul 09 04:32:25 PM PDT 24
Finished Jul 09 04:32:32 PM PDT 24
Peak memory 199668 kb
Host smart-59b06e5d-4f27-4379-9ee1-5e73f4db08e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429601295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3429601295
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4067177877
Short name T813
Test name
Test status
Simulation time 26722545388 ps
CPU time 20.49 seconds
Started Jul 09 04:32:18 PM PDT 24
Finished Jul 09 04:32:43 PM PDT 24
Peak memory 199504 kb
Host smart-4b838626-112c-4574-a78c-1bf526c3099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067177877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4067177877
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.914391293
Short name T453
Test name
Test status
Simulation time 17896033 ps
CPU time 0.57 seconds
Started Jul 09 04:32:23 PM PDT 24
Finished Jul 09 04:32:29 PM PDT 24
Peak memory 195104 kb
Host smart-e57c9070-bc91-4e7c-98b0-00aaed98838f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914391293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.914391293
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3381183384
Short name T835
Test name
Test status
Simulation time 245329421431 ps
CPU time 1311.73 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:54:19 PM PDT 24
Peak memory 199752 kb
Host smart-a71b74bf-084d-45d5-ae68-57efc6244c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381183384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3381183384
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1498332829
Short name T264
Test name
Test status
Simulation time 86426082338 ps
CPU time 157.64 seconds
Started Jul 09 04:32:25 PM PDT 24
Finished Jul 09 04:35:08 PM PDT 24
Peak memory 199768 kb
Host smart-b8a814c9-4c70-457e-97be-ead930c54c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498332829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1498332829
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2033671149
Short name T842
Test name
Test status
Simulation time 54212682620 ps
CPU time 173.96 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:35:20 PM PDT 24
Peak memory 199804 kb
Host smart-a5622e80-b05c-4d1e-b8aa-89140f030599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033671149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2033671149
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1474459347
Short name T124
Test name
Test status
Simulation time 127667721047 ps
CPU time 36.74 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:33:03 PM PDT 24
Peak memory 199592 kb
Host smart-276ab757-6459-46b8-8960-bba9fddc1677
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474459347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1474459347
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3825128885
Short name T508
Test name
Test status
Simulation time 104803802049 ps
CPU time 200.29 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:35:47 PM PDT 24
Peak memory 199744 kb
Host smart-147c8e19-3db1-40e2-ba5c-23ddee8e1aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825128885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3825128885
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3893017110
Short name T898
Test name
Test status
Simulation time 5460398236 ps
CPU time 11.5 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:32:37 PM PDT 24
Peak memory 199744 kb
Host smart-0cf4763a-5134-4bf4-8d07-9e7618cd15c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893017110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3893017110
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2842318422
Short name T848
Test name
Test status
Simulation time 41521882097 ps
CPU time 78.83 seconds
Started Jul 09 04:32:19 PM PDT 24
Finished Jul 09 04:33:42 PM PDT 24
Peak memory 199416 kb
Host smart-d09d0b13-af8c-452c-a32a-3f4ee8fcad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842318422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2842318422
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.520059520
Short name T590
Test name
Test status
Simulation time 7944840322 ps
CPU time 218.4 seconds
Started Jul 09 04:32:23 PM PDT 24
Finished Jul 09 04:36:07 PM PDT 24
Peak memory 199804 kb
Host smart-356b7d76-b323-4fd2-816d-6210d04ed1f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520059520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.520059520
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1438677270
Short name T541
Test name
Test status
Simulation time 2276666309 ps
CPU time 16.16 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:32:43 PM PDT 24
Peak memory 198148 kb
Host smart-265ac232-9ca6-4bd1-879a-66f84f79ff7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1438677270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1438677270
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.836844238
Short name T954
Test name
Test status
Simulation time 198901768306 ps
CPU time 30.72 seconds
Started Jul 09 04:32:23 PM PDT 24
Finished Jul 09 04:32:59 PM PDT 24
Peak memory 199660 kb
Host smart-52e58573-c647-4bdd-8591-4a86376e25d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836844238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.836844238
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1066528848
Short name T424
Test name
Test status
Simulation time 29954933643 ps
CPU time 4.46 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:32:33 PM PDT 24
Peak memory 195844 kb
Host smart-5264d219-089e-4b01-9dfa-2cd086bad543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066528848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1066528848
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1535292434
Short name T911
Test name
Test status
Simulation time 482697504 ps
CPU time 1.24 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:32:27 PM PDT 24
Peak memory 198612 kb
Host smart-572cff2d-c870-46a0-82c9-2cdbfba87676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535292434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1535292434
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2538293613
Short name T1075
Test name
Test status
Simulation time 92818298825 ps
CPU time 216.88 seconds
Started Jul 09 04:32:26 PM PDT 24
Finished Jul 09 04:36:08 PM PDT 24
Peak memory 199808 kb
Host smart-fbef573d-45a6-4857-b601-3e4cd97fa813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538293613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2538293613
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3609858027
Short name T925
Test name
Test status
Simulation time 1840047704 ps
CPU time 3.11 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:32:30 PM PDT 24
Peak memory 199708 kb
Host smart-1a8d8203-f7ce-40f4-b429-7061c783a57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609858027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3609858027
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3790781572
Short name T1017
Test name
Test status
Simulation time 120546810371 ps
CPU time 140.14 seconds
Started Jul 09 04:32:21 PM PDT 24
Finished Jul 09 04:34:47 PM PDT 24
Peak memory 199624 kb
Host smart-8f446bea-f246-4ac0-bb4d-b987c7211d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790781572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3790781572
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.70772059
Short name T487
Test name
Test status
Simulation time 11842583 ps
CPU time 0.57 seconds
Started Jul 09 04:32:26 PM PDT 24
Finished Jul 09 04:32:32 PM PDT 24
Peak memory 195420 kb
Host smart-a72b29a3-f2b3-4bd6-aa29-b93cac66e77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70772059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.70772059
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4099150458
Short name T488
Test name
Test status
Simulation time 79475631920 ps
CPU time 118.56 seconds
Started Jul 09 04:32:26 PM PDT 24
Finished Jul 09 04:34:30 PM PDT 24
Peak memory 199684 kb
Host smart-c2493ef1-7a3d-4272-9401-f5bcd1dbd059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099150458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4099150458
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3830969841
Short name T24
Test name
Test status
Simulation time 71905189364 ps
CPU time 85.2 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:33:58 PM PDT 24
Peak memory 199708 kb
Host smart-5df886a9-0fe3-4d0e-ab2b-47d8354c6f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830969841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3830969841
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.848813279
Short name T1176
Test name
Test status
Simulation time 85466684559 ps
CPU time 33.29 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:33:06 PM PDT 24
Peak memory 199696 kb
Host smart-7971ca90-fc0d-49f7-bad3-c899ce2c0197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848813279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.848813279
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3990444879
Short name T386
Test name
Test status
Simulation time 21563529066 ps
CPU time 34.46 seconds
Started Jul 09 04:32:26 PM PDT 24
Finished Jul 09 04:33:06 PM PDT 24
Peak memory 198576 kb
Host smart-6fe6cf88-0921-4866-bfd3-15d50de7953c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990444879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3990444879
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1800777751
Short name T557
Test name
Test status
Simulation time 82305746764 ps
CPU time 589.26 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:42:22 PM PDT 24
Peak memory 199860 kb
Host smart-29e92184-331d-4360-850a-711d365adbd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800777751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1800777751
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3276972050
Short name T52
Test name
Test status
Simulation time 664043304 ps
CPU time 1.48 seconds
Started Jul 09 04:32:27 PM PDT 24
Finished Jul 09 04:32:33 PM PDT 24
Peak memory 195240 kb
Host smart-fafb6bd5-4e2b-4b75-a3dc-7652ef132f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276972050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3276972050
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2090960217
Short name T1111
Test name
Test status
Simulation time 62017485534 ps
CPU time 51.16 seconds
Started Jul 09 04:32:27 PM PDT 24
Finished Jul 09 04:33:23 PM PDT 24
Peak memory 198408 kb
Host smart-82f9cf83-9856-4f82-9865-7455bb50076b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090960217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2090960217
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1181815418
Short name T446
Test name
Test status
Simulation time 10862401549 ps
CPU time 260.77 seconds
Started Jul 09 04:32:26 PM PDT 24
Finished Jul 09 04:36:52 PM PDT 24
Peak memory 199832 kb
Host smart-21be1859-7517-45a8-be02-58935eb37add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181815418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1181815418
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2317439395
Short name T442
Test name
Test status
Simulation time 6759090821 ps
CPU time 29.13 seconds
Started Jul 09 04:32:25 PM PDT 24
Finished Jul 09 04:32:59 PM PDT 24
Peak memory 198980 kb
Host smart-4061ded3-3aa0-4283-a100-665d8ca8fec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317439395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2317439395
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1750221044
Short name T370
Test name
Test status
Simulation time 100582061290 ps
CPU time 16.12 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:32:49 PM PDT 24
Peak memory 199648 kb
Host smart-e7f20a40-0308-478a-82ef-7598b259796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750221044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1750221044
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2048614931
Short name T280
Test name
Test status
Simulation time 4235701816 ps
CPU time 6.86 seconds
Started Jul 09 04:32:27 PM PDT 24
Finished Jul 09 04:32:39 PM PDT 24
Peak memory 196268 kb
Host smart-9525c101-aced-487d-8f0f-46eb83355cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048614931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2048614931
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3026783034
Short name T444
Test name
Test status
Simulation time 963525168 ps
CPU time 1.93 seconds
Started Jul 09 04:32:22 PM PDT 24
Finished Jul 09 04:32:29 PM PDT 24
Peak memory 199580 kb
Host smart-600fce0d-5eda-4077-be87-f71728b80976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026783034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3026783034
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2782515553
Short name T273
Test name
Test status
Simulation time 249664688704 ps
CPU time 111.41 seconds
Started Jul 09 04:32:27 PM PDT 24
Finished Jul 09 04:34:23 PM PDT 24
Peak memory 199664 kb
Host smart-9b9c37ba-a4b5-4847-a6fa-331ebe70eee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782515553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2782515553
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2746052514
Short name T890
Test name
Test status
Simulation time 27865624364 ps
CPU time 227.46 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:36:20 PM PDT 24
Peak memory 215340 kb
Host smart-ea19d7da-6d4e-4bc7-b5e4-cc65f9142be0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746052514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2746052514
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2165132095
Short name T964
Test name
Test status
Simulation time 987435209 ps
CPU time 2.85 seconds
Started Jul 09 04:32:26 PM PDT 24
Finished Jul 09 04:32:34 PM PDT 24
Peak memory 198704 kb
Host smart-8d968d59-67d8-43fc-a001-ecdaa1397fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165132095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2165132095
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1931995178
Short name T631
Test name
Test status
Simulation time 193168024 ps
CPU time 0.72 seconds
Started Jul 09 04:32:24 PM PDT 24
Finished Jul 09 04:32:30 PM PDT 24
Peak memory 196364 kb
Host smart-50d71208-4c9c-41f2-9473-366fa0acc19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931995178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1931995178
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2804452993
Short name T942
Test name
Test status
Simulation time 13268563 ps
CPU time 0.54 seconds
Started Jul 09 04:32:34 PM PDT 24
Finished Jul 09 04:32:35 PM PDT 24
Peak memory 195072 kb
Host smart-9b022505-3686-4006-90c6-62bed03b725e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804452993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2804452993
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.217148695
Short name T476
Test name
Test status
Simulation time 319594149179 ps
CPU time 98.46 seconds
Started Jul 09 04:32:25 PM PDT 24
Finished Jul 09 04:34:09 PM PDT 24
Peak memory 199808 kb
Host smart-c6ef0c8a-6bed-4e4a-b9fd-a2b75646cad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217148695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.217148695
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2219161367
Short name T475
Test name
Test status
Simulation time 126652315891 ps
CPU time 221.96 seconds
Started Jul 09 04:32:26 PM PDT 24
Finished Jul 09 04:36:13 PM PDT 24
Peak memory 199748 kb
Host smart-8e948cf7-0e2c-40fc-90f3-ddd3a9f0afec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219161367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2219161367
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1532309899
Short name T213
Test name
Test status
Simulation time 89478953402 ps
CPU time 152.53 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:35:05 PM PDT 24
Peak memory 199784 kb
Host smart-b997be7e-e728-471b-82d5-858d70f39d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532309899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1532309899
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.679067414
Short name T1137
Test name
Test status
Simulation time 49983567908 ps
CPU time 83.48 seconds
Started Jul 09 04:32:26 PM PDT 24
Finished Jul 09 04:33:55 PM PDT 24
Peak memory 199768 kb
Host smart-44d1bb2b-b3dc-44b3-aef0-b0e9f9e3e771
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679067414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.679067414
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3755397532
Short name T419
Test name
Test status
Simulation time 96471476610 ps
CPU time 607.42 seconds
Started Jul 09 04:32:33 PM PDT 24
Finished Jul 09 04:42:42 PM PDT 24
Peak memory 199728 kb
Host smart-a8b8c346-dfe2-4b14-ae1c-a52f138dd7f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755397532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3755397532
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3095610433
Short name T849
Test name
Test status
Simulation time 6677974383 ps
CPU time 11.2 seconds
Started Jul 09 04:32:32 PM PDT 24
Finished Jul 09 04:32:46 PM PDT 24
Peak memory 199624 kb
Host smart-2790347f-6398-4f49-abc9-909564d3b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095610433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3095610433
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1519313987
Short name T46
Test name
Test status
Simulation time 125046796911 ps
CPU time 165.54 seconds
Started Jul 09 04:32:33 PM PDT 24
Finished Jul 09 04:35:20 PM PDT 24
Peak memory 199000 kb
Host smart-a906ebc4-36a8-4327-861d-0e7ec723119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519313987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1519313987
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1200154195
Short name T768
Test name
Test status
Simulation time 18245856508 ps
CPU time 51.6 seconds
Started Jul 09 04:32:31 PM PDT 24
Finished Jul 09 04:33:25 PM PDT 24
Peak memory 199716 kb
Host smart-6e6897fa-a3a1-4c08-99f8-9cc03a15de2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1200154195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1200154195
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.470093983
Short name T1084
Test name
Test status
Simulation time 2764608679 ps
CPU time 10.88 seconds
Started Jul 09 04:32:28 PM PDT 24
Finished Jul 09 04:32:44 PM PDT 24
Peak memory 198020 kb
Host smart-3d9f7d7d-ec59-4989-a068-188a68d25c14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470093983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.470093983
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.715667223
Short name T937
Test name
Test status
Simulation time 38447614838 ps
CPU time 145.36 seconds
Started Jul 09 04:32:33 PM PDT 24
Finished Jul 09 04:35:00 PM PDT 24
Peak memory 199700 kb
Host smart-4ec80f2b-704b-41fb-9768-0ad4f808508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715667223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.715667223
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3334978274
Short name T534
Test name
Test status
Simulation time 2953819237 ps
CPU time 4.93 seconds
Started Jul 09 04:32:31 PM PDT 24
Finished Jul 09 04:32:39 PM PDT 24
Peak memory 196256 kb
Host smart-19afe488-7e82-41f2-a57b-bbedee2a54e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334978274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3334978274
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.627985287
Short name T621
Test name
Test status
Simulation time 495024984 ps
CPU time 1.95 seconds
Started Jul 09 04:32:25 PM PDT 24
Finished Jul 09 04:32:33 PM PDT 24
Peak memory 199276 kb
Host smart-a0c55ce2-403f-4f82-8b92-ba5c8f8e568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627985287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.627985287
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.683496829
Short name T880
Test name
Test status
Simulation time 236685810699 ps
CPU time 2101.12 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 05:07:38 PM PDT 24
Peak memory 199804 kb
Host smart-7e6c3b6b-1660-4ccc-a64e-08ceeb79da76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683496829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.683496829
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1544005927
Short name T858
Test name
Test status
Simulation time 125805638021 ps
CPU time 489.13 seconds
Started Jul 09 04:32:32 PM PDT 24
Finished Jul 09 04:40:43 PM PDT 24
Peak memory 224764 kb
Host smart-6015051d-7233-4629-ae3c-c88622162765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544005927 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1544005927
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3896217516
Short name T878
Test name
Test status
Simulation time 521680758 ps
CPU time 1.98 seconds
Started Jul 09 04:32:32 PM PDT 24
Finished Jul 09 04:32:36 PM PDT 24
Peak memory 198756 kb
Host smart-053e201f-08a5-43b0-ba4e-060f3d1c8562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896217516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3896217516
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.483737992
Short name T680
Test name
Test status
Simulation time 63030576025 ps
CPU time 89.99 seconds
Started Jul 09 04:32:25 PM PDT 24
Finished Jul 09 04:34:00 PM PDT 24
Peak memory 199880 kb
Host smart-16a07798-c837-4325-a960-d5871e7236b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483737992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.483737992
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2408190059
Short name T1069
Test name
Test status
Simulation time 23090430 ps
CPU time 0.56 seconds
Started Jul 09 04:32:34 PM PDT 24
Finished Jul 09 04:32:36 PM PDT 24
Peak memory 195352 kb
Host smart-da3e5c25-a19a-451c-aab3-382585c0a75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408190059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2408190059
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2049501664
Short name T717
Test name
Test status
Simulation time 47090429185 ps
CPU time 113.15 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:34:30 PM PDT 24
Peak memory 199716 kb
Host smart-0f94df09-02a7-49fe-8ce6-44d709071ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049501664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2049501664
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3610502350
Short name T174
Test name
Test status
Simulation time 294952254179 ps
CPU time 162.99 seconds
Started Jul 09 04:32:34 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 199656 kb
Host smart-fc79a261-5f15-4b0e-906d-87b018937dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610502350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3610502350
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.256849512
Short name T1163
Test name
Test status
Simulation time 18239559726 ps
CPU time 21.29 seconds
Started Jul 09 04:32:33 PM PDT 24
Finished Jul 09 04:32:56 PM PDT 24
Peak memory 199840 kb
Host smart-6b7320fb-7edc-4fdc-9bc8-7cbf084f4ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256849512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.256849512
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2052818259
Short name T648
Test name
Test status
Simulation time 126964456458 ps
CPU time 192.2 seconds
Started Jul 09 04:32:32 PM PDT 24
Finished Jul 09 04:35:46 PM PDT 24
Peak memory 199724 kb
Host smart-e143cf63-104a-45b4-8476-762f3b875829
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052818259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2052818259
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2543834247
Short name T399
Test name
Test status
Simulation time 110910776649 ps
CPU time 186.89 seconds
Started Jul 09 04:32:33 PM PDT 24
Finished Jul 09 04:35:41 PM PDT 24
Peak memory 199752 kb
Host smart-293e1dce-b59b-4836-a858-78a9774c4518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543834247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2543834247
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3356458596
Short name T1105
Test name
Test status
Simulation time 2649820862 ps
CPU time 2.56 seconds
Started Jul 09 04:32:32 PM PDT 24
Finished Jul 09 04:32:37 PM PDT 24
Peak memory 198484 kb
Host smart-4df7864d-528c-41ae-820b-01d85c29ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356458596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3356458596
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2658551226
Short name T1179
Test name
Test status
Simulation time 27963107386 ps
CPU time 37.27 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:33:14 PM PDT 24
Peak memory 198292 kb
Host smart-27c07aeb-4fc3-4b69-89af-58e457f71e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658551226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2658551226
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1728819202
Short name T382
Test name
Test status
Simulation time 19680071545 ps
CPU time 547.79 seconds
Started Jul 09 04:32:35 PM PDT 24
Finished Jul 09 04:41:44 PM PDT 24
Peak memory 199756 kb
Host smart-0e1568b5-efbc-4bf0-9928-d4acb01686bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728819202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1728819202
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3076429599
Short name T1025
Test name
Test status
Simulation time 6000463949 ps
CPU time 4.14 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:32:41 PM PDT 24
Peak memory 198964 kb
Host smart-449d5ad9-cda9-4c81-ab8d-55f93cac257e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076429599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3076429599
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3866097988
Short name T792
Test name
Test status
Simulation time 58008952744 ps
CPU time 23.24 seconds
Started Jul 09 04:32:34 PM PDT 24
Finished Jul 09 04:32:58 PM PDT 24
Peak memory 199412 kb
Host smart-58d12f0c-2389-418c-bd7c-dceacd777620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866097988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3866097988
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1747369780
Short name T492
Test name
Test status
Simulation time 3325751570 ps
CPU time 5.09 seconds
Started Jul 09 04:32:33 PM PDT 24
Finished Jul 09 04:32:40 PM PDT 24
Peak memory 196120 kb
Host smart-d1ed5269-2b07-43ae-94ff-8081e3fa3d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747369780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1747369780
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1636382344
Short name T436
Test name
Test status
Simulation time 6325606760 ps
CPU time 8.59 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:32:46 PM PDT 24
Peak memory 199812 kb
Host smart-7d10c37f-e376-4c56-8197-c5d1785e156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636382344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1636382344
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3120813146
Short name T905
Test name
Test status
Simulation time 157444782731 ps
CPU time 113.96 seconds
Started Jul 09 04:32:34 PM PDT 24
Finished Jul 09 04:34:29 PM PDT 24
Peak memory 199800 kb
Host smart-4a981c5f-4fbd-4633-bc7a-f696eaf73c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120813146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3120813146
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1502798215
Short name T472
Test name
Test status
Simulation time 71849006203 ps
CPU time 410.78 seconds
Started Jul 09 04:32:32 PM PDT 24
Finished Jul 09 04:39:25 PM PDT 24
Peak memory 208216 kb
Host smart-b2a00a00-e540-4f00-bbf3-f578d1b16a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502798215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1502798215
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.955072677
Short name T999
Test name
Test status
Simulation time 228508988 ps
CPU time 1.23 seconds
Started Jul 09 04:32:32 PM PDT 24
Finished Jul 09 04:32:36 PM PDT 24
Peak memory 198516 kb
Host smart-dacfc410-ea97-4b69-ba5f-a65407a2cdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955072677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.955072677
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3203211899
Short name T544
Test name
Test status
Simulation time 16377754077 ps
CPU time 12.3 seconds
Started Jul 09 04:32:32 PM PDT 24
Finished Jul 09 04:32:47 PM PDT 24
Peak memory 199684 kb
Host smart-93fde415-0b8b-46a5-9db5-a17a42d1841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203211899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3203211899
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3434359395
Short name T708
Test name
Test status
Simulation time 43688960 ps
CPU time 0.56 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:41 PM PDT 24
Peak memory 195372 kb
Host smart-91e04498-2b99-4568-8873-a80ffb0e7d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434359395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3434359395
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3912793898
Short name T703
Test name
Test status
Simulation time 32976005804 ps
CPU time 46.8 seconds
Started Jul 09 04:32:35 PM PDT 24
Finished Jul 09 04:33:23 PM PDT 24
Peak memory 199756 kb
Host smart-4a3aa4d7-30bb-48c3-8b27-ae4d2c1022ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912793898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3912793898
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3676431709
Short name T1181
Test name
Test status
Simulation time 145479117244 ps
CPU time 133.7 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:34:50 PM PDT 24
Peak memory 199648 kb
Host smart-5c4534cb-d82d-4062-9cdf-f3d944dfae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676431709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3676431709
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3051592514
Short name T1089
Test name
Test status
Simulation time 40564174984 ps
CPU time 59.84 seconds
Started Jul 09 04:32:38 PM PDT 24
Finished Jul 09 04:33:39 PM PDT 24
Peak memory 199748 kb
Host smart-83cd3ec2-bce9-4d12-a614-f50e83dec78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051592514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3051592514
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1995823646
Short name T701
Test name
Test status
Simulation time 8134357544 ps
CPU time 10.93 seconds
Started Jul 09 04:32:37 PM PDT 24
Finished Jul 09 04:32:49 PM PDT 24
Peak memory 196548 kb
Host smart-ca85e633-8df8-4dce-bbf2-1b7dae37b2bb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995823646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1995823646
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3387294939
Short name T716
Test name
Test status
Simulation time 89035341082 ps
CPU time 239.56 seconds
Started Jul 09 04:32:37 PM PDT 24
Finished Jul 09 04:36:38 PM PDT 24
Peak memory 199688 kb
Host smart-e61a1fe5-851e-4e1c-92dd-18b85aac2d8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387294939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3387294939
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.908548331
Short name T1099
Test name
Test status
Simulation time 8193144557 ps
CPU time 13.47 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:33:01 PM PDT 24
Peak memory 198164 kb
Host smart-d2abcf66-ba19-4faa-abb2-3574f7550c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908548331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.908548331
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2614300674
Short name T284
Test name
Test status
Simulation time 34434478656 ps
CPU time 40.14 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:33:18 PM PDT 24
Peak memory 198192 kb
Host smart-232c74f1-ce0d-41bb-8c93-de5da38c5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614300674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2614300674
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4231456384
Short name T367
Test name
Test status
Simulation time 9712829120 ps
CPU time 531.02 seconds
Started Jul 09 04:32:39 PM PDT 24
Finished Jul 09 04:41:31 PM PDT 24
Peak memory 199712 kb
Host smart-056865b4-3716-4023-a7ee-ec1380e4a19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231456384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4231456384
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1199892920
Short name T1182
Test name
Test status
Simulation time 1919652355 ps
CPU time 2.86 seconds
Started Jul 09 04:32:38 PM PDT 24
Finished Jul 09 04:32:42 PM PDT 24
Peak memory 197568 kb
Host smart-bb0dd886-2bca-4cad-854c-7d230c6d90a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199892920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1199892920
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.409497946
Short name T516
Test name
Test status
Simulation time 123800411989 ps
CPU time 93.16 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:34:10 PM PDT 24
Peak memory 199912 kb
Host smart-f60f1c7d-0549-4a19-a027-e8b0fa0b5a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409497946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.409497946
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3758809719
Short name T412
Test name
Test status
Simulation time 52417053667 ps
CPU time 16.17 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:57 PM PDT 24
Peak memory 195556 kb
Host smart-b9ea16ff-9e5a-46c8-be94-1d61d5503eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758809719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3758809719
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3018003584
Short name T785
Test name
Test status
Simulation time 11590423520 ps
CPU time 21.16 seconds
Started Jul 09 04:32:39 PM PDT 24
Finished Jul 09 04:33:01 PM PDT 24
Peak memory 199876 kb
Host smart-33689dcc-4d5c-4136-b768-6d5cc10151a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018003584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3018003584
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4089922409
Short name T169
Test name
Test status
Simulation time 282756285510 ps
CPU time 305.47 seconds
Started Jul 09 04:32:38 PM PDT 24
Finished Jul 09 04:37:45 PM PDT 24
Peak memory 199688 kb
Host smart-50ac5313-9bfe-48d2-9dec-60333a96de6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089922409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4089922409
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3120574747
Short name T61
Test name
Test status
Simulation time 66449853862 ps
CPU time 735.95 seconds
Started Jul 09 04:32:37 PM PDT 24
Finished Jul 09 04:44:54 PM PDT 24
Peak memory 211016 kb
Host smart-8bdb0831-51d5-4159-8bc7-ed6af9c6e2b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120574747 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3120574747
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.161220346
Short name T860
Test name
Test status
Simulation time 1486529528 ps
CPU time 3.84 seconds
Started Jul 09 04:32:39 PM PDT 24
Finished Jul 09 04:32:44 PM PDT 24
Peak memory 199492 kb
Host smart-2845c3f4-db47-4148-98e9-fc1bc905503e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161220346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.161220346
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2177351250
Short name T699
Test name
Test status
Simulation time 82515621661 ps
CPU time 117.97 seconds
Started Jul 09 04:32:34 PM PDT 24
Finished Jul 09 04:34:33 PM PDT 24
Peak memory 199712 kb
Host smart-4489239a-7416-4f7b-a6ac-1f3d9696a50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177351250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2177351250
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.220717505
Short name T28
Test name
Test status
Simulation time 40630580 ps
CPU time 0.57 seconds
Started Jul 09 04:32:46 PM PDT 24
Finished Jul 09 04:32:47 PM PDT 24
Peak memory 194512 kb
Host smart-a16e2604-9343-488c-b7fe-6a5d3296c97f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220717505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.220717505
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3365496091
Short name T291
Test name
Test status
Simulation time 61058215823 ps
CPU time 133.79 seconds
Started Jul 09 04:32:35 PM PDT 24
Finished Jul 09 04:34:50 PM PDT 24
Peak memory 199796 kb
Host smart-73010e62-2b34-4e68-9cb0-0f5f4df1934b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365496091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3365496091
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2039427328
Short name T934
Test name
Test status
Simulation time 27441690786 ps
CPU time 15.86 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:57 PM PDT 24
Peak memory 199444 kb
Host smart-508d73c8-05a0-4a83-8f9e-7f12b1e2a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039427328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2039427328
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1011713479
Short name T759
Test name
Test status
Simulation time 97171272372 ps
CPU time 135.13 seconds
Started Jul 09 04:32:44 PM PDT 24
Finished Jul 09 04:35:00 PM PDT 24
Peak memory 199900 kb
Host smart-a7ca0f08-ab01-49d6-a552-c64109f7cc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011713479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1011713479
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.315474003
Short name T17
Test name
Test status
Simulation time 30114533483 ps
CPU time 50.78 seconds
Started Jul 09 04:32:38 PM PDT 24
Finished Jul 09 04:33:30 PM PDT 24
Peak memory 199720 kb
Host smart-7e143a7b-6f89-4d23-ba57-6343d0bbdebf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315474003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.315474003
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3847464736
Short name T282
Test name
Test status
Simulation time 67235243070 ps
CPU time 140.47 seconds
Started Jul 09 04:32:35 PM PDT 24
Finished Jul 09 04:34:57 PM PDT 24
Peak memory 199780 kb
Host smart-37021547-17a1-46fa-834c-fd6d5c75cd7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847464736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3847464736
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1074088118
Short name T908
Test name
Test status
Simulation time 7807105396 ps
CPU time 13 seconds
Started Jul 09 04:32:38 PM PDT 24
Finished Jul 09 04:32:52 PM PDT 24
Peak memory 199488 kb
Host smart-e8245b8b-687b-44c5-82a7-8aabaf726cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074088118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1074088118
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2505308134
Short name T657
Test name
Test status
Simulation time 64635163222 ps
CPU time 107.31 seconds
Started Jul 09 04:32:37 PM PDT 24
Finished Jul 09 04:34:25 PM PDT 24
Peak memory 208184 kb
Host smart-8895b3fd-9ad1-433d-a4d7-a46c10ab802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505308134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2505308134
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.946330525
Short name T523
Test name
Test status
Simulation time 8603109581 ps
CPU time 398.14 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:39:15 PM PDT 24
Peak memory 199752 kb
Host smart-9d880dff-1ac2-46b0-ac5f-13c4bb1d3420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946330525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.946330525
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.994733001
Short name T351
Test name
Test status
Simulation time 2424513461 ps
CPU time 6.24 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:48 PM PDT 24
Peak memory 198200 kb
Host smart-e2d6b964-53af-4260-afc4-02062d0a2f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994733001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.994733001
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2172326930
Short name T686
Test name
Test status
Simulation time 14646801829 ps
CPU time 11.18 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:32:49 PM PDT 24
Peak memory 197096 kb
Host smart-e3595b6d-1dbb-4933-a936-23a78eff8701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172326930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2172326930
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3137602780
Short name T337
Test name
Test status
Simulation time 3159328763 ps
CPU time 1.81 seconds
Started Jul 09 04:32:41 PM PDT 24
Finished Jul 09 04:32:44 PM PDT 24
Peak memory 196200 kb
Host smart-fed451f4-8e20-47c4-927c-478453269d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137602780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3137602780
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1621536963
Short name T565
Test name
Test status
Simulation time 527796057 ps
CPU time 1.2 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:41 PM PDT 24
Peak memory 199600 kb
Host smart-370cafa9-576e-4b01-a4b8-28314e7b46fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621536963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1621536963
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.4059059648
Short name T659
Test name
Test status
Simulation time 279279558146 ps
CPU time 446.62 seconds
Started Jul 09 04:32:37 PM PDT 24
Finished Jul 09 04:40:05 PM PDT 24
Peak memory 199860 kb
Host smart-7863b302-307b-4c7a-9d5c-4538259536ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059059648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4059059648
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3467338690
Short name T626
Test name
Test status
Simulation time 7800755239 ps
CPU time 17.22 seconds
Started Jul 09 04:32:38 PM PDT 24
Finished Jul 09 04:32:56 PM PDT 24
Peak memory 199352 kb
Host smart-d379102a-acc5-40e0-bad1-97c318d13096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467338690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3467338690
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3513627677
Short name T324
Test name
Test status
Simulation time 9572925451 ps
CPU time 17.76 seconds
Started Jul 09 04:32:37 PM PDT 24
Finished Jul 09 04:32:56 PM PDT 24
Peak memory 199780 kb
Host smart-c40cd7ae-138d-45f3-afa8-6cd22a42510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513627677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3513627677
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.4050802265
Short name T1065
Test name
Test status
Simulation time 13486877 ps
CPU time 0.56 seconds
Started Jul 09 04:32:42 PM PDT 24
Finished Jul 09 04:32:43 PM PDT 24
Peak memory 195100 kb
Host smart-e75e2fc6-7282-411c-ad95-c1c97e67cb0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050802265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4050802265
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.963754411
Short name T950
Test name
Test status
Simulation time 50431581811 ps
CPU time 75.31 seconds
Started Jul 09 04:32:37 PM PDT 24
Finished Jul 09 04:33:54 PM PDT 24
Peak memory 199748 kb
Host smart-7ea3099f-987a-4892-852c-b69b77c554bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963754411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.963754411
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.755638608
Short name T940
Test name
Test status
Simulation time 69069031617 ps
CPU time 71.63 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:33:52 PM PDT 24
Peak memory 199828 kb
Host smart-a5f24294-08d1-4c03-aa1a-c1d98b6b9d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755638608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.755638608
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2874747548
Short name T319
Test name
Test status
Simulation time 24097212527 ps
CPU time 6.18 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:32:54 PM PDT 24
Peak memory 199884 kb
Host smart-85dc4356-dacc-431d-9cc2-774a9810dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874747548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2874747548
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.278386153
Short name T690
Test name
Test status
Simulation time 10568425537 ps
CPU time 20.27 seconds
Started Jul 09 04:32:45 PM PDT 24
Finished Jul 09 04:33:06 PM PDT 24
Peak memory 199304 kb
Host smart-4e9a3958-7aa6-4d34-9c95-61c7a348c2c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278386153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.278386153
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3837848585
Short name T918
Test name
Test status
Simulation time 102972987004 ps
CPU time 736.16 seconds
Started Jul 09 04:32:45 PM PDT 24
Finished Jul 09 04:45:02 PM PDT 24
Peak memory 199788 kb
Host smart-9af6921a-01e7-428b-af2d-3f7a10a8dfa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837848585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3837848585
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1206488206
Short name T415
Test name
Test status
Simulation time 4301677887 ps
CPU time 4.23 seconds
Started Jul 09 04:32:38 PM PDT 24
Finished Jul 09 04:32:43 PM PDT 24
Peak memory 199268 kb
Host smart-883eac8c-6dff-4490-b815-6e7902f21b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206488206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1206488206
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3172440919
Short name T737
Test name
Test status
Simulation time 7895640540 ps
CPU time 13.32 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:54 PM PDT 24
Peak memory 195528 kb
Host smart-808fa2f0-1e49-40d7-820f-f6751e913073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172440919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3172440919
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.471869174
Short name T993
Test name
Test status
Simulation time 10188793242 ps
CPU time 280.76 seconds
Started Jul 09 04:32:45 PM PDT 24
Finished Jul 09 04:37:26 PM PDT 24
Peak memory 199832 kb
Host smart-fb748aee-18e0-4e0a-9aa0-34f16573d794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471869174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.471869174
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4265034540
Short name T511
Test name
Test status
Simulation time 5732956573 ps
CPU time 13.18 seconds
Started Jul 09 04:32:37 PM PDT 24
Finished Jul 09 04:32:52 PM PDT 24
Peak memory 198804 kb
Host smart-16ebbb49-8626-4fb3-b730-df038f3a0a07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265034540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4265034540
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2899169641
Short name T167
Test name
Test status
Simulation time 124696255172 ps
CPU time 56.72 seconds
Started Jul 09 04:32:46 PM PDT 24
Finished Jul 09 04:33:44 PM PDT 24
Peak memory 200216 kb
Host smart-058eee61-59c7-459e-9fdf-634108de188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899169641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2899169641
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1359874567
Short name T884
Test name
Test status
Simulation time 3188498438 ps
CPU time 5.74 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:47 PM PDT 24
Peak memory 196200 kb
Host smart-8659c1b1-ac0f-4315-849b-883b8fd02754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359874567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1359874567
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1465425749
Short name T886
Test name
Test status
Simulation time 653843583 ps
CPU time 1.54 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:42 PM PDT 24
Peak memory 198124 kb
Host smart-47374dc1-94c6-44cf-a962-1f7c153c867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465425749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1465425749
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2039822631
Short name T1055
Test name
Test status
Simulation time 35090395559 ps
CPU time 396.82 seconds
Started Jul 09 04:32:36 PM PDT 24
Finished Jul 09 04:39:14 PM PDT 24
Peak memory 216272 kb
Host smart-ec35fd3d-4f86-48d5-aea1-6fd36cbfbddf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039822631 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2039822631
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.556416787
Short name T580
Test name
Test status
Simulation time 1207274688 ps
CPU time 3.04 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:32:50 PM PDT 24
Peak memory 198900 kb
Host smart-534bb37f-5234-4f51-a452-0b3955a09def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556416787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.556416787
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.863084785
Short name T824
Test name
Test status
Simulation time 45271842773 ps
CPU time 7.87 seconds
Started Jul 09 04:32:45 PM PDT 24
Finished Jul 09 04:32:54 PM PDT 24
Peak memory 199824 kb
Host smart-60d974c8-27d1-42e9-8b9c-c5c80ab780de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863084785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.863084785
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3278610122
Short name T332
Test name
Test status
Simulation time 42175747 ps
CPU time 0.54 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:30:28 PM PDT 24
Peak memory 194100 kb
Host smart-8e16c9ea-7591-433b-a1c7-fe3bec6e3191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278610122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3278610122
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3859526245
Short name T1091
Test name
Test status
Simulation time 81481356392 ps
CPU time 19.16 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:30:49 PM PDT 24
Peak memory 199652 kb
Host smart-1e1c61d4-3516-4498-800a-c0bd3106d5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859526245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3859526245
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1654294896
Short name T514
Test name
Test status
Simulation time 27128711856 ps
CPU time 21.29 seconds
Started Jul 09 04:30:33 PM PDT 24
Finished Jul 09 04:30:57 PM PDT 24
Peak memory 199632 kb
Host smart-1b32d75b-6b5d-4653-ac5f-365833b94c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654294896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1654294896
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3765866833
Short name T188
Test name
Test status
Simulation time 26795226157 ps
CPU time 38.24 seconds
Started Jul 09 04:30:37 PM PDT 24
Finished Jul 09 04:31:17 PM PDT 24
Peak memory 200128 kb
Host smart-6f078f0b-0eb8-4f34-9fbb-0adf0566d6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765866833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3765866833
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.653174980
Short name T765
Test name
Test status
Simulation time 2199492365 ps
CPU time 3.56 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:30:31 PM PDT 24
Peak memory 196252 kb
Host smart-7e381d6a-6e9f-4dd3-800e-24c3ffec05d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653174980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.653174980
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2777662454
Short name T1014
Test name
Test status
Simulation time 49060712566 ps
CPU time 507.47 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:39:15 PM PDT 24
Peak memory 199680 kb
Host smart-ac5deceb-033c-4770-9419-02aba4be84e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777662454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2777662454
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3540722731
Short name T779
Test name
Test status
Simulation time 6051395335 ps
CPU time 10.4 seconds
Started Jul 09 04:30:29 PM PDT 24
Finished Jul 09 04:30:43 PM PDT 24
Peak memory 199700 kb
Host smart-d26b18b2-488a-4ce8-90df-c2bdb5f05440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540722731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3540722731
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2760407960
Short name T521
Test name
Test status
Simulation time 313749190145 ps
CPU time 69.27 seconds
Started Jul 09 04:30:26 PM PDT 24
Finished Jul 09 04:31:40 PM PDT 24
Peak memory 208168 kb
Host smart-8bebf36d-e97e-42fb-9d89-d6a349d6a492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760407960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2760407960
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.4154198387
Short name T856
Test name
Test status
Simulation time 19958927439 ps
CPU time 551.38 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:39:41 PM PDT 24
Peak memory 199736 kb
Host smart-b45bc97c-27e4-4627-908e-ab77ab7cc96a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4154198387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4154198387
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1624869235
Short name T986
Test name
Test status
Simulation time 6511813497 ps
CPU time 30.32 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:30:59 PM PDT 24
Peak memory 198516 kb
Host smart-d8b4095d-e786-4b2c-bbab-e8aec069c2fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624869235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1624869235
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3999268643
Short name T411
Test name
Test status
Simulation time 60072890881 ps
CPU time 56.83 seconds
Started Jul 09 04:30:23 PM PDT 24
Finished Jul 09 04:31:22 PM PDT 24
Peak memory 199720 kb
Host smart-d6cfbd7f-6c75-4d89-94da-cdacf519e882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999268643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3999268643
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1100495834
Short name T1027
Test name
Test status
Simulation time 1715526018 ps
CPU time 3.48 seconds
Started Jul 09 04:30:30 PM PDT 24
Finished Jul 09 04:30:37 PM PDT 24
Peak memory 195376 kb
Host smart-b85b06b5-17f6-4bd0-9217-7658135711f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100495834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1100495834
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3549193700
Short name T868
Test name
Test status
Simulation time 5479383880 ps
CPU time 9.81 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:30:38 PM PDT 24
Peak memory 199756 kb
Host smart-5a436223-fdff-4f1e-841f-7f470f51d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549193700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3549193700
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2843833161
Short name T60
Test name
Test status
Simulation time 84400675019 ps
CPU time 567.75 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:39:56 PM PDT 24
Peak memory 216320 kb
Host smart-56a6e646-0b94-4d18-8e1d-03a7c41e4fab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843833161 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2843833161
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1228775262
Short name T1155
Test name
Test status
Simulation time 1404495085 ps
CPU time 4.75 seconds
Started Jul 09 04:30:32 PM PDT 24
Finished Jul 09 04:30:40 PM PDT 24
Peak memory 198476 kb
Host smart-1480bb55-96e6-4134-b817-b0d51bd9dae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228775262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1228775262
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.4189705256
Short name T249
Test name
Test status
Simulation time 111485275776 ps
CPU time 68.73 seconds
Started Jul 09 04:30:24 PM PDT 24
Finished Jul 09 04:31:36 PM PDT 24
Peak memory 199712 kb
Host smart-62aaeed5-8e3f-4dbd-9a90-9740bcdb0a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189705256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.4189705256
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.617606529
Short name T271
Test name
Test status
Simulation time 106603678496 ps
CPU time 81.43 seconds
Started Jul 09 04:32:41 PM PDT 24
Finished Jul 09 04:34:03 PM PDT 24
Peak memory 199720 kb
Host smart-64bea794-ae7f-4e70-8958-dab4d13472b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617606529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.617606529
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3830889105
Short name T62
Test name
Test status
Simulation time 22209775801 ps
CPU time 216.99 seconds
Started Jul 09 04:32:57 PM PDT 24
Finished Jul 09 04:36:35 PM PDT 24
Peak memory 208260 kb
Host smart-68d4486c-5102-4e00-b5c3-aaea11cd953b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830889105 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3830889105
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.96102064
Short name T160
Test name
Test status
Simulation time 19563726031 ps
CPU time 14.77 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:32:56 PM PDT 24
Peak memory 199740 kb
Host smart-3f3afa19-0f94-4ce8-811b-0020b4422090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96102064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.96102064
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1624136409
Short name T1058
Test name
Test status
Simulation time 14908355504 ps
CPU time 158.39 seconds
Started Jul 09 04:32:44 PM PDT 24
Finished Jul 09 04:35:23 PM PDT 24
Peak memory 209580 kb
Host smart-9e59ad3d-f993-4286-bd26-e1cbc9762871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624136409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1624136409
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.935944145
Short name T330
Test name
Test status
Simulation time 19451826248 ps
CPU time 32.62 seconds
Started Jul 09 04:32:44 PM PDT 24
Finished Jul 09 04:33:17 PM PDT 24
Peak memory 199840 kb
Host smart-5d358087-51da-47cd-bc12-a3c4bb3da41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935944145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.935944145
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.4156311037
Short name T152
Test name
Test status
Simulation time 377018291948 ps
CPU time 864.34 seconds
Started Jul 09 04:32:41 PM PDT 24
Finished Jul 09 04:47:06 PM PDT 24
Peak memory 224724 kb
Host smart-f7f77696-cb6b-4a24-886d-b85265b5e439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156311037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.4156311037
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2640289636
Short name T1108
Test name
Test status
Simulation time 29071180006 ps
CPU time 47.74 seconds
Started Jul 09 04:32:42 PM PDT 24
Finished Jul 09 04:33:31 PM PDT 24
Peak memory 199708 kb
Host smart-01672e1e-52fe-460f-9f36-52e30088e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640289636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2640289636
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.163213013
Short name T664
Test name
Test status
Simulation time 53447630120 ps
CPU time 208.41 seconds
Started Jul 09 04:32:46 PM PDT 24
Finished Jul 09 04:36:15 PM PDT 24
Peak memory 212788 kb
Host smart-94a0f47d-f60c-4213-a986-f6b0debd67fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163213013 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.163213013
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.200700209
Short name T1160
Test name
Test status
Simulation time 15038629270 ps
CPU time 20.95 seconds
Started Jul 09 04:32:44 PM PDT 24
Finished Jul 09 04:33:05 PM PDT 24
Peak memory 199660 kb
Host smart-3589ff8d-9784-4b72-9ac4-a8ee3c9a8bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200700209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.200700209
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1527008044
Short name T887
Test name
Test status
Simulation time 40406911288 ps
CPU time 718.04 seconds
Started Jul 09 04:32:44 PM PDT 24
Finished Jul 09 04:44:43 PM PDT 24
Peak memory 216280 kb
Host smart-89fcb8e4-3d14-43c9-a7b5-48a177256b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527008044 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1527008044
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.314626866
Short name T1175
Test name
Test status
Simulation time 218225344843 ps
CPU time 703.98 seconds
Started Jul 09 04:32:42 PM PDT 24
Finished Jul 09 04:44:27 PM PDT 24
Peak memory 216532 kb
Host smart-b89dfe05-cceb-4ecf-b849-4ba5dd8f3d22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314626866 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.314626866
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.89311299
Short name T656
Test name
Test status
Simulation time 101336700024 ps
CPU time 24.26 seconds
Started Jul 09 04:32:41 PM PDT 24
Finished Jul 09 04:33:06 PM PDT 24
Peak memory 199860 kb
Host smart-d5369388-116f-454c-8256-2712ddf6b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89311299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.89311299
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2097011227
Short name T601
Test name
Test status
Simulation time 97112360622 ps
CPU time 111.58 seconds
Started Jul 09 04:32:40 PM PDT 24
Finished Jul 09 04:34:32 PM PDT 24
Peak memory 208148 kb
Host smart-666afc40-3e5d-48ed-b75a-a521c2a1d23f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097011227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2097011227
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1549133750
Short name T1138
Test name
Test status
Simulation time 156998473044 ps
CPU time 118.86 seconds
Started Jul 09 04:32:41 PM PDT 24
Finished Jul 09 04:34:41 PM PDT 24
Peak memory 199744 kb
Host smart-1486693a-c437-411e-ae15-d2860bb9879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549133750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1549133750
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3939697523
Short name T1026
Test name
Test status
Simulation time 180733575097 ps
CPU time 507.38 seconds
Started Jul 09 04:32:43 PM PDT 24
Finished Jul 09 04:41:11 PM PDT 24
Peak memory 216280 kb
Host smart-9fcf0027-3bcc-4e28-a0a5-615157eb5d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939697523 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3939697523
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1527009268
Short name T882
Test name
Test status
Simulation time 109082644152 ps
CPU time 115.25 seconds
Started Jul 09 04:32:44 PM PDT 24
Finished Jul 09 04:34:40 PM PDT 24
Peak memory 199780 kb
Host smart-fe22fbce-7fcd-46b3-b50d-eef198ee76d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527009268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1527009268
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1032649578
Short name T1043
Test name
Test status
Simulation time 11192652317 ps
CPU time 68.48 seconds
Started Jul 09 04:32:48 PM PDT 24
Finished Jul 09 04:33:57 PM PDT 24
Peak memory 215940 kb
Host smart-d73d4af6-d7af-4a6a-b067-50ece6c13644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032649578 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1032649578
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3729555876
Short name T2
Test name
Test status
Simulation time 30105477 ps
CPU time 0.55 seconds
Started Jul 09 04:30:40 PM PDT 24
Finished Jul 09 04:30:43 PM PDT 24
Peak memory 194092 kb
Host smart-7ec06907-535d-4543-9204-3f015fae613d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729555876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3729555876
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1594796007
Short name T138
Test name
Test status
Simulation time 159092410101 ps
CPU time 150.3 seconds
Started Jul 09 04:30:35 PM PDT 24
Finished Jul 09 04:33:07 PM PDT 24
Peak memory 200128 kb
Host smart-1399bfdd-e58e-4c5d-9f9d-bd728d4f7236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594796007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1594796007
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2439190197
Short name T1096
Test name
Test status
Simulation time 64658462394 ps
CPU time 98.9 seconds
Started Jul 09 04:30:40 PM PDT 24
Finished Jul 09 04:32:21 PM PDT 24
Peak memory 199648 kb
Host smart-10b58eee-d094-42df-9de9-4c3fed8259df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439190197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2439190197
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3455221916
Short name T405
Test name
Test status
Simulation time 9425049346 ps
CPU time 18.26 seconds
Started Jul 09 04:30:35 PM PDT 24
Finished Jul 09 04:30:55 PM PDT 24
Peak memory 199652 kb
Host smart-73690374-505b-41d1-a6d5-e1f59c6622d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455221916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3455221916
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3872917170
Short name T670
Test name
Test status
Simulation time 22609576065 ps
CPU time 34.55 seconds
Started Jul 09 04:30:41 PM PDT 24
Finished Jul 09 04:31:18 PM PDT 24
Peak memory 199864 kb
Host smart-0285775f-43b0-4a5f-98f1-d3a0d328c042
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872917170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3872917170
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.125791076
Short name T43
Test name
Test status
Simulation time 121815230268 ps
CPU time 977.64 seconds
Started Jul 09 04:30:34 PM PDT 24
Finished Jul 09 04:46:54 PM PDT 24
Peak memory 199680 kb
Host smart-db65c26c-bc7d-48b2-9e1d-6f69836159f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=125791076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.125791076
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1609472664
Short name T953
Test name
Test status
Simulation time 942074081 ps
CPU time 1.08 seconds
Started Jul 09 04:30:49 PM PDT 24
Finished Jul 09 04:30:53 PM PDT 24
Peak memory 197136 kb
Host smart-cf150550-739f-45c9-a8b3-c45b83cea247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609472664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1609472664
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2094384869
Short name T561
Test name
Test status
Simulation time 25791768902 ps
CPU time 34.94 seconds
Started Jul 09 04:30:51 PM PDT 24
Finished Jul 09 04:31:29 PM PDT 24
Peak memory 198140 kb
Host smart-2c559015-4314-40c4-be5b-ea96f614c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094384869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2094384869
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3134269383
Short name T433
Test name
Test status
Simulation time 19652566903 ps
CPU time 122.98 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:32:52 PM PDT 24
Peak memory 199720 kb
Host smart-52ef929f-f191-4fd5-966e-e867396a227f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134269383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3134269383
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3553594486
Short name T672
Test name
Test status
Simulation time 6495577869 ps
CPU time 12.67 seconds
Started Jul 09 04:30:36 PM PDT 24
Finished Jul 09 04:30:50 PM PDT 24
Peak memory 199092 kb
Host smart-2e964a95-7f02-4fb2-8c94-7ba49a7d7981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553594486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3553594486
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2388167829
Short name T552
Test name
Test status
Simulation time 169049649347 ps
CPU time 393.92 seconds
Started Jul 09 04:30:39 PM PDT 24
Finished Jul 09 04:37:16 PM PDT 24
Peak memory 199780 kb
Host smart-2e852494-0a49-4b4a-ba77-8ce9e3ff8ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388167829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2388167829
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.645271940
Short name T855
Test name
Test status
Simulation time 80826651463 ps
CPU time 67.35 seconds
Started Jul 09 04:30:40 PM PDT 24
Finished Jul 09 04:31:50 PM PDT 24
Peak memory 196528 kb
Host smart-513a5b49-04b3-4b53-8466-8dc319aaa27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645271940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.645271940
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.489244374
Short name T818
Test name
Test status
Simulation time 753449464 ps
CPU time 1.04 seconds
Started Jul 09 04:30:30 PM PDT 24
Finished Jul 09 04:30:35 PM PDT 24
Peak memory 198504 kb
Host smart-73b0646e-100f-4231-bee7-2b4e503cff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489244374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.489244374
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1609406063
Short name T970
Test name
Test status
Simulation time 114075867191 ps
CPU time 35.91 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:31:24 PM PDT 24
Peak memory 199756 kb
Host smart-58de4e4a-00c6-4eb4-90c4-a26c2d33dedf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609406063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1609406063
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1733296239
Short name T678
Test name
Test status
Simulation time 8391356979 ps
CPU time 7.18 seconds
Started Jul 09 04:30:30 PM PDT 24
Finished Jul 09 04:30:41 PM PDT 24
Peak memory 199492 kb
Host smart-7fb87586-38c5-460d-8df0-3dbb3b41c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733296239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1733296239
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1367623050
Short name T5
Test name
Test status
Simulation time 63729286384 ps
CPU time 140.02 seconds
Started Jul 09 04:30:25 PM PDT 24
Finished Jul 09 04:32:50 PM PDT 24
Peak memory 199648 kb
Host smart-d58f02c9-3d31-4ba7-bf56-08bb872758af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367623050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1367623050
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3904992558
Short name T468
Test name
Test status
Simulation time 77782853929 ps
CPU time 25.61 seconds
Started Jul 09 04:32:48 PM PDT 24
Finished Jul 09 04:33:14 PM PDT 24
Peak memory 199604 kb
Host smart-a4a906b9-d6e1-4405-adcc-198f87078686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904992558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3904992558
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3281051739
Short name T533
Test name
Test status
Simulation time 174709434580 ps
CPU time 846.56 seconds
Started Jul 09 04:32:46 PM PDT 24
Finished Jul 09 04:46:53 PM PDT 24
Peak memory 224676 kb
Host smart-f160bc86-f2cc-404f-b0f3-ead3b8ca2851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281051739 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3281051739
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3101822004
Short name T1140
Test name
Test status
Simulation time 52871894233 ps
CPU time 115.56 seconds
Started Jul 09 04:32:48 PM PDT 24
Finished Jul 09 04:34:44 PM PDT 24
Peak memory 199568 kb
Host smart-bbcebb9b-7c46-422c-90c3-eff987b14700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101822004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3101822004
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1788274703
Short name T787
Test name
Test status
Simulation time 126571146804 ps
CPU time 838.76 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:46:50 PM PDT 24
Peak memory 216312 kb
Host smart-9d605125-ba83-40e3-9fff-7ce56b7a9432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788274703 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1788274703
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1841140335
Short name T1153
Test name
Test status
Simulation time 97648631159 ps
CPU time 37.13 seconds
Started Jul 09 04:32:44 PM PDT 24
Finished Jul 09 04:33:22 PM PDT 24
Peak memory 199812 kb
Host smart-aa67c69c-29ba-47ed-b5f4-bddb541a8842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841140335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1841140335
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1148079767
Short name T307
Test name
Test status
Simulation time 8496760476 ps
CPU time 51.95 seconds
Started Jul 09 04:32:45 PM PDT 24
Finished Jul 09 04:33:37 PM PDT 24
Peak memory 216556 kb
Host smart-c35fb4b9-d672-470c-a23b-1ae4c7452141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148079767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1148079767
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.243933888
Short name T832
Test name
Test status
Simulation time 48449692127 ps
CPU time 33.15 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:33:24 PM PDT 24
Peak memory 199720 kb
Host smart-c6e80109-680e-46f0-be42-14aa4e395981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243933888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.243933888
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.312818219
Short name T480
Test name
Test status
Simulation time 138373407852 ps
CPU time 253.78 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:37:02 PM PDT 24
Peak memory 216412 kb
Host smart-3aa32a36-f424-4c3b-b26a-1dd2b48008e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312818219 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.312818219
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.741245390
Short name T979
Test name
Test status
Simulation time 402403961978 ps
CPU time 36.94 seconds
Started Jul 09 04:32:48 PM PDT 24
Finished Jul 09 04:33:26 PM PDT 24
Peak memory 199736 kb
Host smart-41a4c680-800d-4a2f-8170-4a074248f0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741245390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.741245390
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1218194441
Short name T235
Test name
Test status
Simulation time 13167764412 ps
CPU time 9.63 seconds
Started Jul 09 04:32:57 PM PDT 24
Finished Jul 09 04:33:08 PM PDT 24
Peak memory 199252 kb
Host smart-6e70ac65-7d80-4c95-af66-25351bb3b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218194441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1218194441
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.761786851
Short name T912
Test name
Test status
Simulation time 224281177427 ps
CPU time 824.42 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:46:32 PM PDT 24
Peak memory 216424 kb
Host smart-31153af1-db59-4e74-9a15-a44da794c191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761786851 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.761786851
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1458080335
Short name T747
Test name
Test status
Simulation time 142839004068 ps
CPU time 101.19 seconds
Started Jul 09 04:32:45 PM PDT 24
Finished Jul 09 04:34:27 PM PDT 24
Peak memory 199716 kb
Host smart-a5971f15-f727-42cf-8759-3b823ce50330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458080335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1458080335
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.232059593
Short name T407
Test name
Test status
Simulation time 21966674004 ps
CPU time 254.43 seconds
Started Jul 09 04:32:49 PM PDT 24
Finished Jul 09 04:37:04 PM PDT 24
Peak memory 208096 kb
Host smart-a88f5b45-a399-45ec-95c4-cd7c9a75098d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232059593 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.232059593
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3376696512
Short name T193
Test name
Test status
Simulation time 116660661745 ps
CPU time 176.88 seconds
Started Jul 09 04:32:45 PM PDT 24
Finished Jul 09 04:35:42 PM PDT 24
Peak memory 199812 kb
Host smart-76b7f579-47d8-4a95-b971-82a275523cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376696512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3376696512
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3060100610
Short name T1127
Test name
Test status
Simulation time 40757534122 ps
CPU time 361.37 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:38:49 PM PDT 24
Peak memory 215900 kb
Host smart-d377f73a-ddc1-4440-8eb4-b8de8bd1c5f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060100610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3060100610
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2127533551
Short name T896
Test name
Test status
Simulation time 87586950743 ps
CPU time 288.12 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:37:38 PM PDT 24
Peak memory 199776 kb
Host smart-5d3d03fe-b84e-4abd-bbe8-5ebf77e09ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127533551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2127533551
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2584064092
Short name T1119
Test name
Test status
Simulation time 355704942730 ps
CPU time 1146.07 seconds
Started Jul 09 04:32:48 PM PDT 24
Finished Jul 09 04:51:55 PM PDT 24
Peak memory 224724 kb
Host smart-68fc268b-0a2e-47ae-a38b-c00cd9c7617f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584064092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2584064092
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4072667
Short name T215
Test name
Test status
Simulation time 103354057404 ps
CPU time 147.01 seconds
Started Jul 09 04:32:45 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 199836 kb
Host smart-ea8f888a-b8cd-4bdf-bf32-5a014c092624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4072667
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3452594528
Short name T1060
Test name
Test status
Simulation time 251796806668 ps
CPU time 326.04 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:38:14 PM PDT 24
Peak memory 215688 kb
Host smart-c800a302-bb5e-479f-b3ac-739e33d6f0cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452594528 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3452594528
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1972200576
Short name T904
Test name
Test status
Simulation time 23211146 ps
CPU time 0.56 seconds
Started Jul 09 04:30:36 PM PDT 24
Finished Jul 09 04:30:39 PM PDT 24
Peak memory 195124 kb
Host smart-385c8ab5-0bb6-4b3c-9c0c-5b1928f92737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972200576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1972200576
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3564148891
Short name T500
Test name
Test status
Simulation time 38794074872 ps
CPU time 11.14 seconds
Started Jul 09 04:30:36 PM PDT 24
Finished Jul 09 04:30:49 PM PDT 24
Peak memory 198228 kb
Host smart-3193fc8a-52ff-4946-9aed-e4a90db990c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564148891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3564148891
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3131893582
Short name T390
Test name
Test status
Simulation time 171716488734 ps
CPU time 254.12 seconds
Started Jul 09 04:30:46 PM PDT 24
Finished Jul 09 04:35:01 PM PDT 24
Peak memory 199804 kb
Host smart-9db630b2-2c4d-4a39-8276-0755ce85491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131893582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3131893582
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3921215764
Short name T413
Test name
Test status
Simulation time 15492980525 ps
CPU time 26.1 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:31:24 PM PDT 24
Peak memory 199428 kb
Host smart-ef18fbf4-37ff-4afa-a593-dcee52a08dbd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921215764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3921215764
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2784574479
Short name T1053
Test name
Test status
Simulation time 143682136766 ps
CPU time 1238.48 seconds
Started Jul 09 04:30:51 PM PDT 24
Finished Jul 09 04:51:34 PM PDT 24
Peak memory 199732 kb
Host smart-45cd14a5-86c6-45e4-9f3f-7edf0a29b63a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784574479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2784574479
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1356598092
Short name T955
Test name
Test status
Simulation time 4878617616 ps
CPU time 11.8 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:31:09 PM PDT 24
Peak memory 198720 kb
Host smart-57e155ed-6928-4820-97c2-9788a550a301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356598092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1356598092
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2380871619
Short name T982
Test name
Test status
Simulation time 62196796872 ps
CPU time 122.19 seconds
Started Jul 09 04:30:39 PM PDT 24
Finished Jul 09 04:32:43 PM PDT 24
Peak memory 208108 kb
Host smart-34c12bfc-2637-4566-a434-2e1538634606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380871619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2380871619
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.712708356
Short name T1159
Test name
Test status
Simulation time 13234950091 ps
CPU time 371.98 seconds
Started Jul 09 04:30:33 PM PDT 24
Finished Jul 09 04:36:48 PM PDT 24
Peak memory 199800 kb
Host smart-6d7671b2-7698-4b5d-90a6-4094997c78cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712708356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.712708356
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1711003347
Short name T334
Test name
Test status
Simulation time 6021077872 ps
CPU time 13.09 seconds
Started Jul 09 04:30:59 PM PDT 24
Finished Jul 09 04:31:26 PM PDT 24
Peak memory 199316 kb
Host smart-98e456a5-d733-426b-bd43-a034c8ed4d1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711003347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1711003347
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3862353876
Short name T1063
Test name
Test status
Simulation time 84232403878 ps
CPU time 72.68 seconds
Started Jul 09 04:30:45 PM PDT 24
Finished Jul 09 04:31:58 PM PDT 24
Peak memory 200180 kb
Host smart-dd84193f-13cd-4209-a46d-c1d911add903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862353876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3862353876
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3172806288
Short name T587
Test name
Test status
Simulation time 37673629176 ps
CPU time 59.76 seconds
Started Jul 09 04:30:41 PM PDT 24
Finished Jul 09 04:31:42 PM PDT 24
Peak memory 195636 kb
Host smart-bc9d8580-b7d8-49b3-bcab-ae804754fa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172806288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3172806288
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2225218499
Short name T595
Test name
Test status
Simulation time 607151558 ps
CPU time 3.65 seconds
Started Jul 09 04:30:36 PM PDT 24
Finished Jul 09 04:30:41 PM PDT 24
Peak memory 198556 kb
Host smart-969f2075-5f9a-462f-8060-d5c5d402ec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225218499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2225218499
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.931381968
Short name T170
Test name
Test status
Simulation time 542521141540 ps
CPU time 248.72 seconds
Started Jul 09 04:30:38 PM PDT 24
Finished Jul 09 04:34:49 PM PDT 24
Peak memory 208156 kb
Host smart-3b4b2a04-e4a7-4b5c-b434-7527901ffb57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931381968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.931381968
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1783011546
Short name T740
Test name
Test status
Simulation time 6347594355 ps
CPU time 16.34 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:31:05 PM PDT 24
Peak memory 199180 kb
Host smart-b3c80679-4383-4c5d-aae2-a330554863d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783011546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1783011546
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3616758861
Short name T710
Test name
Test status
Simulation time 2609964627 ps
CPU time 2.35 seconds
Started Jul 09 04:30:40 PM PDT 24
Finished Jul 09 04:30:45 PM PDT 24
Peak memory 196460 kb
Host smart-388553d3-b265-469f-8786-82da9e579b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616758861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3616758861
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1302494204
Short name T814
Test name
Test status
Simulation time 26393613057 ps
CPU time 19.09 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:33:09 PM PDT 24
Peak memory 199740 kb
Host smart-a10247b5-7e11-4821-a174-4df01fb17775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302494204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1302494204
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1169100283
Short name T527
Test name
Test status
Simulation time 53863460275 ps
CPU time 601.46 seconds
Started Jul 09 04:32:48 PM PDT 24
Finished Jul 09 04:42:50 PM PDT 24
Peak memory 210884 kb
Host smart-9a6e796c-2d10-4264-a910-c725bdc5f264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169100283 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1169100283
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1774697738
Short name T758
Test name
Test status
Simulation time 92120842164 ps
CPU time 132.62 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:35:01 PM PDT 24
Peak memory 199856 kb
Host smart-39cc851b-aa47-47aa-9401-158ee4d0fecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774697738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1774697738
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2445302497
Short name T1009
Test name
Test status
Simulation time 19430039548 ps
CPU time 415.19 seconds
Started Jul 09 04:32:51 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 216480 kb
Host smart-79160ba1-a211-42a8-bfb0-16a6c6b30c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445302497 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2445302497
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3071555501
Short name T181
Test name
Test status
Simulation time 125768836122 ps
CPU time 62.17 seconds
Started Jul 09 04:32:47 PM PDT 24
Finished Jul 09 04:33:50 PM PDT 24
Peak memory 199352 kb
Host smart-b8b2331f-2fb5-40ff-aaf1-66f9b0aa6afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071555501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3071555501
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3614409871
Short name T1039
Test name
Test status
Simulation time 25901196682 ps
CPU time 225.07 seconds
Started Jul 09 04:32:57 PM PDT 24
Finished Jul 09 04:36:43 PM PDT 24
Peak memory 216552 kb
Host smart-baf6ad2c-b61c-4c8e-be59-d6c0badc5395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614409871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3614409871
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2300626342
Short name T139
Test name
Test status
Simulation time 26355338897 ps
CPU time 36.79 seconds
Started Jul 09 04:33:01 PM PDT 24
Finished Jul 09 04:33:39 PM PDT 24
Peak memory 199912 kb
Host smart-9593ed35-fea5-42e4-9585-4d03db8fa774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300626342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2300626342
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.489311241
Short name T546
Test name
Test status
Simulation time 182502624151 ps
CPU time 402.35 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 224392 kb
Host smart-747ebf7c-f79f-48d9-8eea-ab9368fe2627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489311241 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.489311241
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3101965257
Short name T484
Test name
Test status
Simulation time 83644793057 ps
CPU time 238.7 seconds
Started Jul 09 04:32:52 PM PDT 24
Finished Jul 09 04:36:52 PM PDT 24
Peak memory 216284 kb
Host smart-569c1824-c4b7-4b21-aa50-24e9147bd1ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101965257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3101965257
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3295582254
Short name T194
Test name
Test status
Simulation time 34307834830 ps
CPU time 58.31 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:33:49 PM PDT 24
Peak memory 199856 kb
Host smart-41f5e575-1607-422e-9f1e-3ced50b95c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295582254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3295582254
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.740777683
Short name T225
Test name
Test status
Simulation time 49081542434 ps
CPU time 147.78 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:35:19 PM PDT 24
Peak memory 216492 kb
Host smart-674d1861-546e-4887-8889-bea75de99505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740777683 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.740777683
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1032925161
Short name T201
Test name
Test status
Simulation time 34567763144 ps
CPU time 46.97 seconds
Started Jul 09 04:32:51 PM PDT 24
Finished Jul 09 04:33:39 PM PDT 24
Peak memory 199760 kb
Host smart-dbe045f4-2c76-4082-bb39-f0e2e293ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032925161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1032925161
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2963707413
Short name T646
Test name
Test status
Simulation time 166185494857 ps
CPU time 938.99 seconds
Started Jul 09 04:32:52 PM PDT 24
Finished Jul 09 04:48:32 PM PDT 24
Peak memory 216160 kb
Host smart-a4030d03-7ad2-4f45-a578-5f84e02832b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963707413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2963707413
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2594516254
Short name T641
Test name
Test status
Simulation time 186644195460 ps
CPU time 176.3 seconds
Started Jul 09 04:33:01 PM PDT 24
Finished Jul 09 04:35:58 PM PDT 24
Peak memory 199916 kb
Host smart-a323ec3d-99bd-462f-98b1-4c74ee0242c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594516254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2594516254
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1200360231
Short name T1064
Test name
Test status
Simulation time 43712757326 ps
CPU time 174.71 seconds
Started Jul 09 04:32:52 PM PDT 24
Finished Jul 09 04:35:48 PM PDT 24
Peak memory 212428 kb
Host smart-3ef321eb-7311-432a-a42f-c82db80a6b43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200360231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1200360231
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1208959158
Short name T298
Test name
Test status
Simulation time 28380535768 ps
CPU time 19.1 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:33:09 PM PDT 24
Peak memory 199772 kb
Host smart-3c3237ea-898a-4f04-a4ed-15affc0db450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208959158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1208959158
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.189904711
Short name T108
Test name
Test status
Simulation time 155046570513 ps
CPU time 805.66 seconds
Started Jul 09 04:32:54 PM PDT 24
Finished Jul 09 04:46:20 PM PDT 24
Peak memory 224664 kb
Host smart-9a02bddb-97c4-4d5b-a0fb-d24f2fbfeef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189904711 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.189904711
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1830834716
Short name T438
Test name
Test status
Simulation time 90706907447 ps
CPU time 97.13 seconds
Started Jul 09 04:32:51 PM PDT 24
Finished Jul 09 04:34:29 PM PDT 24
Peak memory 199704 kb
Host smart-090fb5e2-ad0e-4e14-96d3-cdf45d97eae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830834716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1830834716
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3297210233
Short name T308
Test name
Test status
Simulation time 314638561559 ps
CPU time 1096.58 seconds
Started Jul 09 04:32:52 PM PDT 24
Finished Jul 09 04:51:10 PM PDT 24
Peak memory 227608 kb
Host smart-186e0cc4-eca8-48d5-af1c-1a50157c5472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297210233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3297210233
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2612477403
Short name T402
Test name
Test status
Simulation time 43742728 ps
CPU time 0.57 seconds
Started Jul 09 04:30:46 PM PDT 24
Finished Jul 09 04:30:47 PM PDT 24
Peak memory 195052 kb
Host smart-028c6b50-80d6-44b9-b5dc-ab12db9383bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612477403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2612477403
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1207334503
Short name T301
Test name
Test status
Simulation time 125156619984 ps
CPU time 185.75 seconds
Started Jul 09 04:30:41 PM PDT 24
Finished Jul 09 04:33:49 PM PDT 24
Peak memory 199796 kb
Host smart-2169ea29-c0ee-4c09-b8d3-1c883de3d56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207334503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1207334503
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3828556915
Short name T256
Test name
Test status
Simulation time 124996030012 ps
CPU time 51.24 seconds
Started Jul 09 04:30:34 PM PDT 24
Finished Jul 09 04:31:28 PM PDT 24
Peak memory 199568 kb
Host smart-1a14107a-27cb-40e4-aa97-4fed2ec460df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828556915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3828556915
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2536944598
Short name T575
Test name
Test status
Simulation time 29643263757 ps
CPU time 9.92 seconds
Started Jul 09 04:30:53 PM PDT 24
Finished Jul 09 04:31:09 PM PDT 24
Peak memory 199784 kb
Host smart-1af5bc9a-3fb2-4769-b08f-0405c33d29b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536944598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2536944598
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2006200338
Short name T421
Test name
Test status
Simulation time 43918478489 ps
CPU time 26.1 seconds
Started Jul 09 04:30:46 PM PDT 24
Finished Jul 09 04:31:13 PM PDT 24
Peak memory 199728 kb
Host smart-6346aa83-a894-4bbd-bb1e-8148b177148f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006200338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2006200338
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2311755919
Short name T395
Test name
Test status
Simulation time 153077319037 ps
CPU time 298.89 seconds
Started Jul 09 04:30:48 PM PDT 24
Finished Jul 09 04:35:49 PM PDT 24
Peak memory 199860 kb
Host smart-1ae7d40f-9df6-4c45-b64b-2da7465872c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311755919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2311755919
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.734867778
Short name T1144
Test name
Test status
Simulation time 4142618460 ps
CPU time 2.76 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:31:00 PM PDT 24
Peak memory 198572 kb
Host smart-21c0e6ef-aaf8-4132-b071-d267c219c772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734867778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.734867778
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.288019925
Short name T1044
Test name
Test status
Simulation time 109610932349 ps
CPU time 83.79 seconds
Started Jul 09 04:30:42 PM PDT 24
Finished Jul 09 04:32:08 PM PDT 24
Peak memory 199452 kb
Host smart-9babe473-a7a2-404a-8b0a-b342e116d631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288019925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.288019925
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3981710406
Short name T711
Test name
Test status
Simulation time 12895936370 ps
CPU time 568.49 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:40:17 PM PDT 24
Peak memory 199780 kb
Host smart-9ecdcb6e-ac5f-4d08-b8a4-24b822b0ed72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981710406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3981710406
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1837823789
Short name T957
Test name
Test status
Simulation time 1489949720 ps
CPU time 3.18 seconds
Started Jul 09 04:30:54 PM PDT 24
Finished Jul 09 04:31:04 PM PDT 24
Peak memory 197868 kb
Host smart-f18eef38-33ff-4178-8bdf-539097f5c738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1837823789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1837823789
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1229084247
Short name T1061
Test name
Test status
Simulation time 41868208769 ps
CPU time 45.11 seconds
Started Jul 09 04:30:41 PM PDT 24
Finished Jul 09 04:31:28 PM PDT 24
Peak memory 199876 kb
Host smart-df245fcf-3e52-43c4-a2fd-8c3636737866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229084247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1229084247
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2854649403
Short name T1151
Test name
Test status
Simulation time 36100503960 ps
CPU time 57.57 seconds
Started Jul 09 04:30:40 PM PDT 24
Finished Jul 09 04:31:40 PM PDT 24
Peak memory 195592 kb
Host smart-b2b33153-c533-484f-9a5d-01adb39954d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854649403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2854649403
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3410878133
Short name T3
Test name
Test status
Simulation time 6283124045 ps
CPU time 8.99 seconds
Started Jul 09 04:30:43 PM PDT 24
Finished Jul 09 04:30:53 PM PDT 24
Peak memory 199768 kb
Host smart-b39707ab-90c1-4d06-bbf6-62a9329f65e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410878133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3410878133
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3157688421
Short name T526
Test name
Test status
Simulation time 334769622586 ps
CPU time 773.73 seconds
Started Jul 09 04:30:39 PM PDT 24
Finished Jul 09 04:43:35 PM PDT 24
Peak memory 208204 kb
Host smart-4a21c185-69b7-418e-b313-e2292e325bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157688421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3157688421
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1121452274
Short name T1173
Test name
Test status
Simulation time 8890572083 ps
CPU time 398.59 seconds
Started Jul 09 04:30:56 PM PDT 24
Finished Jul 09 04:37:45 PM PDT 24
Peak memory 200048 kb
Host smart-88f924f9-e938-444c-bf4e-9cdec5bb374e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121452274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1121452274
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.891383606
Short name T560
Test name
Test status
Simulation time 1626625214 ps
CPU time 1.56 seconds
Started Jul 09 04:30:57 PM PDT 24
Finished Jul 09 04:31:15 PM PDT 24
Peak memory 198344 kb
Host smart-aba701c4-3b17-4c54-b710-48cd904f9b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891383606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.891383606
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1316036357
Short name T465
Test name
Test status
Simulation time 72457466947 ps
CPU time 111.75 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:32:40 PM PDT 24
Peak memory 199820 kb
Host smart-1a1792ad-74a2-4965-828d-cb5529e64ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316036357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1316036357
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3779506672
Short name T1110
Test name
Test status
Simulation time 71863726504 ps
CPU time 30.72 seconds
Started Jul 09 04:33:01 PM PDT 24
Finished Jul 09 04:33:32 PM PDT 24
Peak memory 199940 kb
Host smart-fa950a19-5ff4-4db5-afe9-663c774513d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779506672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3779506672
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2528787962
Short name T32
Test name
Test status
Simulation time 35336271655 ps
CPU time 200.32 seconds
Started Jul 09 04:32:52 PM PDT 24
Finished Jul 09 04:36:13 PM PDT 24
Peak memory 215208 kb
Host smart-589bdfe2-7402-42a8-87f5-a0ee83370cc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528787962 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2528787962
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1990169356
Short name T114
Test name
Test status
Simulation time 31921547804 ps
CPU time 29.33 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:33:32 PM PDT 24
Peak memory 199396 kb
Host smart-72842ee1-7ca8-4a6c-a37b-9849719000e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990169356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1990169356
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.713837898
Short name T305
Test name
Test status
Simulation time 20861685784 ps
CPU time 56.69 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:33:48 PM PDT 24
Peak memory 216072 kb
Host smart-d7489e9a-c00e-49df-b38f-1e42ea04e8ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713837898 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.713837898
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1059443265
Short name T990
Test name
Test status
Simulation time 36084986601 ps
CPU time 62.58 seconds
Started Jul 09 04:33:02 PM PDT 24
Finished Jul 09 04:34:06 PM PDT 24
Peak memory 199916 kb
Host smart-c792b13f-7896-47c3-8b59-7a399252af00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059443265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1059443265
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2525012863
Short name T76
Test name
Test status
Simulation time 48160603042 ps
CPU time 210.84 seconds
Started Jul 09 04:32:51 PM PDT 24
Finished Jul 09 04:36:23 PM PDT 24
Peak memory 215652 kb
Host smart-67d437f5-8311-4746-b2b6-653838c76439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525012863 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2525012863
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3170387461
Short name T210
Test name
Test status
Simulation time 106186438649 ps
CPU time 218.29 seconds
Started Jul 09 04:32:50 PM PDT 24
Finished Jul 09 04:36:29 PM PDT 24
Peak memory 199832 kb
Host smart-e020621f-78a1-4573-b0a3-445c711d5989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170387461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3170387461
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3464227189
Short name T1073
Test name
Test status
Simulation time 222826393965 ps
CPU time 472.74 seconds
Started Jul 09 04:32:53 PM PDT 24
Finished Jul 09 04:40:47 PM PDT 24
Peak memory 216400 kb
Host smart-c2b1d412-baf5-4008-a87d-c657bd0d3f64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464227189 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3464227189
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2586986986
Short name T1150
Test name
Test status
Simulation time 30554673057 ps
CPU time 276.21 seconds
Started Jul 09 04:32:53 PM PDT 24
Finished Jul 09 04:37:30 PM PDT 24
Peak memory 215460 kb
Host smart-6ed0ae5a-a71b-4043-8aeb-24e4ffef5168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586986986 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2586986986
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1908388773
Short name T682
Test name
Test status
Simulation time 170496472508 ps
CPU time 163.61 seconds
Started Jul 09 04:32:52 PM PDT 24
Finished Jul 09 04:35:36 PM PDT 24
Peak memory 199716 kb
Host smart-dcfef418-4f31-42f4-8064-79c40426eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908388773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1908388773
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1934012878
Short name T1037
Test name
Test status
Simulation time 13201510744 ps
CPU time 112.75 seconds
Started Jul 09 04:32:51 PM PDT 24
Finished Jul 09 04:34:44 PM PDT 24
Peak memory 208752 kb
Host smart-1b2f3bb1-88d7-4663-92ae-7636f50f6bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934012878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1934012878
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.812038482
Short name T936
Test name
Test status
Simulation time 115277999957 ps
CPU time 134.7 seconds
Started Jul 09 04:32:51 PM PDT 24
Finished Jul 09 04:35:07 PM PDT 24
Peak memory 199780 kb
Host smart-027e5282-4ef2-4b7a-8afc-5edbc24ff45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812038482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.812038482
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1835379455
Short name T63
Test name
Test status
Simulation time 221624706443 ps
CPU time 249.36 seconds
Started Jul 09 04:32:52 PM PDT 24
Finished Jul 09 04:37:02 PM PDT 24
Peak memory 216428 kb
Host smart-871cb7f7-9cf4-4e88-b3a9-997138cb94d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835379455 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1835379455
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1780232654
Short name T320
Test name
Test status
Simulation time 23220733270 ps
CPU time 11.83 seconds
Started Jul 09 04:32:51 PM PDT 24
Finished Jul 09 04:33:04 PM PDT 24
Peak memory 199740 kb
Host smart-65ed9336-2aeb-4659-890e-e1a44b08c31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780232654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1780232654
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.35540241
Short name T466
Test name
Test status
Simulation time 22526184808 ps
CPU time 160.46 seconds
Started Jul 09 04:32:56 PM PDT 24
Finished Jul 09 04:35:37 PM PDT 24
Peak memory 215504 kb
Host smart-4362bfb5-bae0-4d52-a76c-651708f1d54c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35540241 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.35540241
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.824185331
Short name T182
Test name
Test status
Simulation time 70801020746 ps
CPU time 107.15 seconds
Started Jul 09 04:32:56 PM PDT 24
Finished Jul 09 04:34:44 PM PDT 24
Peak memory 199796 kb
Host smart-98e75759-33b0-4401-b3e0-0d87e72e9991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824185331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.824185331
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1085796159
Short name T35
Test name
Test status
Simulation time 54774142388 ps
CPU time 494.86 seconds
Started Jul 09 04:32:55 PM PDT 24
Finished Jul 09 04:41:11 PM PDT 24
Peak memory 216272 kb
Host smart-3eb7bb33-3e03-47f2-8eba-53cf21a29ec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085796159 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1085796159
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2527853851
Short name T165
Test name
Test status
Simulation time 11232325143 ps
CPU time 21.69 seconds
Started Jul 09 04:32:56 PM PDT 24
Finished Jul 09 04:33:19 PM PDT 24
Peak memory 199680 kb
Host smart-a31461b5-918c-431e-9d06-0c762d48ba09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527853851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2527853851
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4160627864
Short name T1028
Test name
Test status
Simulation time 88066868 ps
CPU time 0.55 seconds
Started Jul 09 04:30:42 PM PDT 24
Finished Jul 09 04:30:44 PM PDT 24
Peak memory 195132 kb
Host smart-db7910cc-8bc0-43ae-b94d-5bac360f295c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160627864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4160627864
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1284132852
Short name T431
Test name
Test status
Simulation time 22254129560 ps
CPU time 11.35 seconds
Started Jul 09 04:30:46 PM PDT 24
Finished Jul 09 04:30:58 PM PDT 24
Peak memory 199700 kb
Host smart-f7137e19-578d-4913-bdba-40eaa8f2241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284132852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1284132852
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1032608513
Short name T959
Test name
Test status
Simulation time 92140234855 ps
CPU time 33.48 seconds
Started Jul 09 04:31:05 PM PDT 24
Finished Jul 09 04:31:57 PM PDT 24
Peak memory 199484 kb
Host smart-3b818d40-788a-4b29-a2c6-5378394a2158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032608513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1032608513
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.174830213
Short name T281
Test name
Test status
Simulation time 23065568355 ps
CPU time 45.1 seconds
Started Jul 09 04:30:48 PM PDT 24
Finished Jul 09 04:31:35 PM PDT 24
Peak memory 199796 kb
Host smart-a6e05218-31c8-4ff2-abd9-4479ffe107ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174830213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.174830213
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.451102642
Short name T326
Test name
Test status
Simulation time 7431259670 ps
CPU time 2.58 seconds
Started Jul 09 04:30:47 PM PDT 24
Finished Jul 09 04:30:50 PM PDT 24
Peak memory 196396 kb
Host smart-73e4c4d3-47a5-4da4-ae28-cf37c66d09cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451102642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.451102642
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.619568605
Short name T1136
Test name
Test status
Simulation time 61558591131 ps
CPU time 236.61 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:34:54 PM PDT 24
Peak memory 199788 kb
Host smart-a34772e2-f169-4c13-ad14-864d943acb6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619568605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.619568605
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1081239360
Short name T989
Test name
Test status
Simulation time 10282601267 ps
CPU time 19.61 seconds
Started Jul 09 04:30:48 PM PDT 24
Finished Jul 09 04:31:09 PM PDT 24
Peak memory 199812 kb
Host smart-5630e45f-9164-4304-a746-4a9350ef8aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081239360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1081239360
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2716475944
Short name T944
Test name
Test status
Simulation time 44040800845 ps
CPU time 71.07 seconds
Started Jul 09 04:30:39 PM PDT 24
Finished Jul 09 04:31:53 PM PDT 24
Peak memory 199676 kb
Host smart-772ed0c7-4a4f-47bd-868e-123f9d86a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716475944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2716475944
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1115958777
Short name T1004
Test name
Test status
Simulation time 25142642745 ps
CPU time 305.44 seconds
Started Jul 09 04:30:49 PM PDT 24
Finished Jul 09 04:35:57 PM PDT 24
Peak memory 199692 kb
Host smart-5603518c-a601-4cf9-8b76-623c9c9a767f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115958777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1115958777
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.81071251
Short name T1023
Test name
Test status
Simulation time 1586022437 ps
CPU time 5.7 seconds
Started Jul 09 04:30:33 PM PDT 24
Finished Jul 09 04:30:42 PM PDT 24
Peak memory 197780 kb
Host smart-9eb2489c-bb4b-4569-a89d-029afe9223d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81071251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.81071251
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.7557549
Short name T910
Test name
Test status
Simulation time 152680974962 ps
CPU time 19.39 seconds
Started Jul 09 04:30:55 PM PDT 24
Finished Jul 09 04:31:23 PM PDT 24
Peak memory 199748 kb
Host smart-d3ee770a-4755-4eb7-954c-a02b606b4a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7557549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.7557549
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1864213913
Short name T357
Test name
Test status
Simulation time 4736015992 ps
CPU time 4.14 seconds
Started Jul 09 04:30:48 PM PDT 24
Finished Jul 09 04:30:54 PM PDT 24
Peak memory 196020 kb
Host smart-2fa1f282-8b41-4957-ad10-6104698f34b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864213913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1864213913
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.265660878
Short name T683
Test name
Test status
Simulation time 303661682 ps
CPU time 0.95 seconds
Started Jul 09 04:30:55 PM PDT 24
Finished Jul 09 04:31:05 PM PDT 24
Peak memory 198376 kb
Host smart-c9df2e6b-c009-40da-816e-934fbd85eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265660878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.265660878
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1299248040
Short name T752
Test name
Test status
Simulation time 230886000053 ps
CPU time 726.47 seconds
Started Jul 09 04:30:53 PM PDT 24
Finished Jul 09 04:43:06 PM PDT 24
Peak memory 199856 kb
Host smart-ddd7896c-1016-46d1-90b7-366642a4f0b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299248040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1299248040
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1674475481
Short name T1015
Test name
Test status
Simulation time 754399150 ps
CPU time 2.94 seconds
Started Jul 09 04:30:50 PM PDT 24
Finished Jul 09 04:30:56 PM PDT 24
Peak memory 198684 kb
Host smart-e014013f-5dda-4d9f-b41f-1663f914d5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674475481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1674475481
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3719157815
Short name T361
Test name
Test status
Simulation time 45908537319 ps
CPU time 30.73 seconds
Started Jul 09 04:30:52 PM PDT 24
Finished Jul 09 04:31:28 PM PDT 24
Peak memory 199664 kb
Host smart-76e98872-1084-41cd-8858-1ba2e430f141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719157815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3719157815
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1505604995
Short name T142
Test name
Test status
Simulation time 31591216951 ps
CPU time 13.15 seconds
Started Jul 09 04:32:57 PM PDT 24
Finished Jul 09 04:33:11 PM PDT 24
Peak memory 199888 kb
Host smart-626eb43f-b1f5-4c10-8493-aa1c3a0fa960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505604995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1505604995
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.531455069
Short name T107
Test name
Test status
Simulation time 312238002298 ps
CPU time 261.33 seconds
Started Jul 09 04:32:59 PM PDT 24
Finished Jul 09 04:37:20 PM PDT 24
Peak memory 216568 kb
Host smart-caefbe42-e777-4d88-a32b-4e2600cdc446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531455069 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.531455069
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2774643548
Short name T240
Test name
Test status
Simulation time 133464965768 ps
CPU time 117.05 seconds
Started Jul 09 04:32:57 PM PDT 24
Finished Jul 09 04:34:55 PM PDT 24
Peak memory 199624 kb
Host smart-41e36cea-6c49-4234-ac04-4927a0113c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774643548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2774643548
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.721575248
Short name T304
Test name
Test status
Simulation time 493130207124 ps
CPU time 537.94 seconds
Started Jul 09 04:32:56 PM PDT 24
Finished Jul 09 04:41:55 PM PDT 24
Peak memory 216272 kb
Host smart-a49405c8-0ea2-4556-8aad-bf10b6456147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721575248 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.721575248
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1968737476
Short name T681
Test name
Test status
Simulation time 143627268226 ps
CPU time 178.37 seconds
Started Jul 09 04:32:56 PM PDT 24
Finished Jul 09 04:35:55 PM PDT 24
Peak memory 199824 kb
Host smart-d32bec05-945f-4f6f-b844-45949abd8857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968737476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1968737476
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1531363398
Short name T836
Test name
Test status
Simulation time 46723375394 ps
CPU time 154.86 seconds
Started Jul 09 04:32:54 PM PDT 24
Finished Jul 09 04:35:29 PM PDT 24
Peak memory 216428 kb
Host smart-79c66128-639c-4e17-8e31-42482f3083eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531363398 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1531363398
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1832894169
Short name T248
Test name
Test status
Simulation time 114206273406 ps
CPU time 81.76 seconds
Started Jul 09 04:32:57 PM PDT 24
Finished Jul 09 04:34:19 PM PDT 24
Peak memory 199736 kb
Host smart-8fc9f8a5-05d3-4d83-bd58-a7b75dab45e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832894169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1832894169
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3724617742
Short name T151
Test name
Test status
Simulation time 64710221362 ps
CPU time 339.28 seconds
Started Jul 09 04:32:55 PM PDT 24
Finished Jul 09 04:38:35 PM PDT 24
Peak memory 216416 kb
Host smart-fd9ac891-3d8d-41de-b168-e9f7b864388f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724617742 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3724617742
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1352323401
Short name T509
Test name
Test status
Simulation time 67438736983 ps
CPU time 164.38 seconds
Started Jul 09 04:32:55 PM PDT 24
Finished Jul 09 04:35:40 PM PDT 24
Peak memory 199832 kb
Host smart-04ac74ed-0f59-455d-bac7-2a5632c8a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352323401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1352323401
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3520344928
Short name T214
Test name
Test status
Simulation time 10213575830 ps
CPU time 17.55 seconds
Started Jul 09 04:32:54 PM PDT 24
Finished Jul 09 04:33:12 PM PDT 24
Peak memory 199736 kb
Host smart-1960e9c1-e0b9-4b87-99a5-aa30f1241d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520344928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3520344928
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1501007061
Short name T1030
Test name
Test status
Simulation time 55275206329 ps
CPU time 627.77 seconds
Started Jul 09 04:32:56 PM PDT 24
Finished Jul 09 04:43:25 PM PDT 24
Peak memory 224728 kb
Host smart-0e69e8de-b2e7-4539-8a55-8e59ca48f952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501007061 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1501007061
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.406244777
Short name T1083
Test name
Test status
Simulation time 34596039548 ps
CPU time 14.42 seconds
Started Jul 09 04:32:54 PM PDT 24
Finished Jul 09 04:33:09 PM PDT 24
Peak memory 199808 kb
Host smart-dab25d5e-dc13-4c7a-9cbc-cbe7816abfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406244777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.406244777
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3683926009
Short name T994
Test name
Test status
Simulation time 788537368934 ps
CPU time 830.59 seconds
Started Jul 09 04:32:58 PM PDT 24
Finished Jul 09 04:46:49 PM PDT 24
Peak memory 224728 kb
Host smart-63a7a11c-26eb-4dea-b1a7-55a915715ac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683926009 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3683926009
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3543413885
Short name T775
Test name
Test status
Simulation time 210136575109 ps
CPU time 83.88 seconds
Started Jul 09 04:32:57 PM PDT 24
Finished Jul 09 04:34:22 PM PDT 24
Peak memory 199520 kb
Host smart-4fe30fc7-3b8d-40c6-8e2b-07958aeab215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543413885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3543413885
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2971974091
Short name T750
Test name
Test status
Simulation time 252825251544 ps
CPU time 1251.48 seconds
Started Jul 09 04:33:04 PM PDT 24
Finished Jul 09 04:53:57 PM PDT 24
Peak memory 229128 kb
Host smart-69636e8d-031b-4a9e-9a64-1e36c16d296e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971974091 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2971974091
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2403622061
Short name T988
Test name
Test status
Simulation time 26295882799 ps
CPU time 16.41 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:33:20 PM PDT 24
Peak memory 199668 kb
Host smart-1caeb62b-f54d-44f8-a051-5ddd003b6cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403622061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2403622061
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1000607388
Short name T1121
Test name
Test status
Simulation time 105209097157 ps
CPU time 305.36 seconds
Started Jul 09 04:33:03 PM PDT 24
Finished Jul 09 04:38:10 PM PDT 24
Peak memory 216304 kb
Host smart-4aeca77d-80b7-4e6e-a214-7dff53d885ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000607388 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1000607388
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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