Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	120510	1			T1	2		T2	1038		T3	39
all_values[1]	120510	1			T1	2		T2	1038		T3	39
all_values[2]	120510	1			T1	2		T2	1038		T3	39
all_values[3]	120510	1			T1	2		T2	1038		T3	39
all_values[4]	120510	1			T1	2		T2	1038		T3	39
all_values[5]	120510	1			T1	2		T2	1038		T3	39
all_values[6]	120510	1			T1	2		T2	1038		T3	39
all_values[7]	120510	1			T1	2		T2	1038		T3	39
all_values[8]	120510	1			T1	2		T2	1038		T3	39

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

553928

1

T1

18

T2

5360

T3

170

auto[1]

530662

1

T2

3982

T3

181

T4

892

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986547

1

T1

13

T2

8690

T3

287

auto[1]

98043

1

T1

5

T2

652

T3

64

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38179	1			T2	36		T5	22		T6	16
all_values[0]	auto[0]	auto[1]	25003	1			T1	2		T2	8		T3	7
all_values[0]	auto[1]	auto[0]	32661	1			T2	652		T3	3		T4	164
all_values[0]	auto[1]	auto[1]	24667	1			T2	342		T3	29		T4	19
all_values[1]	auto[0]	auto[0]	60210	1			T1	2		T2	481		T4	9
all_values[1]	auto[0]	auto[1]	1673	1			T8	40		T10	1		T14	2
all_values[1]	auto[1]	auto[0]	56785	1			T2	557		T3	37		T4	175
all_values[1]	auto[1]	auto[1]	1842	1			T3	2		T32	11		T48	3
all_values[2]	auto[0]	auto[0]	61493	1			T1	1		T2	771		T3	39
all_values[2]	auto[0]	auto[1]	2819	1			T1	1		T2	8		T4	1
all_values[2]	auto[1]	auto[0]	53668	1			T2	249		T4	175		T5	15
all_values[2]	auto[1]	auto[1]	2530	1			T2	10		T4	8		T5	2
all_values[3]	auto[0]	auto[0]	59723	1			T1	2		T2	778		T3	6
all_values[3]	auto[0]	auto[1]	318	1			T3	1		T12	3		T15	2
all_values[3]	auto[1]	auto[0]	60134	1			T2	260		T3	32		T5	17
all_values[3]	auto[1]	auto[1]	335	1			T12	2		T13	1		T15	1
all_values[4]	auto[0]	auto[0]	59773	1			T1	2		T2	806		T4	18
all_values[4]	auto[0]	auto[1]	562	1			T16	14		T17	2		T20	5
all_values[4]	auto[1]	auto[0]	59717	1			T2	232		T3	38		T4	166
all_values[4]	auto[1]	auto[1]	458	1			T3	1		T14	1		T15	3
all_values[5]	auto[0]	auto[0]	61171	1			T1	2		T2	857		T3	39
all_values[5]	auto[0]	auto[1]	189	1			T16	2		T17	1		T34	11
all_values[5]	auto[1]	auto[0]	58980	1			T2	181		T4	175		T5	17
all_values[5]	auto[1]	auto[1]	170	1			T16	2		T17	1		T34	4
all_values[6]	auto[0]	auto[0]	59596	1			T1	2		T2	384		T3	32
all_values[6]	auto[0]	auto[1]	184	1			T16	1		T17	2		T34	4
all_values[6]	auto[1]	auto[0]	60564	1			T2	654		T3	7		T5	18
all_values[6]	auto[1]	auto[1]	166	1			T34	4		T35	2		T124	1
all_values[7]	auto[0]	auto[0]	63133	1			T1	2		T2	542		T3	39
all_values[7]	auto[0]	auto[1]	403	1			T14	2		T15	1		T25	1
all_values[7]	auto[1]	auto[0]	56585	1			T2	496		T4	1		T5	1
all_values[7]	auto[1]	auto[1]	389	1			T18	3		T14	1		T16	2
all_values[8]	auto[0]	auto[0]	40771	1			T2	441		T4	174		T5	2
all_values[8]	auto[0]	auto[1]	18728	1			T1	2		T2	248		T3	7
all_values[8]	auto[1]	auto[0]	43404	1			T2	313		T3	15		T4	9
all_values[8]	auto[1]	auto[1]	17607	1			T2	36		T3	17		T5	2