Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2614

1

T1

1

T2

6

T3

1

auto[UartRx]

2614

1

T1

1

T2

6

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4643	1			T1	2		T2	10		T3	2
values[1]	55	1			T18	1		T34	2		T35	3
values[2]	56	1			T35	1		T36	1		T38	1
values[3]	56	1			T2	1		T15	1		T17	1
values[4]	44	1			T18	2		T15	2		T17	1
values[5]	53	1			T17	1		T37	1		T39	1
values[6]	58	1			T2	1		T18	1		T15	1
values[7]	62	1			T18	1		T17	1		T35	1
values[8]	59	1			T15	1		T17	1		T34	1
values[9]	60	1			T18	1		T17	1		T34	1
values[10]	51	1			T18	3		T15	1		T34	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2409	1			T1	1		T2	5		T3	1
auto[UartTx]	values[1]	19	1			T18	1		T35	1		T36	1
auto[UartTx]	values[2]	20	1			T35	1		T131	1		T341	1
auto[UartTx]	values[3]	22	1			T2	1		T15	1		T34	1
auto[UartTx]	values[4]	12	1			T37	1		T51	1		T342	1
auto[UartTx]	values[5]	16	1			T17	1		T341	1		T343	2
auto[UartTx]	values[6]	17	1			T36	1		T37	1		T39	1
auto[UartTx]	values[7]	22	1			T18	1		T131	2		T341	1
auto[UartTx]	values[8]	23	1			T17	1		T35	1		T36	2
auto[UartTx]	values[9]	22	1			T109	1		T110	1		T111	1
auto[UartTx]	values[10]	21	1			T18	1		T15	1		T34	1
auto[UartRx]	values[0]	2234	1			T1	1		T2	5		T3	1
auto[UartRx]	values[1]	36	1			T34	2		T35	2		T38	2
auto[UartRx]	values[2]	36	1			T36	1		T38	1		T131	1
auto[UartRx]	values[3]	34	1			T17	1		T34	1		T36	1
auto[UartRx]	values[4]	32	1			T18	2		T15	2		T17	1
auto[UartRx]	values[5]	37	1			T37	1		T39	1		T341	1
auto[UartRx]	values[6]	41	1			T2	1		T18	1		T15	1
auto[UartRx]	values[7]	40	1			T17	1		T35	1		T36	1
auto[UartRx]	values[8]	36	1			T15	1		T34	1		T38	1
auto[UartRx]	values[9]	38	1			T18	1		T17	1		T34	1
auto[UartRx]	values[10]	30	1			T18	2		T35	1		T38	1