Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2384	1			T1	1		T2	1		T4	2
auto[BaudRate115200]	2046	1			T2	8		T3	1		T4	1
auto[BaudRate230400]	2099	1			T1	1		T2	6		T4	2
auto[BaudRate128Kbps]	2032	1			T2	3		T3	1		T7	3
auto[BaudRate256Kbps]	2140	1			T2	4		T5	8		T7	1
auto[BaudRate1Mbps]	1857	1			T2	1		T6	2		T7	1
auto[BaudRate1p5Mbps]	1300	1			T4	2		T6	1		T7	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1461	1			T11	2		T306	4		T269	6
freqs[25]	1687	1			T41	8		T132	6		T314	2
freqs[48]	646	1			T33	2		T49	7		T16	34
freqs[50]	822	1			T3	2		T42	10		T265	18
freqs[100]	1256	1			T48	8		T14	33		T44	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	211	1			T11	1		T269	1		T126	3
auto[BaudRate9600]	freqs[25]	338	1			T132	1		T316	1		T294	4
auto[BaudRate9600]	freqs[48]	121	1			T16	4		T141	2		T344	17
auto[BaudRate9600]	freqs[50]	133	1			T42	4		T265	4		T345	17
auto[BaudRate9600]	freqs[100]	207	1			T48	2		T14	4		T44	2
auto[BaudRate115200]	freqs[24]	209	1			T306	1		T269	1		T20	1
auto[BaudRate115200]	freqs[25]	236	1			T132	2		T172	1		T294	1
auto[BaudRate115200]	freqs[48]	101	1			T49	2		T16	4		T141	4
auto[BaudRate115200]	freqs[50]	117	1			T3	1		T42	1		T265	4
auto[BaudRate115200]	freqs[100]	191	1			T14	4		T133	1		T134	1
auto[BaudRate230400]	freqs[24]	217	1			T306	1		T269	1		T299	1
auto[BaudRate230400]	freqs[25]	260	1			T132	1		T314	1		T172	1
auto[BaudRate230400]	freqs[48]	101	1			T33	1		T49	1		T16	6
auto[BaudRate230400]	freqs[50]	109	1			T265	3		T36	2		T346	21
auto[BaudRate230400]	freqs[100]	166	1			T48	3		T14	6		T44	1
auto[BaudRate128Kbps]	freqs[24]	240	1			T11	1		T269	1		T20	2
auto[BaudRate128Kbps]	freqs[25]	247	1			T314	1		T172	1		T294	1
auto[BaudRate128Kbps]	freqs[48]	74	1			T33	1		T16	9		T141	1
auto[BaudRate128Kbps]	freqs[50]	109	1			T3	1		T42	3		T265	2
auto[BaudRate128Kbps]	freqs[100]	185	1			T48	1		T14	7		T44	1
auto[BaudRate256Kbps]	freqs[24]	251	1			T306	2		T269	1		T129	3
auto[BaudRate256Kbps]	freqs[25]	261	1			T41	4		T132	2		T172	2
auto[BaudRate256Kbps]	freqs[48]	64	1			T49	3		T16	4		T141	1
auto[BaudRate256Kbps]	freqs[50]	119	1			T265	1		T36	3		T346	9
auto[BaudRate256Kbps]	freqs[100]	177	1			T48	1		T14	2		T44	1
auto[BaudRate1Mbps]	freqs[24]	227	1			T269	1		T129	1		T126	1
auto[BaudRate1Mbps]	freqs[25]	236	1			T41	4		T122	1		T294	4
auto[BaudRate1Mbps]	freqs[48]	96	1			T16	4		T266	8		T347	2
auto[BaudRate1Mbps]	freqs[50]	105	1			T42	1		T265	3		T36	6
auto[BaudRate1Mbps]	freqs[100]	145	1			T48	1		T14	6		T44	1
auto[BaudRate1p5Mbps]	freqs[25]	109	1			T122	1		T294	2		T38	5
auto[BaudRate1p5Mbps]	freqs[48]	89	1			T49	1		T16	3		T141	1
auto[BaudRate1p5Mbps]	freqs[50]	130	1			T42	1		T265	1		T36	1
auto[BaudRate1p5Mbps]	freqs[100]	185	1			T14	4		T44	1		T277	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded