Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.88	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	16	114	87.69

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	16	114	87.69	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	35060514	1			T2	265215		T3	2640		T4	390
all_levels[1]	176298	1			T2	135		T5	2224		T7	43
all_levels[2]	2444	1			T2	2		T7	1		T10	10
all_levels[3]	1159	1			T6	1		T8	1		T10	2
all_levels[4]	760	1			T6	2		T8	2		T32	2
all_levels[5]	591	1			T6	1		T8	2		T10	1
all_levels[6]	472	1			T18	3		T14	1		T44	1
all_levels[7]	357	1			T8	1		T32	2		T14	2
all_levels[8]	320	1			T8	3		T18	1		T132	1
all_levels[9]	245	1			T8	2		T18	1		T133	2
all_levels[10]	219	1			T18	1		T14	1		T128	1
all_levels[11]	215	1			T8	3		T18	2		T12	1
all_levels[12]	177	1			T4	1		T8	1		T49	2
all_levels[13]	165	1			T4	1		T6	1		T132	1
all_levels[14]	131	1			T13	1		T134	2		T135	1
all_levels[15]	108	1			T8	1		T14	1		T13	1
all_levels[16]	115	1			T8	1		T14	1		T12	2
all_levels[17]	112	1			T8	1		T132	1		T136	1
all_levels[18]	112	1			T6	1		T8	2		T48	1
all_levels[19]	74	1			T8	1		T18	1		T48	1
all_levels[20]	89	1			T18	1		T12	1		T13	1
all_levels[21]	63	1			T8	2		T18	1		T137	1
all_levels[22]	53	1			T14	1		T49	2		T138	1
all_levels[23]	59	1			T49	1		T25	1		T139	1
all_levels[24]	54	1			T140	1		T35	1		T125	1
all_levels[25]	54	1			T18	1		T49	1		T137	1
all_levels[26]	52	1			T49	1		T126	1		T141	1
all_levels[27]	44	1			T142	1		T143	1		T144	1
all_levels[28]	38	1			T49	2		T35	1		T125	1
all_levels[29]	41	1			T8	1		T139	1		T145	1
all_levels[30]	36	1			T132	2		T146	2		T147	1
all_levels[31]	24	1			T32	1		T18	1		T147	1
all_levels[32]	22	1			T117	1		T125	1		T148	1
all_levels[33]	14	1			T149	1		T150	1		T151	1
all_levels[34]	29	1			T152	1		T148	1		T153	1
all_levels[35]	23	1			T8	1		T117	1		T118	1
all_levels[36]	23	1			T118	1		T154	1		T155	1
all_levels[37]	20	1			T156	1		T157	1		T158	1
all_levels[38]	25	1			T15	1		T118	1		T123	1
all_levels[39]	21	1			T145	1		T159	2		T160	1
all_levels[40]	11	1			T35	1		T161	1		T153	1
all_levels[41]	19	1			T13	1		T142	1		T162	1
all_levels[42]	21	1			T4	1		T163	1		T160	1
all_levels[43]	11	1			T164	1		T113	1		T165	1
all_levels[44]	16	1			T118	1		T141	1		T166	1
all_levels[45]	13	1			T138	1		T123	1		T167	1
all_levels[46]	9	1			T168	2		T169	1		T170	2
all_levels[47]	16	1			T138	1		T171	1		T153	1
all_levels[48]	17	1			T15	1		T172	1		T156	1
all_levels[49]	21	1			T13	1		T118	2		T35	1
all_levels[50]	14	1			T173	1		T162	1		T174	1
all_levels[51]	17	1			T35	2		T154	3		T175	5
all_levels[52]	9	1			T176	1		T38	1		T51	1
all_levels[53]	11	1			T146	1		T176	1		T164	1
all_levels[54]	12	1			T163	1		T177	4		T178	1
all_levels[55]	11	1			T179	1		T38	1		T51	1
all_levels[56]	10	1			T123	1		T180	1		T181	1
all_levels[57]	6	1			T182	1		T155	1		T183	1
all_levels[58]	14	1			T184	2		T185	1		T186	1
all_levels[59]	7	1			T51	1		T187	1		T188	1
all_levels[60]	4	1			T148	1		T51	1		T189	1
all_levels[61]	11	1			T190	4		T51	2		T191	1
all_levels[62]	5	1			T112	2		T180	1		T192	1
all_levels[63]	9	1			T171	1		T181	1		T193	1
all_levels[64]	111	1			T12	1		T13	1		T137	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35240677

1

T2

265352

T3

2622

T4

393

auto[1]

5100

1

T3

18

T6

6

T8

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	16	114	87.69	16

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[31]]	[auto[1]]	0	1	1
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[55] , all_levels[56] , all_levels[57] , all_levels[58]]	[auto[1]]	--	--	4
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	35055904	1			T2	265215		T3	2622		T4	390
all_levels[0]	auto[1]	4610	1			T3	18		T6	6		T8	2
all_levels[1]	auto[0]	176207	1			T2	135		T5	2224		T7	43
all_levels[1]	auto[1]	91	1			T157	1		T179	3		T194	1
all_levels[2]	auto[0]	2421	1			T2	2		T7	1		T10	10
all_levels[2]	auto[1]	23	1			T71	1		T195	1		T196	2
all_levels[3]	auto[0]	1138	1			T6	1		T8	1		T10	2
all_levels[3]	auto[1]	21	1			T197	2		T198	2		T199	1
all_levels[4]	auto[0]	731	1			T6	2		T8	1		T32	2
all_levels[4]	auto[1]	29	1			T8	1		T132	1		T133	1
all_levels[5]	auto[0]	563	1			T6	1		T8	2		T10	1
all_levels[5]	auto[1]	28	1			T135	1		T200	1		T201	3
all_levels[6]	auto[0]	446	1			T18	3		T14	1		T44	1
all_levels[6]	auto[1]	26	1			T139	2		T202	2		T194	1
all_levels[7]	auto[0]	342	1			T8	1		T32	1		T14	2
all_levels[7]	auto[1]	15	1			T32	1		T44	3		T133	1
all_levels[8]	auto[0]	310	1			T8	2		T18	1		T132	1
all_levels[8]	auto[1]	10	1			T8	1		T159	1		T203	1
all_levels[9]	auto[0]	232	1			T8	2		T18	1		T133	2
all_levels[9]	auto[1]	13	1			T190	1		T204	3		T162	3
all_levels[10]	auto[0]	209	1			T18	1		T14	1		T128	1
all_levels[10]	auto[1]	10	1			T157	1		T205	2		T206	2
all_levels[11]	auto[0]	203	1			T8	2		T18	2		T12	1
all_levels[11]	auto[1]	12	1			T8	1		T195	1		T207	3
all_levels[12]	auto[0]	162	1			T4	1		T8	1		T49	2
all_levels[12]	auto[1]	15	1			T136	2		T208	2		T167	1
all_levels[13]	auto[0]	144	1			T4	1		T6	1		T132	1
all_levels[13]	auto[1]	21	1			T209	1		T35	3		T210	1
all_levels[14]	auto[0]	124	1			T13	1		T134	2		T135	1
all_levels[14]	auto[1]	7	1			T157	1		T196	1		T211	3
all_levels[15]	auto[0]	103	1			T8	1		T14	1		T13	1
all_levels[15]	auto[1]	5	1			T212	1		T213	1		T214	2
all_levels[16]	auto[0]	107	1			T8	1		T14	1		T12	1
all_levels[16]	auto[1]	8	1			T12	1		T215	2		T216	1
all_levels[17]	auto[0]	101	1			T8	1		T132	1		T136	1
all_levels[17]	auto[1]	11	1			T204	1		T111	1		T217	2
all_levels[18]	auto[0]	94	1			T6	1		T8	1		T48	1
all_levels[18]	auto[1]	18	1			T8	1		T12	3		T218	4
all_levels[19]	auto[0]	69	1			T8	1		T18	1		T48	1
all_levels[19]	auto[1]	5	1			T219	1		T204	2		T220	1
all_levels[20]	auto[0]	83	1			T18	1		T12	1		T13	1
all_levels[20]	auto[1]	6	1			T221	1		T222	1		T223	1
all_levels[21]	auto[0]	59	1			T8	2		T18	1		T137	1
all_levels[21]	auto[1]	4	1			T190	1		T203	2		T224	1
all_levels[22]	auto[0]	51	1			T14	1		T49	2		T138	1
all_levels[22]	auto[1]	2	1			T225	1		T226	1		-	-
all_levels[23]	auto[0]	57	1			T49	1		T25	1		T139	1
all_levels[23]	auto[1]	2	1			T227	1		T105	1		-	-
all_levels[24]	auto[0]	46	1			T140	1		T35	1		T125	1
all_levels[24]	auto[1]	8	1			T228	1		T187	1		T224	1
all_levels[25]	auto[0]	47	1			T18	1		T49	1		T137	1
all_levels[25]	auto[1]	7	1			T173	3		T206	2		T229	2
all_levels[26]	auto[0]	51	1			T49	1		T126	1		T141	1
all_levels[26]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[27]	auto[0]	38	1			T142	1		T143	1		T144	1
all_levels[27]	auto[1]	6	1			T160	2		T52	1		T188	1
all_levels[28]	auto[0]	33	1			T49	2		T35	1		T125	1
all_levels[28]	auto[1]	5	1			T191	2		T231	1		T232	2
all_levels[29]	auto[0]	37	1			T8	1		T139	1		T145	1
all_levels[29]	auto[1]	4	1			T233	1		T234	1		T235	1
all_levels[30]	auto[0]	28	1			T132	1		T146	2		T147	1
all_levels[30]	auto[1]	8	1			T132	1		T204	2		T75	1
all_levels[31]	auto[0]	24	1			T32	1		T18	1		T147	1
all_levels[32]	auto[0]	21	1			T117	1		T125	1		T148	1
all_levels[32]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[33]	auto[0]	14	1			T149	1		T150	1		T151	1
all_levels[34]	auto[0]	26	1			T152	1		T148	1		T153	1
all_levels[34]	auto[1]	3	1			T237	1		T238	2		-	-
all_levels[35]	auto[0]	23	1			T8	1		T117	1		T118	1
all_levels[36]	auto[0]	21	1			T118	1		T154	1		T155	1
all_levels[36]	auto[1]	2	1			T239	1		T240	1		-	-
all_levels[37]	auto[0]	17	1			T156	1		T157	1		T158	1
all_levels[37]	auto[1]	3	1			T241	1		T242	2		-	-
all_levels[38]	auto[0]	23	1			T15	1		T118	1		T123	1
all_levels[38]	auto[1]	2	1			T129	2		-	-		-	-
all_levels[39]	auto[0]	19	1			T145	1		T159	1		T160	1
all_levels[39]	auto[1]	2	1			T159	1		T243	1		-	-
all_levels[40]	auto[0]	11	1			T35	1		T161	1		T153	1
all_levels[41]	auto[0]	15	1			T13	1		T142	1		T162	1
all_levels[41]	auto[1]	4	1			T166	3		T244	1		-	-
all_levels[42]	auto[0]	17	1			T4	1		T163	1		T160	1
all_levels[42]	auto[1]	4	1			T245	1		T246	1		T247	1
all_levels[43]	auto[0]	11	1			T164	1		T113	1		T165	1
all_levels[44]	auto[0]	15	1			T118	1		T141	1		T166	1
all_levels[44]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[45]	auto[0]	13	1			T138	1		T123	1		T167	1
all_levels[46]	auto[0]	7	1			T168	1		T169	1		T170	1
all_levels[46]	auto[1]	2	1			T168	1		T170	1		-	-
all_levels[47]	auto[0]	16	1			T138	1		T171	1		T153	1
all_levels[48]	auto[0]	14	1			T15	1		T172	1		T156	1
all_levels[48]	auto[1]	3	1			T249	2		T250	1		-	-
all_levels[49]	auto[0]	17	1			T13	1		T118	2		T35	1
all_levels[49]	auto[1]	4	1			T251	3		T238	1		-	-
all_levels[50]	auto[0]	14	1			T173	1		T162	1		T174	1
all_levels[51]	auto[0]	10	1			T35	2		T154	1		T175	1
all_levels[51]	auto[1]	7	1			T154	2		T175	4		T252	1
all_levels[52]	auto[0]	8	1			T176	1		T38	1		T51	1
all_levels[52]	auto[1]	1	1			T253	1		-	-		-	-
all_levels[53]	auto[0]	11	1			T146	1		T176	1		T164	1
all_levels[54]	auto[0]	9	1			T163	1		T177	1		T178	1
all_levels[54]	auto[1]	3	1			T177	3		-	-		-	-
all_levels[55]	auto[0]	11	1			T179	1		T38	1		T51	1
all_levels[56]	auto[0]	10	1			T123	1		T180	1		T181	1
all_levels[57]	auto[0]	6	1			T182	1		T155	1		T183	1
all_levels[58]	auto[0]	14	1			T184	2		T185	1		T186	1
all_levels[59]	auto[0]	6	1			T51	1		T187	1		T188	1
all_levels[59]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[60]	auto[0]	4	1			T148	1		T51	1		T189	1
all_levels[61]	auto[0]	8	1			T190	1		T51	2		T191	1
all_levels[61]	auto[1]	3	1			T190	3		-	-		-	-
all_levels[62]	auto[0]	5	1			T112	2		T180	1		T192	1
all_levels[63]	auto[0]	9	1			T171	1		T181	1		T193	1
all_levels[64]	auto[0]	88	1			T12	1		T13	1		T137	1
all_levels[64]	auto[1]	23	1			T255	4		T171	1		T256	1