Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	120510	1			T1	2		T2	1038		T3	39
all_pins[1]	120510	1			T1	2		T2	1038		T3	39
all_pins[2]	120510	1			T1	2		T2	1038		T3	39
all_pins[3]	120510	1			T1	2		T2	1038		T3	39
all_pins[4]	120510	1			T1	2		T2	1038		T3	39
all_pins[5]	120510	1			T1	2		T2	1038		T3	39
all_pins[6]	120510	1			T1	2		T2	1038		T3	39
all_pins[7]	120510	1			T1	2		T2	1038		T3	39
all_pins[8]	120510	1			T1	2		T2	1038		T3	39

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1035404	1			T1	18		T2	8953		T3	298
values[0x1]	49186	1			T2	389		T3	53		T4	27
transitions[0x0=>0x1]	38203	1			T2	355		T3	33		T4	27
transitions[0x1=>0x0]	37990	1			T2	355		T3	34		T4	26

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95761	1			T1	2		T2	696		T3	9
all_pins[0]	values[0x1]	24749	1			T2	342		T3	30		T4	19
all_pins[0]	transitions[0x0=>0x1]	24078	1			T2	342		T3	30		T4	19
all_pins[0]	transitions[0x1=>0x0]	1164	1			T3	2		T48	3		T134	6
all_pins[1]	values[0x0]	118675	1			T1	2		T2	1038		T3	37
all_pins[1]	values[0x1]	1835	1			T3	2		T32	11		T48	3
all_pins[1]	transitions[0x0=>0x1]	1698	1			T3	2		T32	11		T48	1
all_pins[1]	transitions[0x1=>0x0]	2458	1			T2	10		T4	8		T5	2
all_pins[2]	values[0x0]	117915	1			T1	2		T2	1028		T3	39
all_pins[2]	values[0x1]	2595	1			T2	10		T4	8		T5	2
all_pins[2]	transitions[0x0=>0x1]	2510	1			T2	10		T4	8		T5	2
all_pins[2]	transitions[0x1=>0x0]	250	1			T12	1		T13	1		T15	1
all_pins[3]	values[0x0]	120175	1			T1	2		T2	1038		T3	39
all_pins[3]	values[0x1]	335	1			T12	2		T13	1		T15	1
all_pins[3]	transitions[0x0=>0x1]	276	1			T12	2		T13	1		T16	1
all_pins[3]	transitions[0x1=>0x0]	399	1			T3	1		T14	1		T15	2
all_pins[4]	values[0x0]	120052	1			T1	2		T2	1038		T3	38
all_pins[4]	values[0x1]	458	1			T3	1		T14	1		T15	3
all_pins[4]	transitions[0x0=>0x1]	389	1			T3	1		T14	1		T15	3
all_pins[4]	transitions[0x1=>0x0]	157	1			T16	3		T17	1		T21	1
all_pins[5]	values[0x0]	120284	1			T1	2		T2	1038		T3	39
all_pins[5]	values[0x1]	226	1			T16	5		T17	1		T20	1
all_pins[5]	transitions[0x0=>0x1]	188	1			T16	5		T17	1		T20	1
all_pins[5]	transitions[0x1=>0x0]	845	1			T2	1		T6	1		T18	2
all_pins[6]	values[0x0]	119627	1			T1	2		T2	1037		T3	39
all_pins[6]	values[0x1]	883	1			T2	1		T6	1		T18	2
all_pins[6]	transitions[0x0=>0x1]	829	1			T2	1		T6	1		T48	4
all_pins[6]	transitions[0x1=>0x0]	335	1			T18	1		T14	1		T16	2
all_pins[7]	values[0x0]	120121	1			T1	2		T2	1038		T3	39
all_pins[7]	values[0x1]	389	1			T18	3		T14	1		T16	2
all_pins[7]	transitions[0x0=>0x1]	232	1			T18	3		T14	1		T16	2
all_pins[7]	transitions[0x1=>0x0]	17559	1			T2	36		T3	20		T5	2
all_pins[8]	values[0x0]	102794	1			T1	2		T2	1002		T3	19
all_pins[8]	values[0x1]	17716	1			T2	36		T3	20		T5	2
all_pins[8]	transitions[0x0=>0x1]	8003	1			T2	2		T5	2		T6	3
all_pins[8]	transitions[0x1=>0x0]	14823	1			T2	308		T3	11		T4	18