Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8533705	1			T2	114357		T3	11		T4	33
all_levels[1]	2918507	1			T2	3305		T3	2004		T4	25
all_levels[2]	362763	1			T2	2849		T4	2		T5	45
all_levels[3]	282149	1			T2	3322		T4	12		T5	58
all_levels[4]	294123	1			T2	2880		T5	54		T7	1
all_levels[5]	232823	1			T2	2788		T5	56		T7	3
all_levels[6]	469986	1			T2	2873		T4	2		T5	54
all_levels[7]	267026	1			T2	2120		T4	2		T5	49
all_levels[8]	482674	1			T2	2065		T5	57		T10	4
all_levels[9]	276445	1			T2	1835		T5	54		T8	2
all_levels[10]	246787	1			T2	2113		T4	2		T5	52
all_levels[11]	611209	1			T2	2110		T5	53		T7	1
all_levels[12]	817107	1			T2	5793		T4	1		T5	56
all_levels[13]	254661	1			T2	1770		T5	59		T7	1
all_levels[14]	486936	1			T2	1547		T5	74		T10	4
all_levels[15]	430362	1			T2	1951		T3	11		T5	51
all_levels[16]	376513	1			T2	1996		T3	614		T5	54
all_levels[17]	216348	1			T2	5869		T5	57		T10	2
all_levels[18]	197749	1			T2	1287		T5	54		T7	3
all_levels[19]	321789	1			T2	1496		T5	58		T7	4
all_levels[20]	463155	1			T2	2408		T5	59		T41	57
all_levels[21]	462870	1			T2	1962		T5	66		T7	5
all_levels[22]	187593	1			T2	2076		T5	48		T7	2
all_levels[23]	209654	1			T2	1584		T5	54		T7	2
all_levels[24]	183117	1			T2	2126		T5	49		T10	2
all_levels[25]	183872	1			T2	2387		T5	58		T10	1
all_levels[26]	208146	1			T2	2354		T5	55		T10	7
all_levels[27]	284467	1			T2	2213		T5	53		T10	8
all_levels[28]	167563	1			T2	2251		T4	2		T5	67
all_levels[29]	197571	1			T2	3390		T5	62		T41	68
all_levels[30]	234992	1			T2	2279		T5	54		T41	60
all_levels[31]	745599	1			T2	3492		T5	2447		T7	58
all_levels[32]	13637093	1			T2	72505		T4	313		T5	34763

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35240677

1

T2

265352

T3

2622

T4

393

auto[1]

4677

1

T2

1

T3

18

T4

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8530936	1			T2	114357		T3	3		T4	33
all_levels[0]	auto[1]	2769	1			T3	8		T6	3		T8	1
all_levels[1]	auto[0]	2918229	1			T2	3305		T3	2004		T4	25
all_levels[1]	auto[1]	278	1			T6	1		T8	1		T132	1
all_levels[2]	auto[0]	362733	1			T2	2849		T4	2		T5	45
all_levels[2]	auto[1]	30	1			T13	1		T301	2		T199	1
all_levels[3]	auto[0]	281949	1			T2	3322		T4	12		T5	58
all_levels[3]	auto[1]	200	1			T8	1		T32	1		T14	10
all_levels[4]	auto[0]	294090	1			T2	2880		T5	54		T7	1
all_levels[4]	auto[1]	33	1			T274	1		T323	1		T312	3
all_levels[5]	auto[0]	232790	1			T2	2788		T5	56		T7	3
all_levels[5]	auto[1]	33	1			T197	2		T209	1		T319	1
all_levels[6]	auto[0]	469957	1			T2	2873		T4	2		T5	54
all_levels[6]	auto[1]	29	1			T12	2		T139	1		T119	1
all_levels[7]	auto[0]	266872	1			T2	2120		T4	2		T5	49
all_levels[7]	auto[1]	154	1			T14	1		T21	12		T286	1
all_levels[8]	auto[0]	482655	1			T2	2065		T5	57		T10	4
all_levels[8]	auto[1]	19	1			T32	1		T18	1		T75	1
all_levels[9]	auto[0]	276413	1			T2	1835		T5	54		T8	2
all_levels[9]	auto[1]	32	1			T42	1		T128	1		T16	1
all_levels[10]	auto[0]	246747	1			T2	2113		T4	2		T5	52
all_levels[10]	auto[1]	40	1			T199	2		T326	1		T168	3
all_levels[11]	auto[0]	611167	1			T2	2110		T5	53		T7	1
all_levels[11]	auto[1]	42	1			T133	3		T118	1		T285	4
all_levels[12]	auto[0]	817089	1			T2	5793		T4	1		T5	56
all_levels[12]	auto[1]	18	1			T44	2		T306	1		T133	1
all_levels[13]	auto[0]	254648	1			T2	1770		T5	59		T7	1
all_levels[13]	auto[1]	13	1			T200	1		T351	1		T352	1
all_levels[14]	auto[0]	486909	1			T2	1547		T5	74		T10	4
all_levels[14]	auto[1]	27	1			T48	1		T325	1		T353	1
all_levels[15]	auto[0]	430288	1			T2	1951		T3	1		T5	51
all_levels[15]	auto[1]	74	1			T3	10		T16	8		T21	6
all_levels[16]	auto[0]	376482	1			T2	1996		T3	614		T5	54
all_levels[16]	auto[1]	31	1			T48	1		T139	1		T210	1
all_levels[17]	auto[0]	216329	1			T2	5869		T5	57		T10	2
all_levels[17]	auto[1]	19	1			T197	1		T298	2		T72	2
all_levels[18]	auto[0]	197732	1			T2	1287		T5	54		T7	3
all_levels[18]	auto[1]	17	1			T136	2		T172	2		T204	2
all_levels[19]	auto[0]	321768	1			T2	1496		T5	58		T7	4
all_levels[19]	auto[1]	21	1			T269	1		T341	1		T334	1
all_levels[20]	auto[0]	463133	1			T2	2408		T5	59		T41	57
all_levels[20]	auto[1]	22	1			T278	1		T263	1		T157	3
all_levels[21]	auto[0]	462845	1			T2	1962		T5	66		T7	5
all_levels[21]	auto[1]	25	1			T8	1		T32	2		T136	1
all_levels[22]	auto[0]	187572	1			T2	2076		T5	48		T7	2
all_levels[22]	auto[1]	21	1			T135	2		T145	1		T209	2
all_levels[23]	auto[0]	209634	1			T2	1584		T5	54		T7	2
all_levels[23]	auto[1]	20	1			T205	1		T177	1		T289	1
all_levels[24]	auto[0]	183088	1			T2	2126		T5	49		T10	2
all_levels[24]	auto[1]	29	1			T129	2		T200	1		T39	2
all_levels[25]	auto[0]	183847	1			T2	2387		T5	58		T10	1
all_levels[25]	auto[1]	25	1			T157	1		T202	3		T176	1
all_levels[26]	auto[0]	208124	1			T2	2354		T5	55		T10	7
all_levels[26]	auto[1]	22	1			T135	3		T325	1		T205	1
all_levels[27]	auto[0]	284445	1			T2	2213		T5	53		T10	8
all_levels[27]	auto[1]	22	1			T172	3		T308	1		T146	1
all_levels[28]	auto[0]	167545	1			T2	2251		T4	2		T5	67
all_levels[28]	auto[1]	18	1			T13	1		T139	3		T335	2
all_levels[29]	auto[0]	197563	1			T2	3390		T5	62		T41	68
all_levels[29]	auto[1]	8	1			T48	1		T354	1		T355	4
all_levels[30]	auto[0]	234977	1			T2	2279		T5	54		T41	60
all_levels[30]	auto[1]	15	1			T44	1		T190	1		T283	1
all_levels[31]	auto[0]	745568	1			T2	3492		T5	2447		T7	58
all_levels[31]	auto[1]	31	1			T198	3		T204	3		T356	1
all_levels[32]	auto[0]	13636553	1			T2	72504		T4	312		T5	34763
all_levels[32]	auto[1]	540	1			T2	1		T4	1		T6	2