Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	793	1			T15	4		T16	7		T17	7
all_values[1]	793	1			T15	4		T16	7		T17	7
all_values[2]	793	1			T15	4		T16	7		T17	7
all_values[3]	793	1			T15	4		T16	7		T17	7
all_values[4]	793	1			T15	4		T16	7		T17	7
all_values[5]	793	1			T15	4		T16	7		T17	7
all_values[6]	793	1			T15	4		T16	7		T17	7
all_values[7]	793	1			T15	4		T16	7		T17	7
all_values[8]	793	1			T15	4		T16	7		T17	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3868

1

T15

19

T16

36

T17

29

auto[1]

3269

1

T15

17

T16

27

T17

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2384

1

T15

14

T16

26

T17

15

auto[1]

4753

1

T15

22

T16

37

T17

48

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4268

1

T15

22

T16

36

T17

33

auto[1]

2869

1

T15

14

T16

27

T17

30

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	247	1			T16	1		T17	1		T34	8
all_values[0]	auto[0]	auto[1]	auto[1]	227	1			T15	2		T17	4		T34	4
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T15	1		T16	4		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	141	1			T15	1		T16	2		T34	4
all_values[1]	auto[0]	auto[0]	auto[0]	247	1			T15	1		T16	2		T17	1
all_values[1]	auto[0]	auto[1]	auto[0]	221	1			T15	1		T16	2		T17	3
all_values[1]	auto[1]	auto[0]	auto[1]	179	1			T15	2		T16	3		T17	2
all_values[1]	auto[1]	auto[1]	auto[1]	146	1			T17	1		T34	7		T35	2
all_values[2]	auto[0]	auto[0]	auto[0]	189	1			T15	2		T17	1		T34	9
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T17	1		T34	2		T35	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T15	1		T16	2		T17	2
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T16	2		T34	1		T35	1
all_values[2]	auto[1]	auto[0]	auto[1]	167	1			T16	1		T17	1		T34	2
all_values[2]	auto[1]	auto[1]	auto[1]	147	1			T15	1		T16	2		T17	2
all_values[3]	auto[0]	auto[0]	auto[0]	173	1			T15	1		T16	2		T17	1
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T15	1		T16	3		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	130	1			T16	1		T17	1		T34	6
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T34	2		T124	1		T38	1
all_values[3]	auto[1]	auto[0]	auto[1]	167	1			T15	1		T17	2		T34	3
all_values[3]	auto[1]	auto[1]	auto[1]	153	1			T15	1		T16	1		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	177	1			T16	1		T34	11		T35	2
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T17	1		T124	2		T125	2
all_values[4]	auto[0]	auto[1]	auto[0]	145	1			T16	2		T34	2		T124	2
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T15	1		T16	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	164	1			T15	1		T16	3		T17	1
all_values[4]	auto[1]	auto[1]	auto[1]	155	1			T15	2		T17	4		T34	5
all_values[5]	auto[0]	auto[0]	auto[0]	161	1			T15	2		T16	2		T17	2
all_values[5]	auto[0]	auto[0]	auto[1]	87	1			T17	2		T34	8		T131	2
all_values[5]	auto[0]	auto[1]	auto[0]	161	1			T15	1		T16	1		T17	1
all_values[5]	auto[0]	auto[1]	auto[1]	72	1			T16	1		T35	1		T124	1
all_values[5]	auto[1]	auto[0]	auto[1]	176	1			T15	1		T16	3		T17	1
all_values[5]	auto[1]	auto[1]	auto[1]	136	1			T17	1		T34	5		T35	1
all_values[6]	auto[0]	auto[0]	auto[0]	175	1			T15	1		T16	5		T17	1
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T34	1		T35	1		T124	2
all_values[6]	auto[0]	auto[1]	auto[0]	150	1			T15	2		T16	1		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T17	1		T34	1		T35	1
all_values[6]	auto[1]	auto[0]	auto[1]	187	1			T16	1		T17	3		T34	7
all_values[6]	auto[1]	auto[1]	auto[1]	129	1			T15	1		T17	1		T34	3
all_values[7]	auto[0]	auto[0]	auto[0]	175	1			T15	1		T34	7		T124	2
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T17	2		T34	2		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T15	1		T16	5		T17	1
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T34	1		T35	1		T124	1
all_values[7]	auto[1]	auto[0]	auto[1]	181	1			T15	2		T17	2		T34	1
all_values[7]	auto[1]	auto[1]	auto[1]	148	1			T16	2		T17	2		T34	6
all_values[8]	auto[0]	auto[0]	auto[1]	258	1			T15	2		T16	1		T34	9
all_values[8]	auto[0]	auto[1]	auto[1]	220	1			T15	2		T16	1		T17	4
all_values[8]	auto[1]	auto[0]	auto[1]	178	1			T16	4		T17	1		T34	6
all_values[8]	auto[1]	auto[1]	auto[1]	137	1			T16	1		T17	2		T34	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal