Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.10 97.65 100.00 98.38 100.00 99.41


Total test records in report: 1316
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T1258 /workspace/coverage/cover_reg_top/6.uart_intr_test.2524727479 Jul 10 04:44:50 PM PDT 24 Jul 10 04:44:51 PM PDT 24 14245399 ps
T1259 /workspace/coverage/cover_reg_top/11.uart_intr_test.825813898 Jul 10 04:44:48 PM PDT 24 Jul 10 04:44:50 PM PDT 24 44100913 ps
T1260 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3790665186 Jul 10 04:45:08 PM PDT 24 Jul 10 04:45:10 PM PDT 24 102269527 ps
T1261 /workspace/coverage/cover_reg_top/42.uart_intr_test.3180723759 Jul 10 04:45:00 PM PDT 24 Jul 10 04:45:01 PM PDT 24 15973341 ps
T1262 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2573217749 Jul 10 04:44:21 PM PDT 24 Jul 10 04:44:23 PM PDT 24 38363420 ps
T1263 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.933470693 Jul 10 04:44:24 PM PDT 24 Jul 10 04:44:26 PM PDT 24 70254621 ps
T1264 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2066896967 Jul 10 04:44:47 PM PDT 24 Jul 10 04:44:49 PM PDT 24 86472488 ps
T1265 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3990308327 Jul 10 04:44:38 PM PDT 24 Jul 10 04:44:40 PM PDT 24 24286173 ps
T1266 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1399804071 Jul 10 04:44:37 PM PDT 24 Jul 10 04:44:39 PM PDT 24 20909023 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_tl_errors.996543796 Jul 10 04:44:58 PM PDT 24 Jul 10 04:45:00 PM PDT 24 56678856 ps
T1268 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2905462627 Jul 10 04:45:01 PM PDT 24 Jul 10 04:45:02 PM PDT 24 19226328 ps
T1269 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1328925477 Jul 10 04:44:24 PM PDT 24 Jul 10 04:44:26 PM PDT 24 35626139 ps
T1270 /workspace/coverage/cover_reg_top/1.uart_tl_errors.411807998 Jul 10 04:44:23 PM PDT 24 Jul 10 04:44:26 PM PDT 24 223912721 ps
T1271 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2786760422 Jul 10 04:44:52 PM PDT 24 Jul 10 04:44:54 PM PDT 24 23344930 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_tl_errors.49160315 Jul 10 04:44:44 PM PDT 24 Jul 10 04:44:46 PM PDT 24 37028689 ps
T1273 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4043649555 Jul 10 04:44:58 PM PDT 24 Jul 10 04:45:00 PM PDT 24 1156385454 ps
T1274 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2651019531 Jul 10 04:44:50 PM PDT 24 Jul 10 04:44:52 PM PDT 24 32246934 ps
T1275 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.358299994 Jul 10 04:51:03 PM PDT 24 Jul 10 04:51:05 PM PDT 24 113746015 ps
T1276 /workspace/coverage/cover_reg_top/46.uart_intr_test.2512456466 Jul 10 04:44:50 PM PDT 24 Jul 10 04:44:52 PM PDT 24 12121896 ps
T93 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4260229601 Jul 10 04:44:53 PM PDT 24 Jul 10 04:45:00 PM PDT 24 281857018 ps
T1277 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3089899694 Jul 10 04:44:51 PM PDT 24 Jul 10 04:44:53 PM PDT 24 85955939 ps
T1278 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4233349972 Jul 10 04:44:55 PM PDT 24 Jul 10 04:44:57 PM PDT 24 24811092 ps
T1279 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3858519077 Jul 10 04:44:40 PM PDT 24 Jul 10 04:44:42 PM PDT 24 94198257 ps
T1280 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1153985646 Jul 10 04:45:11 PM PDT 24 Jul 10 04:45:15 PM PDT 24 47961634 ps
T1281 /workspace/coverage/cover_reg_top/1.uart_intr_test.126867003 Jul 10 04:44:15 PM PDT 24 Jul 10 04:44:16 PM PDT 24 30315238 ps
T1282 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.500443193 Jul 10 04:44:27 PM PDT 24 Jul 10 04:44:28 PM PDT 24 126449211 ps
T1283 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3741182083 Jul 10 04:44:44 PM PDT 24 Jul 10 04:44:46 PM PDT 24 58446091 ps
T1284 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2963008064 Jul 10 04:44:54 PM PDT 24 Jul 10 04:44:56 PM PDT 24 17930023 ps
T1285 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3928239583 Jul 10 04:45:02 PM PDT 24 Jul 10 04:45:06 PM PDT 24 131773315 ps
T1286 /workspace/coverage/cover_reg_top/19.uart_intr_test.2324958447 Jul 10 04:45:09 PM PDT 24 Jul 10 04:45:11 PM PDT 24 51532471 ps
T1287 /workspace/coverage/cover_reg_top/5.uart_intr_test.3162967396 Jul 10 04:44:47 PM PDT 24 Jul 10 04:44:48 PM PDT 24 128570265 ps
T1288 /workspace/coverage/cover_reg_top/2.uart_intr_test.3530279042 Jul 10 04:44:30 PM PDT 24 Jul 10 04:44:31 PM PDT 24 11721439 ps
T66 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.617763233 Jul 10 04:44:48 PM PDT 24 Jul 10 04:44:50 PM PDT 24 17966575 ps
T1289 /workspace/coverage/cover_reg_top/31.uart_intr_test.1037385873 Jul 10 04:45:12 PM PDT 24 Jul 10 04:45:15 PM PDT 24 16470651 ps
T1290 /workspace/coverage/cover_reg_top/40.uart_intr_test.1914637429 Jul 10 04:45:11 PM PDT 24 Jul 10 04:45:14 PM PDT 24 13175810 ps
T1291 /workspace/coverage/cover_reg_top/7.uart_csr_rw.4017797063 Jul 10 04:45:05 PM PDT 24 Jul 10 04:45:06 PM PDT 24 43257324 ps
T1292 /workspace/coverage/cover_reg_top/13.uart_intr_test.2790049590 Jul 10 04:45:07 PM PDT 24 Jul 10 04:45:08 PM PDT 24 39362538 ps
T1293 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2595607911 Jul 10 04:44:42 PM PDT 24 Jul 10 04:44:44 PM PDT 24 46988933 ps
T96 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3754895831 Jul 10 04:45:02 PM PDT 24 Jul 10 04:45:05 PM PDT 24 664082669 ps
T1294 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3096362102 Jul 10 04:45:09 PM PDT 24 Jul 10 04:45:12 PM PDT 24 277399762 ps
T1295 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2182378244 Jul 10 04:44:46 PM PDT 24 Jul 10 04:44:47 PM PDT 24 25130464 ps
T1296 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2020700162 Jul 10 04:45:10 PM PDT 24 Jul 10 04:45:14 PM PDT 24 14992096 ps
T1297 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3345486742 Jul 10 04:44:10 PM PDT 24 Jul 10 04:44:13 PM PDT 24 63204596 ps
T1298 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1230641899 Jul 10 04:44:56 PM PDT 24 Jul 10 04:44:58 PM PDT 24 255316818 ps
T1299 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1352963408 Jul 10 04:45:04 PM PDT 24 Jul 10 04:45:05 PM PDT 24 49429175 ps
T1300 /workspace/coverage/cover_reg_top/12.uart_intr_test.3270944045 Jul 10 04:45:04 PM PDT 24 Jul 10 04:45:06 PM PDT 24 19720137 ps
T1301 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3509626905 Jul 10 04:44:55 PM PDT 24 Jul 10 04:44:58 PM PDT 24 404507422 ps
T1302 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3604367183 Jul 10 04:45:08 PM PDT 24 Jul 10 04:45:11 PM PDT 24 157008181 ps
T1303 /workspace/coverage/cover_reg_top/17.uart_intr_test.743773358 Jul 10 04:45:01 PM PDT 24 Jul 10 04:45:03 PM PDT 24 41580582 ps
T1304 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3360996462 Jul 10 04:44:55 PM PDT 24 Jul 10 04:45:02 PM PDT 24 98247491 ps
T1305 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3547512280 Jul 10 04:44:20 PM PDT 24 Jul 10 04:44:22 PM PDT 24 78612529 ps
T1306 /workspace/coverage/cover_reg_top/4.uart_tl_errors.409383704 Jul 10 04:44:32 PM PDT 24 Jul 10 04:44:39 PM PDT 24 474257491 ps
T1307 /workspace/coverage/cover_reg_top/37.uart_intr_test.4133366616 Jul 10 04:45:13 PM PDT 24 Jul 10 04:45:17 PM PDT 24 18055651 ps
T1308 /workspace/coverage/cover_reg_top/48.uart_intr_test.878768154 Jul 10 04:45:08 PM PDT 24 Jul 10 04:45:10 PM PDT 24 52128045 ps
T1309 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3677784729 Jul 10 04:44:22 PM PDT 24 Jul 10 04:44:24 PM PDT 24 18394531 ps
T67 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3923196802 Jul 10 04:44:54 PM PDT 24 Jul 10 04:44:56 PM PDT 24 44177883 ps
T97 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2192689573 Jul 10 04:44:46 PM PDT 24 Jul 10 04:44:48 PM PDT 24 1179969834 ps
T1310 /workspace/coverage/cover_reg_top/3.uart_tl_errors.429625181 Jul 10 04:44:27 PM PDT 24 Jul 10 04:44:29 PM PDT 24 74081726 ps
T1311 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2408309775 Jul 10 04:44:47 PM PDT 24 Jul 10 04:44:49 PM PDT 24 168006874 ps
T1312 /workspace/coverage/cover_reg_top/14.uart_intr_test.1550905347 Jul 10 04:45:09 PM PDT 24 Jul 10 04:45:11 PM PDT 24 88696479 ps
T1313 /workspace/coverage/cover_reg_top/2.uart_csr_rw.204700766 Jul 10 04:44:21 PM PDT 24 Jul 10 04:44:23 PM PDT 24 42629392 ps
T1314 /workspace/coverage/cover_reg_top/26.uart_intr_test.2604751803 Jul 10 04:45:18 PM PDT 24 Jul 10 04:45:21 PM PDT 24 41286507 ps
T1315 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.312599081 Jul 10 04:44:48 PM PDT 24 Jul 10 04:44:50 PM PDT 24 50557334 ps
T68 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2550604634 Jul 10 04:44:43 PM PDT 24 Jul 10 04:44:45 PM PDT 24 19357530 ps
T69 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1871550247 Jul 10 04:44:22 PM PDT 24 Jul 10 04:44:26 PM PDT 24 57058328 ps
T1316 /workspace/coverage/cover_reg_top/32.uart_intr_test.1995859507 Jul 10 04:45:11 PM PDT 24 Jul 10 04:45:15 PM PDT 24 13862651 ps

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2951832437
Short name T2
Test name
Test status
Simulation time 78887135086 ps
CPU time 663.3 seconds
Started Jul 10 04:58:34 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 216464 kb
Host smart-92199392-cb37-4ac3-94ea-42437d795178
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951832437 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2951832437
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1459303024
Short name T38
Test name
Test status
Simulation time 207276426591 ps
CPU time 930.79 seconds
Started Jul 10 04:58:16 PM PDT 24
Finished Jul 10 05:13:47 PM PDT 24
Peak memory 216264 kb
Host smart-62aa771f-eec1-430c-85f5-9c4fe630c2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459303024 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1459303024
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2424577758
Short name T17
Test name
Test status
Simulation time 97414675496 ps
CPU time 886.92 seconds
Started Jul 10 04:54:38 PM PDT 24
Finished Jul 10 05:09:26 PM PDT 24
Peak memory 216496 kb
Host smart-b4d3deaf-77ed-413d-a86a-0a1e499ad1a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424577758 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2424577758
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.445065085
Short name T145
Test name
Test status
Simulation time 211353563856 ps
CPU time 306.38 seconds
Started Jul 10 04:57:15 PM PDT 24
Finished Jul 10 05:02:23 PM PDT 24
Peak memory 199832 kb
Host smart-86e98880-0513-4c17-9bb3-c2393d682a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445065085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.445065085
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all.3113233161
Short name T14
Test name
Test status
Simulation time 132831647800 ps
CPU time 222.82 seconds
Started Jul 10 04:55:10 PM PDT 24
Finished Jul 10 04:58:54 PM PDT 24
Peak memory 208124 kb
Host smart-4c0ea497-110c-402a-83e5-843c34475e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113233161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3113233161
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2274339602
Short name T18
Test name
Test status
Simulation time 146865591089 ps
CPU time 782.83 seconds
Started Jul 10 04:57:57 PM PDT 24
Finished Jul 10 05:11:01 PM PDT 24
Peak memory 224708 kb
Host smart-426fe9d8-5f00-4728-af10-7b563101c82f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274339602 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2274339602
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.1190571791
Short name T16
Test name
Test status
Simulation time 173099626903 ps
CPU time 264.85 seconds
Started Jul 10 04:57:15 PM PDT 24
Finished Jul 10 05:01:41 PM PDT 24
Peak memory 199760 kb
Host smart-284de4c4-c69b-4b56-b1c5-a7fe853e2677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190571791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1190571791
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.809497398
Short name T34
Test name
Test status
Simulation time 115247076631 ps
CPU time 1541.03 seconds
Started Jul 10 04:55:41 PM PDT 24
Finished Jul 10 05:21:23 PM PDT 24
Peak memory 224568 kb
Host smart-eed71ebc-ad42-4372-8f2b-5d8ad69ebae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809497398 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.809497398
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.103915698
Short name T4
Test name
Test status
Simulation time 144031596274 ps
CPU time 230.38 seconds
Started Jul 10 04:53:56 PM PDT 24
Finished Jul 10 04:57:48 PM PDT 24
Peak memory 199788 kb
Host smart-c7355ef2-42ec-4bc0-8985-6c4719ced7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103915698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.103915698
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_full.4009423311
Short name T260
Test name
Test status
Simulation time 171041082940 ps
CPU time 362.74 seconds
Started Jul 10 04:55:29 PM PDT 24
Finished Jul 10 05:01:33 PM PDT 24
Peak memory 199848 kb
Host smart-eea1e7b5-def3-41d9-9b34-726e702fce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009423311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4009423311
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1823856880
Short name T90
Test name
Test status
Simulation time 258750888 ps
CPU time 1.3 seconds
Started Jul 10 04:44:50 PM PDT 24
Finished Jul 10 04:44:52 PM PDT 24
Peak memory 199836 kb
Host smart-32d220b5-2060-41ab-ac65-ab5e3e110cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823856880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1823856880
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2195083285
Short name T78
Test name
Test status
Simulation time 45999489 ps
CPU time 0.58 seconds
Started Jul 10 04:51:32 PM PDT 24
Finished Jul 10 04:51:34 PM PDT 24
Peak memory 195696 kb
Host smart-ca62f50a-9c60-4e6d-b8b1-f0e0fafcf81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195083285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2195083285
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3495522154
Short name T126
Test name
Test status
Simulation time 228078127817 ps
CPU time 150.32 seconds
Started Jul 10 04:59:49 PM PDT 24
Finished Jul 10 05:02:20 PM PDT 24
Peak memory 199840 kb
Host smart-b2fc58c2-a786-45fd-bbd5-ba876df66d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495522154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3495522154
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3570332478
Short name T35
Test name
Test status
Simulation time 116506376163 ps
CPU time 1314.79 seconds
Started Jul 10 04:58:19 PM PDT 24
Finished Jul 10 05:20:15 PM PDT 24
Peak memory 229748 kb
Host smart-9ed1647d-6e5c-4b63-994a-cb6e65e917b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570332478 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3570332478
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2465137528
Short name T32
Test name
Test status
Simulation time 216731648942 ps
CPU time 223.24 seconds
Started Jul 10 04:58:47 PM PDT 24
Finished Jul 10 05:02:31 PM PDT 24
Peak memory 199748 kb
Host smart-3761d814-e755-4868-b451-cec813e519fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465137528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2465137528
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.2846233642
Short name T317
Test name
Test status
Simulation time 431019645575 ps
CPU time 138.34 seconds
Started Jul 10 04:55:42 PM PDT 24
Finished Jul 10 04:58:02 PM PDT 24
Peak memory 208144 kb
Host smart-af2a6e47-5396-42f9-9c13-7138d22c3381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846233642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2846233642
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2861872252
Short name T51
Test name
Test status
Simulation time 290766009041 ps
CPU time 676.24 seconds
Started Jul 10 04:58:15 PM PDT 24
Finished Jul 10 05:09:32 PM PDT 24
Peak memory 224712 kb
Host smart-482f2753-de21-4d9a-a2b3-6d45da583d6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861872252 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2861872252
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.644169791
Short name T98
Test name
Test status
Simulation time 129155254 ps
CPU time 0.77 seconds
Started Jul 10 04:51:32 PM PDT 24
Finished Jul 10 04:51:35 PM PDT 24
Peak memory 218008 kb
Host smart-fbb5fcbd-b772-42d5-a177-1ed8f7bb07a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644169791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.644169791
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1194972579
Short name T233
Test name
Test status
Simulation time 227801380764 ps
CPU time 128.23 seconds
Started Jul 10 04:58:59 PM PDT 24
Finished Jul 10 05:01:08 PM PDT 24
Peak memory 199756 kb
Host smart-294e2aa5-4349-4687-a3a2-ba0f30422a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194972579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1194972579
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1882439060
Short name T118
Test name
Test status
Simulation time 250670084608 ps
CPU time 99.15 seconds
Started Jul 10 04:56:16 PM PDT 24
Finished Jul 10 04:57:56 PM PDT 24
Peak memory 199800 kb
Host smart-e8aeb45e-ed4e-466a-baa7-e8b3c802dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882439060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1882439060
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.4051943857
Short name T36
Test name
Test status
Simulation time 56177793001 ps
CPU time 345.49 seconds
Started Jul 10 04:54:38 PM PDT 24
Finished Jul 10 05:00:25 PM PDT 24
Peak memory 216604 kb
Host smart-08c28903-3282-486c-b4d3-9e44734021d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051943857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.4051943857
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2254384475
Short name T123
Test name
Test status
Simulation time 200122363424 ps
CPU time 164.56 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 04:56:04 PM PDT 24
Peak memory 199760 kb
Host smart-0437a065-bb2b-47bf-ac05-e6e0e51955a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254384475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2254384475
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.917742366
Short name T204
Test name
Test status
Simulation time 20102473183 ps
CPU time 25.88 seconds
Started Jul 10 04:59:46 PM PDT 24
Finished Jul 10 05:00:12 PM PDT 24
Peak memory 199784 kb
Host smart-d967967e-912d-4ab6-ba19-8f66a15dd6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917742366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.917742366
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3877105183
Short name T13
Test name
Test status
Simulation time 33819840840 ps
CPU time 18.71 seconds
Started Jul 10 04:59:32 PM PDT 24
Finished Jul 10 04:59:53 PM PDT 24
Peak memory 199808 kb
Host smart-c37bb663-cfc0-43c9-9979-19ca28959d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877105183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3877105183
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2859940413
Short name T52
Test name
Test status
Simulation time 319316716480 ps
CPU time 812.24 seconds
Started Jul 10 04:55:49 PM PDT 24
Finished Jul 10 05:09:22 PM PDT 24
Peak memory 224708 kb
Host smart-7baaf9e4-b37f-4e53-aac9-c7b69a31e96f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859940413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2859940413
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2298195480
Short name T156
Test name
Test status
Simulation time 175455965443 ps
CPU time 72.37 seconds
Started Jul 10 04:57:24 PM PDT 24
Finished Jul 10 04:58:38 PM PDT 24
Peak memory 199836 kb
Host smart-983442c7-fd8b-4cba-9ae6-98557da14b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298195480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2298195480
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.421323600
Short name T63
Test name
Test status
Simulation time 302687847 ps
CPU time 2.62 seconds
Started Jul 10 04:44:20 PM PDT 24
Finished Jul 10 04:44:24 PM PDT 24
Peak memory 198264 kb
Host smart-2c655e7b-cea8-465e-977d-cd8873cf816b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421323600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.421323600
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1984073952
Short name T83
Test name
Test status
Simulation time 25090258 ps
CPU time 0.72 seconds
Started Jul 10 04:44:30 PM PDT 24
Finished Jul 10 04:44:31 PM PDT 24
Peak memory 197408 kb
Host smart-d8cd210b-f2be-4628-9651-2a573f7fb5f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984073952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1984073952
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.376295961
Short name T179
Test name
Test status
Simulation time 104755201533 ps
CPU time 196.38 seconds
Started Jul 10 05:00:34 PM PDT 24
Finished Jul 10 05:03:51 PM PDT 24
Peak memory 199784 kb
Host smart-7d0f8213-11db-4340-9544-8a171687e5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376295961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.376295961
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1251339267
Short name T112
Test name
Test status
Simulation time 142089752815 ps
CPU time 459.57 seconds
Started Jul 10 04:57:43 PM PDT 24
Finished Jul 10 05:05:23 PM PDT 24
Peak memory 224716 kb
Host smart-26be8fd7-afca-4964-a6fe-e29b54802f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251339267 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1251339267
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.1903314090
Short name T181
Test name
Test status
Simulation time 217400308145 ps
CPU time 1551.83 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 05:19:36 PM PDT 24
Peak memory 199796 kb
Host smart-645ee290-fa33-42e4-bbac-bc7175591b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903314090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1903314090
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1339617964
Short name T49
Test name
Test status
Simulation time 49048843256 ps
CPU time 52.23 seconds
Started Jul 10 04:56:09 PM PDT 24
Finished Jul 10 04:57:03 PM PDT 24
Peak memory 199776 kb
Host smart-c60d632e-f05b-4f3a-a12e-184640e6d1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339617964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1339617964
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2668390995
Short name T109
Test name
Test status
Simulation time 34797914233 ps
CPU time 303.92 seconds
Started Jul 10 04:55:11 PM PDT 24
Finished Jul 10 05:00:17 PM PDT 24
Peak memory 216360 kb
Host smart-9728ba00-4468-48ad-9ac2-0165c748e0fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668390995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2668390995
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3959543133
Short name T39
Test name
Test status
Simulation time 94914526279 ps
CPU time 455.44 seconds
Started Jul 10 04:53:00 PM PDT 24
Finished Jul 10 05:00:37 PM PDT 24
Peak memory 215384 kb
Host smart-cd234034-d702-4295-9c8b-cdc7ae19d0b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959543133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3959543133
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.4283134203
Short name T205
Test name
Test status
Simulation time 39627448007 ps
CPU time 54.23 seconds
Started Jul 10 04:58:59 PM PDT 24
Finished Jul 10 04:59:54 PM PDT 24
Peak memory 199784 kb
Host smart-5bee19fb-d658-4650-af2c-05e45519ec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283134203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.4283134203
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3429062627
Short name T567
Test name
Test status
Simulation time 147040545909 ps
CPU time 464.31 seconds
Started Jul 10 04:52:01 PM PDT 24
Finished Jul 10 04:59:47 PM PDT 24
Peak memory 224636 kb
Host smart-6a082512-b954-4e49-81b0-08ae386d6253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429062627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3429062627
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3754895831
Short name T96
Test name
Test status
Simulation time 664082669 ps
CPU time 1.3 seconds
Started Jul 10 04:45:02 PM PDT 24
Finished Jul 10 04:45:05 PM PDT 24
Peak memory 200044 kb
Host smart-20fd67c8-60a5-460f-b049-6bcdffe29a71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754895831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3754895831
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.738390146
Short name T334
Test name
Test status
Simulation time 160377225588 ps
CPU time 285.41 seconds
Started Jul 10 04:59:49 PM PDT 24
Finished Jul 10 05:04:35 PM PDT 24
Peak memory 199844 kb
Host smart-7ab688cd-6fbd-462e-997a-b205d6b60a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738390146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.738390146
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1572794268
Short name T8
Test name
Test status
Simulation time 40334633219 ps
CPU time 85.3 seconds
Started Jul 10 04:54:52 PM PDT 24
Finished Jul 10 04:56:18 PM PDT 24
Peak memory 199788 kb
Host smart-cf6ad21b-6727-4048-8c1f-d26506b70ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572794268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1572794268
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3497502209
Short name T111
Test name
Test status
Simulation time 176083622044 ps
CPU time 367.73 seconds
Started Jul 10 04:57:51 PM PDT 24
Finished Jul 10 05:04:00 PM PDT 24
Peak memory 224740 kb
Host smart-dcc6098c-736f-4540-8e03-42145f5e0164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497502209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3497502209
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2154105660
Short name T190
Test name
Test status
Simulation time 27726086116 ps
CPU time 24.26 seconds
Started Jul 10 04:59:40 PM PDT 24
Finished Jul 10 05:00:05 PM PDT 24
Peak memory 199784 kb
Host smart-59a56ddd-8223-41b4-a770-1bf2516b4095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154105660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2154105660
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.667111299
Short name T168
Test name
Test status
Simulation time 232583550957 ps
CPU time 36.76 seconds
Started Jul 10 05:00:21 PM PDT 24
Finished Jul 10 05:00:59 PM PDT 24
Peak memory 199772 kb
Host smart-8bfeeff8-8b0a-489c-b394-ba63e0df08dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667111299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.667111299
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_perf.523277505
Short name T263
Test name
Test status
Simulation time 26525894582 ps
CPU time 1191.12 seconds
Started Jul 10 04:55:13 PM PDT 24
Finished Jul 10 05:15:05 PM PDT 24
Peak memory 199848 kb
Host smart-b8e43980-fdbd-47e9-896f-f8191209b0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523277505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.523277505
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/46.uart_fifo_full.7705053
Short name T147
Test name
Test status
Simulation time 52098983781 ps
CPU time 77.67 seconds
Started Jul 10 04:57:08 PM PDT 24
Finished Jul 10 04:58:27 PM PDT 24
Peak memory 200092 kb
Host smart-5fb48048-840f-48fa-ae18-c5d5da08cb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7705053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.7705053
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.477085975
Short name T781
Test name
Test status
Simulation time 157161387027 ps
CPU time 229.71 seconds
Started Jul 10 04:58:44 PM PDT 24
Finished Jul 10 05:02:35 PM PDT 24
Peak memory 199764 kb
Host smart-e2240926-51f2-474c-a0cb-c45d74834e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477085975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.477085975
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.1603557002
Short name T107
Test name
Test status
Simulation time 231236193329 ps
CPU time 535.09 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 05:02:15 PM PDT 24
Peak memory 215536 kb
Host smart-1162e4de-020b-4f21-960b-648e3f745044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603557002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1603557002
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4230194075
Short name T173
Test name
Test status
Simulation time 56898004902 ps
CPU time 24.34 seconds
Started Jul 10 05:00:29 PM PDT 24
Finished Jul 10 05:00:54 PM PDT 24
Peak memory 199840 kb
Host smart-f2d52d3d-f303-4b39-96fe-240f5fbf8e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230194075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4230194075
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1513346678
Short name T185
Test name
Test status
Simulation time 311347043646 ps
CPU time 127.05 seconds
Started Jul 10 04:56:10 PM PDT 24
Finished Jul 10 04:58:18 PM PDT 24
Peak memory 199840 kb
Host smart-fefb333a-4a6e-4e90-8ada-0d0a3b0e154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513346678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1513346678
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.40154299
Short name T777
Test name
Test status
Simulation time 76845491119 ps
CPU time 62.61 seconds
Started Jul 10 04:58:41 PM PDT 24
Finished Jul 10 04:59:45 PM PDT 24
Peak memory 199772 kb
Host smart-eb532221-fe53-43e4-a502-2af276317549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40154299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.40154299
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2505858492
Short name T238
Test name
Test status
Simulation time 175976922552 ps
CPU time 100.75 seconds
Started Jul 10 04:58:58 PM PDT 24
Finished Jul 10 05:00:40 PM PDT 24
Peak memory 199844 kb
Host smart-6bc7b18b-f890-4698-a92e-98c4ce46b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505858492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2505858492
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2357207261
Short name T228
Test name
Test status
Simulation time 47375355567 ps
CPU time 30.43 seconds
Started Jul 10 04:58:58 PM PDT 24
Finished Jul 10 04:59:30 PM PDT 24
Peak memory 199748 kb
Host smart-a74c7323-9618-4cfd-a339-2bbf1254435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357207261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2357207261
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1801211807
Short name T294
Test name
Test status
Simulation time 135979875396 ps
CPU time 124.8 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 04:55:26 PM PDT 24
Peak memory 199848 kb
Host smart-92c75ddd-d4ce-4781-865e-4f91575fc35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801211807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1801211807
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3731905485
Short name T254
Test name
Test status
Simulation time 20074777214 ps
CPU time 31.06 seconds
Started Jul 10 04:53:44 PM PDT 24
Finished Jul 10 04:54:17 PM PDT 24
Peak memory 199728 kb
Host smart-b015b9ac-245b-466a-9d1e-c44bdc125038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731905485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3731905485
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.117115413
Short name T320
Test name
Test status
Simulation time 223956170523 ps
CPU time 285.58 seconds
Started Jul 10 04:52:42 PM PDT 24
Finished Jul 10 04:57:29 PM PDT 24
Peak memory 200100 kb
Host smart-a5c1a6d2-f4c9-4f09-883c-3dd30d2bf87a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117115413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.117115413
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.323580216
Short name T258
Test name
Test status
Simulation time 51306450 ps
CPU time 0.92 seconds
Started Jul 10 04:44:27 PM PDT 24
Finished Jul 10 04:44:29 PM PDT 24
Peak memory 199612 kb
Host smart-91ba947d-a0cf-4bb9-aea3-9861c37a651a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323580216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.323580216
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3273471082
Short name T586
Test name
Test status
Simulation time 62337670692 ps
CPU time 94.74 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:54:17 PM PDT 24
Peak memory 199760 kb
Host smart-75fb4ae6-c2b0-4218-a3cd-3c317e8c158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273471082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3273471082
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3484713829
Short name T227
Test name
Test status
Simulation time 35740701582 ps
CPU time 56.27 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:53:55 PM PDT 24
Peak memory 199836 kb
Host smart-f1b9ec0f-2f81-425c-85ea-97c4668667c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484713829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3484713829
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3945201607
Short name T175
Test name
Test status
Simulation time 22948045002 ps
CPU time 10.87 seconds
Started Jul 10 04:58:40 PM PDT 24
Finished Jul 10 04:58:52 PM PDT 24
Peak memory 199808 kb
Host smart-48caceeb-51bb-4c68-93c3-3e429003b7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945201607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3945201607
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3548073135
Short name T166
Test name
Test status
Simulation time 45862318309 ps
CPU time 60.82 seconds
Started Jul 10 04:58:47 PM PDT 24
Finished Jul 10 04:59:49 PM PDT 24
Peak memory 199840 kb
Host smart-46f3e60b-c762-4a56-b5ec-5320f56280c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548073135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3548073135
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.993039892
Short name T221
Test name
Test status
Simulation time 58361376324 ps
CPU time 49.59 seconds
Started Jul 10 04:58:48 PM PDT 24
Finished Jul 10 04:59:38 PM PDT 24
Peak memory 199824 kb
Host smart-75d9da8f-f6d3-4530-b129-5df29c57c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993039892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.993039892
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.977157651
Short name T191
Test name
Test status
Simulation time 40971943377 ps
CPU time 475.73 seconds
Started Jul 10 04:53:08 PM PDT 24
Finished Jul 10 05:01:05 PM PDT 24
Peak memory 216556 kb
Host smart-215d8919-3537-4ef4-bb89-d33726f92553
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977157651 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.977157651
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1797428771
Short name T159
Test name
Test status
Simulation time 117489240265 ps
CPU time 31.65 seconds
Started Jul 10 04:59:07 PM PDT 24
Finished Jul 10 04:59:40 PM PDT 24
Peak memory 199780 kb
Host smart-b436f82a-9a55-468c-b6f9-53aefac60ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797428771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1797428771
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2351521017
Short name T214
Test name
Test status
Simulation time 17700000854 ps
CPU time 27.08 seconds
Started Jul 10 04:59:10 PM PDT 24
Finished Jul 10 04:59:38 PM PDT 24
Peak memory 199620 kb
Host smart-23d7d86f-4826-4bc4-a02b-e75c6c151517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351521017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2351521017
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3131919093
Short name T253
Test name
Test status
Simulation time 9531368711 ps
CPU time 16.77 seconds
Started Jul 10 04:59:12 PM PDT 24
Finished Jul 10 04:59:30 PM PDT 24
Peak memory 199840 kb
Host smart-2d0470b6-358c-41bc-abc0-e6bca2a6cbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131919093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3131919093
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.915512808
Short name T225
Test name
Test status
Simulation time 402055930502 ps
CPU time 772.47 seconds
Started Jul 10 04:53:45 PM PDT 24
Finished Jul 10 05:06:39 PM PDT 24
Peak memory 216368 kb
Host smart-411bc66e-e51d-48ab-8d3f-dd12ac7daee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915512808 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.915512808
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2346266106
Short name T864
Test name
Test status
Simulation time 49430637188 ps
CPU time 21.16 seconds
Started Jul 10 04:59:31 PM PDT 24
Finished Jul 10 04:59:54 PM PDT 24
Peak memory 199844 kb
Host smart-f7acc0b9-c45e-4fd3-a3e4-0c48c7cfdf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346266106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2346266106
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.160915453
Short name T1027
Test name
Test status
Simulation time 113868414995 ps
CPU time 48.17 seconds
Started Jul 10 04:59:32 PM PDT 24
Finished Jul 10 05:00:22 PM PDT 24
Peak memory 199752 kb
Host smart-0cb712c2-4b0a-487b-b2cf-61cc3b38bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160915453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.160915453
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3108332506
Short name T241
Test name
Test status
Simulation time 76462440433 ps
CPU time 31.35 seconds
Started Jul 10 04:59:46 PM PDT 24
Finished Jul 10 05:00:18 PM PDT 24
Peak memory 199764 kb
Host smart-e2b17c72-9958-40d4-8ffc-b9557664d38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108332506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3108332506
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.174988672
Short name T810
Test name
Test status
Simulation time 191027393628 ps
CPU time 668.67 seconds
Started Jul 10 04:54:27 PM PDT 24
Finished Jul 10 05:05:37 PM PDT 24
Peak memory 199836 kb
Host smart-893323df-8f54-4e07-b9bf-772cff085bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174988672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.174988672
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3717202987
Short name T177
Test name
Test status
Simulation time 17463821290 ps
CPU time 29.07 seconds
Started Jul 10 04:54:27 PM PDT 24
Finished Jul 10 04:54:57 PM PDT 24
Peak memory 199776 kb
Host smart-51be9891-3261-42d1-a995-654e1a3ea2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717202987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3717202987
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3459793301
Short name T236
Test name
Test status
Simulation time 272952383381 ps
CPU time 49.89 seconds
Started Jul 10 05:00:53 PM PDT 24
Finished Jul 10 05:01:45 PM PDT 24
Peak memory 199840 kb
Host smart-b7e48934-3368-49ef-a89b-47d52da3db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459793301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3459793301
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.534796079
Short name T250
Test name
Test status
Simulation time 10029313792 ps
CPU time 15.73 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:09 PM PDT 24
Peak memory 199764 kb
Host smart-c68b282d-3c94-4f4c-82dd-31e7e98f9cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534796079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.534796079
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3180803183
Short name T240
Test name
Test status
Simulation time 61256934505 ps
CPU time 51.87 seconds
Started Jul 10 04:56:12 PM PDT 24
Finished Jul 10 04:57:05 PM PDT 24
Peak memory 199808 kb
Host smart-e52c46b6-b406-4702-b7dc-5ed7425c95b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180803183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3180803183
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3785410710
Short name T230
Test name
Test status
Simulation time 56530785327 ps
CPU time 114.51 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:54:14 PM PDT 24
Peak memory 199820 kb
Host smart-e30e010a-6ce3-46b1-8e29-11e0688ce7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785410710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3785410710
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3015713271
Short name T248
Test name
Test status
Simulation time 19697034900 ps
CPU time 43.48 seconds
Started Jul 10 04:57:51 PM PDT 24
Finished Jul 10 04:58:35 PM PDT 24
Peak memory 199840 kb
Host smart-4956444b-abd5-4d99-a6c2-f9cbcf25645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015713271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3015713271
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.565054080
Short name T129
Test name
Test status
Simulation time 46993661986 ps
CPU time 17.83 seconds
Started Jul 10 04:58:32 PM PDT 24
Finished Jul 10 04:58:50 PM PDT 24
Peak memory 199776 kb
Host smart-098a116d-01f1-496c-80a0-d61b23a3309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565054080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.565054080
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.4037461308
Short name T1242
Test name
Test status
Simulation time 16474915 ps
CPU time 0.77 seconds
Started Jul 10 04:44:27 PM PDT 24
Finished Jul 10 04:44:29 PM PDT 24
Peak memory 196916 kb
Host smart-9e4a3189-cda8-4a03-914b-e8692d18507a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037461308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.4037461308
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.933470693
Short name T1263
Test name
Test status
Simulation time 70254621 ps
CPU time 0.6 seconds
Started Jul 10 04:44:24 PM PDT 24
Finished Jul 10 04:44:26 PM PDT 24
Peak memory 196084 kb
Host smart-896392d6-5656-4bce-9687-bc9c61dad1c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933470693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.933470693
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3547512280
Short name T1305
Test name
Test status
Simulation time 78612529 ps
CPU time 0.74 seconds
Started Jul 10 04:44:20 PM PDT 24
Finished Jul 10 04:44:22 PM PDT 24
Peak memory 199360 kb
Host smart-610b64d8-a9bc-48aa-b666-3d87ba08568b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547512280 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3547512280
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3446814893
Short name T1248
Test name
Test status
Simulation time 23272004 ps
CPU time 0.61 seconds
Started Jul 10 04:44:22 PM PDT 24
Finished Jul 10 04:44:24 PM PDT 24
Peak memory 196108 kb
Host smart-7eac3a73-98f7-452b-836d-022dce4e5168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446814893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3446814893
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3765758943
Short name T1210
Test name
Test status
Simulation time 41250579 ps
CPU time 0.56 seconds
Started Jul 10 04:44:20 PM PDT 24
Finished Jul 10 04:44:22 PM PDT 24
Peak memory 194988 kb
Host smart-a5039bf4-fd2e-4ed0-a380-abba0e55d0ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765758943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3765758943
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3345486742
Short name T1297
Test name
Test status
Simulation time 63204596 ps
CPU time 0.74 seconds
Started Jul 10 04:44:10 PM PDT 24
Finished Jul 10 04:44:13 PM PDT 24
Peak memory 197176 kb
Host smart-95b15431-c038-40ac-bc7b-127a839af28b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345486742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3345486742
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.4195142237
Short name T1196
Test name
Test status
Simulation time 712052900 ps
CPU time 2.32 seconds
Started Jul 10 04:44:20 PM PDT 24
Finished Jul 10 04:44:24 PM PDT 24
Peak memory 200712 kb
Host smart-89a32525-5e52-4c0d-b48a-f2b7d90c1f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195142237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4195142237
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2930688696
Short name T94
Test name
Test status
Simulation time 68965727 ps
CPU time 1.02 seconds
Started Jul 10 04:44:16 PM PDT 24
Finished Jul 10 04:44:18 PM PDT 24
Peak memory 199676 kb
Host smart-810e801b-04b5-4239-8b49-3f5c2ab289d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930688696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2930688696
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2880892046
Short name T61
Test name
Test status
Simulation time 86320708 ps
CPU time 0.76 seconds
Started Jul 10 04:44:42 PM PDT 24
Finished Jul 10 04:44:43 PM PDT 24
Peak memory 196976 kb
Host smart-e5c06cdf-9f0b-4da9-90b3-c6f490b9ccab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880892046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2880892046
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1783100949
Short name T1202
Test name
Test status
Simulation time 230912357 ps
CPU time 1.49 seconds
Started Jul 10 04:44:25 PM PDT 24
Finished Jul 10 04:44:27 PM PDT 24
Peak memory 198016 kb
Host smart-1a088dbb-ceaa-421b-9bcb-2ec374cb4f63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783100949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1783100949
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2142188742
Short name T1206
Test name
Test status
Simulation time 72664218 ps
CPU time 0.58 seconds
Started Jul 10 04:44:23 PM PDT 24
Finished Jul 10 04:44:25 PM PDT 24
Peak memory 196080 kb
Host smart-95c8aecf-1fbc-40b7-88b8-b94169d44f39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142188742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2142188742
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2852682407
Short name T1252
Test name
Test status
Simulation time 20960447 ps
CPU time 1.08 seconds
Started Jul 10 04:44:30 PM PDT 24
Finished Jul 10 04:44:32 PM PDT 24
Peak memory 200732 kb
Host smart-36bbd0e3-0425-4e53-b56a-df0f12c73d61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852682407 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2852682407
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.364784150
Short name T1217
Test name
Test status
Simulation time 22490642 ps
CPU time 0.64 seconds
Started Jul 10 04:44:19 PM PDT 24
Finished Jul 10 04:44:21 PM PDT 24
Peak memory 196088 kb
Host smart-2ffd132c-2cc7-4ada-9de1-58e53e3e7867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364784150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.364784150
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.126867003
Short name T1281
Test name
Test status
Simulation time 30315238 ps
CPU time 0.63 seconds
Started Jul 10 04:44:15 PM PDT 24
Finished Jul 10 04:44:16 PM PDT 24
Peak memory 195004 kb
Host smart-baa62c3d-4694-4820-a8b0-cdbf75815d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126867003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.126867003
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.411807998
Short name T1270
Test name
Test status
Simulation time 223912721 ps
CPU time 1.65 seconds
Started Jul 10 04:44:23 PM PDT 24
Finished Jul 10 04:44:26 PM PDT 24
Peak memory 200720 kb
Host smart-8031be62-76a1-4262-b170-2afd1018c849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411807998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.411807998
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2408309775
Short name T1311
Test name
Test status
Simulation time 168006874 ps
CPU time 1.48 seconds
Started Jul 10 04:44:47 PM PDT 24
Finished Jul 10 04:44:49 PM PDT 24
Peak memory 200700 kb
Host smart-57d8e439-aab4-41b9-b8dd-ee3d6e344edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408309775 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2408309775
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2696370908
Short name T1222
Test name
Test status
Simulation time 50315527 ps
CPU time 0.56 seconds
Started Jul 10 04:44:52 PM PDT 24
Finished Jul 10 04:44:54 PM PDT 24
Peak memory 196088 kb
Host smart-efad7cd6-24ab-4b8d-b649-20849d82fbfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696370908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2696370908
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.449532746
Short name T1247
Test name
Test status
Simulation time 15637905 ps
CPU time 0.57 seconds
Started Jul 10 04:44:44 PM PDT 24
Finished Jul 10 04:44:46 PM PDT 24
Peak memory 195040 kb
Host smart-03da4272-8dd2-46cb-86d3-fc693c91018f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449532746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.449532746
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2182378244
Short name T1295
Test name
Test status
Simulation time 25130464 ps
CPU time 0.75 seconds
Started Jul 10 04:44:46 PM PDT 24
Finished Jul 10 04:44:47 PM PDT 24
Peak memory 197516 kb
Host smart-3bbf2d66-c90c-4855-a65b-48147d011fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182378244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2182378244
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.508378963
Short name T1188
Test name
Test status
Simulation time 43588250 ps
CPU time 2.03 seconds
Started Jul 10 04:44:56 PM PDT 24
Finished Jul 10 04:44:59 PM PDT 24
Peak memory 200664 kb
Host smart-002b5fd4-4dcf-4eab-b779-97c3865014a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508378963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.508378963
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3432954
Short name T259
Test name
Test status
Simulation time 87400250 ps
CPU time 1.43 seconds
Started Jul 10 04:45:03 PM PDT 24
Finished Jul 10 04:45:05 PM PDT 24
Peak memory 200028 kb
Host smart-32e4ac52-bcad-40c0-a9c9-15e8914ed2c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3432954
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4233349972
Short name T1278
Test name
Test status
Simulation time 24811092 ps
CPU time 0.82 seconds
Started Jul 10 04:44:55 PM PDT 24
Finished Jul 10 04:44:57 PM PDT 24
Peak memory 199876 kb
Host smart-7888e19a-5edf-432b-8689-4c26057bed12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233349972 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4233349972
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2544987438
Short name T1227
Test name
Test status
Simulation time 30393914 ps
CPU time 0.58 seconds
Started Jul 10 04:44:54 PM PDT 24
Finished Jul 10 04:44:55 PM PDT 24
Peak memory 196052 kb
Host smart-6d9e74bb-efa0-4c7f-94dc-b641dea998fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544987438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2544987438
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.825813898
Short name T1259
Test name
Test status
Simulation time 44100913 ps
CPU time 0.56 seconds
Started Jul 10 04:44:48 PM PDT 24
Finished Jul 10 04:44:50 PM PDT 24
Peak memory 195024 kb
Host smart-f78b618e-2556-4257-98d9-c79da5966ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825813898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.825813898
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3594474763
Short name T81
Test name
Test status
Simulation time 270710813 ps
CPU time 0.77 seconds
Started Jul 10 04:45:00 PM PDT 24
Finished Jul 10 04:45:02 PM PDT 24
Peak memory 198412 kb
Host smart-24ac040c-66bd-4d92-a307-01d07149a913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594474763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3594474763
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3509626905
Short name T1301
Test name
Test status
Simulation time 404507422 ps
CPU time 1.33 seconds
Started Jul 10 04:44:55 PM PDT 24
Finished Jul 10 04:44:58 PM PDT 24
Peak memory 200720 kb
Host smart-9dc1715a-1f76-4abc-b412-99237f9f12be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509626905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3509626905
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4043649555
Short name T1273
Test name
Test status
Simulation time 1156385454 ps
CPU time 1.34 seconds
Started Jul 10 04:44:58 PM PDT 24
Finished Jul 10 04:45:00 PM PDT 24
Peak memory 200068 kb
Host smart-30b42ce9-eb29-42f3-a6c2-37974df8adb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043649555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4043649555
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.913891550
Short name T1189
Test name
Test status
Simulation time 38167211 ps
CPU time 0.75 seconds
Started Jul 10 04:45:07 PM PDT 24
Finished Jul 10 04:45:08 PM PDT 24
Peak memory 198792 kb
Host smart-8b1281b7-18ad-4509-afc2-b1c3fbd37a1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913891550 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.913891550
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2905462627
Short name T1268
Test name
Test status
Simulation time 19226328 ps
CPU time 0.63 seconds
Started Jul 10 04:45:01 PM PDT 24
Finished Jul 10 04:45:02 PM PDT 24
Peak memory 196152 kb
Host smart-d108ede8-7083-4fd6-a026-cdd1603d1601
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905462627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2905462627
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3270944045
Short name T1300
Test name
Test status
Simulation time 19720137 ps
CPU time 0.64 seconds
Started Jul 10 04:45:04 PM PDT 24
Finished Jul 10 04:45:06 PM PDT 24
Peak memory 195052 kb
Host smart-32dd7274-b5dc-46c1-9283-054e687fa528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270944045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3270944045
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3360996462
Short name T1304
Test name
Test status
Simulation time 98247491 ps
CPU time 0.7 seconds
Started Jul 10 04:44:55 PM PDT 24
Finished Jul 10 04:45:02 PM PDT 24
Peak memory 197468 kb
Host smart-b9a7610c-4660-4541-a469-2d724a475612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360996462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3360996462
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.116995018
Short name T1185
Test name
Test status
Simulation time 192760495 ps
CPU time 2.1 seconds
Started Jul 10 04:44:58 PM PDT 24
Finished Jul 10 04:45:01 PM PDT 24
Peak memory 200724 kb
Host smart-a4364061-957e-4066-a082-49a269da4274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116995018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.116995018
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2869517926
Short name T95
Test name
Test status
Simulation time 233984626 ps
CPU time 1.09 seconds
Started Jul 10 04:44:40 PM PDT 24
Finished Jul 10 04:44:42 PM PDT 24
Peak memory 199792 kb
Host smart-f6ccfa85-ed70-4ef3-9c75-b9533b2a465b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869517926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2869517926
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1755037280
Short name T1220
Test name
Test status
Simulation time 53215330 ps
CPU time 0.68 seconds
Started Jul 10 04:44:59 PM PDT 24
Finished Jul 10 04:45:00 PM PDT 24
Peak memory 198716 kb
Host smart-56c16480-0546-4cd2-b247-077b2c16ccdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755037280 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1755037280
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1245762876
Short name T65
Test name
Test status
Simulation time 16099883 ps
CPU time 0.6 seconds
Started Jul 10 04:45:09 PM PDT 24
Finished Jul 10 04:45:12 PM PDT 24
Peak memory 195924 kb
Host smart-d74daa10-9a07-49d7-a951-49b75c070397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245762876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1245762876
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2790049590
Short name T1292
Test name
Test status
Simulation time 39362538 ps
CPU time 0.56 seconds
Started Jul 10 04:45:07 PM PDT 24
Finished Jul 10 04:45:08 PM PDT 24
Peak memory 195064 kb
Host smart-e16f1dd5-47e1-4475-840c-5544132e972d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790049590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2790049590
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4077228301
Short name T1239
Test name
Test status
Simulation time 360524904 ps
CPU time 0.81 seconds
Started Jul 10 04:45:24 PM PDT 24
Finished Jul 10 04:45:27 PM PDT 24
Peak memory 198220 kb
Host smart-b8699870-52d0-4417-859a-5341b0c8aadc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077228301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.4077228301
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.461356646
Short name T1240
Test name
Test status
Simulation time 180132648 ps
CPU time 1.95 seconds
Started Jul 10 04:44:50 PM PDT 24
Finished Jul 10 04:44:53 PM PDT 24
Peak memory 200572 kb
Host smart-478355fd-3228-4f47-bf32-44f6db233b29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461356646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.461356646
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3284071147
Short name T1199
Test name
Test status
Simulation time 297862313 ps
CPU time 0.77 seconds
Started Jul 10 04:44:53 PM PDT 24
Finished Jul 10 04:44:54 PM PDT 24
Peak memory 200472 kb
Host smart-d76dc703-feb4-401c-88fa-0e5bb07c146d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284071147 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3284071147
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.4048168135
Short name T1200
Test name
Test status
Simulation time 178279367 ps
CPU time 0.59 seconds
Started Jul 10 04:44:48 PM PDT 24
Finished Jul 10 04:44:49 PM PDT 24
Peak memory 196116 kb
Host smart-c185e937-0ecd-4685-87de-066b4be620a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048168135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4048168135
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1550905347
Short name T1312
Test name
Test status
Simulation time 88696479 ps
CPU time 0.6 seconds
Started Jul 10 04:45:09 PM PDT 24
Finished Jul 10 04:45:11 PM PDT 24
Peak memory 194940 kb
Host smart-e0a15707-e942-48eb-877a-ff8c2493b6a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550905347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1550905347
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2020700162
Short name T1296
Test name
Test status
Simulation time 14992096 ps
CPU time 0.66 seconds
Started Jul 10 04:45:10 PM PDT 24
Finished Jul 10 04:45:14 PM PDT 24
Peak memory 196468 kb
Host smart-94fec0f7-2205-48a3-863e-a4b6fef1e84b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020700162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2020700162
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.79313448
Short name T1190
Test name
Test status
Simulation time 178996989 ps
CPU time 1.92 seconds
Started Jul 10 04:44:57 PM PDT 24
Finished Jul 10 04:45:00 PM PDT 24
Peak memory 200712 kb
Host smart-1cbe1fb3-5b85-4d9d-a433-949e3ecf79d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79313448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.79313448
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2928781947
Short name T92
Test name
Test status
Simulation time 101446713 ps
CPU time 1.25 seconds
Started Jul 10 04:44:45 PM PDT 24
Finished Jul 10 04:44:47 PM PDT 24
Peak memory 199868 kb
Host smart-3d75c59e-610a-464f-8b6a-424028f9c0ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928781947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2928781947
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3654635586
Short name T1256
Test name
Test status
Simulation time 100011977 ps
CPU time 1.2 seconds
Started Jul 10 04:44:48 PM PDT 24
Finished Jul 10 04:44:50 PM PDT 24
Peak memory 200604 kb
Host smart-3fe2f638-111e-472b-972b-f7c2a0f7fde0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654635586 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3654635586
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1727706810
Short name T87
Test name
Test status
Simulation time 118753531 ps
CPU time 0.67 seconds
Started Jul 10 04:44:54 PM PDT 24
Finished Jul 10 04:44:55 PM PDT 24
Peak memory 196200 kb
Host smart-ee108f45-bba1-47a9-bd70-c9fab548f1f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727706810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1727706810
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3274918254
Short name T1195
Test name
Test status
Simulation time 18946958 ps
CPU time 0.6 seconds
Started Jul 10 04:44:56 PM PDT 24
Finished Jul 10 04:44:58 PM PDT 24
Peak memory 195032 kb
Host smart-951b24b2-c371-47f3-b9c7-aa49f7b87dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274918254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3274918254
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1621300871
Short name T84
Test name
Test status
Simulation time 13520509 ps
CPU time 0.65 seconds
Started Jul 10 04:44:42 PM PDT 24
Finished Jul 10 04:44:44 PM PDT 24
Peak memory 197268 kb
Host smart-d216d382-0228-433c-82d2-96d9dc9df6ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621300871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1621300871
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3089899694
Short name T1277
Test name
Test status
Simulation time 85955939 ps
CPU time 0.91 seconds
Started Jul 10 04:44:51 PM PDT 24
Finished Jul 10 04:44:53 PM PDT 24
Peak memory 200480 kb
Host smart-bb04779c-166d-44b2-9a76-9e5bc6f091de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089899694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3089899694
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4260229601
Short name T93
Test name
Test status
Simulation time 281857018 ps
CPU time 1.31 seconds
Started Jul 10 04:44:53 PM PDT 24
Finished Jul 10 04:45:00 PM PDT 24
Peak memory 200240 kb
Host smart-31a16bff-10dc-4b13-aaff-66e5063b8917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260229601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.4260229601
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2956761702
Short name T1215
Test name
Test status
Simulation time 42830211 ps
CPU time 0.75 seconds
Started Jul 10 04:44:54 PM PDT 24
Finished Jul 10 04:44:56 PM PDT 24
Peak memory 199552 kb
Host smart-7041297f-f736-41a2-86ac-d978de6f8767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956761702 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2956761702
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2342460591
Short name T70
Test name
Test status
Simulation time 34725169 ps
CPU time 0.58 seconds
Started Jul 10 04:44:49 PM PDT 24
Finished Jul 10 04:44:50 PM PDT 24
Peak memory 196136 kb
Host smart-c0e2fcc2-ef36-4589-a757-f7cf80e86a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342460591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2342460591
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2674616679
Short name T1211
Test name
Test status
Simulation time 38187040 ps
CPU time 0.55 seconds
Started Jul 10 04:45:15 PM PDT 24
Finished Jul 10 04:45:18 PM PDT 24
Peak memory 194856 kb
Host smart-5a5ea160-9d60-416b-9c8d-afa494b8306e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674616679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2674616679
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.4047161646
Short name T1234
Test name
Test status
Simulation time 17220992 ps
CPU time 0.73 seconds
Started Jul 10 04:44:50 PM PDT 24
Finished Jul 10 04:44:52 PM PDT 24
Peak memory 196492 kb
Host smart-489a146d-6ff7-46dc-83fd-b5149276c1a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047161646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.4047161646
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.996543796
Short name T1267
Test name
Test status
Simulation time 56678856 ps
CPU time 1.53 seconds
Started Jul 10 04:44:58 PM PDT 24
Finished Jul 10 04:45:00 PM PDT 24
Peak memory 200724 kb
Host smart-067971c4-c5d9-44dc-8528-84b884f2ec9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996543796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.996543796
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3096362102
Short name T1294
Test name
Test status
Simulation time 277399762 ps
CPU time 1.24 seconds
Started Jul 10 04:45:09 PM PDT 24
Finished Jul 10 04:45:12 PM PDT 24
Peak memory 199892 kb
Host smart-f6ae69fa-3ad6-4f9d-8cd7-5868182ae9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096362102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3096362102
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3655391234
Short name T1231
Test name
Test status
Simulation time 279928610 ps
CPU time 1.36 seconds
Started Jul 10 04:45:07 PM PDT 24
Finished Jul 10 04:45:10 PM PDT 24
Peak memory 200716 kb
Host smart-2ebd5196-aa18-47bd-b4d2-66d25b23222e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655391234 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3655391234
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.4283612141
Short name T60
Test name
Test status
Simulation time 98092914 ps
CPU time 0.6 seconds
Started Jul 10 04:45:19 PM PDT 24
Finished Jul 10 04:45:21 PM PDT 24
Peak memory 196048 kb
Host smart-b1735f75-00d2-4216-9a24-9c1993a89640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283612141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.4283612141
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.743773358
Short name T1303
Test name
Test status
Simulation time 41580582 ps
CPU time 0.55 seconds
Started Jul 10 04:45:01 PM PDT 24
Finished Jul 10 04:45:03 PM PDT 24
Peak memory 194956 kb
Host smart-20faa145-2a2c-4827-a915-fe17daf3345b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743773358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.743773358
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1366610132
Short name T85
Test name
Test status
Simulation time 57815418 ps
CPU time 0.78 seconds
Started Jul 10 04:44:56 PM PDT 24
Finished Jul 10 04:44:58 PM PDT 24
Peak memory 197880 kb
Host smart-ca16fb52-8518-454d-9be4-f450e23f8dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366610132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1366610132
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1886914439
Short name T1237
Test name
Test status
Simulation time 82560169 ps
CPU time 1.67 seconds
Started Jul 10 04:44:52 PM PDT 24
Finished Jul 10 04:44:55 PM PDT 24
Peak memory 200720 kb
Host smart-e8bfe60b-3c8d-44fe-8da1-de8e58ea2846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886914439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1886914439
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3604367183
Short name T1302
Test name
Test status
Simulation time 157008181 ps
CPU time 1.33 seconds
Started Jul 10 04:45:08 PM PDT 24
Finished Jul 10 04:45:11 PM PDT 24
Peak memory 199988 kb
Host smart-0b58646c-1567-45bd-aba3-0ead5febd89b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604367183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3604367183
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1153985646
Short name T1280
Test name
Test status
Simulation time 47961634 ps
CPU time 0.84 seconds
Started Jul 10 04:45:11 PM PDT 24
Finished Jul 10 04:45:15 PM PDT 24
Peak memory 200492 kb
Host smart-da083c8e-d9a5-44e0-92a7-eff8f7bc94b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153985646 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1153985646
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3923196802
Short name T67
Test name
Test status
Simulation time 44177883 ps
CPU time 0.59 seconds
Started Jul 10 04:44:54 PM PDT 24
Finished Jul 10 04:44:56 PM PDT 24
Peak memory 196272 kb
Host smart-3fd306f2-d3ca-4a4f-9e22-07fef903c234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923196802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3923196802
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3306467393
Short name T1186
Test name
Test status
Simulation time 22371088 ps
CPU time 0.61 seconds
Started Jul 10 04:45:01 PM PDT 24
Finished Jul 10 04:45:03 PM PDT 24
Peak memory 195080 kb
Host smart-e94e93b1-9985-4465-9539-d28ec5a3e0c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306467393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3306467393
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.132537993
Short name T1241
Test name
Test status
Simulation time 17071104 ps
CPU time 0.65 seconds
Started Jul 10 04:44:55 PM PDT 24
Finished Jul 10 04:44:57 PM PDT 24
Peak memory 196136 kb
Host smart-c07191cf-14e4-4aff-bdef-74375a71231a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132537993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.132537993
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2856798593
Short name T1218
Test name
Test status
Simulation time 78929712 ps
CPU time 1.03 seconds
Started Jul 10 04:44:51 PM PDT 24
Finished Jul 10 04:44:53 PM PDT 24
Peak memory 200640 kb
Host smart-f9f3246b-3bb5-448a-b027-e2e9b6c0ecad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856798593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2856798593
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3790665186
Short name T1260
Test name
Test status
Simulation time 102269527 ps
CPU time 1.1 seconds
Started Jul 10 04:45:08 PM PDT 24
Finished Jul 10 04:45:10 PM PDT 24
Peak memory 199692 kb
Host smart-0c26f07c-1c34-4e98-8f51-0f611619ce95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790665186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3790665186
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3712755477
Short name T1194
Test name
Test status
Simulation time 59548336 ps
CPU time 0.69 seconds
Started Jul 10 04:45:13 PM PDT 24
Finished Jul 10 04:45:17 PM PDT 24
Peak memory 198268 kb
Host smart-cbf786eb-9c2b-475c-8066-fbae9c049a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712755477 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3712755477
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2547402139
Short name T82
Test name
Test status
Simulation time 35033222 ps
CPU time 0.59 seconds
Started Jul 10 04:45:18 PM PDT 24
Finished Jul 10 04:45:20 PM PDT 24
Peak memory 196288 kb
Host smart-3071778f-9cfb-43eb-9285-125ece0d2aef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547402139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2547402139
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2324958447
Short name T1286
Test name
Test status
Simulation time 51532471 ps
CPU time 0.6 seconds
Started Jul 10 04:45:09 PM PDT 24
Finished Jul 10 04:45:11 PM PDT 24
Peak memory 195068 kb
Host smart-f3cba67a-5b6e-44ad-82d2-48760dfdbe24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324958447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2324958447
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1286596917
Short name T88
Test name
Test status
Simulation time 32504462 ps
CPU time 0.8 seconds
Started Jul 10 04:45:13 PM PDT 24
Finished Jul 10 04:45:17 PM PDT 24
Peak memory 197776 kb
Host smart-eb8073e9-2b86-4556-8a7f-1f85450822ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286596917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1286596917
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.301826907
Short name T1193
Test name
Test status
Simulation time 48507967 ps
CPU time 2.02 seconds
Started Jul 10 04:45:01 PM PDT 24
Finished Jul 10 04:45:04 PM PDT 24
Peak memory 200688 kb
Host smart-d665997c-8dc4-4c4d-a74e-373c28d4e6f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301826907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.301826907
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3031010882
Short name T91
Test name
Test status
Simulation time 106706739 ps
CPU time 1.24 seconds
Started Jul 10 04:45:10 PM PDT 24
Finished Jul 10 04:45:13 PM PDT 24
Peak memory 200236 kb
Host smart-5a07e14c-cce3-447a-8572-0a1eee0b496f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031010882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3031010882
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3754827275
Short name T62
Test name
Test status
Simulation time 218122574 ps
CPU time 0.82 seconds
Started Jul 10 04:44:41 PM PDT 24
Finished Jul 10 04:44:43 PM PDT 24
Peak memory 197020 kb
Host smart-fec987e2-ce82-4c1e-a593-1a05ee1a17ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754827275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3754827275
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1871550247
Short name T69
Test name
Test status
Simulation time 57058328 ps
CPU time 2.47 seconds
Started Jul 10 04:44:22 PM PDT 24
Finished Jul 10 04:44:26 PM PDT 24
Peak memory 198708 kb
Host smart-0b391a22-d5dd-45fd-b3b3-e6ed920f6aa6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871550247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1871550247
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2954351936
Short name T1208
Test name
Test status
Simulation time 28621563 ps
CPU time 0.59 seconds
Started Jul 10 04:44:29 PM PDT 24
Finished Jul 10 04:44:30 PM PDT 24
Peak memory 196084 kb
Host smart-ca01a6d9-e062-499b-9b77-0ca2db5a9b6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954351936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2954351936
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1900101472
Short name T1233
Test name
Test status
Simulation time 68018587 ps
CPU time 1.01 seconds
Started Jul 10 04:44:20 PM PDT 24
Finished Jul 10 04:44:22 PM PDT 24
Peak memory 200488 kb
Host smart-92efcba1-0eb2-4444-9be0-d7298a4884e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900101472 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1900101472
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.204700766
Short name T1313
Test name
Test status
Simulation time 42629392 ps
CPU time 0.63 seconds
Started Jul 10 04:44:21 PM PDT 24
Finished Jul 10 04:44:23 PM PDT 24
Peak memory 196088 kb
Host smart-2e7bb7bb-06de-4d5d-986e-9fed19d9b961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204700766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.204700766
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3530279042
Short name T1288
Test name
Test status
Simulation time 11721439 ps
CPU time 0.56 seconds
Started Jul 10 04:44:30 PM PDT 24
Finished Jul 10 04:44:31 PM PDT 24
Peak memory 195220 kb
Host smart-db043914-558b-4db0-98ea-1cd2668694c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530279042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3530279042
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2288395595
Short name T1219
Test name
Test status
Simulation time 14513989 ps
CPU time 0.63 seconds
Started Jul 10 04:44:21 PM PDT 24
Finished Jul 10 04:44:23 PM PDT 24
Peak memory 197128 kb
Host smart-a0a18599-47c5-44ca-a3ff-4c19e0feaa5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288395595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2288395595
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.947496855
Short name T1228
Test name
Test status
Simulation time 40997096 ps
CPU time 1.14 seconds
Started Jul 10 04:44:23 PM PDT 24
Finished Jul 10 04:44:30 PM PDT 24
Peak memory 200696 kb
Host smart-cdd25f4f-7d06-4302-ada5-29e1db0f9248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947496855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.947496855
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.500443193
Short name T1282
Test name
Test status
Simulation time 126449211 ps
CPU time 0.97 seconds
Started Jul 10 04:44:27 PM PDT 24
Finished Jul 10 04:44:28 PM PDT 24
Peak memory 199532 kb
Host smart-c939c6a3-e222-44fc-bc73-a43f9043ffda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500443193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.500443193
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.222764392
Short name T1235
Test name
Test status
Simulation time 27946004 ps
CPU time 0.57 seconds
Started Jul 10 04:45:02 PM PDT 24
Finished Jul 10 04:45:04 PM PDT 24
Peak memory 195060 kb
Host smart-98abc48c-c79e-4ccd-a569-14806477c725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222764392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.222764392
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.541185554
Short name T1246
Test name
Test status
Simulation time 13305812 ps
CPU time 0.57 seconds
Started Jul 10 04:45:12 PM PDT 24
Finished Jul 10 04:45:16 PM PDT 24
Peak memory 195068 kb
Host smart-53cfeef5-bd31-440b-a712-c874535bec18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541185554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.541185554
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2272898300
Short name T1224
Test name
Test status
Simulation time 41821314 ps
CPU time 0.54 seconds
Started Jul 10 04:45:09 PM PDT 24
Finished Jul 10 04:45:12 PM PDT 24
Peak memory 194916 kb
Host smart-08cfeb2e-39e3-40c9-b075-d181e4cba232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272898300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2272898300
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1800053962
Short name T1213
Test name
Test status
Simulation time 34883982 ps
CPU time 0.54 seconds
Started Jul 10 04:45:15 PM PDT 24
Finished Jul 10 04:45:18 PM PDT 24
Peak memory 194920 kb
Host smart-442aff4a-27f5-4f6e-a1b3-bfabcfd1eb0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800053962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1800053962
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1300346283
Short name T1236
Test name
Test status
Simulation time 15078744 ps
CPU time 0.55 seconds
Started Jul 10 04:45:19 PM PDT 24
Finished Jul 10 04:45:21 PM PDT 24
Peak memory 194944 kb
Host smart-f1a7bff0-1fc4-4acb-a3ca-c5b86d3a0301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300346283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1300346283
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1711899212
Short name T1198
Test name
Test status
Simulation time 12194190 ps
CPU time 0.62 seconds
Started Jul 10 04:45:03 PM PDT 24
Finished Jul 10 04:45:04 PM PDT 24
Peak memory 195064 kb
Host smart-a59fa203-bd73-4d5d-88ae-79138ee2e8d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711899212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1711899212
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2604751803
Short name T1314
Test name
Test status
Simulation time 41286507 ps
CPU time 0.54 seconds
Started Jul 10 04:45:18 PM PDT 24
Finished Jul 10 04:45:21 PM PDT 24
Peak memory 195008 kb
Host smart-83859649-85a8-4b51-9030-ed9a05229e74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604751803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2604751803
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.364971942
Short name T1243
Test name
Test status
Simulation time 50647679 ps
CPU time 0.58 seconds
Started Jul 10 04:45:08 PM PDT 24
Finished Jul 10 04:45:10 PM PDT 24
Peak memory 194984 kb
Host smart-d0191d46-734b-404a-b931-34c1b51fc903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364971942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.364971942
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.4256799409
Short name T1238
Test name
Test status
Simulation time 32102334 ps
CPU time 0.57 seconds
Started Jul 10 04:45:10 PM PDT 24
Finished Jul 10 04:45:13 PM PDT 24
Peak memory 194976 kb
Host smart-14516e0b-b144-47a7-81b3-5278db984cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256799409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4256799409
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.4156916920
Short name T1207
Test name
Test status
Simulation time 12741945 ps
CPU time 0.58 seconds
Started Jul 10 04:44:51 PM PDT 24
Finished Jul 10 04:44:53 PM PDT 24
Peak memory 195000 kb
Host smart-1880a7ef-a4d3-43bb-8b4f-336e652865e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156916920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.4156916920
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.617763233
Short name T66
Test name
Test status
Simulation time 17966575 ps
CPU time 0.72 seconds
Started Jul 10 04:44:48 PM PDT 24
Finished Jul 10 04:44:50 PM PDT 24
Peak memory 197016 kb
Host smart-eae3fb83-ee0d-4528-97bb-b1ff6a9807ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617763233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.617763233
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.93392700
Short name T1226
Test name
Test status
Simulation time 131951815 ps
CPU time 1.59 seconds
Started Jul 10 04:44:22 PM PDT 24
Finished Jul 10 04:44:29 PM PDT 24
Peak memory 198660 kb
Host smart-75bf9096-867a-40fd-8fc8-de673761a44c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93392700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.93392700
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2550604634
Short name T68
Test name
Test status
Simulation time 19357530 ps
CPU time 0.61 seconds
Started Jul 10 04:44:43 PM PDT 24
Finished Jul 10 04:44:45 PM PDT 24
Peak memory 196068 kb
Host smart-395045ef-2946-420b-8d80-3576d5c87a3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550604634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2550604634
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.358299994
Short name T1275
Test name
Test status
Simulation time 113746015 ps
CPU time 0.91 seconds
Started Jul 10 04:51:03 PM PDT 24
Finished Jul 10 04:51:05 PM PDT 24
Peak memory 200564 kb
Host smart-f6d48515-6415-4f41-b8dd-847c4cb56a5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358299994 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.358299994
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2730557811
Short name T1230
Test name
Test status
Simulation time 112535184 ps
CPU time 0.59 seconds
Started Jul 10 04:44:37 PM PDT 24
Finished Jul 10 04:44:39 PM PDT 24
Peak memory 196044 kb
Host smart-98447bd2-245a-49b5-a34b-327cb52354b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730557811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2730557811
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3761718284
Short name T1254
Test name
Test status
Simulation time 24401158 ps
CPU time 0.57 seconds
Started Jul 10 04:44:44 PM PDT 24
Finished Jul 10 04:44:45 PM PDT 24
Peak memory 194960 kb
Host smart-ca02799b-e56b-4145-a036-ac8f160cbf6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761718284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3761718284
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3677784729
Short name T1309
Test name
Test status
Simulation time 18394531 ps
CPU time 0.71 seconds
Started Jul 10 04:44:22 PM PDT 24
Finished Jul 10 04:44:24 PM PDT 24
Peak memory 198264 kb
Host smart-2ff61bc0-9b70-453e-a0b0-af6f50e43dab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677784729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3677784729
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.429625181
Short name T1310
Test name
Test status
Simulation time 74081726 ps
CPU time 1.58 seconds
Started Jul 10 04:44:27 PM PDT 24
Finished Jul 10 04:44:29 PM PDT 24
Peak memory 200724 kb
Host smart-3e227158-e940-4795-9094-cd3c3f88df54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429625181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.429625181
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2651487222
Short name T257
Test name
Test status
Simulation time 63641714 ps
CPU time 1.04 seconds
Started Jul 10 04:44:39 PM PDT 24
Finished Jul 10 04:44:40 PM PDT 24
Peak memory 199912 kb
Host smart-be4bbbc0-ada7-47c0-bca0-d2b9366547ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651487222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2651487222
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1287636948
Short name T1192
Test name
Test status
Simulation time 16527845 ps
CPU time 0.59 seconds
Started Jul 10 04:45:18 PM PDT 24
Finished Jul 10 04:45:21 PM PDT 24
Peak memory 195064 kb
Host smart-5aa8f4bd-0013-4852-b268-22aeeb15cc5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287636948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1287636948
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1037385873
Short name T1289
Test name
Test status
Simulation time 16470651 ps
CPU time 0.57 seconds
Started Jul 10 04:45:12 PM PDT 24
Finished Jul 10 04:45:15 PM PDT 24
Peak memory 195068 kb
Host smart-55a6ea3d-fe5c-4f09-b281-08e0aa0a03e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037385873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1037385873
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1995859507
Short name T1316
Test name
Test status
Simulation time 13862651 ps
CPU time 0.57 seconds
Started Jul 10 04:45:11 PM PDT 24
Finished Jul 10 04:45:15 PM PDT 24
Peak memory 195000 kb
Host smart-8d8c9d7f-7e9b-4a0d-952e-702a3a3ab875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995859507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1995859507
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2308276267
Short name T1205
Test name
Test status
Simulation time 14082916 ps
CPU time 0.58 seconds
Started Jul 10 04:45:12 PM PDT 24
Finished Jul 10 04:45:16 PM PDT 24
Peak memory 195080 kb
Host smart-fbf5ea8b-73ae-4559-ab6d-a0e62c245cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308276267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2308276267
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.449030503
Short name T1251
Test name
Test status
Simulation time 43239309 ps
CPU time 0.62 seconds
Started Jul 10 04:45:13 PM PDT 24
Finished Jul 10 04:45:17 PM PDT 24
Peak memory 195052 kb
Host smart-4eb5c0a4-7305-44b7-99d4-f1f8afdf91fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449030503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.449030503
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3160830339
Short name T1184
Test name
Test status
Simulation time 13943725 ps
CPU time 0.57 seconds
Started Jul 10 04:45:02 PM PDT 24
Finished Jul 10 04:45:03 PM PDT 24
Peak memory 194964 kb
Host smart-364ea0f9-9d9a-4252-af64-1fed949b5429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160830339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3160830339
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2707602819
Short name T1209
Test name
Test status
Simulation time 12498530 ps
CPU time 0.57 seconds
Started Jul 10 04:45:10 PM PDT 24
Finished Jul 10 04:45:14 PM PDT 24
Peak memory 195044 kb
Host smart-531efc26-9a2f-4e5f-924d-5e300a6ed154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707602819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2707602819
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4133366616
Short name T1307
Test name
Test status
Simulation time 18055651 ps
CPU time 0.57 seconds
Started Jul 10 04:45:13 PM PDT 24
Finished Jul 10 04:45:17 PM PDT 24
Peak memory 195068 kb
Host smart-363ca0ab-b260-4b79-a3aa-18e35269b752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133366616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4133366616
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2064218700
Short name T1203
Test name
Test status
Simulation time 80815762 ps
CPU time 0.55 seconds
Started Jul 10 04:45:10 PM PDT 24
Finished Jul 10 04:45:13 PM PDT 24
Peak memory 195080 kb
Host smart-9770f892-6763-4334-b249-cef43c0b3a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064218700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2064218700
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.196286510
Short name T1197
Test name
Test status
Simulation time 32110404 ps
CPU time 0.57 seconds
Started Jul 10 04:44:59 PM PDT 24
Finished Jul 10 04:45:00 PM PDT 24
Peak memory 195036 kb
Host smart-56cfc503-64e0-4161-9426-92157d43a3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196286510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.196286510
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2963008064
Short name T1284
Test name
Test status
Simulation time 17930023 ps
CPU time 0.68 seconds
Started Jul 10 04:44:54 PM PDT 24
Finished Jul 10 04:44:56 PM PDT 24
Peak memory 196152 kb
Host smart-544cba66-034f-4fd4-9e72-73eff906c2af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963008064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2963008064
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2078321175
Short name T1244
Test name
Test status
Simulation time 122837918 ps
CPU time 1.36 seconds
Started Jul 10 04:44:23 PM PDT 24
Finished Jul 10 04:44:26 PM PDT 24
Peak memory 198836 kb
Host smart-b1d196f5-a339-44de-9019-69246c6db33a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078321175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2078321175
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2573217749
Short name T1262
Test name
Test status
Simulation time 38363420 ps
CPU time 0.61 seconds
Started Jul 10 04:44:21 PM PDT 24
Finished Jul 10 04:44:23 PM PDT 24
Peak memory 196076 kb
Host smart-6cab7951-0531-4671-8d61-70589aa8f196
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573217749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2573217749
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3858519077
Short name T1279
Test name
Test status
Simulation time 94198257 ps
CPU time 0.85 seconds
Started Jul 10 04:44:40 PM PDT 24
Finished Jul 10 04:44:42 PM PDT 24
Peak memory 200452 kb
Host smart-9fa882be-3c15-415e-835f-2d144720d13a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858519077 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3858519077
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1328925477
Short name T1269
Test name
Test status
Simulation time 35626139 ps
CPU time 0.6 seconds
Started Jul 10 04:44:24 PM PDT 24
Finished Jul 10 04:44:26 PM PDT 24
Peak memory 196148 kb
Host smart-2990b3ac-6eb2-491a-b4e4-28464a9269b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328925477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1328925477
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2933320684
Short name T1214
Test name
Test status
Simulation time 13774830 ps
CPU time 0.58 seconds
Started Jul 10 04:44:30 PM PDT 24
Finished Jul 10 04:44:31 PM PDT 24
Peak memory 195068 kb
Host smart-19eaa9ce-86a5-4b95-be0b-d62c2b21d1b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933320684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2933320684
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2066896967
Short name T1264
Test name
Test status
Simulation time 86472488 ps
CPU time 0.75 seconds
Started Jul 10 04:44:47 PM PDT 24
Finished Jul 10 04:44:49 PM PDT 24
Peak memory 197748 kb
Host smart-c2aa1059-2e94-420a-ba77-7158a987e5c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066896967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2066896967
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.409383704
Short name T1306
Test name
Test status
Simulation time 474257491 ps
CPU time 1.84 seconds
Started Jul 10 04:44:32 PM PDT 24
Finished Jul 10 04:44:39 PM PDT 24
Peak memory 200656 kb
Host smart-8cf66025-8b9b-4ad5-9206-237cdbf54e04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409383704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.409383704
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2192689573
Short name T97
Test name
Test status
Simulation time 1179969834 ps
CPU time 1.2 seconds
Started Jul 10 04:44:46 PM PDT 24
Finished Jul 10 04:44:48 PM PDT 24
Peak memory 200004 kb
Host smart-c121f82f-5316-4b82-a1ab-b34169ada1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192689573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2192689573
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1914637429
Short name T1290
Test name
Test status
Simulation time 13175810 ps
CPU time 0.57 seconds
Started Jul 10 04:45:11 PM PDT 24
Finished Jul 10 04:45:14 PM PDT 24
Peak memory 195064 kb
Host smart-77423cb5-1ae9-437d-ad0f-e1ca773aa55a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914637429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1914637429
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1633812791
Short name T1245
Test name
Test status
Simulation time 70225363 ps
CPU time 0.61 seconds
Started Jul 10 04:45:11 PM PDT 24
Finished Jul 10 04:45:14 PM PDT 24
Peak memory 195044 kb
Host smart-7208068b-6976-43f1-ab2d-8a9bf3f7ed05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633812791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1633812791
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3180723759
Short name T1261
Test name
Test status
Simulation time 15973341 ps
CPU time 0.56 seconds
Started Jul 10 04:45:00 PM PDT 24
Finished Jul 10 04:45:01 PM PDT 24
Peak memory 195056 kb
Host smart-8d269d44-28f5-4378-89cf-65b5a67a3aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180723759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3180723759
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2962491355
Short name T1204
Test name
Test status
Simulation time 91737384 ps
CPU time 0.53 seconds
Started Jul 10 04:45:04 PM PDT 24
Finished Jul 10 04:45:06 PM PDT 24
Peak memory 195052 kb
Host smart-bf88534b-0f98-43c4-8fb8-e3c13b329293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962491355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2962491355
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1199247556
Short name T1232
Test name
Test status
Simulation time 15420359 ps
CPU time 0.57 seconds
Started Jul 10 04:45:15 PM PDT 24
Finished Jul 10 04:45:19 PM PDT 24
Peak memory 194992 kb
Host smart-16532be6-7436-459d-8cf6-d75499eebef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199247556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1199247556
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2134578147
Short name T1253
Test name
Test status
Simulation time 16386444 ps
CPU time 0.57 seconds
Started Jul 10 04:45:07 PM PDT 24
Finished Jul 10 04:45:08 PM PDT 24
Peak memory 195052 kb
Host smart-3c5d7e3a-3c9b-4b72-a841-1a01680092ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134578147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2134578147
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2512456466
Short name T1276
Test name
Test status
Simulation time 12121896 ps
CPU time 0.64 seconds
Started Jul 10 04:44:50 PM PDT 24
Finished Jul 10 04:44:52 PM PDT 24
Peak memory 195068 kb
Host smart-7f3ac026-7d08-4199-b450-4c2bb168ac53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512456466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2512456466
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.387938307
Short name T1249
Test name
Test status
Simulation time 16998551 ps
CPU time 0.56 seconds
Started Jul 10 04:45:11 PM PDT 24
Finished Jul 10 04:45:15 PM PDT 24
Peak memory 195088 kb
Host smart-2bda7376-2774-4ca8-8c15-03ca12829b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387938307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.387938307
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.878768154
Short name T1308
Test name
Test status
Simulation time 52128045 ps
CPU time 0.58 seconds
Started Jul 10 04:45:08 PM PDT 24
Finished Jul 10 04:45:10 PM PDT 24
Peak memory 195064 kb
Host smart-f02ab291-b642-415c-a443-7b221339438b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878768154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.878768154
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.194050157
Short name T1216
Test name
Test status
Simulation time 14955333 ps
CPU time 0.54 seconds
Started Jul 10 04:45:02 PM PDT 24
Finished Jul 10 04:45:04 PM PDT 24
Peak memory 194996 kb
Host smart-7289aed3-e8a2-4b6c-9b1e-c6997e4e607e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194050157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.194050157
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2595607911
Short name T1293
Test name
Test status
Simulation time 46988933 ps
CPU time 0.77 seconds
Started Jul 10 04:44:42 PM PDT 24
Finished Jul 10 04:44:44 PM PDT 24
Peak memory 199424 kb
Host smart-bcb473da-212b-4c99-a17c-a0b91c4654c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595607911 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2595607911
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.83948832
Short name T1229
Test name
Test status
Simulation time 25440230 ps
CPU time 0.59 seconds
Started Jul 10 04:44:40 PM PDT 24
Finished Jul 10 04:44:42 PM PDT 24
Peak memory 196048 kb
Host smart-7492b44e-d479-4ad5-aac3-f544b35dd1df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83948832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.83948832
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3162967396
Short name T1287
Test name
Test status
Simulation time 128570265 ps
CPU time 0.58 seconds
Started Jul 10 04:44:47 PM PDT 24
Finished Jul 10 04:44:48 PM PDT 24
Peak memory 194980 kb
Host smart-f21ac2ec-a41a-4945-99b3-b97e8b91627c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162967396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3162967396
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3741182083
Short name T1283
Test name
Test status
Simulation time 58446091 ps
CPU time 0.64 seconds
Started Jul 10 04:44:44 PM PDT 24
Finished Jul 10 04:44:46 PM PDT 24
Peak memory 195124 kb
Host smart-f15d8880-669b-468b-8708-2b2b371680e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741182083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3741182083
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.49160315
Short name T1272
Test name
Test status
Simulation time 37028689 ps
CPU time 1.85 seconds
Started Jul 10 04:44:44 PM PDT 24
Finished Jul 10 04:44:46 PM PDT 24
Peak memory 200692 kb
Host smart-df38ad1c-6058-488f-8c49-408d0a5736ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49160315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.49160315
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.466586981
Short name T89
Test name
Test status
Simulation time 606365572 ps
CPU time 1.39 seconds
Started Jul 10 04:44:51 PM PDT 24
Finished Jul 10 04:44:54 PM PDT 24
Peak memory 199936 kb
Host smart-e0527687-1c6f-49cb-86ed-b9caff38653d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466586981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.466586981
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3990308327
Short name T1265
Test name
Test status
Simulation time 24286173 ps
CPU time 1.18 seconds
Started Jul 10 04:44:38 PM PDT 24
Finished Jul 10 04:44:40 PM PDT 24
Peak memory 201012 kb
Host smart-fa376629-55c7-4e4f-a0a8-0804d8063b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990308327 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3990308327
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4083947581
Short name T64
Test name
Test status
Simulation time 25701057 ps
CPU time 0.55 seconds
Started Jul 10 04:44:55 PM PDT 24
Finished Jul 10 04:44:57 PM PDT 24
Peak memory 195952 kb
Host smart-47f6c1dc-d698-4187-b129-8d367270d2d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083947581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4083947581
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2524727479
Short name T1258
Test name
Test status
Simulation time 14245399 ps
CPU time 0.53 seconds
Started Jul 10 04:44:50 PM PDT 24
Finished Jul 10 04:44:51 PM PDT 24
Peak memory 195004 kb
Host smart-70622081-e5f4-4d46-85ac-cb7b6b6c315f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524727479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2524727479
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2746789176
Short name T1221
Test name
Test status
Simulation time 99796334 ps
CPU time 0.79 seconds
Started Jul 10 04:44:45 PM PDT 24
Finished Jul 10 04:44:47 PM PDT 24
Peak memory 197852 kb
Host smart-d12ec381-ce60-4431-9216-f2ce1c2baaff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746789176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2746789176
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.245398875
Short name T1250
Test name
Test status
Simulation time 144601494 ps
CPU time 2.21 seconds
Started Jul 10 04:44:54 PM PDT 24
Finished Jul 10 04:44:57 PM PDT 24
Peak memory 200712 kb
Host smart-3ac5b4fc-482e-4a82-9ed2-2f92e60e008d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245398875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.245398875
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1399804071
Short name T1266
Test name
Test status
Simulation time 20909023 ps
CPU time 0.99 seconds
Started Jul 10 04:44:37 PM PDT 24
Finished Jul 10 04:44:39 PM PDT 24
Peak memory 200488 kb
Host smart-4b87b75b-dc63-47df-81f9-62397c0e2b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399804071 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1399804071
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4017797063
Short name T1291
Test name
Test status
Simulation time 43257324 ps
CPU time 0.62 seconds
Started Jul 10 04:45:05 PM PDT 24
Finished Jul 10 04:45:06 PM PDT 24
Peak memory 196208 kb
Host smart-ae7241f2-4829-4a53-9ccd-a78ad0af6898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017797063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4017797063
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2320049176
Short name T1191
Test name
Test status
Simulation time 75037852 ps
CPU time 0.58 seconds
Started Jul 10 04:44:51 PM PDT 24
Finished Jul 10 04:44:53 PM PDT 24
Peak memory 195052 kb
Host smart-8a3d01f7-cb1c-40d9-aa21-6c6ac6664ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320049176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2320049176
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1171534941
Short name T1223
Test name
Test status
Simulation time 67475388 ps
CPU time 0.62 seconds
Started Jul 10 04:44:57 PM PDT 24
Finished Jul 10 04:44:58 PM PDT 24
Peak memory 196044 kb
Host smart-53f7eaf0-9487-4950-a748-f24169d60fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171534941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1171534941
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4249215621
Short name T1212
Test name
Test status
Simulation time 390459250 ps
CPU time 2.04 seconds
Started Jul 10 04:45:05 PM PDT 24
Finished Jul 10 04:45:08 PM PDT 24
Peak memory 200636 kb
Host smart-1b8f3aef-9081-41fb-9b70-3a72af217a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249215621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4249215621
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1230641899
Short name T1298
Test name
Test status
Simulation time 255316818 ps
CPU time 1.31 seconds
Started Jul 10 04:44:56 PM PDT 24
Finished Jul 10 04:44:58 PM PDT 24
Peak memory 199988 kb
Host smart-dcf77348-f22a-4701-af4a-0583ae8e2000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230641899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1230641899
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1352963408
Short name T1299
Test name
Test status
Simulation time 49429175 ps
CPU time 0.66 seconds
Started Jul 10 04:45:04 PM PDT 24
Finished Jul 10 04:45:05 PM PDT 24
Peak memory 198824 kb
Host smart-6681974f-b2ef-4589-9536-7ecb293afc0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352963408 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1352963408
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.901048153
Short name T80
Test name
Test status
Simulation time 33331031 ps
CPU time 0.61 seconds
Started Jul 10 04:44:41 PM PDT 24
Finished Jul 10 04:44:43 PM PDT 24
Peak memory 196368 kb
Host smart-cd7689bc-d3b2-4ad1-9424-c38df0c34553
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901048153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.901048153
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1734793623
Short name T1225
Test name
Test status
Simulation time 32415033 ps
CPU time 0.56 seconds
Started Jul 10 04:44:48 PM PDT 24
Finished Jul 10 04:44:50 PM PDT 24
Peak memory 194956 kb
Host smart-4ff613c7-d08b-43fc-8467-f2dfd645bcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734793623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1734793623
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1021986486
Short name T86
Test name
Test status
Simulation time 20395527 ps
CPU time 0.67 seconds
Started Jul 10 04:44:47 PM PDT 24
Finished Jul 10 04:44:48 PM PDT 24
Peak memory 196432 kb
Host smart-56373997-d61b-4ee4-93e3-5a3bd80dffba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021986486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1021986486
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.962154613
Short name T1187
Test name
Test status
Simulation time 87308912 ps
CPU time 1.57 seconds
Started Jul 10 04:44:43 PM PDT 24
Finished Jul 10 04:44:46 PM PDT 24
Peak memory 200728 kb
Host smart-0ebf610e-f060-4b6b-a4a2-28bd449899b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962154613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.962154613
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.312599081
Short name T1315
Test name
Test status
Simulation time 50557334 ps
CPU time 0.97 seconds
Started Jul 10 04:44:48 PM PDT 24
Finished Jul 10 04:44:50 PM PDT 24
Peak memory 199628 kb
Host smart-9649d8b3-9f68-4fee-baf3-102409f294c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312599081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.312599081
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2786760422
Short name T1271
Test name
Test status
Simulation time 23344930 ps
CPU time 0.99 seconds
Started Jul 10 04:44:52 PM PDT 24
Finished Jul 10 04:44:54 PM PDT 24
Peak memory 200428 kb
Host smart-1abd000e-4f2e-4245-b3f0-622a303464ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786760422 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2786760422
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3272588593
Short name T1255
Test name
Test status
Simulation time 37974122 ps
CPU time 0.61 seconds
Started Jul 10 04:45:00 PM PDT 24
Finished Jul 10 04:45:01 PM PDT 24
Peak memory 196056 kb
Host smart-2e30c1ac-f595-4a7a-9d63-e36a53d79e70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272588593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3272588593
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.4027946414
Short name T1201
Test name
Test status
Simulation time 42151513 ps
CPU time 0.55 seconds
Started Jul 10 04:44:52 PM PDT 24
Finished Jul 10 04:44:54 PM PDT 24
Peak memory 195032 kb
Host smart-6a3ca4be-2164-4141-a28f-2ad59e31d8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027946414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.4027946414
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2651019531
Short name T1274
Test name
Test status
Simulation time 32246934 ps
CPU time 0.72 seconds
Started Jul 10 04:44:50 PM PDT 24
Finished Jul 10 04:44:52 PM PDT 24
Peak memory 198332 kb
Host smart-e6f23b11-8905-4451-bfd2-5599d3f56289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651019531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2651019531
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3928239583
Short name T1285
Test name
Test status
Simulation time 131773315 ps
CPU time 2.32 seconds
Started Jul 10 04:45:02 PM PDT 24
Finished Jul 10 04:45:06 PM PDT 24
Peak memory 200720 kb
Host smart-9872f497-c26a-4bb7-a345-9b89d3067e67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928239583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3928239583
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2355004987
Short name T1257
Test name
Test status
Simulation time 189257804 ps
CPU time 1.33 seconds
Started Jul 10 04:44:47 PM PDT 24
Finished Jul 10 04:44:49 PM PDT 24
Peak memory 200320 kb
Host smart-6218bbdb-0990-4b23-aa43-b3fcd272e2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355004987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2355004987
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3753039356
Short name T405
Test name
Test status
Simulation time 8991327621 ps
CPU time 5.34 seconds
Started Jul 10 04:51:28 PM PDT 24
Finished Jul 10 04:51:34 PM PDT 24
Peak memory 199556 kb
Host smart-4b65203f-834c-4480-a6ad-5c77e2a472e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753039356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3753039356
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3486211514
Short name T127
Test name
Test status
Simulation time 61575315408 ps
CPU time 27.32 seconds
Started Jul 10 04:51:27 PM PDT 24
Finished Jul 10 04:51:56 PM PDT 24
Peak memory 199780 kb
Host smart-516a2cec-b95d-43f5-a71e-0e6ac1f49547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486211514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3486211514
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1087021597
Short name T101
Test name
Test status
Simulation time 46234445241 ps
CPU time 61.39 seconds
Started Jul 10 04:51:26 PM PDT 24
Finished Jul 10 04:52:29 PM PDT 24
Peak memory 199804 kb
Host smart-e99bb184-d700-4fc1-8706-221b77d816d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087021597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1087021597
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3438300113
Short name T815
Test name
Test status
Simulation time 41474864503 ps
CPU time 15.1 seconds
Started Jul 10 04:51:30 PM PDT 24
Finished Jul 10 04:51:46 PM PDT 24
Peak memory 199700 kb
Host smart-ff50b816-310b-4f10-86ea-9719d73fcd6c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438300113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3438300113
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.408387533
Short name T860
Test name
Test status
Simulation time 98535133710 ps
CPU time 246.32 seconds
Started Jul 10 04:51:34 PM PDT 24
Finished Jul 10 04:55:41 PM PDT 24
Peak memory 199812 kb
Host smart-4f6da1e4-1924-4bd2-baf8-b9ce9f570cb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408387533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.408387533
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2474644497
Short name T382
Test name
Test status
Simulation time 6807511799 ps
CPU time 7.81 seconds
Started Jul 10 04:51:34 PM PDT 24
Finished Jul 10 04:51:43 PM PDT 24
Peak memory 198860 kb
Host smart-4d47ab8c-c493-4e3c-a934-b75e47e260fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474644497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2474644497
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3538987178
Short name T939
Test name
Test status
Simulation time 101675639896 ps
CPU time 37.96 seconds
Started Jul 10 04:51:32 PM PDT 24
Finished Jul 10 04:52:11 PM PDT 24
Peak memory 200008 kb
Host smart-a0906df0-cc2b-47d2-8804-7315e63b430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538987178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3538987178
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1339450327
Short name T796
Test name
Test status
Simulation time 7962804635 ps
CPU time 212.32 seconds
Started Jul 10 04:51:33 PM PDT 24
Finished Jul 10 04:55:07 PM PDT 24
Peak memory 199684 kb
Host smart-be2cd5be-b38b-4c53-9aab-acf764396648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339450327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1339450327
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2876844406
Short name T511
Test name
Test status
Simulation time 5840393132 ps
CPU time 52.6 seconds
Started Jul 10 04:51:33 PM PDT 24
Finished Jul 10 04:52:27 PM PDT 24
Peak memory 198088 kb
Host smart-419f25ac-c39d-4d2b-8b5a-a1a093ff93d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876844406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2876844406
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1486131270
Short name T262
Test name
Test status
Simulation time 62833862665 ps
CPU time 104.45 seconds
Started Jul 10 04:51:33 PM PDT 24
Finished Jul 10 04:53:19 PM PDT 24
Peak memory 199768 kb
Host smart-45a3c4bf-8607-46af-a76f-89518a3f5aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486131270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1486131270
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3783556429
Short name T539
Test name
Test status
Simulation time 3926526457 ps
CPU time 3.84 seconds
Started Jul 10 04:51:33 PM PDT 24
Finished Jul 10 04:51:38 PM PDT 24
Peak memory 196144 kb
Host smart-7f279d1f-b8ac-482c-b8b9-68bceb70d289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783556429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3783556429
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.990618946
Short name T936
Test name
Test status
Simulation time 245260229 ps
CPU time 1.28 seconds
Started Jul 10 04:51:27 PM PDT 24
Finished Jul 10 04:51:30 PM PDT 24
Peak memory 198340 kb
Host smart-aef9f556-8606-4c59-b669-0a1bd92eec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990618946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.990618946
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.583754130
Short name T615
Test name
Test status
Simulation time 195689476551 ps
CPU time 434.7 seconds
Started Jul 10 04:51:32 PM PDT 24
Finished Jul 10 04:58:48 PM PDT 24
Peak memory 199816 kb
Host smart-bacf0537-e79d-4607-ab0a-a4faec876d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583754130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.583754130
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2265259946
Short name T343
Test name
Test status
Simulation time 50576082902 ps
CPU time 584.44 seconds
Started Jul 10 04:51:33 PM PDT 24
Finished Jul 10 05:01:19 PM PDT 24
Peak memory 224676 kb
Host smart-3a53c29c-72af-41a1-8bff-5b4ef6952935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265259946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2265259946
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2938910456
Short name T981
Test name
Test status
Simulation time 2923933599 ps
CPU time 2.16 seconds
Started Jul 10 04:51:33 PM PDT 24
Finished Jul 10 04:51:36 PM PDT 24
Peak memory 198252 kb
Host smart-de3610cf-dc75-4860-873a-e355fdecffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938910456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2938910456
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2691022374
Short name T793
Test name
Test status
Simulation time 87539967078 ps
CPU time 26.95 seconds
Started Jul 10 04:51:26 PM PDT 24
Finished Jul 10 04:51:54 PM PDT 24
Peak memory 199788 kb
Host smart-994a5a35-e582-45c8-b504-80f9d794f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691022374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2691022374
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1722682326
Short name T653
Test name
Test status
Simulation time 13778940 ps
CPU time 0.58 seconds
Started Jul 10 04:51:38 PM PDT 24
Finished Jul 10 04:51:40 PM PDT 24
Peak memory 195152 kb
Host smart-5dfe0dc2-4469-4f5b-b07f-d079d296408a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722682326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1722682326
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1106679195
Short name T1033
Test name
Test status
Simulation time 48822384803 ps
CPU time 39.94 seconds
Started Jul 10 04:51:35 PM PDT 24
Finished Jul 10 04:52:16 PM PDT 24
Peak memory 199804 kb
Host smart-7ccc3179-228f-41d2-8ce1-73fe0ffbe2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106679195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1106679195
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.218722429
Short name T1137
Test name
Test status
Simulation time 211836627290 ps
CPU time 85.52 seconds
Started Jul 10 04:51:37 PM PDT 24
Finished Jul 10 04:53:04 PM PDT 24
Peak memory 199732 kb
Host smart-50ac8745-07ac-411c-975a-88d6f37f52c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218722429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.218722429
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1283407167
Short name T142
Test name
Test status
Simulation time 89081550336 ps
CPU time 18.26 seconds
Started Jul 10 04:51:37 PM PDT 24
Finished Jul 10 04:51:56 PM PDT 24
Peak memory 199788 kb
Host smart-35f7a247-01ca-4453-aed2-6db39bb9f87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283407167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1283407167
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3781379052
Short name T386
Test name
Test status
Simulation time 31153102105 ps
CPU time 49.42 seconds
Started Jul 10 04:51:39 PM PDT 24
Finished Jul 10 04:52:30 PM PDT 24
Peak memory 199796 kb
Host smart-52777cf4-280b-46c2-afc0-d6a58c82a599
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781379052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3781379052
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1064402526
Short name T562
Test name
Test status
Simulation time 25361412493 ps
CPU time 137.45 seconds
Started Jul 10 04:51:41 PM PDT 24
Finished Jul 10 04:53:59 PM PDT 24
Peak memory 199816 kb
Host smart-f086ce71-9175-4161-b824-d17b1c1602a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064402526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1064402526
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1882195420
Short name T1167
Test name
Test status
Simulation time 5974026662 ps
CPU time 3.21 seconds
Started Jul 10 04:51:43 PM PDT 24
Finished Jul 10 04:51:47 PM PDT 24
Peak memory 199236 kb
Host smart-7a6b5470-38fd-4f64-9afb-dd0309a26882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882195420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1882195420
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.4154328653
Short name T1136
Test name
Test status
Simulation time 32836120239 ps
CPU time 14.78 seconds
Started Jul 10 04:51:40 PM PDT 24
Finished Jul 10 04:51:56 PM PDT 24
Peak memory 199744 kb
Host smart-4626f764-3bd5-4cd7-81fd-3cbd15b4dc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154328653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4154328653
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3207766543
Short name T682
Test name
Test status
Simulation time 21080930150 ps
CPU time 940.39 seconds
Started Jul 10 04:51:37 PM PDT 24
Finished Jul 10 05:07:18 PM PDT 24
Peak memory 199728 kb
Host smart-600368aa-7067-4bad-8ca2-9aa866de2a29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207766543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3207766543
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.189676450
Short name T840
Test name
Test status
Simulation time 4937890070 ps
CPU time 9.17 seconds
Started Jul 10 04:51:39 PM PDT 24
Finished Jul 10 04:51:50 PM PDT 24
Peak memory 198088 kb
Host smart-4a9018ad-92af-4453-970c-6ae8fad0e4c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189676450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.189676450
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2026528481
Short name T784
Test name
Test status
Simulation time 103436299787 ps
CPU time 91.01 seconds
Started Jul 10 04:51:36 PM PDT 24
Finished Jul 10 04:53:08 PM PDT 24
Peak memory 199700 kb
Host smart-5e97efe1-9da1-4c8a-b2f0-60bac7bf22ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026528481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2026528481
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.649452879
Short name T347
Test name
Test status
Simulation time 695235592 ps
CPU time 1.17 seconds
Started Jul 10 04:51:39 PM PDT 24
Finished Jul 10 04:51:42 PM PDT 24
Peak memory 195248 kb
Host smart-2a33b9d2-0f97-4c41-a063-274ce5ffaa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649452879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.649452879
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4190391907
Short name T99
Test name
Test status
Simulation time 271108204 ps
CPU time 0.82 seconds
Started Jul 10 04:51:40 PM PDT 24
Finished Jul 10 04:51:42 PM PDT 24
Peak memory 217400 kb
Host smart-4eee1153-785a-4acf-90c8-2b50a8654107
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190391907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4190391907
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1974955768
Short name T940
Test name
Test status
Simulation time 674297551 ps
CPU time 1.66 seconds
Started Jul 10 04:51:33 PM PDT 24
Finished Jul 10 04:51:36 PM PDT 24
Peak memory 199712 kb
Host smart-588b9fd5-38d0-4a7a-a8f3-00b6307f82fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974955768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1974955768
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2973050000
Short name T1073
Test name
Test status
Simulation time 183841195998 ps
CPU time 1266.94 seconds
Started Jul 10 04:51:40 PM PDT 24
Finished Jul 10 05:12:49 PM PDT 24
Peak memory 198872 kb
Host smart-4dcaa7e6-70b8-41b8-a3b6-23b00c4447f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973050000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2973050000
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.4214238425
Short name T414
Test name
Test status
Simulation time 21982010604 ps
CPU time 184.99 seconds
Started Jul 10 04:51:40 PM PDT 24
Finished Jul 10 04:54:46 PM PDT 24
Peak memory 215948 kb
Host smart-84c73bbf-d1b3-4550-b4dd-4f832f0f411a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214238425 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.4214238425
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.66082675
Short name T374
Test name
Test status
Simulation time 3022466226 ps
CPU time 1.66 seconds
Started Jul 10 04:51:42 PM PDT 24
Finished Jul 10 04:51:44 PM PDT 24
Peak memory 198064 kb
Host smart-6f8f25ed-dbc4-4890-b61a-d0f965f462bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66082675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.66082675
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4059306951
Short name T717
Test name
Test status
Simulation time 47362511764 ps
CPU time 31.34 seconds
Started Jul 10 04:51:31 PM PDT 24
Finished Jul 10 04:52:04 PM PDT 24
Peak memory 199716 kb
Host smart-24abbfef-15fc-49e7-b95b-4ff02cd7fd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059306951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4059306951
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2784190979
Short name T459
Test name
Test status
Simulation time 13998837 ps
CPU time 0.56 seconds
Started Jul 10 04:52:50 PM PDT 24
Finished Jul 10 04:52:51 PM PDT 24
Peak memory 194476 kb
Host smart-82cc7d5f-d759-4dbe-a9c4-07f38ca2f42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784190979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2784190979
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2848063179
Short name T928
Test name
Test status
Simulation time 63896475601 ps
CPU time 80.58 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:54:03 PM PDT 24
Peak memory 199800 kb
Host smart-8dbd4069-8b20-405c-910d-bfa76e73d898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848063179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2848063179
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3193126968
Short name T903
Test name
Test status
Simulation time 240768321077 ps
CPU time 22.97 seconds
Started Jul 10 04:52:39 PM PDT 24
Finished Jul 10 04:53:03 PM PDT 24
Peak memory 199584 kb
Host smart-9c2695c4-3135-4c4f-8220-51196ce15289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193126968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3193126968
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2532549672
Short name T455
Test name
Test status
Simulation time 127254517863 ps
CPU time 40.7 seconds
Started Jul 10 04:52:49 PM PDT 24
Finished Jul 10 04:53:30 PM PDT 24
Peak memory 199836 kb
Host smart-5b5bda05-3921-40f6-a2d3-4ee5aec15ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532549672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2532549672
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2483918474
Short name T1022
Test name
Test status
Simulation time 38341823458 ps
CPU time 68.13 seconds
Started Jul 10 04:52:49 PM PDT 24
Finished Jul 10 04:53:58 PM PDT 24
Peak memory 199800 kb
Host smart-cb526f47-321d-4e9d-8344-5c9d83293d85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483918474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2483918474
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.4039244259
Short name T1069
Test name
Test status
Simulation time 88187109640 ps
CPU time 314.68 seconds
Started Jul 10 04:52:49 PM PDT 24
Finished Jul 10 04:58:04 PM PDT 24
Peak memory 199820 kb
Host smart-c2159de0-54b5-4c37-860a-4ce8b2384b6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039244259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4039244259
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3424556843
Short name T656
Test name
Test status
Simulation time 6151703751 ps
CPU time 6.67 seconds
Started Jul 10 04:52:49 PM PDT 24
Finished Jul 10 04:52:56 PM PDT 24
Peak memory 199340 kb
Host smart-d52ac86c-ca70-4c43-9956-d16c59362cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424556843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3424556843
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.575720632
Short name T960
Test name
Test status
Simulation time 44527160461 ps
CPU time 68.01 seconds
Started Jul 10 04:52:49 PM PDT 24
Finished Jul 10 04:53:57 PM PDT 24
Peak memory 200032 kb
Host smart-8f1e6e6b-b3c3-4644-aed7-5c900e928903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575720632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.575720632
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.901157754
Short name T690
Test name
Test status
Simulation time 29400507919 ps
CPU time 226.9 seconds
Started Jul 10 04:52:48 PM PDT 24
Finished Jul 10 04:56:36 PM PDT 24
Peak memory 199712 kb
Host smart-ccade3ae-008c-4e6f-9f87-5bdc0fbffbab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901157754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.901157754
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2521159590
Short name T983
Test name
Test status
Simulation time 5110186264 ps
CPU time 11.14 seconds
Started Jul 10 04:52:51 PM PDT 24
Finished Jul 10 04:53:04 PM PDT 24
Peak memory 199072 kb
Host smart-cce4f1be-9f82-4626-9133-d8e16c7cd91c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521159590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2521159590
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3135822895
Short name T583
Test name
Test status
Simulation time 240596425784 ps
CPU time 107.03 seconds
Started Jul 10 04:52:48 PM PDT 24
Finished Jul 10 04:54:36 PM PDT 24
Peak memory 199748 kb
Host smart-2ab6880c-68c8-47c6-8608-377215fd4c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135822895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3135822895
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2049240061
Short name T634
Test name
Test status
Simulation time 6599097738 ps
CPU time 10.71 seconds
Started Jul 10 04:52:51 PM PDT 24
Finished Jul 10 04:53:03 PM PDT 24
Peak memory 195880 kb
Host smart-ae91b86c-03ee-416d-92ac-052e48958dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049240061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2049240061
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2836927729
Short name T601
Test name
Test status
Simulation time 317312419 ps
CPU time 1.02 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:52:44 PM PDT 24
Peak memory 198216 kb
Host smart-db7ce67f-9cb7-466e-b219-f606a2043665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836927729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2836927729
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2055397252
Short name T800
Test name
Test status
Simulation time 420613478078 ps
CPU time 129.61 seconds
Started Jul 10 04:52:48 PM PDT 24
Finished Jul 10 04:54:58 PM PDT 24
Peak memory 208228 kb
Host smart-f9800fa4-1b08-4922-9a1d-012de7a3fd3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055397252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2055397252
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.598396339
Short name T352
Test name
Test status
Simulation time 239758077684 ps
CPU time 1195.28 seconds
Started Jul 10 04:52:48 PM PDT 24
Finished Jul 10 05:12:44 PM PDT 24
Peak memory 216812 kb
Host smart-ce59cfcb-8aeb-4d38-a1b8-42d304b4e13b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598396339 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.598396339
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3880943067
Short name T11
Test name
Test status
Simulation time 7483909803 ps
CPU time 9.21 seconds
Started Jul 10 04:52:49 PM PDT 24
Finished Jul 10 04:52:59 PM PDT 24
Peak memory 199808 kb
Host smart-de983607-0d3d-4fc1-8105-9f411e0a1661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880943067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3880943067
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.998342566
Short name T318
Test name
Test status
Simulation time 120500939204 ps
CPU time 48.98 seconds
Started Jul 10 04:58:33 PM PDT 24
Finished Jul 10 04:59:23 PM PDT 24
Peak memory 199784 kb
Host smart-2adb3469-7630-4567-a8ca-06091e079198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998342566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.998342566
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3493926588
Short name T614
Test name
Test status
Simulation time 86466301883 ps
CPU time 35.5 seconds
Started Jul 10 04:58:33 PM PDT 24
Finished Jul 10 04:59:09 PM PDT 24
Peak memory 199620 kb
Host smart-baf0d34b-6bcd-4da5-89ae-e49d1ae771ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493926588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3493926588
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1771773682
Short name T1072
Test name
Test status
Simulation time 109096335618 ps
CPU time 30.05 seconds
Started Jul 10 04:58:34 PM PDT 24
Finished Jul 10 04:59:06 PM PDT 24
Peak memory 199820 kb
Host smart-2e336f6b-ec95-45b8-ab2a-12f2553bde91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771773682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1771773682
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2364736920
Short name T167
Test name
Test status
Simulation time 119554434619 ps
CPU time 180.69 seconds
Started Jul 10 04:58:42 PM PDT 24
Finished Jul 10 05:01:44 PM PDT 24
Peak memory 199360 kb
Host smart-ee6be1c5-1a5f-4d15-8e1a-b6fef47c5dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364736920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2364736920
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2500753815
Short name T560
Test name
Test status
Simulation time 17698428457 ps
CPU time 20.12 seconds
Started Jul 10 04:58:40 PM PDT 24
Finished Jul 10 04:59:02 PM PDT 24
Peak memory 199780 kb
Host smart-0c384609-8688-448c-8b20-9facfa048bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500753815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2500753815
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2889292269
Short name T466
Test name
Test status
Simulation time 75551547213 ps
CPU time 59.97 seconds
Started Jul 10 04:58:42 PM PDT 24
Finished Jul 10 04:59:43 PM PDT 24
Peak memory 199844 kb
Host smart-fad8524b-907e-4f5e-a824-234ceba9cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889292269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2889292269
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1751328463
Short name T1160
Test name
Test status
Simulation time 70518050071 ps
CPU time 42.21 seconds
Started Jul 10 04:58:43 PM PDT 24
Finished Jul 10 04:59:27 PM PDT 24
Peak memory 199828 kb
Host smart-808aa4fe-6e8c-4a5b-8d33-49ef2010a514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751328463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1751328463
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3834229733
Short name T1061
Test name
Test status
Simulation time 23318002708 ps
CPU time 37.96 seconds
Started Jul 10 04:58:42 PM PDT 24
Finished Jul 10 04:59:21 PM PDT 24
Peak memory 199720 kb
Host smart-66e3810e-8737-4612-ac2c-21ca2d60ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834229733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3834229733
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3483972906
Short name T356
Test name
Test status
Simulation time 42054623127 ps
CPU time 51.4 seconds
Started Jul 10 04:58:41 PM PDT 24
Finished Jul 10 04:59:34 PM PDT 24
Peak memory 199808 kb
Host smart-efd9cc33-5a85-4ab0-bbf5-21393faab789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483972906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3483972906
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2644442445
Short name T588
Test name
Test status
Simulation time 12530414 ps
CPU time 0.57 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:53:00 PM PDT 24
Peak memory 195436 kb
Host smart-2f6f6748-0352-4ef8-9f48-e04592becaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644442445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2644442445
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1130710345
Short name T778
Test name
Test status
Simulation time 102913639230 ps
CPU time 53.58 seconds
Started Jul 10 04:52:51 PM PDT 24
Finished Jul 10 04:53:46 PM PDT 24
Peak memory 199764 kb
Host smart-86c50dc5-0c3d-4816-8980-021fb4553215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130710345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1130710345
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2770715462
Short name T564
Test name
Test status
Simulation time 135596846857 ps
CPU time 246.96 seconds
Started Jul 10 04:53:00 PM PDT 24
Finished Jul 10 04:57:08 PM PDT 24
Peak memory 199828 kb
Host smart-5962b3b4-f061-4d73-91bc-6ba7f0f8d1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770715462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2770715462
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.1269402175
Short name T387
Test name
Test status
Simulation time 34789660312 ps
CPU time 18.02 seconds
Started Jul 10 04:52:59 PM PDT 24
Finished Jul 10 04:53:19 PM PDT 24
Peak memory 199772 kb
Host smart-0b2d0b85-6292-4e3b-b7b7-5106a2a12ae3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269402175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1269402175
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1667351836
Short name T41
Test name
Test status
Simulation time 114746125044 ps
CPU time 314.66 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:58:13 PM PDT 24
Peak memory 199760 kb
Host smart-400bcddc-b7e8-4522-8bde-93d593e0dcde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667351836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1667351836
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.912380401
Short name T357
Test name
Test status
Simulation time 8322803589 ps
CPU time 17.2 seconds
Started Jul 10 04:52:59 PM PDT 24
Finished Jul 10 04:53:18 PM PDT 24
Peak memory 199776 kb
Host smart-29e48589-2e9a-4d04-92ad-a4b5d44e5ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912380401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.912380401
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2044042805
Short name T1112
Test name
Test status
Simulation time 58825622566 ps
CPU time 61.22 seconds
Started Jul 10 04:52:56 PM PDT 24
Finished Jul 10 04:53:58 PM PDT 24
Peak memory 200004 kb
Host smart-41027ca6-5953-4d99-83e2-640916c52462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044042805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2044042805
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.254993819
Short name T1182
Test name
Test status
Simulation time 11650258933 ps
CPU time 153.6 seconds
Started Jul 10 04:52:59 PM PDT 24
Finished Jul 10 04:55:34 PM PDT 24
Peak memory 200024 kb
Host smart-c3624275-df52-4077-8299-b1de11663224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254993819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.254993819
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1784841503
Short name T951
Test name
Test status
Simulation time 7316584069 ps
CPU time 64.65 seconds
Started Jul 10 04:52:59 PM PDT 24
Finished Jul 10 04:54:05 PM PDT 24
Peak memory 199096 kb
Host smart-2dcd0840-92b7-49a4-8f94-10fbb323c873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784841503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1784841503
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.35298320
Short name T542
Test name
Test status
Simulation time 36089886872 ps
CPU time 55 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:53:53 PM PDT 24
Peak memory 199732 kb
Host smart-d20402f2-00cf-4ab7-8441-88dc493d457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35298320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.35298320
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.960669285
Short name T915
Test name
Test status
Simulation time 2776106631 ps
CPU time 1.64 seconds
Started Jul 10 04:52:56 PM PDT 24
Finished Jul 10 04:52:58 PM PDT 24
Peak memory 195592 kb
Host smart-178f6c8d-b055-4406-9017-963880001fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960669285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.960669285
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1879503359
Short name T1088
Test name
Test status
Simulation time 983113873 ps
CPU time 2.73 seconds
Started Jul 10 04:52:48 PM PDT 24
Finished Jul 10 04:52:51 PM PDT 24
Peak memory 199728 kb
Host smart-5244601d-5342-45bf-96e3-da89d1870e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879503359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1879503359
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.4049381464
Short name T396
Test name
Test status
Simulation time 142102546778 ps
CPU time 365.52 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:59:05 PM PDT 24
Peak memory 199808 kb
Host smart-370d6ccd-145a-41ac-a745-b5d5593a66e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049381464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.4049381464
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3233989051
Short name T545
Test name
Test status
Simulation time 41396187514 ps
CPU time 413.63 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:59:54 PM PDT 24
Peak memory 216280 kb
Host smart-e8ec74f9-99cc-41c9-9d64-9bc2c79f5d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233989051 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3233989051
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.4238559194
Short name T739
Test name
Test status
Simulation time 7747640029 ps
CPU time 13.99 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:53:12 PM PDT 24
Peak memory 199780 kb
Host smart-bb7085f8-073c-4ace-bac6-d3ceeaf3162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238559194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4238559194
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3846033829
Short name T353
Test name
Test status
Simulation time 20308291358 ps
CPU time 8.45 seconds
Started Jul 10 04:52:49 PM PDT 24
Finished Jul 10 04:52:58 PM PDT 24
Peak memory 199912 kb
Host smart-34924866-e253-4e65-a712-cabc59f0cdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846033829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3846033829
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1821371837
Short name T837
Test name
Test status
Simulation time 9562429125 ps
CPU time 16.9 seconds
Started Jul 10 04:58:41 PM PDT 24
Finished Jul 10 04:58:59 PM PDT 24
Peak memory 199772 kb
Host smart-0efd9a5c-1dd5-44ef-b341-b4d156b8a6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821371837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1821371837
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3239134008
Short name T163
Test name
Test status
Simulation time 29550695431 ps
CPU time 26.07 seconds
Started Jul 10 04:58:43 PM PDT 24
Finished Jul 10 04:59:10 PM PDT 24
Peak memory 200108 kb
Host smart-1276fbec-bbe8-4a53-8c51-084a1709a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239134008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3239134008
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.215723528
Short name T973
Test name
Test status
Simulation time 226164133887 ps
CPU time 60.68 seconds
Started Jul 10 04:58:41 PM PDT 24
Finished Jul 10 04:59:43 PM PDT 24
Peak memory 199828 kb
Host smart-4a238b52-1e2c-407e-a042-e7e0f68f767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215723528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.215723528
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2426323020
Short name T1064
Test name
Test status
Simulation time 94212710008 ps
CPU time 157.67 seconds
Started Jul 10 04:58:40 PM PDT 24
Finished Jul 10 05:01:19 PM PDT 24
Peak memory 199844 kb
Host smart-46d00319-7f5b-4fee-9c53-8ce9cbe4cc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426323020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2426323020
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2322546672
Short name T172
Test name
Test status
Simulation time 41450390173 ps
CPU time 23 seconds
Started Jul 10 04:58:41 PM PDT 24
Finished Jul 10 04:59:05 PM PDT 24
Peak memory 199804 kb
Host smart-cdfa0af2-af7f-427d-b0af-83156f1d5f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322546672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2322546672
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.370107927
Short name T325
Test name
Test status
Simulation time 34387119184 ps
CPU time 12.79 seconds
Started Jul 10 04:58:42 PM PDT 24
Finished Jul 10 04:58:56 PM PDT 24
Peak memory 199868 kb
Host smart-e26e610b-aca6-4745-a3e2-036344e04da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370107927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.370107927
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.53048678
Short name T171
Test name
Test status
Simulation time 85638137002 ps
CPU time 39.48 seconds
Started Jul 10 04:58:50 PM PDT 24
Finished Jul 10 04:59:30 PM PDT 24
Peak memory 199784 kb
Host smart-9be2a732-0ac1-45d7-b44c-c713a827520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53048678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.53048678
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.155422016
Short name T707
Test name
Test status
Simulation time 41098461 ps
CPU time 0.64 seconds
Started Jul 10 04:53:09 PM PDT 24
Finished Jul 10 04:53:11 PM PDT 24
Peak memory 195052 kb
Host smart-7355f61f-f72e-46ac-87e4-46d9f0eec8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155422016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.155422016
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1527234859
Short name T877
Test name
Test status
Simulation time 231137625777 ps
CPU time 26.77 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:53:24 PM PDT 24
Peak memory 199896 kb
Host smart-26ab30f3-77b7-42d6-8b4d-a336622e6c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527234859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1527234859
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2583370569
Short name T848
Test name
Test status
Simulation time 6713769876 ps
CPU time 10.2 seconds
Started Jul 10 04:52:59 PM PDT 24
Finished Jul 10 04:53:11 PM PDT 24
Peak memory 199420 kb
Host smart-45c62d96-af5b-4faf-93b2-edb4519e0da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583370569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2583370569
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3296706045
Short name T44
Test name
Test status
Simulation time 65633288779 ps
CPU time 115.03 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:54:54 PM PDT 24
Peak memory 199904 kb
Host smart-0ea2f03c-b861-4a90-be8d-05631fb2c54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296706045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3296706045
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2817936196
Short name T688
Test name
Test status
Simulation time 41706269504 ps
CPU time 39.11 seconds
Started Jul 10 04:53:00 PM PDT 24
Finished Jul 10 04:53:41 PM PDT 24
Peak memory 199892 kb
Host smart-73304b54-d7d3-40d8-be0a-1e1bdabaecab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817936196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2817936196
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1728067116
Short name T664
Test name
Test status
Simulation time 209448278054 ps
CPU time 243.02 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:57:03 PM PDT 24
Peak memory 199772 kb
Host smart-5783d79c-b4c5-4781-b83f-e11bc870ac8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728067116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1728067116
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4210084571
Short name T399
Test name
Test status
Simulation time 1954626241 ps
CPU time 1.49 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:53:02 PM PDT 24
Peak memory 198300 kb
Host smart-db512111-71eb-467e-8c01-65d280b54685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210084571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4210084571
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.698018054
Short name T954
Test name
Test status
Simulation time 92503897886 ps
CPU time 127.34 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:55:08 PM PDT 24
Peak memory 199468 kb
Host smart-e487067c-0e4f-42e9-9c5c-26824b688815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698018054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.698018054
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3917821232
Short name T1015
Test name
Test status
Simulation time 21987922402 ps
CPU time 137.93 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:55:18 PM PDT 24
Peak memory 199724 kb
Host smart-c5adfbe0-212b-4486-830e-fcc0a96b5fd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917821232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3917821232
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.389758537
Short name T581
Test name
Test status
Simulation time 1915422110 ps
CPU time 6.59 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:53:07 PM PDT 24
Peak memory 198468 kb
Host smart-7d6b7ec1-57ea-48ce-a9df-a0313f4e6ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389758537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.389758537
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3308732110
Short name T645
Test name
Test status
Simulation time 71016669426 ps
CPU time 23.33 seconds
Started Jul 10 04:53:00 PM PDT 24
Finished Jul 10 04:53:25 PM PDT 24
Peak memory 199604 kb
Host smart-a99eed80-cedf-45ff-92bd-90aaccad3aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308732110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3308732110
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.625200097
Short name T400
Test name
Test status
Simulation time 421670881 ps
CPU time 0.99 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:52:59 PM PDT 24
Peak memory 195416 kb
Host smart-5213f4a7-6dcf-4753-a714-1617a22710a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625200097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.625200097
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3291508510
Short name T883
Test name
Test status
Simulation time 6203223690 ps
CPU time 13.98 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:53:13 PM PDT 24
Peak memory 199812 kb
Host smart-4179c3a5-8b74-4bb7-add7-2d6b2f09c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291508510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3291508510
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.618053614
Short name T1058
Test name
Test status
Simulation time 2102212447 ps
CPU time 6.41 seconds
Started Jul 10 04:52:59 PM PDT 24
Finished Jul 10 04:53:07 PM PDT 24
Peak memory 199132 kb
Host smart-b45a8aa1-177c-4525-94b2-580d4b1d5132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618053614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.618053614
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2195059780
Short name T368
Test name
Test status
Simulation time 1965114226 ps
CPU time 1.44 seconds
Started Jul 10 04:52:58 PM PDT 24
Finished Jul 10 04:53:01 PM PDT 24
Peak memory 196844 kb
Host smart-6d0f7c03-1677-4494-b4d0-b29a9d5274db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195059780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2195059780
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3907785796
Short name T431
Test name
Test status
Simulation time 155040083029 ps
CPU time 97.59 seconds
Started Jul 10 04:52:57 PM PDT 24
Finished Jul 10 04:54:36 PM PDT 24
Peak memory 199852 kb
Host smart-3079ee5b-f67b-4a80-a715-00419838cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907785796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3907785796
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.888526374
Short name T363
Test name
Test status
Simulation time 23809245267 ps
CPU time 34.57 seconds
Started Jul 10 04:58:49 PM PDT 24
Finished Jul 10 04:59:24 PM PDT 24
Peak memory 198444 kb
Host smart-4320eb6a-4bd6-4638-b9cc-c09485448c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888526374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.888526374
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1580006373
Short name T202
Test name
Test status
Simulation time 174118939681 ps
CPU time 73.73 seconds
Started Jul 10 04:58:50 PM PDT 24
Finished Jul 10 05:00:04 PM PDT 24
Peak memory 199844 kb
Host smart-2f538397-9c0f-4189-ae4d-9a5dcc94a128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580006373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1580006373
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3729434907
Short name T966
Test name
Test status
Simulation time 136767554463 ps
CPU time 117.74 seconds
Started Jul 10 04:58:49 PM PDT 24
Finished Jul 10 05:00:48 PM PDT 24
Peak memory 199824 kb
Host smart-6a1eba13-e86e-4bbd-bb03-6292399d5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729434907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3729434907
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.642179091
Short name T1166
Test name
Test status
Simulation time 11226798976 ps
CPU time 10 seconds
Started Jul 10 04:58:57 PM PDT 24
Finished Jul 10 04:59:08 PM PDT 24
Peak memory 199516 kb
Host smart-3952c53e-57c8-4d46-a745-5bdd58e505e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642179091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.642179091
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2700602308
Short name T854
Test name
Test status
Simulation time 50712601074 ps
CPU time 37.43 seconds
Started Jul 10 04:58:58 PM PDT 24
Finished Jul 10 04:59:37 PM PDT 24
Peak memory 199840 kb
Host smart-d0cf55b7-b400-4a57-967c-459b0bbbc3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700602308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2700602308
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2521854937
Short name T788
Test name
Test status
Simulation time 113450032005 ps
CPU time 34.62 seconds
Started Jul 10 04:58:59 PM PDT 24
Finished Jul 10 04:59:35 PM PDT 24
Peak memory 199828 kb
Host smart-ecd3ed47-9575-484e-844f-4451ddfe95a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521854937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2521854937
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1805668299
Short name T534
Test name
Test status
Simulation time 12825422 ps
CPU time 0.58 seconds
Started Jul 10 04:53:08 PM PDT 24
Finished Jul 10 04:53:10 PM PDT 24
Peak memory 195420 kb
Host smart-ad5e08ff-e6f4-4ae3-83cf-d05c64fba8c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805668299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1805668299
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1617416810
Short name T991
Test name
Test status
Simulation time 55479643134 ps
CPU time 52.65 seconds
Started Jul 10 04:53:08 PM PDT 24
Finished Jul 10 04:54:02 PM PDT 24
Peak memory 199824 kb
Host smart-57734206-6783-4290-be7d-7e4cefc86a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617416810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1617416810
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.4263480057
Short name T381
Test name
Test status
Simulation time 192264057325 ps
CPU time 159.88 seconds
Started Jul 10 04:53:12 PM PDT 24
Finished Jul 10 04:55:52 PM PDT 24
Peak memory 199788 kb
Host smart-91319449-5c48-4ba9-bc57-431c086b47b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263480057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.4263480057
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.648354888
Short name T223
Test name
Test status
Simulation time 47595890632 ps
CPU time 63.84 seconds
Started Jul 10 04:53:08 PM PDT 24
Finished Jul 10 04:54:13 PM PDT 24
Peak memory 199908 kb
Host smart-07f5b791-77c8-482b-a7bf-9f35d0c27035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648354888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.648354888
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3017074173
Short name T1074
Test name
Test status
Simulation time 7135929006 ps
CPU time 7.29 seconds
Started Jul 10 04:53:12 PM PDT 24
Finished Jul 10 04:53:20 PM PDT 24
Peak memory 198912 kb
Host smart-76206699-c5be-4c81-ae09-f7397304cb5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017074173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3017074173
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3448656095
Short name T1063
Test name
Test status
Simulation time 204459376462 ps
CPU time 195.27 seconds
Started Jul 10 04:53:08 PM PDT 24
Finished Jul 10 04:56:25 PM PDT 24
Peak memory 199780 kb
Host smart-5d5854d5-16cd-4c5b-a523-31ec990ef88c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448656095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3448656095
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.467087535
Short name T434
Test name
Test status
Simulation time 1848191532 ps
CPU time 2.58 seconds
Started Jul 10 04:53:09 PM PDT 24
Finished Jul 10 04:53:13 PM PDT 24
Peak memory 198660 kb
Host smart-db2999e9-fb6f-4539-b179-d075eac9297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467087535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.467087535
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3545035401
Short name T658
Test name
Test status
Simulation time 130339077681 ps
CPU time 138.68 seconds
Started Jul 10 04:53:09 PM PDT 24
Finished Jul 10 04:55:29 PM PDT 24
Peak memory 200256 kb
Host smart-af8d6e94-713c-4af6-8374-145e97b62dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545035401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3545035401
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.4211827951
Short name T641
Test name
Test status
Simulation time 11699701228 ps
CPU time 123.74 seconds
Started Jul 10 04:53:08 PM PDT 24
Finished Jul 10 04:55:14 PM PDT 24
Peak memory 199808 kb
Host smart-376dea21-55bd-4914-aa10-cfd0c4671f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211827951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4211827951
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2289693373
Short name T499
Test name
Test status
Simulation time 5372888591 ps
CPU time 11.26 seconds
Started Jul 10 04:53:11 PM PDT 24
Finished Jul 10 04:53:23 PM PDT 24
Peak memory 198848 kb
Host smart-e2e79db1-47a9-4287-bd12-e3311ae98607
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2289693373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2289693373
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3714964349
Short name T551
Test name
Test status
Simulation time 43831080541 ps
CPU time 35.59 seconds
Started Jul 10 04:53:11 PM PDT 24
Finished Jul 10 04:53:47 PM PDT 24
Peak memory 199788 kb
Host smart-b238d6cf-1760-4c51-9d90-79b23f45e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714964349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3714964349
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3165126515
Short name T268
Test name
Test status
Simulation time 3507957437 ps
CPU time 1.82 seconds
Started Jul 10 04:53:09 PM PDT 24
Finished Jul 10 04:53:12 PM PDT 24
Peak memory 195812 kb
Host smart-05d80324-100e-4928-90bb-7023cdc08a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165126515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3165126515
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2541146891
Short name T1151
Test name
Test status
Simulation time 489536993 ps
CPU time 2.74 seconds
Started Jul 10 04:53:07 PM PDT 24
Finished Jul 10 04:53:11 PM PDT 24
Peak memory 199484 kb
Host smart-94b1bcc3-4da8-4336-b798-aa1888d8cf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541146891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2541146891
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1226964412
Short name T918
Test name
Test status
Simulation time 267865297704 ps
CPU time 470.12 seconds
Started Jul 10 04:53:06 PM PDT 24
Finished Jul 10 05:00:58 PM PDT 24
Peak memory 199816 kb
Host smart-6971999c-f046-4e12-8a1a-5e14fff70273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226964412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1226964412
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.30710766
Short name T404
Test name
Test status
Simulation time 1070331389 ps
CPU time 2.67 seconds
Started Jul 10 04:53:11 PM PDT 24
Finished Jul 10 04:53:14 PM PDT 24
Peak memory 199440 kb
Host smart-4506b516-1696-4532-8a8e-854fecb88520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30710766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.30710766
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3983833787
Short name T1081
Test name
Test status
Simulation time 52572752220 ps
CPU time 76.39 seconds
Started Jul 10 04:53:10 PM PDT 24
Finished Jul 10 04:54:28 PM PDT 24
Peak memory 199848 kb
Host smart-d3aace96-f36b-4e59-9ab8-4a90baab0174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983833787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3983833787
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.782722772
Short name T326
Test name
Test status
Simulation time 16835354055 ps
CPU time 8.28 seconds
Started Jul 10 04:58:58 PM PDT 24
Finished Jul 10 04:59:08 PM PDT 24
Peak memory 199796 kb
Host smart-b341c727-fa17-489f-92a2-84438e079e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782722772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.782722772
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2762978680
Short name T79
Test name
Test status
Simulation time 58426429024 ps
CPU time 117.99 seconds
Started Jul 10 04:58:57 PM PDT 24
Finished Jul 10 05:00:55 PM PDT 24
Peak memory 199772 kb
Host smart-b436ac06-7469-4bae-8058-e45ba1b0a0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762978680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2762978680
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1020027310
Short name T48
Test name
Test status
Simulation time 75701215554 ps
CPU time 133.76 seconds
Started Jul 10 04:58:58 PM PDT 24
Finished Jul 10 05:01:13 PM PDT 24
Peak memory 200176 kb
Host smart-520433e0-0132-4ae3-ad0d-f49472c51a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020027310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1020027310
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3670715990
Short name T577
Test name
Test status
Simulation time 174594268281 ps
CPU time 110.15 seconds
Started Jul 10 04:58:57 PM PDT 24
Finished Jul 10 05:00:48 PM PDT 24
Peak memory 199776 kb
Host smart-850959a7-bf10-48d8-8373-eb80ab371594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670715990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3670715990
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3864041707
Short name T465
Test name
Test status
Simulation time 155888757399 ps
CPU time 162.23 seconds
Started Jul 10 04:58:59 PM PDT 24
Finished Jul 10 05:01:42 PM PDT 24
Peak memory 199784 kb
Host smart-217f515e-c0ab-476e-b536-55da7b029da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864041707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3864041707
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3674052206
Short name T354
Test name
Test status
Simulation time 16303076037 ps
CPU time 25.52 seconds
Started Jul 10 04:58:57 PM PDT 24
Finished Jul 10 04:59:24 PM PDT 24
Peak memory 199696 kb
Host smart-98c94c58-18b8-4caa-a37f-d092ed7d99a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674052206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3674052206
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1003498906
Short name T722
Test name
Test status
Simulation time 28299881017 ps
CPU time 40.18 seconds
Started Jul 10 04:59:05 PM PDT 24
Finished Jul 10 04:59:47 PM PDT 24
Peak memory 199704 kb
Host smart-0383196a-90d2-49c3-b1c1-780a50901f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003498906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1003498906
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1475320733
Short name T200
Test name
Test status
Simulation time 284772695437 ps
CPU time 124.36 seconds
Started Jul 10 04:59:07 PM PDT 24
Finished Jul 10 05:01:13 PM PDT 24
Peak memory 199784 kb
Host smart-b0b2cddc-c83b-4753-a547-c014a35e1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475320733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1475320733
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.612667536
Short name T1101
Test name
Test status
Simulation time 21424891 ps
CPU time 0.53 seconds
Started Jul 10 04:53:21 PM PDT 24
Finished Jul 10 04:53:23 PM PDT 24
Peak memory 195144 kb
Host smart-62be61b9-1332-47fa-a97c-c6765329d851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612667536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.612667536
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1499829236
Short name T579
Test name
Test status
Simulation time 99885273578 ps
CPU time 16.17 seconds
Started Jul 10 04:53:20 PM PDT 24
Finished Jul 10 04:53:38 PM PDT 24
Peak memory 199560 kb
Host smart-b72db97a-1e76-460d-84e2-c24da6872a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499829236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1499829236
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3726431132
Short name T1152
Test name
Test status
Simulation time 196856965621 ps
CPU time 73.78 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 04:54:34 PM PDT 24
Peak memory 199836 kb
Host smart-2837d1dd-d275-49a9-a8b9-a5fa13cc6b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726431132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3726431132
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2533275395
Short name T632
Test name
Test status
Simulation time 45805423714 ps
CPU time 80.27 seconds
Started Jul 10 04:53:19 PM PDT 24
Finished Jul 10 04:54:41 PM PDT 24
Peak memory 199828 kb
Host smart-d591b618-9079-4f99-9379-8e20d259e0c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533275395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2533275395
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.781093719
Short name T540
Test name
Test status
Simulation time 181301673355 ps
CPU time 1427.9 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 05:17:09 PM PDT 24
Peak memory 199868 kb
Host smart-99b0a8ef-3488-487e-9a1a-a337736239ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781093719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.781093719
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3392941714
Short name T346
Test name
Test status
Simulation time 4796631473 ps
CPU time 6.75 seconds
Started Jul 10 04:53:19 PM PDT 24
Finished Jul 10 04:53:28 PM PDT 24
Peak memory 199764 kb
Host smart-a9b244f8-f5ce-4313-99d6-dbe71e733181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392941714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3392941714
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1897013765
Short name T819
Test name
Test status
Simulation time 113183527644 ps
CPU time 175.04 seconds
Started Jul 10 04:53:19 PM PDT 24
Finished Jul 10 04:56:16 PM PDT 24
Peak memory 199076 kb
Host smart-7b765467-3044-43af-ac78-fa83766bcf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897013765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1897013765
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.605108823
Short name T1091
Test name
Test status
Simulation time 24695553257 ps
CPU time 129.89 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 04:55:30 PM PDT 24
Peak memory 199760 kb
Host smart-d40eba07-66a7-4778-b52e-50223746ea4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605108823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.605108823
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1643834096
Short name T45
Test name
Test status
Simulation time 2117738964 ps
CPU time 12.85 seconds
Started Jul 10 04:53:17 PM PDT 24
Finished Jul 10 04:53:31 PM PDT 24
Peak memory 197888 kb
Host smart-663cfe16-3c72-402c-93bf-5a230c00ce3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643834096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1643834096
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.322381464
Short name T971
Test name
Test status
Simulation time 198817666641 ps
CPU time 120.43 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 04:55:20 PM PDT 24
Peak memory 199780 kb
Host smart-c28701f9-04a1-4e6f-8bab-18dcb699ea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322381464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.322381464
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.339631231
Short name T479
Test name
Test status
Simulation time 2173527807 ps
CPU time 2.12 seconds
Started Jul 10 04:53:22 PM PDT 24
Finished Jul 10 04:53:26 PM PDT 24
Peak memory 195304 kb
Host smart-5476a56f-0403-489b-aa17-1a0617c9b277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339631231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.339631231
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.277990030
Short name T740
Test name
Test status
Simulation time 935069648 ps
CPU time 1.83 seconds
Started Jul 10 04:53:11 PM PDT 24
Finished Jul 10 04:53:14 PM PDT 24
Peak memory 198624 kb
Host smart-70d1ce12-1408-46d0-89b7-ee1a9217c59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277990030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.277990030
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.395786045
Short name T196
Test name
Test status
Simulation time 45600011666 ps
CPU time 1316.62 seconds
Started Jul 10 04:53:20 PM PDT 24
Finished Jul 10 05:15:19 PM PDT 24
Peak memory 216320 kb
Host smart-2aba4c86-09b4-4bca-8585-65f48c86ab0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395786045 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.395786045
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.558883314
Short name T727
Test name
Test status
Simulation time 2652539593 ps
CPU time 2.09 seconds
Started Jul 10 04:53:19 PM PDT 24
Finished Jul 10 04:53:23 PM PDT 24
Peak memory 198308 kb
Host smart-3dbeeba3-2b3f-4b60-9cf0-7c81bd901b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558883314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.558883314
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.312309331
Short name T304
Test name
Test status
Simulation time 31413817834 ps
CPU time 47.07 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 04:54:08 PM PDT 24
Peak memory 199796 kb
Host smart-e381a067-927e-4a6d-b3ac-57156410bd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312309331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.312309331
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3154684783
Short name T229
Test name
Test status
Simulation time 166959255553 ps
CPU time 80.93 seconds
Started Jul 10 04:59:06 PM PDT 24
Finished Jul 10 05:00:28 PM PDT 24
Peak memory 199808 kb
Host smart-04c4ece2-5f0c-4198-915d-52d1cb6d3cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154684783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3154684783
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2000591012
Short name T170
Test name
Test status
Simulation time 10525318357 ps
CPU time 16.01 seconds
Started Jul 10 04:59:06 PM PDT 24
Finished Jul 10 04:59:24 PM PDT 24
Peak memory 199856 kb
Host smart-6b8593ff-ebd9-4d9c-b98b-bb34e4789244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000591012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2000591012
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.4016933600
Short name T875
Test name
Test status
Simulation time 41173366906 ps
CPU time 29.19 seconds
Started Jul 10 04:59:07 PM PDT 24
Finished Jul 10 04:59:37 PM PDT 24
Peak memory 199784 kb
Host smart-07664b91-6bd2-41d3-9493-cdb503319b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016933600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.4016933600
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1751141131
Short name T1082
Test name
Test status
Simulation time 106354418012 ps
CPU time 151.15 seconds
Started Jul 10 04:59:05 PM PDT 24
Finished Jul 10 05:01:38 PM PDT 24
Peak memory 199804 kb
Host smart-00fc181c-a34c-49f8-9b2e-1df399a9c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751141131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1751141131
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2497500454
Short name T726
Test name
Test status
Simulation time 272172680816 ps
CPU time 23.58 seconds
Started Jul 10 04:59:05 PM PDT 24
Finished Jul 10 04:59:30 PM PDT 24
Peak memory 199720 kb
Host smart-bade2d80-7b2f-4e93-9bf5-0795550c1328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497500454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2497500454
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4124555794
Short name T871
Test name
Test status
Simulation time 42252843506 ps
CPU time 41.74 seconds
Started Jul 10 04:59:07 PM PDT 24
Finished Jul 10 04:59:50 PM PDT 24
Peak memory 199764 kb
Host smart-f86f2218-ede1-4ff4-b5f0-6d0b30c0a685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124555794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4124555794
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.4107081690
Short name T482
Test name
Test status
Simulation time 32214497251 ps
CPU time 47.82 seconds
Started Jul 10 04:59:05 PM PDT 24
Finished Jul 10 04:59:55 PM PDT 24
Peak memory 199500 kb
Host smart-4f86b87e-0a4c-4692-8262-3c59f780f19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107081690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4107081690
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1191247398
Short name T696
Test name
Test status
Simulation time 134906697620 ps
CPU time 181.16 seconds
Started Jul 10 04:59:06 PM PDT 24
Finished Jul 10 05:02:09 PM PDT 24
Peak memory 199848 kb
Host smart-39f2e3b9-abe6-44ea-a4f7-77f7d89f48ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191247398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1191247398
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3207930390
Short name T201
Test name
Test status
Simulation time 17593037253 ps
CPU time 30.58 seconds
Started Jul 10 04:59:09 PM PDT 24
Finished Jul 10 04:59:40 PM PDT 24
Peak memory 199792 kb
Host smart-8280c3fc-dc5d-44d0-9842-91b59e5f73e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207930390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3207930390
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3076536640
Short name T633
Test name
Test status
Simulation time 23727498 ps
CPU time 0.55 seconds
Started Jul 10 04:53:28 PM PDT 24
Finished Jul 10 04:53:30 PM PDT 24
Peak memory 195156 kb
Host smart-bc6f4e2e-f137-4bec-afba-01a3e501afd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076536640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3076536640
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1571969802
Short name T1100
Test name
Test status
Simulation time 35220301516 ps
CPU time 21.37 seconds
Started Jul 10 04:53:16 PM PDT 24
Finished Jul 10 04:53:38 PM PDT 24
Peak memory 199400 kb
Host smart-6a150d9c-8292-4fa2-8cc4-fcd6796e2129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571969802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1571969802
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1038262228
Short name T858
Test name
Test status
Simulation time 92565237091 ps
CPU time 78.68 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 04:54:38 PM PDT 24
Peak memory 199716 kb
Host smart-a1ebe5d3-ff2c-4a44-98f5-3eafc9c31033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038262228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1038262228
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1105428854
Short name T494
Test name
Test status
Simulation time 11249680449 ps
CPU time 18.05 seconds
Started Jul 10 04:53:17 PM PDT 24
Finished Jul 10 04:53:37 PM PDT 24
Peak memory 199740 kb
Host smart-8ad91c2a-b58b-41d4-adf4-4ffa6b51ff9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105428854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1105428854
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2754995188
Short name T769
Test name
Test status
Simulation time 68653675892 ps
CPU time 27.59 seconds
Started Jul 10 04:53:18 PM PDT 24
Finished Jul 10 04:53:48 PM PDT 24
Peak memory 199708 kb
Host smart-5642f3f0-2a69-4876-be70-dfbde185236b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754995188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2754995188
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3045806093
Short name T584
Test name
Test status
Simulation time 99439238827 ps
CPU time 223.79 seconds
Started Jul 10 04:53:24 PM PDT 24
Finished Jul 10 04:57:09 PM PDT 24
Peak memory 199828 kb
Host smart-a17c0223-158b-440c-9763-dacad0e3fefe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045806093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3045806093
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1380761483
Short name T450
Test name
Test status
Simulation time 6782436914 ps
CPU time 9.96 seconds
Started Jul 10 04:53:27 PM PDT 24
Finished Jul 10 04:53:38 PM PDT 24
Peak memory 198664 kb
Host smart-aa453b10-15a2-4327-acfc-5109fb577fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380761483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1380761483
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.4294216217
Short name T725
Test name
Test status
Simulation time 119053077807 ps
CPU time 54.91 seconds
Started Jul 10 04:53:19 PM PDT 24
Finished Jul 10 04:54:16 PM PDT 24
Peak memory 208228 kb
Host smart-530a47bb-dca8-467c-a348-435de1e7fcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294216217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4294216217
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1873812769
Short name T489
Test name
Test status
Simulation time 6764372029 ps
CPU time 163.21 seconds
Started Jul 10 04:53:31 PM PDT 24
Finished Jul 10 04:56:15 PM PDT 24
Peak memory 199784 kb
Host smart-50568511-89cd-4bca-ae61-b0226d0c9147
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873812769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1873812769
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1197313997
Short name T803
Test name
Test status
Simulation time 2622315560 ps
CPU time 19.52 seconds
Started Jul 10 04:53:20 PM PDT 24
Finished Jul 10 04:53:42 PM PDT 24
Peak memory 198200 kb
Host smart-f218430a-1c63-4992-b283-f7ce9f66499a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197313997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1197313997
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.4253774199
Short name T789
Test name
Test status
Simulation time 20318658756 ps
CPU time 13.98 seconds
Started Jul 10 04:53:29 PM PDT 24
Finished Jul 10 04:53:44 PM PDT 24
Peak memory 199820 kb
Host smart-fa887d60-9411-4dc3-9adc-e06c083f9bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253774199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4253774199
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.321911243
Short name T933
Test name
Test status
Simulation time 35324331558 ps
CPU time 12.46 seconds
Started Jul 10 04:53:27 PM PDT 24
Finished Jul 10 04:53:41 PM PDT 24
Peak memory 195648 kb
Host smart-be64fbc7-b0be-4833-9865-a6e245dd71dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321911243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.321911243
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.20255735
Short name T832
Test name
Test status
Simulation time 454544159 ps
CPU time 1.82 seconds
Started Jul 10 04:53:17 PM PDT 24
Finished Jul 10 04:53:20 PM PDT 24
Peak memory 199308 kb
Host smart-ce397c85-3afa-459e-881c-78b0a13c48b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20255735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.20255735
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1964637186
Short name T1038
Test name
Test status
Simulation time 83604849183 ps
CPU time 49.1 seconds
Started Jul 10 04:53:32 PM PDT 24
Finished Jul 10 04:54:22 PM PDT 24
Peak memory 215792 kb
Host smart-a5a233b3-d0f6-4499-9cc5-e2b6696b786e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964637186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1964637186
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2236008597
Short name T113
Test name
Test status
Simulation time 320904973233 ps
CPU time 553.24 seconds
Started Jul 10 04:53:26 PM PDT 24
Finished Jul 10 05:02:41 PM PDT 24
Peak memory 216376 kb
Host smart-17d62650-f281-4c77-8c07-c23914556c13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236008597 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2236008597
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.386150890
Short name T585
Test name
Test status
Simulation time 6945732651 ps
CPU time 9.38 seconds
Started Jul 10 04:53:26 PM PDT 24
Finished Jul 10 04:53:36 PM PDT 24
Peak memory 199096 kb
Host smart-638c1fce-1ebc-4c02-8361-9f15ec882373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386150890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.386150890
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1838360625
Short name T1120
Test name
Test status
Simulation time 109014388131 ps
CPU time 53.67 seconds
Started Jul 10 04:59:06 PM PDT 24
Finished Jul 10 05:00:01 PM PDT 24
Peak memory 200112 kb
Host smart-f79238e0-ced3-4c04-ae52-b7610fea0e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838360625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1838360625
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2590836612
Short name T705
Test name
Test status
Simulation time 159909775944 ps
CPU time 57.59 seconds
Started Jul 10 04:59:12 PM PDT 24
Finished Jul 10 05:00:10 PM PDT 24
Peak memory 199840 kb
Host smart-30afd81d-48c1-4134-89b1-22e37dd1c5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590836612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2590836612
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3679817620
Short name T199
Test name
Test status
Simulation time 5359522530 ps
CPU time 9.28 seconds
Started Jul 10 04:59:12 PM PDT 24
Finished Jul 10 04:59:22 PM PDT 24
Peak memory 199808 kb
Host smart-e02100dc-609b-412e-a2b6-3e660e4e7816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679817620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3679817620
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2694680466
Short name T158
Test name
Test status
Simulation time 172083450042 ps
CPU time 58.64 seconds
Started Jul 10 04:59:11 PM PDT 24
Finished Jul 10 05:00:11 PM PDT 24
Peak memory 199840 kb
Host smart-25ceda7a-3b9d-4c9c-a3fc-cb442e9f1ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694680466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2694680466
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1645485684
Short name T315
Test name
Test status
Simulation time 97164745053 ps
CPU time 90.24 seconds
Started Jul 10 04:59:11 PM PDT 24
Finished Jul 10 05:00:41 PM PDT 24
Peak memory 199780 kb
Host smart-adf94785-ef3c-4fa9-ab5a-c79fb909d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645485684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1645485684
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3457976348
Short name T1010
Test name
Test status
Simulation time 75494495553 ps
CPU time 98.88 seconds
Started Jul 10 04:59:12 PM PDT 24
Finished Jul 10 05:00:52 PM PDT 24
Peak memory 199860 kb
Host smart-6facd1fb-e084-4c7d-93d8-858275be12b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457976348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3457976348
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.932620231
Short name T794
Test name
Test status
Simulation time 7237215390 ps
CPU time 43.14 seconds
Started Jul 10 04:59:12 PM PDT 24
Finished Jul 10 04:59:56 PM PDT 24
Peak memory 199840 kb
Host smart-3188a606-2a5f-44c9-8894-32ad5b21d51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932620231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.932620231
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.71160163
Short name T748
Test name
Test status
Simulation time 228690317241 ps
CPU time 322.8 seconds
Started Jul 10 04:59:11 PM PDT 24
Finished Jul 10 05:04:35 PM PDT 24
Peak memory 199844 kb
Host smart-653e7bb8-7f37-4278-a01d-a54beb22d1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71160163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.71160163
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.4029542330
Short name T186
Test name
Test status
Simulation time 91130680195 ps
CPU time 116.43 seconds
Started Jul 10 04:59:11 PM PDT 24
Finished Jul 10 05:01:08 PM PDT 24
Peak memory 199864 kb
Host smart-296f1cde-31e9-4f0f-ba32-259e23fb5259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029542330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.4029542330
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.539025152
Short name T675
Test name
Test status
Simulation time 11235693 ps
CPU time 0.56 seconds
Started Jul 10 04:53:37 PM PDT 24
Finished Jul 10 04:53:39 PM PDT 24
Peak memory 194108 kb
Host smart-f8a7ddfc-cdd7-4efe-a31b-ae6ed1f2fa4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539025152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.539025152
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2739193945
Short name T535
Test name
Test status
Simulation time 13775128624 ps
CPU time 21.98 seconds
Started Jul 10 04:53:26 PM PDT 24
Finished Jul 10 04:53:49 PM PDT 24
Peak memory 199868 kb
Host smart-ddbf6241-e921-42ee-8704-79e6d7937cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739193945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2739193945
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1270121678
Short name T524
Test name
Test status
Simulation time 74114385774 ps
CPU time 74.96 seconds
Started Jul 10 04:53:27 PM PDT 24
Finished Jul 10 04:54:43 PM PDT 24
Peak memory 199824 kb
Host smart-c79c9064-0529-4e5a-96a4-a574c5be3ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270121678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1270121678
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3172946119
Short name T1089
Test name
Test status
Simulation time 11086134908 ps
CPU time 19.04 seconds
Started Jul 10 04:53:30 PM PDT 24
Finished Jul 10 04:53:49 PM PDT 24
Peak memory 199752 kb
Host smart-42da5abb-7cf3-41f8-9bd6-6b1d8c6d6be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172946119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3172946119
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.235368333
Short name T1117
Test name
Test status
Simulation time 392973164866 ps
CPU time 674.32 seconds
Started Jul 10 04:53:31 PM PDT 24
Finished Jul 10 05:04:46 PM PDT 24
Peak memory 199744 kb
Host smart-00c011a2-b25c-4607-abeb-bfd6e01874a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235368333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.235368333
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.967703271
Short name T843
Test name
Test status
Simulation time 115575003752 ps
CPU time 209.49 seconds
Started Jul 10 04:53:35 PM PDT 24
Finished Jul 10 04:57:06 PM PDT 24
Peak memory 199680 kb
Host smart-37874461-b02c-42c6-a930-5bc8d7ad662b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967703271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.967703271
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3429451775
Short name T1051
Test name
Test status
Simulation time 9225435178 ps
CPU time 15.21 seconds
Started Jul 10 04:53:35 PM PDT 24
Finished Jul 10 04:53:52 PM PDT 24
Peak memory 198548 kb
Host smart-6a4fd99c-0e51-4449-97c9-d2ae41a7be73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429451775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3429451775
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2960921872
Short name T950
Test name
Test status
Simulation time 127787631238 ps
CPU time 70.68 seconds
Started Jul 10 04:53:30 PM PDT 24
Finished Jul 10 04:54:41 PM PDT 24
Peak memory 199628 kb
Host smart-8e32cd4e-717f-4367-b427-57bf2fb50f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960921872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2960921872
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2342222700
Short name T867
Test name
Test status
Simulation time 7509492942 ps
CPU time 102.62 seconds
Started Jul 10 04:53:37 PM PDT 24
Finished Jul 10 04:55:21 PM PDT 24
Peak memory 199780 kb
Host smart-ab51f006-98f3-4774-b4f5-75eadede496a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342222700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2342222700
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.503662660
Short name T649
Test name
Test status
Simulation time 5354407294 ps
CPU time 44.29 seconds
Started Jul 10 04:53:27 PM PDT 24
Finished Jul 10 04:54:12 PM PDT 24
Peak memory 198608 kb
Host smart-f4776f03-6f10-4802-86bd-c9aad986f64a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503662660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.503662660
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1214431766
Short name T176
Test name
Test status
Simulation time 20111171110 ps
CPU time 31.7 seconds
Started Jul 10 04:53:29 PM PDT 24
Finished Jul 10 04:54:01 PM PDT 24
Peak memory 199764 kb
Host smart-5f3484dd-3442-4795-a384-17055fd275a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214431766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1214431766
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3121225374
Short name T267
Test name
Test status
Simulation time 5544135426 ps
CPU time 8.82 seconds
Started Jul 10 04:53:33 PM PDT 24
Finished Jul 10 04:53:42 PM PDT 24
Peak memory 196084 kb
Host smart-9c6ad041-da19-4ff7-96af-2b67cb31bb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121225374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3121225374
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.989435905
Short name T502
Test name
Test status
Simulation time 6103046306 ps
CPU time 9.05 seconds
Started Jul 10 04:53:33 PM PDT 24
Finished Jul 10 04:53:43 PM PDT 24
Peak memory 199752 kb
Host smart-255830a0-8c1a-4ed8-ae8d-97bd454ca45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989435905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.989435905
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3182143404
Short name T736
Test name
Test status
Simulation time 509243824121 ps
CPU time 475.23 seconds
Started Jul 10 04:53:37 PM PDT 24
Finished Jul 10 05:01:33 PM PDT 24
Peak memory 209020 kb
Host smart-d6c87db3-5b8d-4274-a728-cada173f4a80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182143404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3182143404
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3689609518
Short name T445
Test name
Test status
Simulation time 43965864360 ps
CPU time 1379.12 seconds
Started Jul 10 04:53:35 PM PDT 24
Finished Jul 10 05:16:35 PM PDT 24
Peak memory 216336 kb
Host smart-20007d94-f81b-45fc-b0b8-0b20bd9748fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689609518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3689609518
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3570593174
Short name T43
Test name
Test status
Simulation time 2161157396 ps
CPU time 1.73 seconds
Started Jul 10 04:53:26 PM PDT 24
Finished Jul 10 04:53:29 PM PDT 24
Peak memory 198764 kb
Host smart-fc4effeb-c36b-49df-bbbe-c7475fd134ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570593174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3570593174
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2117684206
Short name T329
Test name
Test status
Simulation time 17496784513 ps
CPU time 13.74 seconds
Started Jul 10 04:53:33 PM PDT 24
Finished Jul 10 04:53:47 PM PDT 24
Peak memory 198752 kb
Host smart-93e4f10a-c72c-4c48-a6a1-282c2f76b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117684206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2117684206
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.145227270
Short name T219
Test name
Test status
Simulation time 104508080505 ps
CPU time 15.43 seconds
Started Jul 10 04:59:20 PM PDT 24
Finished Jul 10 04:59:37 PM PDT 24
Peak memory 199908 kb
Host smart-fb9cc95f-34d0-4e37-93a7-a224988ac503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145227270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.145227270
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.74441439
Short name T301
Test name
Test status
Simulation time 9716544253 ps
CPU time 23.67 seconds
Started Jul 10 04:59:17 PM PDT 24
Finished Jul 10 04:59:41 PM PDT 24
Peak memory 199896 kb
Host smart-a511a141-e1ba-4a7c-b998-cc50659a8f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74441439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.74441439
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2195831276
Short name T913
Test name
Test status
Simulation time 20619740924 ps
CPU time 8.41 seconds
Started Jul 10 04:59:19 PM PDT 24
Finished Jul 10 04:59:28 PM PDT 24
Peak memory 199788 kb
Host smart-39b3c50d-7d2c-40aa-84f1-65684dd840a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195831276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2195831276
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1105353839
Short name T309
Test name
Test status
Simulation time 39513499755 ps
CPU time 34.74 seconds
Started Jul 10 04:59:18 PM PDT 24
Finished Jul 10 04:59:53 PM PDT 24
Peak memory 199836 kb
Host smart-6f0f4eb1-c73c-496a-9947-07cf80c5a316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105353839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1105353839
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.4196626792
Short name T600
Test name
Test status
Simulation time 31264791462 ps
CPU time 71.89 seconds
Started Jul 10 04:59:25 PM PDT 24
Finished Jul 10 05:00:39 PM PDT 24
Peak memory 199904 kb
Host smart-dff68b83-3911-496a-8460-06b8fb0fb568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196626792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4196626792
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2771144265
Short name T421
Test name
Test status
Simulation time 28079790094 ps
CPU time 11.41 seconds
Started Jul 10 04:59:25 PM PDT 24
Finished Jul 10 04:59:39 PM PDT 24
Peak memory 199532 kb
Host smart-243bd8f9-6c8a-4700-bd8e-541ba12f7a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771144265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2771144265
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2925340179
Short name T198
Test name
Test status
Simulation time 221890574833 ps
CPU time 123.91 seconds
Started Jul 10 04:59:26 PM PDT 24
Finished Jul 10 05:01:32 PM PDT 24
Peak memory 199760 kb
Host smart-70f16d01-0a5d-4c76-9464-1934810e8684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925340179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2925340179
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1587682507
Short name T907
Test name
Test status
Simulation time 42142494170 ps
CPU time 27.37 seconds
Started Jul 10 04:59:26 PM PDT 24
Finished Jul 10 04:59:56 PM PDT 24
Peak memory 199608 kb
Host smart-7a113ec4-17ad-457a-ba3d-2bd7a30d05fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587682507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1587682507
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3500698451
Short name T963
Test name
Test status
Simulation time 132498183177 ps
CPU time 246.42 seconds
Started Jul 10 04:59:25 PM PDT 24
Finished Jul 10 05:03:34 PM PDT 24
Peak memory 199852 kb
Host smart-75b20aad-3a3b-4fb1-b2b5-9c543cc8fbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500698451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3500698451
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1116080096
Short name T729
Test name
Test status
Simulation time 11954060 ps
CPU time 0.55 seconds
Started Jul 10 04:53:44 PM PDT 24
Finished Jul 10 04:53:46 PM PDT 24
Peak memory 194616 kb
Host smart-019c5693-4bd1-479b-bf08-ce07969dca7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116080096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1116080096
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3879996534
Short name T846
Test name
Test status
Simulation time 85210643368 ps
CPU time 38.95 seconds
Started Jul 10 04:53:34 PM PDT 24
Finished Jul 10 04:54:14 PM PDT 24
Peak memory 199792 kb
Host smart-6d1c1f25-499d-40a9-848a-d5bcdf9699d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879996534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3879996534
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1945509983
Short name T134
Test name
Test status
Simulation time 17557376405 ps
CPU time 30.55 seconds
Started Jul 10 04:53:34 PM PDT 24
Finished Jul 10 04:54:06 PM PDT 24
Peak memory 199820 kb
Host smart-f1417d71-7792-4bed-93f6-6762297138f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945509983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1945509983
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.81698294
Short name T573
Test name
Test status
Simulation time 94100875966 ps
CPU time 67.02 seconds
Started Jul 10 04:53:35 PM PDT 24
Finished Jul 10 04:54:43 PM PDT 24
Peak memory 199412 kb
Host smart-d6519591-658a-49ec-9abe-5625cb58b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81698294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.81698294
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3067456209
Short name T393
Test name
Test status
Simulation time 40446336419 ps
CPU time 320.98 seconds
Started Jul 10 04:53:44 PM PDT 24
Finished Jul 10 04:59:07 PM PDT 24
Peak memory 199776 kb
Host smart-7669ed4d-14c7-4d08-a197-c1499f68e7c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067456209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3067456209
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.809998876
Short name T1118
Test name
Test status
Simulation time 5383691368 ps
CPU time 3.8 seconds
Started Jul 10 04:53:42 PM PDT 24
Finished Jul 10 04:53:47 PM PDT 24
Peak memory 199756 kb
Host smart-51ed5328-ca62-459b-9489-5fa9bb9e894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809998876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.809998876
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.4198692022
Short name T392
Test name
Test status
Simulation time 23896379636 ps
CPU time 32.22 seconds
Started Jul 10 04:53:37 PM PDT 24
Finished Jul 10 04:54:10 PM PDT 24
Peak memory 198744 kb
Host smart-d4b838b4-6d1f-49f4-bcd8-dda7dcfc587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198692022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.4198692022
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1592932423
Short name T514
Test name
Test status
Simulation time 7048233349 ps
CPU time 300.3 seconds
Started Jul 10 04:53:46 PM PDT 24
Finished Jul 10 04:58:47 PM PDT 24
Peak memory 199804 kb
Host smart-694da997-48b2-4592-9967-d6772d774385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592932423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1592932423
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3880114056
Short name T546
Test name
Test status
Simulation time 7601553239 ps
CPU time 19.26 seconds
Started Jul 10 04:53:35 PM PDT 24
Finished Jul 10 04:53:55 PM PDT 24
Peak memory 197940 kb
Host smart-8897bb00-3a31-4c35-9275-bb9e789fe3b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880114056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3880114056
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.66356509
Short name T149
Test name
Test status
Simulation time 19495137752 ps
CPU time 16.4 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:54:02 PM PDT 24
Peak memory 199676 kb
Host smart-cade7dc2-3189-4793-892e-8c375d9a629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66356509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.66356509
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1699126022
Short name T863
Test name
Test status
Simulation time 4470358153 ps
CPU time 3.9 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:53:49 PM PDT 24
Peak memory 196516 kb
Host smart-32066198-d4a8-498c-8d5d-b332ed985ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699126022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1699126022
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2184618630
Short name T975
Test name
Test status
Simulation time 715291904 ps
CPU time 2.63 seconds
Started Jul 10 04:53:34 PM PDT 24
Finished Jul 10 04:53:37 PM PDT 24
Peak memory 199760 kb
Host smart-ac1dfab4-5dbc-4724-8589-f8d10add34c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184618630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2184618630
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1388330628
Short name T366
Test name
Test status
Simulation time 1432511483 ps
CPU time 2.76 seconds
Started Jul 10 04:53:47 PM PDT 24
Finished Jul 10 04:53:50 PM PDT 24
Peak memory 199704 kb
Host smart-26d9fcd4-3d3f-446b-9c40-727300c9a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388330628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1388330628
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.4001152171
Short name T306
Test name
Test status
Simulation time 14699649894 ps
CPU time 6.41 seconds
Started Jul 10 04:53:35 PM PDT 24
Finished Jul 10 04:53:43 PM PDT 24
Peak memory 199648 kb
Host smart-bdd5cd73-7bd4-4669-93b4-838aa8f13518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001152171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4001152171
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2560726475
Short name T488
Test name
Test status
Simulation time 68241668942 ps
CPU time 48.49 seconds
Started Jul 10 04:59:25 PM PDT 24
Finished Jul 10 05:00:15 PM PDT 24
Peak memory 199756 kb
Host smart-e53f2cad-fc5f-4df5-8b8b-8adbfa9bdc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560726475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2560726475
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3926115065
Short name T504
Test name
Test status
Simulation time 64943880211 ps
CPU time 152.87 seconds
Started Jul 10 04:59:26 PM PDT 24
Finished Jul 10 05:02:01 PM PDT 24
Peak memory 199772 kb
Host smart-bc5f8ec5-ae26-4b41-8ae2-abb15c8f7c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926115065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3926115065
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3352566451
Short name T438
Test name
Test status
Simulation time 181621538122 ps
CPU time 64.58 seconds
Started Jul 10 04:59:24 PM PDT 24
Finished Jul 10 05:00:30 PM PDT 24
Peak memory 199808 kb
Host smart-730e02ae-b2ac-4b4f-9d72-a312df843448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352566451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3352566451
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3735808541
Short name T1025
Test name
Test status
Simulation time 127694003365 ps
CPU time 56.17 seconds
Started Jul 10 04:59:25 PM PDT 24
Finished Jul 10 05:00:23 PM PDT 24
Peak memory 199796 kb
Host smart-172667fd-bfe0-4945-8358-dda483231017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735808541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3735808541
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1280673734
Short name T218
Test name
Test status
Simulation time 96740821045 ps
CPU time 76.58 seconds
Started Jul 10 04:59:26 PM PDT 24
Finished Jul 10 05:00:44 PM PDT 24
Peak memory 199800 kb
Host smart-dae72e61-0f97-42b3-94eb-97a3d1e7935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280673734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1280673734
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2912781484
Short name T1052
Test name
Test status
Simulation time 107896866968 ps
CPU time 409.39 seconds
Started Jul 10 04:59:25 PM PDT 24
Finished Jul 10 05:06:16 PM PDT 24
Peak memory 199812 kb
Host smart-60167028-ead7-4b8a-b08b-9ba7bc9bae19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912781484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2912781484
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2574657233
Short name T672
Test name
Test status
Simulation time 26947144996 ps
CPU time 47.47 seconds
Started Jul 10 04:59:26 PM PDT 24
Finished Jul 10 05:00:16 PM PDT 24
Peak memory 199796 kb
Host smart-5cc25f85-0078-48f6-879d-decfd5cfe7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574657233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2574657233
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3350735382
Short name T1094
Test name
Test status
Simulation time 14349596062 ps
CPU time 24.7 seconds
Started Jul 10 04:59:27 PM PDT 24
Finished Jul 10 04:59:54 PM PDT 24
Peak memory 199772 kb
Host smart-a29e35f5-7b81-4b6f-9195-26b7ea12a236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350735382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3350735382
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1175595122
Short name T290
Test name
Test status
Simulation time 23818418240 ps
CPU time 33.48 seconds
Started Jul 10 04:59:24 PM PDT 24
Finished Jul 10 04:59:59 PM PDT 24
Peak memory 199772 kb
Host smart-77618c66-91a6-4083-a28e-22f9c3bd2fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175595122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1175595122
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2210951013
Short name T1048
Test name
Test status
Simulation time 22819226291 ps
CPU time 33.85 seconds
Started Jul 10 04:59:31 PM PDT 24
Finished Jul 10 05:00:07 PM PDT 24
Peak memory 199832 kb
Host smart-c7b5e401-ff69-498f-9168-309b22cdde05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210951013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2210951013
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1418606213
Short name T686
Test name
Test status
Simulation time 58053241 ps
CPU time 0.62 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:53:45 PM PDT 24
Peak memory 195152 kb
Host smart-20dd710c-6980-4ad0-bb19-272819a529e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418606213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1418606213
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.846968496
Short name T1031
Test name
Test status
Simulation time 210558379011 ps
CPU time 254.34 seconds
Started Jul 10 04:53:45 PM PDT 24
Finished Jul 10 04:58:01 PM PDT 24
Peak memory 199756 kb
Host smart-964d65ce-f62a-43fb-a30f-7957f9ec37ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846968496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.846968496
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.668487292
Short name T339
Test name
Test status
Simulation time 48477321762 ps
CPU time 19.56 seconds
Started Jul 10 04:53:44 PM PDT 24
Finished Jul 10 04:54:06 PM PDT 24
Peak memory 199728 kb
Host smart-c3faf76a-4cb1-44d8-8da3-cb79194a443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668487292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.668487292
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.3758980364
Short name T433
Test name
Test status
Simulation time 45033489062 ps
CPU time 13.68 seconds
Started Jul 10 04:53:42 PM PDT 24
Finished Jul 10 04:53:57 PM PDT 24
Peak memory 199820 kb
Host smart-7dced7d6-9755-43b2-b0ae-338b5be94c31
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758980364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3758980364
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.589626109
Short name T771
Test name
Test status
Simulation time 104248930143 ps
CPU time 525.41 seconds
Started Jul 10 04:53:46 PM PDT 24
Finished Jul 10 05:02:32 PM PDT 24
Peak memory 199804 kb
Host smart-b714d56a-5f4f-43b5-b153-d9af61f721e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589626109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.589626109
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2057541039
Short name T820
Test name
Test status
Simulation time 7964324948 ps
CPU time 5.23 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:53:49 PM PDT 24
Peak memory 199332 kb
Host smart-892fcfdb-2b82-4e62-86bf-be2865045f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057541039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2057541039
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3624853564
Short name T1066
Test name
Test status
Simulation time 11287110659 ps
CPU time 2.18 seconds
Started Jul 10 04:53:48 PM PDT 24
Finished Jul 10 04:53:51 PM PDT 24
Peak memory 199740 kb
Host smart-2e65c28b-3f6f-41ad-bef5-504c5b474367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624853564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3624853564
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1413687130
Short name T302
Test name
Test status
Simulation time 11250759267 ps
CPU time 229.6 seconds
Started Jul 10 04:53:44 PM PDT 24
Finished Jul 10 04:57:36 PM PDT 24
Peak memory 199784 kb
Host smart-dae422c7-2c47-48ef-b43f-375aceac4b2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413687130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1413687130
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1276957470
Short name T447
Test name
Test status
Simulation time 6187448266 ps
CPU time 12.55 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:53:57 PM PDT 24
Peak memory 198900 kb
Host smart-79e87aec-154c-4e72-8071-9d202db2e51c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1276957470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1276957470
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1873200634
Short name T590
Test name
Test status
Simulation time 113040464260 ps
CPU time 77.92 seconds
Started Jul 10 04:53:44 PM PDT 24
Finished Jul 10 04:55:03 PM PDT 24
Peak memory 199632 kb
Host smart-d910a7fd-a124-4956-844f-fa1c7e794774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873200634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1873200634
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1983010230
Short name T964
Test name
Test status
Simulation time 6044454537 ps
CPU time 5.09 seconds
Started Jul 10 04:53:45 PM PDT 24
Finished Jul 10 04:53:51 PM PDT 24
Peak memory 196292 kb
Host smart-86afccbd-bcc1-4566-96f3-bd7913870c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983010230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1983010230
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3114006282
Short name T783
Test name
Test status
Simulation time 267442488 ps
CPU time 2.17 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:53:47 PM PDT 24
Peak memory 198028 kb
Host smart-93854a33-82df-4c77-b083-ab558e9c8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114006282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3114006282
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.4033199326
Short name T1055
Test name
Test status
Simulation time 601128066052 ps
CPU time 1011.6 seconds
Started Jul 10 04:53:42 PM PDT 24
Finished Jul 10 05:10:34 PM PDT 24
Peak memory 199808 kb
Host smart-aa402c6e-4160-4473-a70d-88dfd6c90701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033199326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4033199326
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.433669279
Short name T1018
Test name
Test status
Simulation time 312433100 ps
CPU time 1.72 seconds
Started Jul 10 04:53:48 PM PDT 24
Finished Jul 10 04:53:50 PM PDT 24
Peak memory 198960 kb
Host smart-611fe377-5ce0-4bd8-94fb-b87551296aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433669279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.433669279
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.68949516
Short name T765
Test name
Test status
Simulation time 75489017818 ps
CPU time 30.14 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:54:14 PM PDT 24
Peak memory 199732 kb
Host smart-66e18d8a-5c9d-474b-a1eb-1e988e0bda78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68949516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.68949516
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2654268721
Short name T835
Test name
Test status
Simulation time 8761564419 ps
CPU time 13.67 seconds
Started Jul 10 04:59:31 PM PDT 24
Finished Jul 10 04:59:46 PM PDT 24
Peak memory 198192 kb
Host smart-ef7007dc-530b-4f07-b4d0-ca8aba91918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654268721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2654268721
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3837565945
Short name T449
Test name
Test status
Simulation time 112159384612 ps
CPU time 82.13 seconds
Started Jul 10 04:59:32 PM PDT 24
Finished Jul 10 05:00:56 PM PDT 24
Peak memory 199832 kb
Host smart-942363e8-08a2-43c6-8ab9-f431d1aa6b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837565945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3837565945
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.222186064
Short name T162
Test name
Test status
Simulation time 28400374510 ps
CPU time 49.97 seconds
Started Jul 10 04:59:31 PM PDT 24
Finished Jul 10 05:00:23 PM PDT 24
Peak memory 199820 kb
Host smart-dd0ae4bb-b563-4632-ada1-c8c43f046f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222186064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.222186064
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.478334672
Short name T103
Test name
Test status
Simulation time 67007267161 ps
CPU time 103.23 seconds
Started Jul 10 04:59:31 PM PDT 24
Finished Jul 10 05:01:15 PM PDT 24
Peak memory 199844 kb
Host smart-8ee9b49d-fdc7-4a93-b60b-1b813281dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478334672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.478334672
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.373493146
Short name T528
Test name
Test status
Simulation time 65603994466 ps
CPU time 112.14 seconds
Started Jul 10 04:59:31 PM PDT 24
Finished Jul 10 05:01:25 PM PDT 24
Peak memory 199712 kb
Host smart-47a1a7c8-ee3c-4658-b643-15e67e3ab48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373493146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.373493146
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3152818957
Short name T423
Test name
Test status
Simulation time 77300050670 ps
CPU time 59 seconds
Started Jul 10 04:59:32 PM PDT 24
Finished Jul 10 05:00:32 PM PDT 24
Peak memory 199796 kb
Host smart-feaba717-9a83-4668-a626-56fe454b9ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152818957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3152818957
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2981457817
Short name T470
Test name
Test status
Simulation time 22592228018 ps
CPU time 45.51 seconds
Started Jul 10 04:59:32 PM PDT 24
Finished Jul 10 05:00:19 PM PDT 24
Peak memory 200064 kb
Host smart-084f839c-09e8-4fd8-97b2-379111152c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981457817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2981457817
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2515498609
Short name T750
Test name
Test status
Simulation time 84778409163 ps
CPU time 125.19 seconds
Started Jul 10 04:59:32 PM PDT 24
Finished Jul 10 05:01:39 PM PDT 24
Peak memory 199836 kb
Host smart-43e50337-ac59-44c4-8fdf-a03371f0a36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515498609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2515498609
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2763297453
Short name T1164
Test name
Test status
Simulation time 13765049 ps
CPU time 0.55 seconds
Started Jul 10 04:53:50 PM PDT 24
Finished Jul 10 04:53:52 PM PDT 24
Peak memory 195156 kb
Host smart-b6d39da6-89b9-4573-bac0-ca7fee6b3e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763297453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2763297453
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3370694931
Short name T684
Test name
Test status
Simulation time 31878664588 ps
CPU time 11.25 seconds
Started Jul 10 04:53:46 PM PDT 24
Finished Jul 10 04:53:58 PM PDT 24
Peak memory 199684 kb
Host smart-60f19995-40b8-4b30-98d7-d5d581305613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370694931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3370694931
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.4149344690
Short name T138
Test name
Test status
Simulation time 113130162281 ps
CPU time 246.99 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:57:51 PM PDT 24
Peak memory 199788 kb
Host smart-ff2355ac-b2ff-470d-8583-eae3f915141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149344690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4149344690
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2889526275
Short name T754
Test name
Test status
Simulation time 113247305009 ps
CPU time 72.18 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:54:57 PM PDT 24
Peak memory 199752 kb
Host smart-2d9a05e6-04e6-41b3-821b-2412cd62ab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889526275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2889526275
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2422238647
Short name T911
Test name
Test status
Simulation time 33200890478 ps
CPU time 53.31 seconds
Started Jul 10 04:53:48 PM PDT 24
Finished Jul 10 04:54:42 PM PDT 24
Peak memory 199828 kb
Host smart-2cc0dc30-ced1-4453-a1ed-290472ecc35a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422238647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2422238647
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.50881014
Short name T398
Test name
Test status
Simulation time 202304750260 ps
CPU time 835.44 seconds
Started Jul 10 04:53:52 PM PDT 24
Finished Jul 10 05:07:49 PM PDT 24
Peak memory 199824 kb
Host smart-fd86e615-d632-4faf-808f-4351dcb1656a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50881014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.50881014
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2065215228
Short name T1062
Test name
Test status
Simulation time 7988723871 ps
CPU time 11.45 seconds
Started Jul 10 04:53:51 PM PDT 24
Finished Jul 10 04:54:03 PM PDT 24
Peak memory 199376 kb
Host smart-a7c24bc6-79e5-439f-b584-04bc9db102c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065215228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2065215228
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.56646932
Short name T945
Test name
Test status
Simulation time 21648203776 ps
CPU time 31.53 seconds
Started Jul 10 04:53:46 PM PDT 24
Finished Jul 10 04:54:19 PM PDT 24
Peak memory 196076 kb
Host smart-780fe7c5-c072-400f-b13d-9919808e5748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56646932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.56646932
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1315609476
Short name T710
Test name
Test status
Simulation time 22154658949 ps
CPU time 585.35 seconds
Started Jul 10 04:53:52 PM PDT 24
Finished Jul 10 05:03:38 PM PDT 24
Peak memory 199884 kb
Host smart-be9c9097-9e30-4367-88b0-e12f9616bed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315609476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1315609476
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3013055550
Short name T852
Test name
Test status
Simulation time 5714314965 ps
CPU time 8.44 seconds
Started Jul 10 04:53:45 PM PDT 24
Finished Jul 10 04:53:55 PM PDT 24
Peak memory 199312 kb
Host smart-371a75e5-2b02-4f58-9420-62760e85884a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013055550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3013055550
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.4235535235
Short name T1146
Test name
Test status
Simulation time 178271323320 ps
CPU time 74.99 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:55:00 PM PDT 24
Peak memory 199736 kb
Host smart-c7c83f46-5306-42c1-a0ee-91ed2def56d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235535235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4235535235
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3660898715
Short name T478
Test name
Test status
Simulation time 3040933060 ps
CPU time 1.74 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:53:47 PM PDT 24
Peak memory 196060 kb
Host smart-33be4540-1243-41f9-a2f5-9d2e5fbee114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660898715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3660898715
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1013757774
Short name T531
Test name
Test status
Simulation time 282316645 ps
CPU time 1.12 seconds
Started Jul 10 04:53:48 PM PDT 24
Finished Jul 10 04:53:49 PM PDT 24
Peak memory 198252 kb
Host smart-abbfcad2-1c36-4f6d-8143-f836a74ed044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013757774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1013757774
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1659160173
Short name T1143
Test name
Test status
Simulation time 249977747844 ps
CPU time 89.59 seconds
Started Jul 10 04:53:49 PM PDT 24
Finished Jul 10 04:55:20 PM PDT 24
Peak memory 199704 kb
Host smart-eec048fa-a5fd-44e4-b126-445dcf244bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659160173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1659160173
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1395527751
Short name T608
Test name
Test status
Simulation time 17027374481 ps
CPU time 286.62 seconds
Started Jul 10 04:53:51 PM PDT 24
Finished Jul 10 04:58:39 PM PDT 24
Peak memory 208204 kb
Host smart-1d8df03f-af98-430d-af4a-357e59dac156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395527751 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1395527751
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1143978466
Short name T413
Test name
Test status
Simulation time 781820554 ps
CPU time 2.72 seconds
Started Jul 10 04:53:43 PM PDT 24
Finished Jul 10 04:53:48 PM PDT 24
Peak memory 199560 kb
Host smart-0b69f7bd-df5e-41bc-bc7a-12c621857076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143978466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1143978466
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.866840533
Short name T278
Test name
Test status
Simulation time 44241043606 ps
CPU time 62.94 seconds
Started Jul 10 04:53:46 PM PDT 24
Finished Jul 10 04:54:50 PM PDT 24
Peak memory 199788 kb
Host smart-5b50d85c-3dd3-47a3-886a-f86f7d67afd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866840533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.866840533
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1311445882
Short name T298
Test name
Test status
Simulation time 22330600501 ps
CPU time 33.27 seconds
Started Jul 10 04:59:32 PM PDT 24
Finished Jul 10 05:00:07 PM PDT 24
Peak memory 199800 kb
Host smart-6b998ab9-e09c-4e80-9b1f-189190fcb48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311445882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1311445882
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1259951822
Short name T160
Test name
Test status
Simulation time 115939908162 ps
CPU time 184.6 seconds
Started Jul 10 04:59:33 PM PDT 24
Finished Jul 10 05:02:39 PM PDT 24
Peak memory 199792 kb
Host smart-25d7ef01-126b-4eaf-87bc-7fe399bef430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259951822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1259951822
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2848201349
Short name T708
Test name
Test status
Simulation time 127658821485 ps
CPU time 179.52 seconds
Started Jul 10 04:59:34 PM PDT 24
Finished Jul 10 05:02:34 PM PDT 24
Peak memory 199868 kb
Host smart-268b16c7-e110-428b-91bf-ef96b3c30ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848201349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2848201349
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2245228181
Short name T876
Test name
Test status
Simulation time 143549635771 ps
CPU time 30.83 seconds
Started Jul 10 04:59:41 PM PDT 24
Finished Jul 10 05:00:12 PM PDT 24
Peak memory 199908 kb
Host smart-f7a4f6ab-c682-484a-ac55-1987d9a0597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245228181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2245228181
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4247817133
Short name T711
Test name
Test status
Simulation time 133927415910 ps
CPU time 199.86 seconds
Started Jul 10 04:59:40 PM PDT 24
Finished Jul 10 05:03:00 PM PDT 24
Peak memory 199808 kb
Host smart-e3e798eb-a4f3-4dc4-9669-60aa7fcfd30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247817133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4247817133
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1072015527
Short name T71
Test name
Test status
Simulation time 125128056120 ps
CPU time 199.86 seconds
Started Jul 10 04:59:39 PM PDT 24
Finished Jul 10 05:03:00 PM PDT 24
Peak memory 199800 kb
Host smart-cec68e89-1132-4cde-8cc2-3792f7483268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072015527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1072015527
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1632032641
Short name T1110
Test name
Test status
Simulation time 33534989701 ps
CPU time 40.5 seconds
Started Jul 10 04:59:39 PM PDT 24
Finished Jul 10 05:00:21 PM PDT 24
Peak memory 199784 kb
Host smart-f20a58a5-0bdb-4773-86af-6e50c4d465e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632032641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1632032641
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.902502255
Short name T833
Test name
Test status
Simulation time 62324499908 ps
CPU time 32.34 seconds
Started Jul 10 04:59:38 PM PDT 24
Finished Jul 10 05:00:11 PM PDT 24
Peak memory 199568 kb
Host smart-9bc984f7-601e-4fc3-87f3-2b12a29e01de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902502255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.902502255
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.379302741
Short name T484
Test name
Test status
Simulation time 29017053 ps
CPU time 0.56 seconds
Started Jul 10 04:51:54 PM PDT 24
Finished Jul 10 04:51:56 PM PDT 24
Peak memory 195436 kb
Host smart-c621cae0-0896-424b-b573-e6d9a0dbc3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379302741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.379302741
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1568198755
Short name T743
Test name
Test status
Simulation time 152116114076 ps
CPU time 57.2 seconds
Started Jul 10 04:51:37 PM PDT 24
Finished Jul 10 04:52:35 PM PDT 24
Peak memory 199840 kb
Host smart-41bcdda6-1bc7-4aad-a875-cb322ea96715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568198755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1568198755
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.82487335
Short name T311
Test name
Test status
Simulation time 142308838783 ps
CPU time 233.79 seconds
Started Jul 10 04:51:54 PM PDT 24
Finished Jul 10 04:55:49 PM PDT 24
Peak memory 199832 kb
Host smart-3d781041-7960-4b91-b0f5-e08b9832273d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82487335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.82487335
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1449076972
Short name T288
Test name
Test status
Simulation time 31465957128 ps
CPU time 17.7 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:52:12 PM PDT 24
Peak memory 199752 kb
Host smart-5d773e6f-7d3a-4ee1-8507-6bfce6bd6ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449076972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1449076972
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.85276370
Short name T429
Test name
Test status
Simulation time 5079973759 ps
CPU time 9.22 seconds
Started Jul 10 04:51:54 PM PDT 24
Finished Jul 10 04:52:05 PM PDT 24
Peak memory 199796 kb
Host smart-431f5222-27fc-4b83-be36-1af59627556a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85276370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.85276370
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1302541491
Short name T643
Test name
Test status
Simulation time 115773387208 ps
CPU time 290.23 seconds
Started Jul 10 04:51:56 PM PDT 24
Finished Jul 10 04:56:48 PM PDT 24
Peak memory 199844 kb
Host smart-4e4ab466-7392-4781-8145-b542bf50aab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302541491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1302541491
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2035029907
Short name T1086
Test name
Test status
Simulation time 6217832643 ps
CPU time 7.15 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:52:02 PM PDT 24
Peak memory 199580 kb
Host smart-f8ea735f-5e8c-4a6e-bc1f-864919bd069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035029907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2035029907
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1821654634
Short name T269
Test name
Test status
Simulation time 126046719910 ps
CPU time 49.76 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:52:44 PM PDT 24
Peak memory 199996 kb
Host smart-a995165e-8f61-4c0d-b4c8-b1b27914e0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821654634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1821654634
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2060457766
Short name T416
Test name
Test status
Simulation time 15201739162 ps
CPU time 231.41 seconds
Started Jul 10 04:51:55 PM PDT 24
Finished Jul 10 04:55:48 PM PDT 24
Peak memory 199848 kb
Host smart-e7ab8e16-23f5-4b2c-963f-f90bd8c1fcd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060457766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2060457766
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.56554773
Short name T437
Test name
Test status
Simulation time 1698520074 ps
CPU time 2.03 seconds
Started Jul 10 04:51:54 PM PDT 24
Finished Jul 10 04:51:58 PM PDT 24
Peak memory 198488 kb
Host smart-443ee311-081e-4cbc-a81d-2e8038a9161c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56554773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.56554773
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4030551518
Short name T603
Test name
Test status
Simulation time 37453386091 ps
CPU time 16.2 seconds
Started Jul 10 04:51:50 PM PDT 24
Finished Jul 10 04:52:07 PM PDT 24
Peak memory 199764 kb
Host smart-892e8425-b0fb-4cfc-a35c-304023d085ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030551518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4030551518
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.500808458
Short name T879
Test name
Test status
Simulation time 1890841569 ps
CPU time 3.17 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:51:57 PM PDT 24
Peak memory 195420 kb
Host smart-9a18b403-5a88-46c2-b74a-224c630acff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500808458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.500808458
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2867678817
Short name T29
Test name
Test status
Simulation time 38144370 ps
CPU time 0.79 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:51:55 PM PDT 24
Peak memory 218184 kb
Host smart-461b9ec3-f87c-4f7c-acbe-4e9d8b705896
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867678817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2867678817
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2168638598
Short name T977
Test name
Test status
Simulation time 725347036 ps
CPU time 2.66 seconds
Started Jul 10 04:51:41 PM PDT 24
Finished Jul 10 04:51:44 PM PDT 24
Peak memory 199328 kb
Host smart-41b1c587-3d8d-46af-b6ef-41c5f8701958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168638598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2168638598
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1256624676
Short name T501
Test name
Test status
Simulation time 37611455015 ps
CPU time 732.09 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 05:04:07 PM PDT 24
Peak memory 199812 kb
Host smart-7890a29c-d717-4adf-a9c5-d1e4b9291300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256624676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1256624676
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.280391677
Short name T15
Test name
Test status
Simulation time 74616155100 ps
CPU time 816.24 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 05:05:32 PM PDT 24
Peak memory 216256 kb
Host smart-704718aa-e388-4d29-86f1-6927932e68fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280391677 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.280391677
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3506775416
Short name T1145
Test name
Test status
Simulation time 1837717831 ps
CPU time 1.47 seconds
Started Jul 10 04:51:51 PM PDT 24
Finished Jul 10 04:51:53 PM PDT 24
Peak memory 196720 kb
Host smart-524bf08c-80d8-4dc3-beee-4eeecb7b488f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506775416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3506775416
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2020389528
Short name T987
Test name
Test status
Simulation time 38909741292 ps
CPU time 33.3 seconds
Started Jul 10 04:51:39 PM PDT 24
Finished Jul 10 04:52:13 PM PDT 24
Peak memory 199832 kb
Host smart-d6271f66-22ac-4f2b-8d92-81486e67793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020389528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2020389528
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.129117587
Short name T104
Test name
Test status
Simulation time 39160647 ps
CPU time 0.54 seconds
Started Jul 10 04:53:54 PM PDT 24
Finished Jul 10 04:53:56 PM PDT 24
Peak memory 194128 kb
Host smart-7e12580e-1f8d-4e34-a0f1-a35b7acdd682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129117587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.129117587
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.670368909
Short name T814
Test name
Test status
Simulation time 41750946049 ps
CPU time 23.57 seconds
Started Jul 10 04:53:52 PM PDT 24
Finished Jul 10 04:54:17 PM PDT 24
Peak memory 199840 kb
Host smart-cb7f13d8-7ac4-4064-a57e-01e6a8bc2b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670368909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.670368909
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.715437240
Short name T1005
Test name
Test status
Simulation time 55495418358 ps
CPU time 82.77 seconds
Started Jul 10 04:53:48 PM PDT 24
Finished Jul 10 04:55:12 PM PDT 24
Peak memory 199840 kb
Host smart-616b9e2f-4e44-423a-9fd8-6284044cf645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715437240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.715437240
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2332491053
Short name T194
Test name
Test status
Simulation time 97493688026 ps
CPU time 120.01 seconds
Started Jul 10 04:53:53 PM PDT 24
Finished Jul 10 04:55:54 PM PDT 24
Peak memory 199756 kb
Host smart-f67ce9fe-16a1-4225-b7de-111440fa4cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332491053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2332491053
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3409835349
Short name T941
Test name
Test status
Simulation time 43658649897 ps
CPU time 58.69 seconds
Started Jul 10 04:53:50 PM PDT 24
Finished Jul 10 04:54:50 PM PDT 24
Peak memory 199768 kb
Host smart-143a189a-2bd9-4851-84ac-7f533d7972e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409835349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3409835349
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2523591649
Short name T1116
Test name
Test status
Simulation time 107080031300 ps
CPU time 1175.2 seconds
Started Jul 10 04:53:59 PM PDT 24
Finished Jul 10 05:13:35 PM PDT 24
Peak memory 199852 kb
Host smart-a1c62f59-1e09-4882-899c-530412f1cd58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523591649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2523591649
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2485199879
Short name T1169
Test name
Test status
Simulation time 12037815396 ps
CPU time 21.22 seconds
Started Jul 10 04:53:50 PM PDT 24
Finished Jul 10 04:54:12 PM PDT 24
Peak memory 198748 kb
Host smart-0a4bb7c9-1f38-4421-9526-86edf1ececac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485199879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2485199879
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2414533217
Short name T720
Test name
Test status
Simulation time 123195088446 ps
CPU time 55.52 seconds
Started Jul 10 04:53:49 PM PDT 24
Finished Jul 10 04:54:46 PM PDT 24
Peak memory 200012 kb
Host smart-c8d800ef-cb01-429a-a5ef-1dc8220fe1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414533217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2414533217
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1651563758
Short name T330
Test name
Test status
Simulation time 15730414407 ps
CPU time 699.09 seconds
Started Jul 10 04:53:56 PM PDT 24
Finished Jul 10 05:05:36 PM PDT 24
Peak memory 199824 kb
Host smart-d1520ed7-5dc5-46bb-ac23-41b4be9df57f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651563758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1651563758
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2130630632
Short name T772
Test name
Test status
Simulation time 3709606875 ps
CPU time 30.33 seconds
Started Jul 10 04:53:49 PM PDT 24
Finished Jul 10 04:54:20 PM PDT 24
Peak memory 198900 kb
Host smart-bbb89f33-5982-4ae4-89b6-3644d62d4dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130630632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2130630632
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.751423252
Short name T731
Test name
Test status
Simulation time 24362287329 ps
CPU time 9.63 seconds
Started Jul 10 04:53:49 PM PDT 24
Finished Jul 10 04:53:59 PM PDT 24
Peak memory 199856 kb
Host smart-53d36688-c317-402b-926c-815e21aa3ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751423252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.751423252
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3885387108
Short name T613
Test name
Test status
Simulation time 3275114658 ps
CPU time 3.26 seconds
Started Jul 10 04:53:51 PM PDT 24
Finished Jul 10 04:53:55 PM PDT 24
Peak memory 195852 kb
Host smart-11939e5f-cacd-44b4-b3b9-891ff84d7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885387108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3885387108
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1109523631
Short name T401
Test name
Test status
Simulation time 840371526 ps
CPU time 3.52 seconds
Started Jul 10 04:53:49 PM PDT 24
Finished Jul 10 04:53:54 PM PDT 24
Peak memory 199444 kb
Host smart-4b82ab25-243f-41ff-b120-c1cda941e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109523631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1109523631
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1347784305
Short name T1103
Test name
Test status
Simulation time 238685243579 ps
CPU time 314.73 seconds
Started Jul 10 04:54:00 PM PDT 24
Finished Jul 10 04:59:16 PM PDT 24
Peak memory 199752 kb
Host smart-c289ffbb-7507-4c0a-9dbc-74c36ca7e9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347784305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1347784305
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.181253437
Short name T1114
Test name
Test status
Simulation time 139139673689 ps
CPU time 1295.1 seconds
Started Jul 10 04:54:00 PM PDT 24
Finished Jul 10 05:15:36 PM PDT 24
Peak memory 216372 kb
Host smart-473bd14a-897b-4bdb-bbec-21ec5d9ec781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181253437 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.181253437
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.298928654
Short name T1128
Test name
Test status
Simulation time 7385287944 ps
CPU time 15.05 seconds
Started Jul 10 04:53:49 PM PDT 24
Finished Jul 10 04:54:06 PM PDT 24
Peak memory 199816 kb
Host smart-94a14420-861b-484b-ba11-e9ab60dc83e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298928654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.298928654
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2589076036
Short name T636
Test name
Test status
Simulation time 67833716307 ps
CPU time 73.91 seconds
Started Jul 10 04:53:50 PM PDT 24
Finished Jul 10 04:55:05 PM PDT 24
Peak memory 199744 kb
Host smart-333ae65a-8207-4fbe-bd5f-531396b6d06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589076036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2589076036
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1225076918
Short name T694
Test name
Test status
Simulation time 14305413752 ps
CPU time 34.54 seconds
Started Jul 10 04:59:40 PM PDT 24
Finished Jul 10 05:00:15 PM PDT 24
Peak memory 199784 kb
Host smart-0aab3089-7286-41b3-bae9-efe9d422d515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225076918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1225076918
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1556226019
Short name T734
Test name
Test status
Simulation time 97560147131 ps
CPU time 50.53 seconds
Started Jul 10 04:59:40 PM PDT 24
Finished Jul 10 05:00:31 PM PDT 24
Peak memory 199772 kb
Host smart-2851a417-82a8-47d1-947e-5b0e4c72ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556226019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1556226019
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3700503109
Short name T1017
Test name
Test status
Simulation time 176376955120 ps
CPU time 22.72 seconds
Started Jul 10 04:59:46 PM PDT 24
Finished Jul 10 05:00:10 PM PDT 24
Peak memory 199820 kb
Host smart-61098fd9-7df1-413c-85bd-a03d8fb3e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700503109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3700503109
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3259633667
Short name T213
Test name
Test status
Simulation time 19126292258 ps
CPU time 15.92 seconds
Started Jul 10 04:59:45 PM PDT 24
Finished Jul 10 05:00:02 PM PDT 24
Peak memory 199712 kb
Host smart-8cce8a8a-067c-4dc5-80b1-9d6c07eb62fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259633667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3259633667
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3286383864
Short name T592
Test name
Test status
Simulation time 3190951303 ps
CPU time 6.19 seconds
Started Jul 10 04:59:46 PM PDT 24
Finished Jul 10 04:59:53 PM PDT 24
Peak memory 199824 kb
Host smart-625b52a5-c7bb-496c-8392-31d61f8a8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286383864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3286383864
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.454703379
Short name T927
Test name
Test status
Simulation time 13898559228 ps
CPU time 20.3 seconds
Started Jul 10 04:59:48 PM PDT 24
Finished Jul 10 05:00:09 PM PDT 24
Peak memory 199800 kb
Host smart-a7f0da97-ed4c-486e-a7fb-9b54d64268e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454703379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.454703379
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2945575577
Short name T920
Test name
Test status
Simulation time 41406293027 ps
CPU time 63.4 seconds
Started Jul 10 04:59:48 PM PDT 24
Finished Jul 10 05:00:52 PM PDT 24
Peak memory 199772 kb
Host smart-d626dc71-e79e-40d9-976e-72b311ee414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945575577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2945575577
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3739570247
Short name T861
Test name
Test status
Simulation time 16746051050 ps
CPU time 14.22 seconds
Started Jul 10 04:59:48 PM PDT 24
Finished Jul 10 05:00:03 PM PDT 24
Peak memory 199684 kb
Host smart-b7c92365-0546-4ee2-8f21-61e4a13eeaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739570247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3739570247
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2824911575
Short name T1004
Test name
Test status
Simulation time 74219474685 ps
CPU time 14.05 seconds
Started Jul 10 04:59:45 PM PDT 24
Finished Jul 10 05:00:00 PM PDT 24
Peak memory 199800 kb
Host smart-50a11ab6-c4e3-4e46-9b1d-9a610810aa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824911575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2824911575
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4276988533
Short name T908
Test name
Test status
Simulation time 41256809 ps
CPU time 0.55 seconds
Started Jul 10 04:54:07 PM PDT 24
Finished Jul 10 04:54:08 PM PDT 24
Peak memory 194684 kb
Host smart-89e57934-a9ba-4652-a6a3-e3baf7b45b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276988533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4276988533
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.645890701
Short name T1008
Test name
Test status
Simulation time 166811751980 ps
CPU time 221.13 seconds
Started Jul 10 04:53:58 PM PDT 24
Finished Jul 10 04:57:40 PM PDT 24
Peak memory 199928 kb
Host smart-456d5502-1d4d-4457-87a9-4201a21533ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645890701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.645890701
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2622394741
Short name T216
Test name
Test status
Simulation time 34179356704 ps
CPU time 33.64 seconds
Started Jul 10 04:53:56 PM PDT 24
Finished Jul 10 04:54:31 PM PDT 24
Peak memory 199840 kb
Host smart-5041f2fb-b12f-49b7-8477-6da61f48798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622394741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2622394741
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1310839474
Short name T338
Test name
Test status
Simulation time 15125336546 ps
CPU time 3.27 seconds
Started Jul 10 04:53:59 PM PDT 24
Finished Jul 10 04:54:03 PM PDT 24
Peak memory 196836 kb
Host smart-011202f9-cb06-4034-920a-33c629343bb7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310839474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1310839474
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3921739131
Short name T938
Test name
Test status
Simulation time 132519100681 ps
CPU time 235.56 seconds
Started Jul 10 04:54:05 PM PDT 24
Finished Jul 10 04:58:02 PM PDT 24
Peak memory 199764 kb
Host smart-1f6f81b3-ecbb-442f-8da7-e5c75e7fb8e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921739131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3921739131
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3474416830
Short name T654
Test name
Test status
Simulation time 8323046334 ps
CPU time 10.32 seconds
Started Jul 10 04:54:02 PM PDT 24
Finished Jul 10 04:54:14 PM PDT 24
Peak memory 199040 kb
Host smart-c9f6b6a0-690c-46bd-93ee-ab67eacf7d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474416830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3474416830
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3290516641
Short name T128
Test name
Test status
Simulation time 173953743924 ps
CPU time 36.62 seconds
Started Jul 10 04:53:55 PM PDT 24
Finished Jul 10 04:54:33 PM PDT 24
Peak memory 199944 kb
Host smart-fa12afcc-22ec-49c9-a4fb-77be5dfe1fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290516641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3290516641
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3909163644
Short name T1009
Test name
Test status
Simulation time 17479733093 ps
CPU time 267.16 seconds
Started Jul 10 04:54:05 PM PDT 24
Finished Jul 10 04:58:34 PM PDT 24
Peak memory 199884 kb
Host smart-789a1fe4-d802-427c-86fe-dc74002c549d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909163644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3909163644
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2633168007
Short name T397
Test name
Test status
Simulation time 1584469611 ps
CPU time 5.91 seconds
Started Jul 10 04:53:55 PM PDT 24
Finished Jul 10 04:54:02 PM PDT 24
Peak memory 197852 kb
Host smart-d9234a4c-7069-4d31-8b5b-aa0afc56eccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633168007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2633168007
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1359482398
Short name T1102
Test name
Test status
Simulation time 92816726416 ps
CPU time 16.56 seconds
Started Jul 10 04:53:56 PM PDT 24
Finished Jul 10 04:54:13 PM PDT 24
Peak memory 199652 kb
Host smart-ba492a5a-2285-4642-b71a-7d20ff05f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359482398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1359482398
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3141827513
Short name T895
Test name
Test status
Simulation time 4548252880 ps
CPU time 6.91 seconds
Started Jul 10 04:53:55 PM PDT 24
Finished Jul 10 04:54:03 PM PDT 24
Peak memory 196588 kb
Host smart-553c4df0-50b5-47ab-bbf1-91f7d71ef869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141827513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3141827513
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.53915157
Short name T410
Test name
Test status
Simulation time 689461398 ps
CPU time 2.69 seconds
Started Jul 10 04:53:56 PM PDT 24
Finished Jul 10 04:54:00 PM PDT 24
Peak memory 199312 kb
Host smart-c5c29fb9-3a8c-4fb3-8b7c-1e4d1730301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53915157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.53915157
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1873086729
Short name T441
Test name
Test status
Simulation time 112069687255 ps
CPU time 46.65 seconds
Started Jul 10 04:54:06 PM PDT 24
Finished Jul 10 04:54:54 PM PDT 24
Peak memory 199876 kb
Host smart-55f10721-aac9-440a-b518-4b8ad3b67112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873086729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1873086729
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1785389215
Short name T59
Test name
Test status
Simulation time 51020345843 ps
CPU time 440.53 seconds
Started Jul 10 04:54:02 PM PDT 24
Finished Jul 10 05:01:24 PM PDT 24
Peak memory 216360 kb
Host smart-e2504fa7-b52a-4529-8d15-c10bef3d3a04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785389215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1785389215
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.598996510
Short name T1111
Test name
Test status
Simulation time 806724274 ps
CPU time 2.56 seconds
Started Jul 10 04:54:01 PM PDT 24
Finished Jul 10 04:54:05 PM PDT 24
Peak memory 198244 kb
Host smart-0f76cdae-8f2b-4bc2-bc8d-f4c90c5e21db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598996510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.598996510
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2136487054
Short name T730
Test name
Test status
Simulation time 9051244720 ps
CPU time 12.64 seconds
Started Jul 10 04:53:55 PM PDT 24
Finished Jul 10 04:54:09 PM PDT 24
Peak memory 199628 kb
Host smart-205aa060-5dff-4f04-a783-37b6bf55f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136487054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2136487054
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.4248520224
Short name T626
Test name
Test status
Simulation time 44369628796 ps
CPU time 64 seconds
Started Jul 10 04:59:46 PM PDT 24
Finished Jul 10 05:00:50 PM PDT 24
Peak memory 199696 kb
Host smart-c08025ed-81e2-4a5f-8e04-4aa8a4f857ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248520224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4248520224
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3190822585
Short name T979
Test name
Test status
Simulation time 25019211875 ps
CPU time 42.2 seconds
Started Jul 10 04:59:46 PM PDT 24
Finished Jul 10 05:00:28 PM PDT 24
Peak memory 199840 kb
Host smart-69febfd1-98dc-421e-85ee-f44339a55237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190822585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3190822585
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.592929363
Short name T195
Test name
Test status
Simulation time 147222247329 ps
CPU time 288.55 seconds
Started Jul 10 04:59:46 PM PDT 24
Finished Jul 10 05:04:35 PM PDT 24
Peak memory 199840 kb
Host smart-a72d6d1e-9f8f-47da-8306-0451ee531201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592929363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.592929363
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3581105768
Short name T1147
Test name
Test status
Simulation time 37951201607 ps
CPU time 15.3 seconds
Started Jul 10 04:59:47 PM PDT 24
Finished Jul 10 05:00:03 PM PDT 24
Peak memory 199844 kb
Host smart-ac8f1bc1-36c0-4c26-8e44-5198d0a82655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581105768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3581105768
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1003899406
Short name T667
Test name
Test status
Simulation time 237402571523 ps
CPU time 24.98 seconds
Started Jul 10 05:00:21 PM PDT 24
Finished Jul 10 05:00:47 PM PDT 24
Peak memory 199836 kb
Host smart-ccb49e1e-d235-4f31-9a74-aed0bfae3f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003899406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1003899406
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1566087750
Short name T811
Test name
Test status
Simulation time 103076344221 ps
CPU time 46.84 seconds
Started Jul 10 05:00:29 PM PDT 24
Finished Jul 10 05:01:17 PM PDT 24
Peak memory 199844 kb
Host smart-99d9ef7c-64ea-4226-89d1-6e557c20fffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566087750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1566087750
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3340249292
Short name T418
Test name
Test status
Simulation time 20363075 ps
CPU time 0.52 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:54:18 PM PDT 24
Peak memory 194412 kb
Host smart-e4114946-037e-4d03-97c2-616550a44142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340249292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3340249292
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3480739132
Short name T448
Test name
Test status
Simulation time 166843450021 ps
CPU time 98.33 seconds
Started Jul 10 04:54:02 PM PDT 24
Finished Jul 10 04:55:42 PM PDT 24
Peak memory 199836 kb
Host smart-80b7b72d-d96e-4700-b4ff-8b50fde80129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480739132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3480739132
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2493662509
Short name T277
Test name
Test status
Simulation time 149933940591 ps
CPU time 223.9 seconds
Started Jul 10 04:54:02 PM PDT 24
Finished Jul 10 04:57:46 PM PDT 24
Peak memory 199824 kb
Host smart-235aad8f-b7aa-4670-b61a-8ba78e0da77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493662509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2493662509
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.64831691
Short name T949
Test name
Test status
Simulation time 88359741638 ps
CPU time 193.77 seconds
Started Jul 10 04:54:04 PM PDT 24
Finished Jul 10 04:57:19 PM PDT 24
Peak memory 199748 kb
Host smart-b8d07f84-5332-437c-824a-f7b633058289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64831691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.64831691
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1684437291
Short name T755
Test name
Test status
Simulation time 33080146207 ps
CPU time 51.45 seconds
Started Jul 10 04:54:05 PM PDT 24
Finished Jul 10 04:54:58 PM PDT 24
Peak memory 198964 kb
Host smart-15730c96-0994-41c3-b2ac-7d899d623dd5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684437291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1684437291
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.325308916
Short name T953
Test name
Test status
Simulation time 52118888781 ps
CPU time 362.53 seconds
Started Jul 10 04:54:10 PM PDT 24
Finished Jul 10 05:00:13 PM PDT 24
Peak memory 199608 kb
Host smart-591da982-17df-4e82-bee3-3f3c8a0e3b98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325308916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.325308916
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2116232202
Short name T728
Test name
Test status
Simulation time 3114865694 ps
CPU time 6.21 seconds
Started Jul 10 04:54:09 PM PDT 24
Finished Jul 10 04:54:16 PM PDT 24
Peak memory 199804 kb
Host smart-b8ca9876-7b54-4dc7-94fa-6bdf7470cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116232202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2116232202
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.963108125
Short name T273
Test name
Test status
Simulation time 144293572859 ps
CPU time 236.53 seconds
Started Jul 10 04:54:05 PM PDT 24
Finished Jul 10 04:58:03 PM PDT 24
Peak memory 199644 kb
Host smart-4a847061-e4c9-4517-b5fb-1f8dd4fd6a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963108125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.963108125
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2774441112
Short name T1002
Test name
Test status
Simulation time 12712402497 ps
CPU time 370.13 seconds
Started Jul 10 04:54:11 PM PDT 24
Finished Jul 10 05:00:22 PM PDT 24
Peak memory 199816 kb
Host smart-1353216d-356f-4c59-aacf-a3afc0d40c83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774441112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2774441112
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2728986510
Short name T550
Test name
Test status
Simulation time 6843073105 ps
CPU time 66.98 seconds
Started Jul 10 04:54:02 PM PDT 24
Finished Jul 10 04:55:10 PM PDT 24
Peak memory 198052 kb
Host smart-49542e7b-73b0-42f0-86f7-d3fcf6c41a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728986510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2728986510
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1599641624
Short name T184
Test name
Test status
Simulation time 140450116023 ps
CPU time 14.58 seconds
Started Jul 10 04:54:08 PM PDT 24
Finished Jul 10 04:54:24 PM PDT 24
Peak memory 199556 kb
Host smart-454d1f22-6734-45ad-ad58-fbc442a74f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599641624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1599641624
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.645886063
Short name T834
Test name
Test status
Simulation time 4192539679 ps
CPU time 7.6 seconds
Started Jul 10 04:54:03 PM PDT 24
Finished Jul 10 04:54:11 PM PDT 24
Peak memory 196608 kb
Host smart-d8348a6d-f73e-44d9-b216-2a917b6cf7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645886063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.645886063
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2406760163
Short name T280
Test name
Test status
Simulation time 5395468997 ps
CPU time 10.76 seconds
Started Jul 10 04:54:02 PM PDT 24
Finished Jul 10 04:54:14 PM PDT 24
Peak memory 199828 kb
Host smart-24be4f1d-ee77-48c1-993e-3098344fb6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406760163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2406760163
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2122098969
Short name T704
Test name
Test status
Simulation time 87353432368 ps
CPU time 132.3 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:56:30 PM PDT 24
Peak memory 199732 kb
Host smart-fa3e26e9-30af-4ea4-b054-9859660be159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122098969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2122098969
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2766783743
Short name T55
Test name
Test status
Simulation time 232252400172 ps
CPU time 506.49 seconds
Started Jul 10 04:54:11 PM PDT 24
Finished Jul 10 05:02:38 PM PDT 24
Peak memory 216524 kb
Host smart-9c362ae5-6c69-42d9-adeb-6a91cd61c863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766783743 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2766783743
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.460288223
Short name T316
Test name
Test status
Simulation time 7781161469 ps
CPU time 7.8 seconds
Started Jul 10 04:54:09 PM PDT 24
Finished Jul 10 04:54:17 PM PDT 24
Peak memory 199800 kb
Host smart-c49d0ec7-01cd-4896-aca7-a689fdde823e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460288223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.460288223
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2270852857
Short name T119
Test name
Test status
Simulation time 25588377562 ps
CPU time 37.55 seconds
Started Jul 10 04:54:06 PM PDT 24
Finished Jul 10 04:54:45 PM PDT 24
Peak memory 199908 kb
Host smart-c8e19e79-d563-4545-9c30-573d06c49e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270852857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2270852857
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3840904581
Short name T106
Test name
Test status
Simulation time 29809468656 ps
CPU time 45.26 seconds
Started Jul 10 05:00:25 PM PDT 24
Finished Jul 10 05:01:11 PM PDT 24
Peak memory 199872 kb
Host smart-5fd994d1-b99a-42e7-9a42-38bb2774e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840904581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3840904581
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.266900724
Short name T925
Test name
Test status
Simulation time 8079764776 ps
CPU time 12.68 seconds
Started Jul 10 05:00:21 PM PDT 24
Finished Jul 10 05:00:35 PM PDT 24
Peak memory 199608 kb
Host smart-022266ed-df62-4ba3-825d-c23c6285dcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266900724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.266900724
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.278160451
Short name T224
Test name
Test status
Simulation time 69162652886 ps
CPU time 281.15 seconds
Started Jul 10 05:00:29 PM PDT 24
Finished Jul 10 05:05:12 PM PDT 24
Peak memory 199828 kb
Host smart-93e87ad6-07e8-4938-bb4a-6a8334750803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278160451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.278160451
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3436322655
Short name T709
Test name
Test status
Simulation time 21857793755 ps
CPU time 33.04 seconds
Started Jul 10 05:00:27 PM PDT 24
Finished Jul 10 05:01:02 PM PDT 24
Peak memory 199740 kb
Host smart-8e32d80d-a1c6-4bee-b97f-aeba7a89d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436322655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3436322655
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1719150451
Short name T974
Test name
Test status
Simulation time 47040391016 ps
CPU time 100.31 seconds
Started Jul 10 05:00:27 PM PDT 24
Finished Jul 10 05:02:08 PM PDT 24
Peak memory 199844 kb
Host smart-2246554b-3a14-45e3-b6a2-f785c0891e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719150451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1719150451
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1526150669
Short name T469
Test name
Test status
Simulation time 17712035780 ps
CPU time 20.88 seconds
Started Jul 10 05:00:31 PM PDT 24
Finished Jul 10 05:00:53 PM PDT 24
Peak memory 199808 kb
Host smart-1d8a2c4f-c78f-4825-9e74-51254af805b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526150669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1526150669
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1159215460
Short name T666
Test name
Test status
Simulation time 97440643180 ps
CPU time 331.99 seconds
Started Jul 10 05:00:29 PM PDT 24
Finished Jul 10 05:06:03 PM PDT 24
Peak memory 199780 kb
Host smart-6e1749d8-5c59-45b2-a87d-3a3769291bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159215460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1159215460
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1181058020
Short name T1076
Test name
Test status
Simulation time 24844836401 ps
CPU time 19.67 seconds
Started Jul 10 05:00:28 PM PDT 24
Finished Jul 10 05:00:49 PM PDT 24
Peak memory 199824 kb
Host smart-1ffe3c97-42d5-4e90-8ad3-208951d125a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181058020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1181058020
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1962779470
Short name T880
Test name
Test status
Simulation time 46229509240 ps
CPU time 56.91 seconds
Started Jul 10 05:00:31 PM PDT 24
Finished Jul 10 05:01:28 PM PDT 24
Peak memory 199832 kb
Host smart-1daabd69-7313-4638-b9c9-d5838c0336c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962779470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1962779470
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2845762855
Short name T1180
Test name
Test status
Simulation time 42236724 ps
CPU time 0.56 seconds
Started Jul 10 04:54:26 PM PDT 24
Finished Jul 10 04:54:28 PM PDT 24
Peak memory 195156 kb
Host smart-72969531-ab0b-436d-abc8-fb43b89aa08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845762855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2845762855
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2837249285
Short name T319
Test name
Test status
Simulation time 78473459142 ps
CPU time 108.65 seconds
Started Jul 10 04:54:16 PM PDT 24
Finished Jul 10 04:56:05 PM PDT 24
Peak memory 199780 kb
Host smart-d3a2e6c3-3f14-46e0-bc28-2f0d2bc87049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837249285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2837249285
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2927015723
Short name T1174
Test name
Test status
Simulation time 26321036806 ps
CPU time 19.4 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:54:38 PM PDT 24
Peak memory 199876 kb
Host smart-912273ae-7ba0-48dc-b3a7-2d63c263bdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927015723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2927015723
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1121808431
Short name T917
Test name
Test status
Simulation time 286987155147 ps
CPU time 171.09 seconds
Started Jul 10 04:54:18 PM PDT 24
Finished Jul 10 04:57:10 PM PDT 24
Peak memory 199824 kb
Host smart-f4c126d0-0777-4b11-881d-13cfe21766d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121808431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1121808431
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2428394667
Short name T3
Test name
Test status
Simulation time 9422767381 ps
CPU time 11.07 seconds
Started Jul 10 04:54:18 PM PDT 24
Finished Jul 10 04:54:30 PM PDT 24
Peak memory 199704 kb
Host smart-471d20d9-e9df-469c-bf97-094aae8b8886
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428394667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2428394667
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2853387139
Short name T894
Test name
Test status
Simulation time 260918617692 ps
CPU time 489.03 seconds
Started Jul 10 04:54:27 PM PDT 24
Finished Jul 10 05:02:38 PM PDT 24
Peak memory 199852 kb
Host smart-5a4a27c4-c03d-4638-b23d-eee1d9b108fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853387139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2853387139
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.472038105
Short name T1131
Test name
Test status
Simulation time 2511802084 ps
CPU time 3.56 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:54:21 PM PDT 24
Peak memory 198940 kb
Host smart-839ff0d3-557e-419c-b95c-1485dffd0f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472038105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.472038105
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1076090029
Short name T997
Test name
Test status
Simulation time 58113681129 ps
CPU time 15.39 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:54:34 PM PDT 24
Peak memory 199944 kb
Host smart-f9be177c-3a36-4206-936e-73d70527764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076090029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1076090029
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3903092945
Short name T1042
Test name
Test status
Simulation time 24036920121 ps
CPU time 1346.9 seconds
Started Jul 10 04:54:26 PM PDT 24
Finished Jul 10 05:16:54 PM PDT 24
Peak memory 199816 kb
Host smart-63216a2b-49fe-4420-af40-faa13d451d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903092945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3903092945
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.461369930
Short name T637
Test name
Test status
Simulation time 2033225261 ps
CPU time 2.1 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:54:20 PM PDT 24
Peak memory 197968 kb
Host smart-994b1d51-ed02-4dfd-85be-f93ccffe4a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461369930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.461369930
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2068608818
Short name T764
Test name
Test status
Simulation time 132318829604 ps
CPU time 103.2 seconds
Started Jul 10 04:54:18 PM PDT 24
Finished Jul 10 04:56:02 PM PDT 24
Peak memory 199780 kb
Host smart-3cb56915-3bf8-4662-acc0-b61a6ca3b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068608818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2068608818
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.39811906
Short name T310
Test name
Test status
Simulation time 1290343587 ps
CPU time 2.77 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:54:20 PM PDT 24
Peak memory 195232 kb
Host smart-1db68fc0-f54f-4204-8079-484ffae64e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39811906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.39811906
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.919570614
Short name T369
Test name
Test status
Simulation time 849966564 ps
CPU time 2.56 seconds
Started Jul 10 04:54:18 PM PDT 24
Finished Jul 10 04:54:22 PM PDT 24
Peak memory 198088 kb
Host smart-dadd7ef7-0435-4bde-a0e3-1bbb9d6a7dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919570614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.919570614
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.4044032197
Short name T503
Test name
Test status
Simulation time 61143810921 ps
CPU time 379.68 seconds
Started Jul 10 04:54:26 PM PDT 24
Finished Jul 10 05:00:47 PM PDT 24
Peak memory 209248 kb
Host smart-607af853-484d-4094-938b-e3e55b1ed884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044032197 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4044032197
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2849751292
Short name T801
Test name
Test status
Simulation time 6416411302 ps
CPU time 22.46 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:54:40 PM PDT 24
Peak memory 199828 kb
Host smart-b8e2ec72-688d-4a5d-8f7c-8332e8df5722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849751292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2849751292
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2300459992
Short name T351
Test name
Test status
Simulation time 48285925189 ps
CPU time 63.64 seconds
Started Jul 10 04:54:17 PM PDT 24
Finished Jul 10 04:55:22 PM PDT 24
Peak memory 199772 kb
Host smart-ccfadb70-569e-48ec-9ad8-2d6608ea2909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300459992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2300459992
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1678395985
Short name T1171
Test name
Test status
Simulation time 207065269111 ps
CPU time 231.83 seconds
Started Jul 10 05:00:29 PM PDT 24
Finished Jul 10 05:04:22 PM PDT 24
Peak memory 199840 kb
Host smart-10c43bce-d131-431b-a7d0-40fa3a7b4e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678395985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1678395985
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1473270136
Short name T1097
Test name
Test status
Simulation time 34517955405 ps
CPU time 13.29 seconds
Started Jul 10 05:00:35 PM PDT 24
Finished Jul 10 05:00:49 PM PDT 24
Peak memory 199424 kb
Host smart-e1ba8482-9119-47f2-8462-2aa3189435a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473270136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1473270136
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1347736861
Short name T868
Test name
Test status
Simulation time 51634507810 ps
CPU time 25.77 seconds
Started Jul 10 05:00:37 PM PDT 24
Finished Jul 10 05:01:04 PM PDT 24
Peak memory 199864 kb
Host smart-9b9adac5-c4ba-41cd-854b-47a62b8d8493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347736861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1347736861
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.4196933844
Short name T978
Test name
Test status
Simulation time 59880246690 ps
CPU time 19.34 seconds
Started Jul 10 05:00:36 PM PDT 24
Finished Jul 10 05:00:56 PM PDT 24
Peak memory 199912 kb
Host smart-ab231dae-c9a7-4694-8783-38780b0befb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196933844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4196933844
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3554745590
Short name T498
Test name
Test status
Simulation time 169174367312 ps
CPU time 57.8 seconds
Started Jul 10 05:00:36 PM PDT 24
Finished Jul 10 05:01:36 PM PDT 24
Peak memory 199764 kb
Host smart-9a06f294-0a9f-48e1-a08f-acb9e212c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554745590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3554745590
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3670598112
Short name T565
Test name
Test status
Simulation time 17370460716 ps
CPU time 16.42 seconds
Started Jul 10 05:00:35 PM PDT 24
Finished Jul 10 05:00:53 PM PDT 24
Peak memory 199820 kb
Host smart-f41c2a8d-3852-45ff-89eb-049354c7579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670598112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3670598112
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1412909462
Short name T312
Test name
Test status
Simulation time 13919501459 ps
CPU time 21.85 seconds
Started Jul 10 05:00:35 PM PDT 24
Finished Jul 10 05:00:58 PM PDT 24
Peak memory 199784 kb
Host smart-c597b7c5-d25b-4fb0-b75c-49db410a80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412909462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1412909462
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3354193996
Short name T135
Test name
Test status
Simulation time 77937640668 ps
CPU time 13.43 seconds
Started Jul 10 05:00:34 PM PDT 24
Finished Jul 10 05:00:49 PM PDT 24
Peak memory 199820 kb
Host smart-c31d82be-9a71-40b8-80bb-da0564db6f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354193996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3354193996
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2542535131
Short name T285
Test name
Test status
Simulation time 42526887480 ps
CPU time 19.26 seconds
Started Jul 10 05:00:35 PM PDT 24
Finished Jul 10 05:00:56 PM PDT 24
Peak memory 199844 kb
Host smart-66279c80-be12-4c9c-9c8f-ccabe35f0f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542535131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2542535131
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2831109143
Short name T139
Test name
Test status
Simulation time 58942755197 ps
CPU time 112.99 seconds
Started Jul 10 05:00:33 PM PDT 24
Finished Jul 10 05:02:27 PM PDT 24
Peak memory 199792 kb
Host smart-d9e7a8bd-8d42-4341-b108-6ecd950da99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831109143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2831109143
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.447419647
Short name T806
Test name
Test status
Simulation time 11368496 ps
CPU time 0.55 seconds
Started Jul 10 04:54:29 PM PDT 24
Finished Jul 10 04:54:30 PM PDT 24
Peak memory 195152 kb
Host smart-5326ed1a-cb90-45fd-8c1f-b13379b042f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447419647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.447419647
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3271431554
Short name T289
Test name
Test status
Simulation time 72308756739 ps
CPU time 138.78 seconds
Started Jul 10 04:54:26 PM PDT 24
Finished Jul 10 04:56:46 PM PDT 24
Peak memory 199824 kb
Host smart-df698623-6a64-4bfd-8f2e-48193d432175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271431554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3271431554
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3140314858
Short name T150
Test name
Test status
Simulation time 51780291004 ps
CPU time 67.29 seconds
Started Jul 10 04:54:26 PM PDT 24
Finished Jul 10 04:55:34 PM PDT 24
Peak memory 199776 kb
Host smart-e01b9851-7b45-419b-9a0e-d53ea0ce3a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140314858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3140314858
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.2815662221
Short name T869
Test name
Test status
Simulation time 63081659119 ps
CPU time 24.72 seconds
Started Jul 10 04:54:27 PM PDT 24
Finished Jul 10 04:54:53 PM PDT 24
Peak memory 199796 kb
Host smart-466f3627-15bf-4194-96cf-6f69db9d0bfe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815662221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2815662221
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.554835712
Short name T1043
Test name
Test status
Simulation time 71965984201 ps
CPU time 71.39 seconds
Started Jul 10 04:54:27 PM PDT 24
Finished Jul 10 04:55:39 PM PDT 24
Peak memory 199732 kb
Host smart-f9ce0b5f-d2cd-4920-9dbb-44856c71f073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=554835712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.554835712
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.430447184
Short name T1077
Test name
Test status
Simulation time 20146708 ps
CPU time 0.57 seconds
Started Jul 10 04:54:35 PM PDT 24
Finished Jul 10 04:54:37 PM PDT 24
Peak memory 195580 kb
Host smart-6675d24c-988f-4ac8-88f4-b75fdb09370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430447184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.430447184
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1014000047
Short name T422
Test name
Test status
Simulation time 89106985745 ps
CPU time 41.65 seconds
Started Jul 10 04:54:29 PM PDT 24
Finished Jul 10 04:55:11 PM PDT 24
Peak memory 199412 kb
Host smart-02656802-bd4d-4534-b543-f9273c8b5f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014000047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1014000047
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3829488326
Short name T561
Test name
Test status
Simulation time 28382109601 ps
CPU time 1489.8 seconds
Started Jul 10 04:54:26 PM PDT 24
Finished Jul 10 05:19:17 PM PDT 24
Peak memory 199836 kb
Host smart-e12e4b9e-ed5a-4c60-9deb-6b6fcd192bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829488326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3829488326
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1038380451
Short name T1162
Test name
Test status
Simulation time 4640142222 ps
CPU time 19.75 seconds
Started Jul 10 04:54:25 PM PDT 24
Finished Jul 10 04:54:46 PM PDT 24
Peak memory 198648 kb
Host smart-f71e9398-0286-430d-b6a7-dedc2639ce5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038380451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1038380451
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1681641275
Short name T752
Test name
Test status
Simulation time 12382512536 ps
CPU time 18.72 seconds
Started Jul 10 04:54:27 PM PDT 24
Finished Jul 10 04:54:46 PM PDT 24
Peak memory 199508 kb
Host smart-8d68fde0-4eae-49ef-93a4-d601d847c859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681641275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1681641275
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.4111522463
Short name T76
Test name
Test status
Simulation time 39082803038 ps
CPU time 14.9 seconds
Started Jul 10 04:54:28 PM PDT 24
Finished Jul 10 04:54:44 PM PDT 24
Peak memory 195772 kb
Host smart-ed03b8a5-bec5-4e76-a5a1-eacea9b47c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111522463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.4111522463
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.78062259
Short name T297
Test name
Test status
Simulation time 301928941 ps
CPU time 1.38 seconds
Started Jul 10 04:54:27 PM PDT 24
Finished Jul 10 04:54:30 PM PDT 24
Peak memory 199108 kb
Host smart-e778fcf5-c7d1-4e09-b244-81a027d39c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78062259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.78062259
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3426311432
Short name T1106
Test name
Test status
Simulation time 105945598170 ps
CPU time 52.04 seconds
Started Jul 10 04:54:26 PM PDT 24
Finished Jul 10 04:55:19 PM PDT 24
Peak memory 199772 kb
Host smart-f54eabb0-bac4-44a1-9804-853b162ba8a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426311432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3426311432
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.402520384
Short name T622
Test name
Test status
Simulation time 212520574840 ps
CPU time 404.19 seconds
Started Jul 10 04:54:35 PM PDT 24
Finished Jul 10 05:01:20 PM PDT 24
Peak memory 216484 kb
Host smart-1c38e0c7-041e-4e3a-9a71-212d8e126527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402520384 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.402520384
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2426791477
Short name T1099
Test name
Test status
Simulation time 6537659536 ps
CPU time 15.5 seconds
Started Jul 10 04:54:28 PM PDT 24
Finished Jul 10 04:54:45 PM PDT 24
Peak memory 199268 kb
Host smart-cc62043f-7d85-46d3-8f13-5091986ee5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426791477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2426791477
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1053910939
Short name T1123
Test name
Test status
Simulation time 32688412751 ps
CPU time 66.16 seconds
Started Jul 10 04:54:28 PM PDT 24
Finished Jul 10 04:55:35 PM PDT 24
Peak memory 199852 kb
Host smart-5e1e4e99-df60-4e4f-b558-a88dfe9d3761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053910939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1053910939
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3247189812
Short name T237
Test name
Test status
Simulation time 113714545869 ps
CPU time 189.86 seconds
Started Jul 10 05:00:37 PM PDT 24
Finished Jul 10 05:03:48 PM PDT 24
Peak memory 199760 kb
Host smart-474b9451-fe3f-4795-a346-a61ac152a16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247189812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3247189812
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2542755961
Short name T557
Test name
Test status
Simulation time 61085411964 ps
CPU time 61.59 seconds
Started Jul 10 05:00:37 PM PDT 24
Finished Jul 10 05:01:40 PM PDT 24
Peak memory 199784 kb
Host smart-5e7919dd-82dd-4394-95bb-4f1b5c979f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542755961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2542755961
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3762706310
Short name T508
Test name
Test status
Simulation time 160887908765 ps
CPU time 530.14 seconds
Started Jul 10 05:00:35 PM PDT 24
Finished Jul 10 05:09:27 PM PDT 24
Peak memory 199768 kb
Host smart-afc00389-f078-4f03-8c78-3db0ccc56ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762706310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3762706310
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4178185499
Short name T693
Test name
Test status
Simulation time 30364259948 ps
CPU time 51.12 seconds
Started Jul 10 05:00:35 PM PDT 24
Finished Jul 10 05:01:28 PM PDT 24
Peak memory 199880 kb
Host smart-5d7198c7-5507-427e-8309-7bdfe459a5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178185499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4178185499
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2921034925
Short name T669
Test name
Test status
Simulation time 6151627384 ps
CPU time 39.77 seconds
Started Jul 10 05:00:37 PM PDT 24
Finished Jul 10 05:01:18 PM PDT 24
Peak memory 199540 kb
Host smart-8d1be98c-5eae-4d4f-84f8-32e3e51e338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921034925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2921034925
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3848163150
Short name T571
Test name
Test status
Simulation time 23565604081 ps
CPU time 34.63 seconds
Started Jul 10 05:00:38 PM PDT 24
Finished Jul 10 05:01:14 PM PDT 24
Peak memory 199768 kb
Host smart-710c5d0a-b608-4d3b-bd2f-b37af39dd546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848163150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3848163150
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.783304478
Short name T962
Test name
Test status
Simulation time 21143740809 ps
CPU time 10.3 seconds
Started Jul 10 05:00:37 PM PDT 24
Finished Jul 10 05:00:49 PM PDT 24
Peak memory 199784 kb
Host smart-32d5bb2b-9863-4661-88cf-0e5638db4f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783304478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.783304478
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2211259402
Short name T1150
Test name
Test status
Simulation time 64830367162 ps
CPU time 23.82 seconds
Started Jul 10 05:00:35 PM PDT 24
Finished Jul 10 05:01:00 PM PDT 24
Peak memory 199828 kb
Host smart-a7566bef-6fa3-4f12-8779-1aeff2356042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211259402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2211259402
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.518690614
Short name T749
Test name
Test status
Simulation time 121319121032 ps
CPU time 44.09 seconds
Started Jul 10 05:00:35 PM PDT 24
Finished Jul 10 05:01:21 PM PDT 24
Peak memory 199808 kb
Host smart-84f015e0-d5d6-4a60-beae-439b39177caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518690614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.518690614
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.873067214
Short name T536
Test name
Test status
Simulation time 13438336 ps
CPU time 0.57 seconds
Started Jul 10 04:54:38 PM PDT 24
Finished Jul 10 04:54:40 PM PDT 24
Peak memory 195376 kb
Host smart-feeacc8c-a8b8-4e00-a406-6531701e04cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873067214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.873067214
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2686985915
Short name T657
Test name
Test status
Simulation time 15528595975 ps
CPU time 24.02 seconds
Started Jul 10 04:54:30 PM PDT 24
Finished Jul 10 04:54:56 PM PDT 24
Peak memory 200108 kb
Host smart-0a59666b-fc4a-4bef-a1af-ceeae96255a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686985915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2686985915
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1929248326
Short name T152
Test name
Test status
Simulation time 15636406292 ps
CPU time 29.66 seconds
Started Jul 10 04:54:31 PM PDT 24
Finished Jul 10 04:55:02 PM PDT 24
Peak memory 199656 kb
Host smart-961576ce-59b9-4a79-89a4-242eafe0366b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929248326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1929248326
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3305666481
Short name T215
Test name
Test status
Simulation time 24693364754 ps
CPU time 38.86 seconds
Started Jul 10 04:54:34 PM PDT 24
Finished Jul 10 04:55:14 PM PDT 24
Peak memory 199788 kb
Host smart-76895984-4723-418d-b6cc-50f37a77306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305666481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3305666481
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.440412165
Short name T905
Test name
Test status
Simulation time 16947361717 ps
CPU time 27.7 seconds
Started Jul 10 04:54:34 PM PDT 24
Finished Jul 10 04:55:02 PM PDT 24
Peak memory 199712 kb
Host smart-ac3badb4-03a9-49b1-8995-4e951c67aeb0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440412165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.440412165
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2528881970
Short name T1170
Test name
Test status
Simulation time 169315682614 ps
CPU time 675.92 seconds
Started Jul 10 04:54:32 PM PDT 24
Finished Jul 10 05:05:49 PM PDT 24
Peak memory 199800 kb
Host smart-d5333f37-df15-428e-b736-32ebb9b1fb60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528881970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2528881970
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3591518908
Short name T407
Test name
Test status
Simulation time 6515884724 ps
CPU time 6.89 seconds
Started Jul 10 04:54:35 PM PDT 24
Finished Jul 10 04:54:43 PM PDT 24
Peak memory 199740 kb
Host smart-d07e1a37-7089-4ffe-82b0-3508d259ea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591518908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3591518908
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3253410716
Short name T989
Test name
Test status
Simulation time 168069789291 ps
CPU time 443.85 seconds
Started Jul 10 04:54:33 PM PDT 24
Finished Jul 10 05:01:58 PM PDT 24
Peak memory 199600 kb
Host smart-58da8148-f542-4c6c-8b33-4e7558bfec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253410716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3253410716
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1626658672
Short name T714
Test name
Test status
Simulation time 20146499811 ps
CPU time 525.62 seconds
Started Jul 10 04:54:31 PM PDT 24
Finished Jul 10 05:03:17 PM PDT 24
Peak memory 199720 kb
Host smart-c73f3a64-ed6c-48f6-88d9-e3f395e31e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626658672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1626658672
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.225078257
Short name T468
Test name
Test status
Simulation time 4812450364 ps
CPU time 2.56 seconds
Started Jul 10 04:54:33 PM PDT 24
Finished Jul 10 04:54:36 PM PDT 24
Peak memory 198780 kb
Host smart-b081f0c7-0a7b-4366-8bda-739967721c7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225078257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.225078257
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.68309271
Short name T782
Test name
Test status
Simulation time 128682041324 ps
CPU time 207.97 seconds
Started Jul 10 04:54:38 PM PDT 24
Finished Jul 10 04:58:07 PM PDT 24
Peak memory 199716 kb
Host smart-022fb6d1-0410-484a-bed1-d32b7da0f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68309271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.68309271
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3127821037
Short name T1041
Test name
Test status
Simulation time 1788446493 ps
CPU time 1.32 seconds
Started Jul 10 04:54:30 PM PDT 24
Finished Jul 10 04:54:33 PM PDT 24
Peak memory 195228 kb
Host smart-498560b3-9186-4a00-a852-862c6a421939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127821037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3127821037
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2750539980
Short name T660
Test name
Test status
Simulation time 503004630 ps
CPU time 1.43 seconds
Started Jul 10 04:54:35 PM PDT 24
Finished Jul 10 04:54:37 PM PDT 24
Peak memory 198368 kb
Host smart-be9e514a-d7f4-412f-b2ad-d37bcf4210c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750539980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2750539980
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1801624977
Short name T1159
Test name
Test status
Simulation time 133964370680 ps
CPU time 601.85 seconds
Started Jul 10 04:54:31 PM PDT 24
Finished Jul 10 05:04:34 PM PDT 24
Peak memory 199880 kb
Host smart-538c1a3b-9a5c-43ef-81a6-98cdc54cdaf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801624977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1801624977
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2886408423
Short name T1001
Test name
Test status
Simulation time 451032805 ps
CPU time 1.74 seconds
Started Jul 10 04:54:39 PM PDT 24
Finished Jul 10 04:54:42 PM PDT 24
Peak memory 198056 kb
Host smart-d023925e-df79-48d4-bdcc-c1c75db5fe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886408423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2886408423
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1755217180
Short name T424
Test name
Test status
Simulation time 9603904376 ps
CPU time 8.7 seconds
Started Jul 10 04:54:31 PM PDT 24
Finished Jul 10 04:54:41 PM PDT 24
Peak memory 198568 kb
Host smart-df7d74fc-790a-4650-9472-a59c7d0ff554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755217180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1755217180
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2362867013
Short name T967
Test name
Test status
Simulation time 24022012253 ps
CPU time 13.12 seconds
Started Jul 10 05:00:36 PM PDT 24
Finished Jul 10 05:00:50 PM PDT 24
Peak memory 199784 kb
Host smart-f171971a-6ca7-446b-93b7-02d93c67eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362867013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2362867013
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2834801290
Short name T1122
Test name
Test status
Simulation time 38045526299 ps
CPU time 54.8 seconds
Started Jul 10 05:00:34 PM PDT 24
Finished Jul 10 05:01:30 PM PDT 24
Peak memory 199812 kb
Host smart-c81024cb-2e2d-4b0a-abb2-2fb04b47feb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834801290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2834801290
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2640212727
Short name T432
Test name
Test status
Simulation time 60213546144 ps
CPU time 27.02 seconds
Started Jul 10 05:00:38 PM PDT 24
Finished Jul 10 05:01:06 PM PDT 24
Peak memory 199780 kb
Host smart-d61e1f66-57e8-41f7-a3bb-1c29fbf51f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640212727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2640212727
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2978716245
Short name T274
Test name
Test status
Simulation time 39528228572 ps
CPU time 21.19 seconds
Started Jul 10 05:00:37 PM PDT 24
Finished Jul 10 05:00:59 PM PDT 24
Peak memory 199736 kb
Host smart-8988e073-4d63-4796-8a13-564bd20628f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978716245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2978716245
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2358022191
Short name T475
Test name
Test status
Simulation time 51930420926 ps
CPU time 41.73 seconds
Started Jul 10 05:00:44 PM PDT 24
Finished Jul 10 05:01:27 PM PDT 24
Peak memory 199836 kb
Host smart-56d55d6c-0e11-4abd-ad2d-609e90ecfbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358022191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2358022191
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.930036955
Short name T245
Test name
Test status
Simulation time 27143424449 ps
CPU time 48.26 seconds
Started Jul 10 05:00:45 PM PDT 24
Finished Jul 10 05:01:34 PM PDT 24
Peak memory 199840 kb
Host smart-d941ebcc-7b11-4369-8c32-d280242d7582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930036955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.930036955
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.25274106
Short name T1130
Test name
Test status
Simulation time 68333578286 ps
CPU time 29.33 seconds
Started Jul 10 05:00:46 PM PDT 24
Finished Jul 10 05:01:16 PM PDT 24
Peak memory 199740 kb
Host smart-512a3935-0031-46d7-93a0-71446ad89d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25274106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.25274106
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1110546153
Short name T75
Test name
Test status
Simulation time 51072755667 ps
CPU time 33.97 seconds
Started Jul 10 05:00:44 PM PDT 24
Finished Jul 10 05:01:19 PM PDT 24
Peak memory 199808 kb
Host smart-df836616-f17e-4374-b839-c72474622b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110546153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1110546153
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3245156141
Short name T220
Test name
Test status
Simulation time 115656229280 ps
CPU time 179.44 seconds
Started Jul 10 05:00:44 PM PDT 24
Finished Jul 10 05:03:45 PM PDT 24
Peak memory 199832 kb
Host smart-711c0887-c3ee-448a-89ff-dc0d96d7ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245156141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3245156141
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4114464517
Short name T247
Test name
Test status
Simulation time 36685902106 ps
CPU time 54.5 seconds
Started Jul 10 05:00:45 PM PDT 24
Finished Jul 10 05:01:41 PM PDT 24
Peak memory 199784 kb
Host smart-321fa07d-0e99-4ab9-bd90-e8fd8ae5dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114464517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4114464517
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2526478657
Short name T1006
Test name
Test status
Simulation time 19103192 ps
CPU time 0.56 seconds
Started Jul 10 04:54:39 PM PDT 24
Finished Jul 10 04:54:41 PM PDT 24
Peak memory 195132 kb
Host smart-95c14a95-1872-4e56-baa0-a457f79707dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526478657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2526478657
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.883925376
Short name T517
Test name
Test status
Simulation time 121967862816 ps
CPU time 141.52 seconds
Started Jul 10 04:54:30 PM PDT 24
Finished Jul 10 04:56:53 PM PDT 24
Peak memory 199772 kb
Host smart-cff690ee-0819-4c2b-883a-44cee174e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883925376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.883925376
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1552565128
Short name T460
Test name
Test status
Simulation time 65958326828 ps
CPU time 21.22 seconds
Started Jul 10 04:54:38 PM PDT 24
Finished Jul 10 04:55:00 PM PDT 24
Peak memory 199740 kb
Host smart-f081785e-d1bb-48c6-85d1-69a1cb0500ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552565128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1552565128
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3044289821
Short name T426
Test name
Test status
Simulation time 82901780572 ps
CPU time 96.13 seconds
Started Jul 10 04:54:39 PM PDT 24
Finished Jul 10 04:56:16 PM PDT 24
Peak memory 199724 kb
Host smart-ce31ee02-1b51-4373-9bc3-1b59a0052afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044289821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3044289821
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2968384269
Short name T1054
Test name
Test status
Simulation time 257134079192 ps
CPU time 350.23 seconds
Started Jul 10 04:54:37 PM PDT 24
Finished Jul 10 05:00:28 PM PDT 24
Peak memory 199824 kb
Host smart-0ca9cf38-3700-4da8-90c1-3189816eb177
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968384269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2968384269
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.579009722
Short name T74
Test name
Test status
Simulation time 56697820470 ps
CPU time 171.95 seconds
Started Jul 10 04:54:39 PM PDT 24
Finished Jul 10 04:57:32 PM PDT 24
Peak memory 199780 kb
Host smart-29d20cc7-950f-41bc-89a3-0f66feb6b2c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579009722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.579009722
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.367551839
Short name T774
Test name
Test status
Simulation time 7825424589 ps
CPU time 14.39 seconds
Started Jul 10 04:54:46 PM PDT 24
Finished Jul 10 04:55:02 PM PDT 24
Peak memory 198420 kb
Host smart-1ded9332-b9e1-4ee7-8c1d-33179f57fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367551839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.367551839
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1893025091
Short name T650
Test name
Test status
Simulation time 7331513391 ps
CPU time 12.03 seconds
Started Jul 10 04:54:46 PM PDT 24
Finished Jul 10 04:54:59 PM PDT 24
Peak memory 198408 kb
Host smart-a96e6b29-51fa-4879-85cd-1f3e2c6c71a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893025091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1893025091
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.330667018
Short name T923
Test name
Test status
Simulation time 11009183078 ps
CPU time 291.04 seconds
Started Jul 10 04:54:39 PM PDT 24
Finished Jul 10 04:59:31 PM PDT 24
Peak memory 199808 kb
Host smart-9dd95559-fe2e-4ee9-8a8e-7458608f76eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330667018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.330667018
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2286601974
Short name T758
Test name
Test status
Simulation time 5494757025 ps
CPU time 50.14 seconds
Started Jul 10 04:54:37 PM PDT 24
Finished Jul 10 04:55:28 PM PDT 24
Peak memory 198992 kb
Host smart-43cb14bf-f3ac-45a8-82d9-952e68140276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286601974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2286601974
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2551201704
Short name T1168
Test name
Test status
Simulation time 28792772950 ps
CPU time 27.81 seconds
Started Jul 10 04:54:37 PM PDT 24
Finished Jul 10 04:55:06 PM PDT 24
Peak memory 199760 kb
Host smart-481d78dc-44dd-421f-a1e4-d6f7b90f3005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551201704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2551201704
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.651171025
Short name T379
Test name
Test status
Simulation time 4672699791 ps
CPU time 2.42 seconds
Started Jul 10 04:54:39 PM PDT 24
Finished Jul 10 04:54:43 PM PDT 24
Peak memory 196168 kb
Host smart-2c4c551e-82ea-408b-8ba5-40e1c669468d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651171025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.651171025
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3371260597
Short name T505
Test name
Test status
Simulation time 313100467 ps
CPU time 1.04 seconds
Started Jul 10 04:54:33 PM PDT 24
Finished Jul 10 04:54:34 PM PDT 24
Peak memory 198592 kb
Host smart-76f988f7-2651-4522-8f5d-cb8e6ab2c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371260597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3371260597
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.126232446
Short name T703
Test name
Test status
Simulation time 278752683877 ps
CPU time 101.82 seconds
Started Jul 10 04:54:39 PM PDT 24
Finished Jul 10 04:56:22 PM PDT 24
Peak memory 208224 kb
Host smart-18f25713-ee2e-4040-8b9f-9a9a6212c01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126232446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.126232446
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4159531844
Short name T377
Test name
Test status
Simulation time 1405136134 ps
CPU time 1.76 seconds
Started Jul 10 04:54:40 PM PDT 24
Finished Jul 10 04:54:43 PM PDT 24
Peak memory 198368 kb
Host smart-df24d7d5-2b52-48f5-9168-c6f0b0a4930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159531844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4159531844
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1245689698
Short name T870
Test name
Test status
Simulation time 41183077749 ps
CPU time 4.43 seconds
Started Jul 10 04:54:30 PM PDT 24
Finished Jul 10 04:54:35 PM PDT 24
Peak memory 199856 kb
Host smart-480d86f4-c06c-4504-bf31-95c11f29e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245689698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1245689698
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.563672698
Short name T209
Test name
Test status
Simulation time 31600373580 ps
CPU time 12.85 seconds
Started Jul 10 05:00:45 PM PDT 24
Finished Jul 10 05:00:59 PM PDT 24
Peak memory 199808 kb
Host smart-61fde989-1a60-4b5e-9ce0-83eca25749c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563672698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.563672698
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1120704914
Short name T890
Test name
Test status
Simulation time 51070066452 ps
CPU time 22.31 seconds
Started Jul 10 05:00:44 PM PDT 24
Finished Jul 10 05:01:08 PM PDT 24
Peak memory 199924 kb
Host smart-73937ed3-a348-4e88-bea0-38ce4ca4de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120704914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1120704914
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2795784705
Short name T165
Test name
Test status
Simulation time 88595896731 ps
CPU time 129.79 seconds
Started Jul 10 05:00:45 PM PDT 24
Finished Jul 10 05:02:56 PM PDT 24
Peak memory 199844 kb
Host smart-79172abc-122a-41eb-9884-d6e5ff3b02ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795784705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2795784705
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1837247509
Short name T133
Test name
Test status
Simulation time 8510480790 ps
CPU time 18.33 seconds
Started Jul 10 05:00:45 PM PDT 24
Finished Jul 10 05:01:05 PM PDT 24
Peak memory 200088 kb
Host smart-fbb6ae18-651e-401e-9e49-31b17aa46cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837247509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1837247509
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2622446219
Short name T566
Test name
Test status
Simulation time 67612692302 ps
CPU time 57.32 seconds
Started Jul 10 05:00:46 PM PDT 24
Finished Jul 10 05:01:44 PM PDT 24
Peak memory 199740 kb
Host smart-0346d1af-7351-4d23-8031-bb92aff4dfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622446219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2622446219
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2891190757
Short name T959
Test name
Test status
Simulation time 17192382058 ps
CPU time 25.83 seconds
Started Jul 10 05:00:43 PM PDT 24
Finished Jul 10 05:01:10 PM PDT 24
Peak memory 199804 kb
Host smart-a15c4ca8-e7d9-4488-8e4e-ebacba5cb384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891190757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2891190757
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3517168649
Short name T1138
Test name
Test status
Simulation time 203283159291 ps
CPU time 142.4 seconds
Started Jul 10 05:00:45 PM PDT 24
Finished Jul 10 05:03:08 PM PDT 24
Peak memory 199736 kb
Host smart-2d1d1d47-2a6c-4222-b4a3-40a01277ca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517168649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3517168649
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1654374980
Short name T532
Test name
Test status
Simulation time 94785200029 ps
CPU time 69.73 seconds
Started Jul 10 05:00:45 PM PDT 24
Finished Jul 10 05:01:56 PM PDT 24
Peak memory 199844 kb
Host smart-bb2272ec-f845-449b-a8e3-ed4cbd3d971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654374980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1654374980
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1028513621
Short name T256
Test name
Test status
Simulation time 273284828943 ps
CPU time 531.18 seconds
Started Jul 10 05:00:44 PM PDT 24
Finished Jul 10 05:09:37 PM PDT 24
Peak memory 199832 kb
Host smart-3b691030-a4e5-4cda-9a2c-b46272808dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028513621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1028513621
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2742684690
Short name T593
Test name
Test status
Simulation time 21361533020 ps
CPU time 8.13 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:01:03 PM PDT 24
Peak memory 199580 kb
Host smart-d274121c-4565-4b3e-8de2-06ba63107fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742684690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2742684690
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2803189180
Short name T1011
Test name
Test status
Simulation time 26305025 ps
CPU time 0.55 seconds
Started Jul 10 04:54:49 PM PDT 24
Finished Jul 10 04:54:51 PM PDT 24
Peak memory 194420 kb
Host smart-685db29d-8e94-4339-a99e-9337c32a0adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803189180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2803189180
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2186490613
Short name T272
Test name
Test status
Simulation time 152750355850 ps
CPU time 539.87 seconds
Started Jul 10 04:54:48 PM PDT 24
Finished Jul 10 05:03:48 PM PDT 24
Peak memory 199860 kb
Host smart-101294f9-ef3c-4254-af52-8213b3061e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186490613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2186490613
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2697300638
Short name T1075
Test name
Test status
Simulation time 49401800309 ps
CPU time 19.46 seconds
Started Jul 10 04:54:49 PM PDT 24
Finished Jul 10 04:55:10 PM PDT 24
Peak memory 199836 kb
Host smart-1a24d946-477a-4fec-a835-d215bbe8b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697300638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2697300638
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3678895795
Short name T252
Test name
Test status
Simulation time 59207662938 ps
CPU time 16.16 seconds
Started Jul 10 04:54:48 PM PDT 24
Finished Jul 10 04:55:05 PM PDT 24
Peak memory 199840 kb
Host smart-c4815e23-df76-4c50-9d23-802c3fe824f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678895795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3678895795
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1628327602
Short name T21
Test name
Test status
Simulation time 37138793325 ps
CPU time 79.98 seconds
Started Jul 10 04:54:50 PM PDT 24
Finished Jul 10 04:56:11 PM PDT 24
Peak memory 199824 kb
Host smart-9d34d11d-cd04-463a-9f29-0a4a9f9cc3d9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628327602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1628327602
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2486225088
Short name T264
Test name
Test status
Simulation time 59695789473 ps
CPU time 470.52 seconds
Started Jul 10 04:54:49 PM PDT 24
Finished Jul 10 05:02:41 PM PDT 24
Peak memory 199832 kb
Host smart-4d10ce6c-85df-4060-a9ab-e8fe15ae24fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486225088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2486225088
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2085733637
Short name T827
Test name
Test status
Simulation time 1877812782 ps
CPU time 3.64 seconds
Started Jul 10 04:54:50 PM PDT 24
Finished Jul 10 04:54:55 PM PDT 24
Peak memory 199440 kb
Host smart-c840273f-9a3e-4d4f-96ad-b4841080689a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085733637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2085733637
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1330815767
Short name T956
Test name
Test status
Simulation time 48528367849 ps
CPU time 75.62 seconds
Started Jul 10 04:54:49 PM PDT 24
Finished Jul 10 04:56:07 PM PDT 24
Peak memory 199896 kb
Host smart-47ab80d2-55f8-4418-9542-8f57ae3eeac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330815767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1330815767
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3171804026
Short name T582
Test name
Test status
Simulation time 31501005720 ps
CPU time 1921.02 seconds
Started Jul 10 04:54:50 PM PDT 24
Finished Jul 10 05:26:53 PM PDT 24
Peak memory 199816 kb
Host smart-67059daa-29ac-41c0-b2b1-83f54b89fdd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171804026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3171804026
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1793801775
Short name T576
Test name
Test status
Simulation time 5581890708 ps
CPU time 13.22 seconds
Started Jul 10 04:54:48 PM PDT 24
Finished Jul 10 04:55:03 PM PDT 24
Peak memory 198480 kb
Host smart-aaa44baa-ab82-43c2-a311-2a099d9e2bd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793801775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1793801775
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.332685175
Short name T1172
Test name
Test status
Simulation time 263739262556 ps
CPU time 59.94 seconds
Started Jul 10 04:54:49 PM PDT 24
Finished Jul 10 04:55:50 PM PDT 24
Peak memory 199828 kb
Host smart-82735db5-99c8-47e2-ac2d-f2764ae293db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332685175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.332685175
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.434804466
Short name T850
Test name
Test status
Simulation time 4126019727 ps
CPU time 1.93 seconds
Started Jul 10 04:54:49 PM PDT 24
Finished Jul 10 04:54:52 PM PDT 24
Peak memory 195856 kb
Host smart-2a8e7491-548c-42e0-b953-9c67441b42e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434804466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.434804466
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2325097333
Short name T1019
Test name
Test status
Simulation time 560515607 ps
CPU time 1.51 seconds
Started Jul 10 04:54:38 PM PDT 24
Finished Jul 10 04:54:41 PM PDT 24
Peak memory 198988 kb
Host smart-45874e92-37a8-4595-a7d1-2c3c9452737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325097333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2325097333
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1319499446
Short name T349
Test name
Test status
Simulation time 72230698830 ps
CPU time 1150.83 seconds
Started Jul 10 04:54:51 PM PDT 24
Finished Jul 10 05:14:03 PM PDT 24
Peak memory 200156 kb
Host smart-f0fa6e6b-4ca7-4419-8595-f1d202fc2f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319499446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1319499446
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1805418749
Short name T1157
Test name
Test status
Simulation time 128552149520 ps
CPU time 357.72 seconds
Started Jul 10 04:54:50 PM PDT 24
Finished Jul 10 05:00:49 PM PDT 24
Peak memory 224756 kb
Host smart-1a1ff6a7-fcd4-4a96-88ce-8c14b0062014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805418749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1805418749
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.485173308
Short name T456
Test name
Test status
Simulation time 682560111 ps
CPU time 1.76 seconds
Started Jul 10 04:54:50 PM PDT 24
Finished Jul 10 04:54:53 PM PDT 24
Peak memory 199668 kb
Host smart-310546a3-d15f-4e5d-bf21-3aca0108baaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485173308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.485173308
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.154050105
Short name T279
Test name
Test status
Simulation time 26907917950 ps
CPU time 47.14 seconds
Started Jul 10 04:54:38 PM PDT 24
Finished Jul 10 04:55:27 PM PDT 24
Peak memory 199772 kb
Host smart-e2abbb9b-1154-4910-bc95-3c911e174e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154050105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.154050105
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3718983314
Short name T792
Test name
Test status
Simulation time 37671517633 ps
CPU time 63.29 seconds
Started Jul 10 05:00:54 PM PDT 24
Finished Jul 10 05:01:59 PM PDT 24
Peak memory 200028 kb
Host smart-d9e0c9f4-2480-43b6-9450-f863634c575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718983314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3718983314
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3471995845
Short name T1148
Test name
Test status
Simulation time 238004882090 ps
CPU time 173.46 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:03:48 PM PDT 24
Peak memory 199844 kb
Host smart-0abd383d-5946-4c1d-b571-4ce9ebf1a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471995845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3471995845
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3294598810
Short name T537
Test name
Test status
Simulation time 196152063895 ps
CPU time 36.13 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:30 PM PDT 24
Peak memory 199792 kb
Host smart-6ba1d580-b85a-4ca3-91e0-46df2bd63e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294598810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3294598810
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3523703920
Short name T902
Test name
Test status
Simulation time 27872654929 ps
CPU time 15.44 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:01:09 PM PDT 24
Peak memory 199684 kb
Host smart-c625fc17-65ec-485b-a7e3-aa2693dbfeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523703920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3523703920
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2967955038
Short name T1095
Test name
Test status
Simulation time 74721256302 ps
CPU time 49.48 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:01:44 PM PDT 24
Peak memory 199812 kb
Host smart-4efa35fd-3cec-4492-ad25-2ae9813103f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967955038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2967955038
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.4129960954
Short name T154
Test name
Test status
Simulation time 54544268825 ps
CPU time 19.69 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:01:14 PM PDT 24
Peak memory 199844 kb
Host smart-8c89f809-948a-4c8f-b12d-15631ab0e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129960954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.4129960954
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3653129243
Short name T178
Test name
Test status
Simulation time 200580809167 ps
CPU time 84.16 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:02:16 PM PDT 24
Peak memory 199708 kb
Host smart-4f77346d-cf3e-4804-a9ab-a01f4a55e38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653129243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3653129243
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.286416286
Short name T187
Test name
Test status
Simulation time 186762355550 ps
CPU time 254.07 seconds
Started Jul 10 05:00:53 PM PDT 24
Finished Jul 10 05:05:09 PM PDT 24
Peak memory 199932 kb
Host smart-b14c15f6-a0a7-4f24-98ee-4925a09ffa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286416286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.286416286
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2364806764
Short name T886
Test name
Test status
Simulation time 54745657522 ps
CPU time 68.25 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:02:00 PM PDT 24
Peak memory 199780 kb
Host smart-7cd35a62-53f6-462b-9bb1-b92eb7a0216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364806764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2364806764
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1673177571
Short name T26
Test name
Test status
Simulation time 14305676 ps
CPU time 0.54 seconds
Started Jul 10 04:54:53 PM PDT 24
Finished Jul 10 04:54:55 PM PDT 24
Peak memory 195108 kb
Host smart-f40f4283-0ffd-43bc-9101-d88deb7c6d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673177571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1673177571
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3141326332
Short name T612
Test name
Test status
Simulation time 111193653053 ps
CPU time 264.35 seconds
Started Jul 10 04:54:54 PM PDT 24
Finished Jul 10 04:59:20 PM PDT 24
Peak memory 199792 kb
Host smart-d20693ed-f894-4f70-847a-f20bc29ef1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141326332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3141326332
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3467538966
Short name T533
Test name
Test status
Simulation time 115002426877 ps
CPU time 44 seconds
Started Jul 10 04:54:56 PM PDT 24
Finished Jul 10 04:55:41 PM PDT 24
Peak memory 199812 kb
Host smart-e0cc1668-2dad-457b-ba62-0265bec00a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467538966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3467538966
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.2937322043
Short name T1125
Test name
Test status
Simulation time 215068668122 ps
CPU time 100.62 seconds
Started Jul 10 04:54:54 PM PDT 24
Finished Jul 10 04:56:36 PM PDT 24
Peak memory 199828 kb
Host smart-77b91024-0fc4-4dbc-a77f-79cdbf956b48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937322043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2937322043
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.154985082
Short name T444
Test name
Test status
Simulation time 104388768660 ps
CPU time 175.17 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 04:57:52 PM PDT 24
Peak memory 199780 kb
Host smart-1ed41d38-9d6e-4990-917d-594ecd7e70d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154985082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.154985082
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.234494970
Short name T480
Test name
Test status
Simulation time 1507940675 ps
CPU time 2.11 seconds
Started Jul 10 04:54:54 PM PDT 24
Finished Jul 10 04:54:58 PM PDT 24
Peak memory 195248 kb
Host smart-f7ca25a4-2c03-463a-8c0a-bd87bf0c2f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234494970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.234494970
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.241851866
Short name T630
Test name
Test status
Simulation time 52706804034 ps
CPU time 5.27 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 04:55:02 PM PDT 24
Peak memory 199744 kb
Host smart-8ce4d07e-f1c9-4d87-becf-3cc32da1f0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241851866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.241851866
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1855538363
Short name T490
Test name
Test status
Simulation time 31240892966 ps
CPU time 436.5 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 05:02:13 PM PDT 24
Peak memory 199784 kb
Host smart-cab3a483-4a72-456d-b23f-0d20c933966e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855538363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1855538363
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2299457592
Short name T344
Test name
Test status
Simulation time 7186353468 ps
CPU time 28.79 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 04:55:26 PM PDT 24
Peak memory 197800 kb
Host smart-7ea0ae91-07e9-49c4-851a-1d1444d35575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299457592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2299457592
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3783675103
Short name T597
Test name
Test status
Simulation time 91435059003 ps
CPU time 281.62 seconds
Started Jul 10 04:54:53 PM PDT 24
Finished Jul 10 04:59:36 PM PDT 24
Peak memory 199768 kb
Host smart-6447d4c5-0b3b-46ec-80f3-e57b2596c0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783675103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3783675103
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3920274629
Short name T314
Test name
Test status
Simulation time 4020111172 ps
CPU time 2.06 seconds
Started Jul 10 04:54:56 PM PDT 24
Finished Jul 10 04:55:00 PM PDT 24
Peak memory 196076 kb
Host smart-bafac2e8-368d-4777-bdb8-d16023f16905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920274629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3920274629
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.68176608
Short name T327
Test name
Test status
Simulation time 290850421 ps
CPU time 2.37 seconds
Started Jul 10 04:54:49 PM PDT 24
Finished Jul 10 04:54:53 PM PDT 24
Peak memory 199348 kb
Host smart-af1c779c-f7d8-4186-ba1a-f30e6b0c5a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68176608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.68176608
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.4143970076
Short name T1020
Test name
Test status
Simulation time 253867321737 ps
CPU time 125.3 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 04:57:02 PM PDT 24
Peak memory 199776 kb
Host smart-2e6bcdcc-72f0-4937-90ae-560a7803aaaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143970076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4143970076
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.4005644127
Short name T992
Test name
Test status
Simulation time 119094684003 ps
CPU time 657.08 seconds
Started Jul 10 04:54:56 PM PDT 24
Finished Jul 10 05:05:55 PM PDT 24
Peak memory 225548 kb
Host smart-b648419d-709f-4dff-a62c-fa3e2cbfcb0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005644127 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.4005644127
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.4171355486
Short name T372
Test name
Test status
Simulation time 2251599077 ps
CPU time 2.25 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 04:54:59 PM PDT 24
Peak memory 198392 kb
Host smart-cbd0ffc9-f04d-412e-989d-818d655235c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171355486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4171355486
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.381605503
Short name T828
Test name
Test status
Simulation time 71702301530 ps
CPU time 40.81 seconds
Started Jul 10 04:54:51 PM PDT 24
Finished Jul 10 04:55:33 PM PDT 24
Peak memory 200180 kb
Host smart-fe415e93-80db-47a6-819e-3faac26fd094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381605503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.381605503
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1173025917
Short name T295
Test name
Test status
Simulation time 154604260839 ps
CPU time 21.81 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:16 PM PDT 24
Peak memory 199884 kb
Host smart-15c9d582-a067-46b3-812d-c48a4da5d17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173025917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1173025917
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.563029587
Short name T208
Test name
Test status
Simulation time 136409100625 ps
CPU time 62.11 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:55 PM PDT 24
Peak memory 199868 kb
Host smart-e8a46ac8-cf01-4fa7-a741-0b4315a78945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563029587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.563029587
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.235279104
Short name T746
Test name
Test status
Simulation time 35192114133 ps
CPU time 76.52 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:02:11 PM PDT 24
Peak memory 199784 kb
Host smart-f8c1e44d-24d4-494f-a908-cde00440adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235279104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.235279104
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.4122324393
Short name T1016
Test name
Test status
Simulation time 83680948366 ps
CPU time 61.41 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:55 PM PDT 24
Peak memory 199904 kb
Host smart-b34d35ca-8114-406f-a5c6-32c58099d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122324393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4122324393
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.370020915
Short name T203
Test name
Test status
Simulation time 156148258773 ps
CPU time 65.97 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:58 PM PDT 24
Peak memory 199756 kb
Host smart-acef707d-6a40-4bb3-adc7-c96f8539de32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370020915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.370020915
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1120310164
Short name T1133
Test name
Test status
Simulation time 45771676055 ps
CPU time 16.94 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:09 PM PDT 24
Peak memory 199752 kb
Host smart-b3ef2336-3f2e-4eba-a6ee-7ecf90ea6add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120310164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1120310164
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.737690885
Short name T922
Test name
Test status
Simulation time 42884639911 ps
CPU time 80.79 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:02:15 PM PDT 24
Peak memory 199844 kb
Host smart-ac4ea153-744f-4f23-ad59-d72e50a1cb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737690885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.737690885
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.222397401
Short name T217
Test name
Test status
Simulation time 17822643554 ps
CPU time 14.19 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:01:09 PM PDT 24
Peak memory 199844 kb
Host smart-1f58e7db-cc0e-4674-91c9-bb11f596a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222397401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.222397401
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1685269359
Short name T100
Test name
Test status
Simulation time 306540218530 ps
CPU time 46.23 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:40 PM PDT 24
Peak memory 200176 kb
Host smart-bc7d1008-77ec-41eb-9afa-c0f730265c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685269359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1685269359
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.267598709
Short name T1070
Test name
Test status
Simulation time 40100630394 ps
CPU time 12.64 seconds
Started Jul 10 05:00:50 PM PDT 24
Finished Jul 10 05:01:03 PM PDT 24
Peak memory 198860 kb
Host smart-396e4e32-518c-4d42-8fc4-0f4d81b2855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267598709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.267598709
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3493757907
Short name T572
Test name
Test status
Simulation time 13336859 ps
CPU time 0.57 seconds
Started Jul 10 04:55:03 PM PDT 24
Finished Jul 10 04:55:04 PM PDT 24
Peak memory 195220 kb
Host smart-5826fc73-9508-48df-8514-ed8ee941179b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493757907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3493757907
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.498379219
Short name T174
Test name
Test status
Simulation time 181363524608 ps
CPU time 93.99 seconds
Started Jul 10 04:54:56 PM PDT 24
Finished Jul 10 04:56:31 PM PDT 24
Peak memory 199768 kb
Host smart-c43184fd-25a2-4392-baae-b1016dec96ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498379219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.498379219
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2757479046
Short name T995
Test name
Test status
Simulation time 21880427983 ps
CPU time 16.73 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 04:55:14 PM PDT 24
Peak memory 199904 kb
Host smart-0e171a61-e7f4-412c-9636-f87b91f9f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757479046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2757479046
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2018959773
Short name T132
Test name
Test status
Simulation time 37611356971 ps
CPU time 15.18 seconds
Started Jul 10 04:54:54 PM PDT 24
Finished Jul 10 04:55:11 PM PDT 24
Peak memory 199652 kb
Host smart-d1932bfa-e567-42a9-b5cd-b49e10e479c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018959773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2018959773
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.830448793
Short name T996
Test name
Test status
Simulation time 19702661800 ps
CPU time 35.65 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 04:55:33 PM PDT 24
Peak memory 199788 kb
Host smart-323aaade-fba0-402f-8105-32ab8f6771be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830448793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.830448793
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3815977676
Short name T417
Test name
Test status
Simulation time 151432439111 ps
CPU time 468.77 seconds
Started Jul 10 04:55:02 PM PDT 24
Finished Jul 10 05:02:52 PM PDT 24
Peak memory 199848 kb
Host smart-4605aa60-e1af-4fef-8314-d8a2e16fb5e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815977676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3815977676
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2410937980
Short name T759
Test name
Test status
Simulation time 2309304678 ps
CPU time 4.01 seconds
Started Jul 10 04:55:02 PM PDT 24
Finished Jul 10 04:55:07 PM PDT 24
Peak memory 197276 kb
Host smart-9394a5a0-22dd-467a-a9ed-738b70043fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410937980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2410937980
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.684044971
Short name T411
Test name
Test status
Simulation time 172383591046 ps
CPU time 79.1 seconds
Started Jul 10 04:54:54 PM PDT 24
Finished Jul 10 04:56:15 PM PDT 24
Peak memory 199976 kb
Host smart-ea5f9027-e545-4f75-80ab-ce868393c01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684044971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.684044971
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.4282453456
Short name T1139
Test name
Test status
Simulation time 10782968887 ps
CPU time 442.03 seconds
Started Jul 10 04:55:03 PM PDT 24
Finished Jul 10 05:02:26 PM PDT 24
Peak memory 199756 kb
Host smart-568db5af-ed81-41c2-8ec0-58a2e6d86a5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282453456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4282453456
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.639732840
Short name T822
Test name
Test status
Simulation time 4863550556 ps
CPU time 41.53 seconds
Started Jul 10 04:54:53 PM PDT 24
Finished Jul 10 04:55:36 PM PDT 24
Peak memory 198892 kb
Host smart-79c6a6cf-b339-44ff-b3b9-ea4c5c26022d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639732840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.639732840
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3151711224
Short name T476
Test name
Test status
Simulation time 21871101566 ps
CPU time 34.74 seconds
Started Jul 10 04:55:01 PM PDT 24
Finished Jul 10 04:55:36 PM PDT 24
Peak memory 199808 kb
Host smart-1b5c1c6b-5a1e-4e52-a633-60d4e7dfc05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151711224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3151711224
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.351669994
Short name T428
Test name
Test status
Simulation time 3101813999 ps
CPU time 1.28 seconds
Started Jul 10 04:55:04 PM PDT 24
Finished Jul 10 04:55:06 PM PDT 24
Peak memory 196232 kb
Host smart-b9ba5e7c-4aab-48d4-b525-674714587295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351669994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.351669994
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3255718640
Short name T830
Test name
Test status
Simulation time 691694155 ps
CPU time 2 seconds
Started Jul 10 04:54:55 PM PDT 24
Finished Jul 10 04:54:58 PM PDT 24
Peak memory 199756 kb
Host smart-b1db9059-70b8-441c-bcd3-a4069246d8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255718640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3255718640
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.23953575
Short name T639
Test name
Test status
Simulation time 119039576636 ps
CPU time 590.63 seconds
Started Jul 10 04:55:02 PM PDT 24
Finished Jul 10 05:04:54 PM PDT 24
Peak memory 199780 kb
Host smart-809ce76f-5d2b-49c0-ba5b-b704dc56c452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23953575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.23953575
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.888954064
Short name T342
Test name
Test status
Simulation time 25281401883 ps
CPU time 423.79 seconds
Started Jul 10 04:55:02 PM PDT 24
Finished Jul 10 05:02:07 PM PDT 24
Peak memory 216248 kb
Host smart-640412b5-6658-4e7f-9f72-bbb417ad15b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888954064 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.888954064
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3978484536
Short name T443
Test name
Test status
Simulation time 1635454875 ps
CPU time 1.38 seconds
Started Jul 10 04:55:01 PM PDT 24
Finished Jul 10 04:55:03 PM PDT 24
Peak memory 199020 kb
Host smart-ddcef90d-bbc5-4bd4-a8d4-8269466439ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978484536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3978484536
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1378631878
Short name T491
Test name
Test status
Simulation time 18224587948 ps
CPU time 26.78 seconds
Started Jul 10 04:54:53 PM PDT 24
Finished Jul 10 04:55:21 PM PDT 24
Peak memory 199588 kb
Host smart-afb3797e-cf9a-44c5-8070-7971af6ad376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378631878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1378631878
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1609885872
Short name T244
Test name
Test status
Simulation time 95099224215 ps
CPU time 36.1 seconds
Started Jul 10 05:00:53 PM PDT 24
Finished Jul 10 05:01:31 PM PDT 24
Peak memory 199784 kb
Host smart-8e1a0822-4923-4960-8622-7f96b6bd1393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609885872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1609885872
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2717417679
Short name T408
Test name
Test status
Simulation time 34981422388 ps
CPU time 31.99 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:26 PM PDT 24
Peak memory 199844 kb
Host smart-6b6ceee0-7903-4d74-8a80-29049203c3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717417679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2717417679
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1423186586
Short name T527
Test name
Test status
Simulation time 26527242789 ps
CPU time 40.27 seconds
Started Jul 10 05:00:52 PM PDT 24
Finished Jul 10 05:01:34 PM PDT 24
Peak memory 199684 kb
Host smart-63b7ade0-1b66-47c2-ac67-a8830edeb6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423186586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1423186586
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.180479451
Short name T766
Test name
Test status
Simulation time 13419543191 ps
CPU time 21.06 seconds
Started Jul 10 05:00:54 PM PDT 24
Finished Jul 10 05:01:17 PM PDT 24
Peak memory 199836 kb
Host smart-f91fa510-8f4c-41aa-9694-2575af48272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180479451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.180479451
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.81085914
Short name T849
Test name
Test status
Simulation time 44407783324 ps
CPU time 33.07 seconds
Started Jul 10 05:00:53 PM PDT 24
Finished Jul 10 05:01:28 PM PDT 24
Peak memory 199804 kb
Host smart-a3e3e8a4-9f9b-4dbf-a1bc-76b216c90cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81085914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.81085914
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2367438022
Short name T625
Test name
Test status
Simulation time 199098845988 ps
CPU time 16.92 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:10 PM PDT 24
Peak memory 199552 kb
Host smart-0ee1e049-fdad-4426-8693-743cd6248e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367438022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2367438022
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.4031728604
Short name T495
Test name
Test status
Simulation time 89735664735 ps
CPU time 323.8 seconds
Started Jul 10 05:00:54 PM PDT 24
Finished Jul 10 05:06:19 PM PDT 24
Peak memory 199780 kb
Host smart-b9af261c-18cb-4845-a906-bd1fed05d7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031728604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4031728604
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.173871660
Short name T699
Test name
Test status
Simulation time 96033558431 ps
CPU time 153.02 seconds
Started Jul 10 05:00:54 PM PDT 24
Finished Jul 10 05:03:28 PM PDT 24
Peak memory 199860 kb
Host smart-d3a21d9f-2850-4cf5-8bfb-f27fdc161336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173871660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.173871660
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.54313331
Short name T72
Test name
Test status
Simulation time 116106150601 ps
CPU time 58.42 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:01:51 PM PDT 24
Peak memory 199868 kb
Host smart-52b1f51c-16e4-4281-b2b9-7bd5344d9833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54313331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.54313331
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3244417454
Short name T808
Test name
Test status
Simulation time 19305731 ps
CPU time 0.54 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:52:00 PM PDT 24
Peak memory 195104 kb
Host smart-6b427a25-fb87-42df-ad09-e0055f2b26aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244417454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3244417454
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3876836627
Short name T985
Test name
Test status
Simulation time 197930018598 ps
CPU time 187.19 seconds
Started Jul 10 04:51:52 PM PDT 24
Finished Jul 10 04:55:00 PM PDT 24
Peak memory 199844 kb
Host smart-2c55266a-3cb6-4639-9763-04eccfd00a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876836627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3876836627
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2960700609
Short name T148
Test name
Test status
Simulation time 44180941744 ps
CPU time 39.19 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:52:34 PM PDT 24
Peak memory 199776 kb
Host smart-930ffd69-1428-4085-ae5d-628aebf8cfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960700609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2960700609
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1976984048
Short name T674
Test name
Test status
Simulation time 70533912626 ps
CPU time 76.75 seconds
Started Jul 10 04:51:52 PM PDT 24
Finished Jul 10 04:53:10 PM PDT 24
Peak memory 199756 kb
Host smart-51d0605a-fd2a-4d65-bd15-92670cc6ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976984048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1976984048
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1746137513
Short name T659
Test name
Test status
Simulation time 35569552565 ps
CPU time 33.7 seconds
Started Jul 10 04:51:52 PM PDT 24
Finished Jul 10 04:52:26 PM PDT 24
Peak memory 199080 kb
Host smart-33a22334-35a5-48d6-913d-52210b25b9a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746137513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1746137513
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.637425853
Short name T515
Test name
Test status
Simulation time 181420724742 ps
CPU time 517.84 seconds
Started Jul 10 04:52:00 PM PDT 24
Finished Jul 10 05:00:39 PM PDT 24
Peak memory 199820 kb
Host smart-6d360416-085e-4fdc-bac1-b8f30d7aba0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=637425853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.637425853
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3832143302
Short name T646
Test name
Test status
Simulation time 7628168852 ps
CPU time 4.68 seconds
Started Jul 10 04:52:01 PM PDT 24
Finished Jul 10 04:52:07 PM PDT 24
Peak memory 198212 kb
Host smart-94e4882d-3320-4dc4-b14e-03bcecc86955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832143302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3832143302
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3372958211
Short name T7
Test name
Test status
Simulation time 27178409831 ps
CPU time 45.85 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:52:41 PM PDT 24
Peak memory 198928 kb
Host smart-94851872-ecec-4e6b-a227-ec94bc24bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372958211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3372958211
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.177044338
Short name T980
Test name
Test status
Simulation time 9532598812 ps
CPU time 480.84 seconds
Started Jul 10 04:52:00 PM PDT 24
Finished Jul 10 05:00:03 PM PDT 24
Peak memory 199796 kb
Host smart-58ad32ed-c2f8-4594-ad78-39edc3169f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177044338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.177044338
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.684137273
Short name T419
Test name
Test status
Simulation time 5348395213 ps
CPU time 42.06 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:52:37 PM PDT 24
Peak memory 198580 kb
Host smart-fd2147c5-3bbb-4660-bf47-404d76dbe7a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684137273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.684137273
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3489729290
Short name T661
Test name
Test status
Simulation time 111868956865 ps
CPU time 151.15 seconds
Started Jul 10 04:52:00 PM PDT 24
Finished Jul 10 04:54:32 PM PDT 24
Peak memory 199640 kb
Host smart-e0ef721e-f042-4c4d-b1f9-7b987b9570ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489729290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3489729290
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3816054151
Short name T619
Test name
Test status
Simulation time 1641118397 ps
CPU time 2.96 seconds
Started Jul 10 04:51:55 PM PDT 24
Finished Jul 10 04:52:00 PM PDT 24
Peak memory 195296 kb
Host smart-371cc01d-187a-4237-bedb-654a93d2cb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816054151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3816054151
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1007343507
Short name T30
Test name
Test status
Simulation time 528623996 ps
CPU time 0.87 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:52:01 PM PDT 24
Peak memory 218232 kb
Host smart-eb374058-3427-460a-bb71-8c25942ee018
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007343507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1007343507
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.696421831
Short name T364
Test name
Test status
Simulation time 312462998 ps
CPU time 0.99 seconds
Started Jul 10 04:51:53 PM PDT 24
Finished Jul 10 04:51:57 PM PDT 24
Peak memory 198656 kb
Host smart-a863702b-1a79-46aa-bb8b-f97cae342f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696421831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.696421831
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.794800190
Short name T823
Test name
Test status
Simulation time 229936666196 ps
CPU time 264.12 seconds
Started Jul 10 04:52:03 PM PDT 24
Finished Jul 10 04:56:28 PM PDT 24
Peak memory 198916 kb
Host smart-f255e076-bead-489f-924f-eff42a2d0f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794800190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.794800190
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4103397105
Short name T487
Test name
Test status
Simulation time 379949212 ps
CPU time 1.49 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:52:02 PM PDT 24
Peak memory 197740 kb
Host smart-4e8106bb-8dd9-434d-87c5-18ce77a40c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103397105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4103397105
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3349811921
Short name T805
Test name
Test status
Simulation time 42821429147 ps
CPU time 99.91 seconds
Started Jul 10 04:51:54 PM PDT 24
Finished Jul 10 04:53:36 PM PDT 24
Peak memory 199860 kb
Host smart-0ea13f4e-f0b6-43b5-a00d-222e74ad05f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349811921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3349811921
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2554189517
Short name T984
Test name
Test status
Simulation time 37035099 ps
CPU time 0.57 seconds
Started Jul 10 04:55:10 PM PDT 24
Finished Jul 10 04:55:12 PM PDT 24
Peak memory 194888 kb
Host smart-abae1334-0fe2-4854-bcb6-0ab7c21d8922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554189517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2554189517
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3333363002
Short name T1056
Test name
Test status
Simulation time 46540258748 ps
CPU time 35.96 seconds
Started Jul 10 04:55:00 PM PDT 24
Finished Jul 10 04:55:36 PM PDT 24
Peak memory 199812 kb
Host smart-434c43a2-516a-475a-a026-4c7179d8c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333363002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3333363002
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1540491968
Short name T519
Test name
Test status
Simulation time 12866917160 ps
CPU time 21.86 seconds
Started Jul 10 04:55:07 PM PDT 24
Finished Jul 10 04:55:30 PM PDT 24
Peak memory 199604 kb
Host smart-040e2e11-171f-4b38-adb3-40fc92cc4abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540491968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1540491968
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2319664916
Short name T544
Test name
Test status
Simulation time 72210389665 ps
CPU time 27.5 seconds
Started Jul 10 04:55:01 PM PDT 24
Finished Jul 10 04:55:29 PM PDT 24
Peak memory 199736 kb
Host smart-004d6a11-02da-4e5d-9589-f8c7ec06e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319664916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2319664916
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2807645566
Short name T673
Test name
Test status
Simulation time 35919029155 ps
CPU time 32.21 seconds
Started Jul 10 04:55:03 PM PDT 24
Finished Jul 10 04:55:36 PM PDT 24
Peak memory 199872 kb
Host smart-e46c03be-e5c2-46a3-978f-2af60e72f5b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807645566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2807645566
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1938693423
Short name T5
Test name
Test status
Simulation time 224961588309 ps
CPU time 492.74 seconds
Started Jul 10 04:55:10 PM PDT 24
Finished Jul 10 05:03:23 PM PDT 24
Peak memory 199824 kb
Host smart-89589434-b3d5-4d3e-b8ef-cc6e942d6d27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938693423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1938693423
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1641306916
Short name T22
Test name
Test status
Simulation time 8246091163 ps
CPU time 13.55 seconds
Started Jul 10 04:55:12 PM PDT 24
Finished Jul 10 04:55:27 PM PDT 24
Peak memory 199704 kb
Host smart-1c50078b-c9b3-479b-bd6b-b92c0fd7cc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641306916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1641306916
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2971230025
Short name T716
Test name
Test status
Simulation time 117956715353 ps
CPU time 123.58 seconds
Started Jul 10 04:55:13 PM PDT 24
Finished Jul 10 04:57:17 PM PDT 24
Peak memory 208204 kb
Host smart-14438a6e-364b-47b8-b965-90b202a41a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971230025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2971230025
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3902514271
Short name T598
Test name
Test status
Simulation time 1980860592 ps
CPU time 11.1 seconds
Started Jul 10 04:55:04 PM PDT 24
Finished Jul 10 04:55:16 PM PDT 24
Peak memory 197760 kb
Host smart-a6350791-f0a6-4f9b-8221-5fe1ff918df9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902514271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3902514271
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3886692943
Short name T919
Test name
Test status
Simulation time 74144445271 ps
CPU time 54.79 seconds
Started Jul 10 04:55:12 PM PDT 24
Finished Jul 10 04:56:08 PM PDT 24
Peak memory 199888 kb
Host smart-8eac3952-a459-4659-897f-5751d61f7e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886692943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3886692943
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.839436247
Short name T713
Test name
Test status
Simulation time 27933739825 ps
CPU time 5.42 seconds
Started Jul 10 04:55:10 PM PDT 24
Finished Jul 10 04:55:17 PM PDT 24
Peak memory 195900 kb
Host smart-87e1a75c-315c-4862-8e0f-82794d6c2dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839436247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.839436247
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2539652464
Short name T807
Test name
Test status
Simulation time 742304574 ps
CPU time 2.22 seconds
Started Jul 10 04:55:00 PM PDT 24
Finished Jul 10 04:55:03 PM PDT 24
Peak memory 198584 kb
Host smart-c781c132-d06d-467a-9624-e240b69c6368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539652464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2539652464
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.860824144
Short name T496
Test name
Test status
Simulation time 1107733746 ps
CPU time 1.81 seconds
Started Jul 10 04:55:13 PM PDT 24
Finished Jul 10 04:55:15 PM PDT 24
Peak memory 198492 kb
Host smart-f34252f2-8b4f-4320-a317-5dcdf3faaf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860824144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.860824144
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.351907107
Short name T275
Test name
Test status
Simulation time 68636201506 ps
CPU time 29.95 seconds
Started Jul 10 04:55:07 PM PDT 24
Finished Jul 10 04:55:38 PM PDT 24
Peak memory 199740 kb
Host smart-28ebfb7a-f547-4dfc-8c54-7fbeb09424dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351907107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.351907107
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2355820296
Short name T28
Test name
Test status
Simulation time 70237406 ps
CPU time 0.58 seconds
Started Jul 10 04:55:20 PM PDT 24
Finished Jul 10 04:55:22 PM PDT 24
Peak memory 195180 kb
Host smart-bfc68d6b-4ff1-4310-abdd-2bda8d0e1abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355820296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2355820296
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3810486711
Short name T164
Test name
Test status
Simulation time 46985650127 ps
CPU time 86.37 seconds
Started Jul 10 04:55:11 PM PDT 24
Finished Jul 10 04:56:39 PM PDT 24
Peak memory 199864 kb
Host smart-1db23584-1a16-483a-be17-c716e0c77800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810486711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3810486711
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.508590117
Short name T1087
Test name
Test status
Simulation time 137886721578 ps
CPU time 188.69 seconds
Started Jul 10 04:55:21 PM PDT 24
Finished Jul 10 04:58:31 PM PDT 24
Peak memory 199792 kb
Host smart-5be736ca-5262-48ae-92ef-4133d46a3aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508590117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.508590117
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3909420023
Short name T700
Test name
Test status
Simulation time 110332512003 ps
CPU time 113.2 seconds
Started Jul 10 04:55:18 PM PDT 24
Finished Jul 10 04:57:12 PM PDT 24
Peak memory 199796 kb
Host smart-50166743-981f-407e-ace1-ba2d1f94a64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909420023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3909420023
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.864228683
Short name T375
Test name
Test status
Simulation time 7306106187 ps
CPU time 11.3 seconds
Started Jul 10 04:55:18 PM PDT 24
Finished Jul 10 04:55:30 PM PDT 24
Peak memory 195692 kb
Host smart-1bbe948c-25d5-4ae0-ae27-b8ddbc8ce143
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864228683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.864228683
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2859766347
Short name T1142
Test name
Test status
Simulation time 133745944809 ps
CPU time 736.91 seconds
Started Jul 10 04:55:22 PM PDT 24
Finished Jul 10 05:07:40 PM PDT 24
Peak memory 199824 kb
Host smart-d857a850-abbf-4749-aed4-42f4edb6dabb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859766347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2859766347
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2226851443
Short name T383
Test name
Test status
Simulation time 3124571997 ps
CPU time 5.9 seconds
Started Jul 10 04:55:22 PM PDT 24
Finished Jul 10 04:55:29 PM PDT 24
Peak memory 197924 kb
Host smart-1d32b51b-90ac-4a8b-b00b-a62a1db1a4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226851443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2226851443
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.120269780
Short name T1029
Test name
Test status
Simulation time 220701924674 ps
CPU time 27.16 seconds
Started Jul 10 04:55:18 PM PDT 24
Finished Jul 10 04:55:46 PM PDT 24
Peak memory 199064 kb
Host smart-13bbab34-94da-4547-a41d-91c5a86ddc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120269780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.120269780
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1431167490
Short name T678
Test name
Test status
Simulation time 8997166811 ps
CPU time 126.6 seconds
Started Jul 10 04:55:21 PM PDT 24
Finished Jul 10 04:57:29 PM PDT 24
Peak memory 199804 kb
Host smart-8be4b07b-d41c-4a4d-9bf4-2fa7125620a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1431167490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1431167490
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1751104820
Short name T719
Test name
Test status
Simulation time 4286567212 ps
CPU time 16.19 seconds
Started Jul 10 04:55:22 PM PDT 24
Finished Jul 10 04:55:39 PM PDT 24
Peak memory 198812 kb
Host smart-ab8e04f2-c04b-47d1-96f1-2a8696835c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751104820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1751104820
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1678035182
Short name T144
Test name
Test status
Simulation time 33312333735 ps
CPU time 77.67 seconds
Started Jul 10 04:55:21 PM PDT 24
Finished Jul 10 04:56:40 PM PDT 24
Peak memory 199764 kb
Host smart-36bad5ec-1074-4ea7-8c10-b7e6e921eb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678035182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1678035182
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1239381838
Short name T50
Test name
Test status
Simulation time 859988458 ps
CPU time 2 seconds
Started Jul 10 04:55:18 PM PDT 24
Finished Jul 10 04:55:21 PM PDT 24
Peak memory 195212 kb
Host smart-b54222b8-c43b-4e22-89a9-e3552451f51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239381838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1239381838
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.859274933
Short name T812
Test name
Test status
Simulation time 699946583 ps
CPU time 2.38 seconds
Started Jul 10 04:55:12 PM PDT 24
Finished Jul 10 04:55:15 PM PDT 24
Peak memory 199604 kb
Host smart-4278cc74-d913-4a6e-a66e-a5ca13e40d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859274933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.859274933
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3851171388
Short name T892
Test name
Test status
Simulation time 162558405121 ps
CPU time 259.47 seconds
Started Jul 10 04:55:19 PM PDT 24
Finished Jul 10 04:59:40 PM PDT 24
Peak memory 199880 kb
Host smart-0fd09ac7-46e4-4b13-946a-8275e668633c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851171388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3851171388
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.413147482
Short name T651
Test name
Test status
Simulation time 123660997148 ps
CPU time 304.7 seconds
Started Jul 10 04:55:20 PM PDT 24
Finished Jul 10 05:00:26 PM PDT 24
Peak memory 215644 kb
Host smart-db8ca585-6112-483c-81c3-b8f0942da3ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413147482 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.413147482
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.395167453
Short name T912
Test name
Test status
Simulation time 9327763108 ps
CPU time 4.15 seconds
Started Jul 10 04:55:20 PM PDT 24
Finished Jul 10 04:55:25 PM PDT 24
Peak memory 199784 kb
Host smart-7aa51372-b171-49d7-905c-9099ec556835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395167453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.395167453
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1101591721
Short name T773
Test name
Test status
Simulation time 31770800868 ps
CPU time 14.46 seconds
Started Jul 10 04:55:10 PM PDT 24
Finished Jul 10 04:55:27 PM PDT 24
Peak memory 199852 kb
Host smart-9c4354f5-acda-4d01-a7df-7f8840bdd55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101591721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1101591721
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1266612913
Short name T1039
Test name
Test status
Simulation time 12937569 ps
CPU time 0.59 seconds
Started Jul 10 04:55:30 PM PDT 24
Finished Jul 10 04:55:32 PM PDT 24
Peak memory 195136 kb
Host smart-10c1ffb1-b317-436b-9b17-12928aab9321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266612913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1266612913
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4180403621
Short name T804
Test name
Test status
Simulation time 94569868677 ps
CPU time 42.53 seconds
Started Jul 10 04:55:20 PM PDT 24
Finished Jul 10 04:56:03 PM PDT 24
Peak memory 199852 kb
Host smart-1fbaee78-6c6e-454b-8e6d-988f0b3cab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180403621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4180403621
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.918453047
Short name T1154
Test name
Test status
Simulation time 116809204990 ps
CPU time 133.59 seconds
Started Jul 10 04:55:21 PM PDT 24
Finished Jul 10 04:57:35 PM PDT 24
Peak memory 199848 kb
Host smart-f08014dd-b883-481a-bef9-60f68a738634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918453047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.918453047
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1773707501
Short name T825
Test name
Test status
Simulation time 55507541457 ps
CPU time 17.71 seconds
Started Jul 10 04:55:19 PM PDT 24
Finished Jul 10 04:55:38 PM PDT 24
Peak memory 199776 kb
Host smart-a7f1bbed-525b-4d04-9dd8-3c42d4fd4319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773707501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1773707501
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1357376734
Short name T1183
Test name
Test status
Simulation time 12172580818 ps
CPU time 15.86 seconds
Started Jul 10 04:55:18 PM PDT 24
Finished Jul 10 04:55:35 PM PDT 24
Peak memory 196856 kb
Host smart-bd39d29e-07d1-4831-9810-a66bfbc624ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357376734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1357376734
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2367739396
Short name T937
Test name
Test status
Simulation time 111629034820 ps
CPU time 178.45 seconds
Started Jul 10 04:55:29 PM PDT 24
Finished Jul 10 04:58:29 PM PDT 24
Peak memory 199888 kb
Host smart-54a8b5a5-9799-4842-8701-5ad5f7dcb2f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367739396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2367739396
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3086700076
Short name T635
Test name
Test status
Simulation time 11008062287 ps
CPU time 9.11 seconds
Started Jul 10 04:55:31 PM PDT 24
Finished Jul 10 04:55:41 PM PDT 24
Peak memory 199768 kb
Host smart-0fdcb493-2c54-4a9a-928d-60e03a94eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086700076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3086700076
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.811099496
Short name T1165
Test name
Test status
Simulation time 45961916010 ps
CPU time 69.71 seconds
Started Jul 10 04:55:19 PM PDT 24
Finished Jul 10 04:56:29 PM PDT 24
Peak memory 200008 kb
Host smart-6213a85b-ed9b-4b2a-8c85-f875f831375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811099496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.811099496
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1727265117
Short name T847
Test name
Test status
Simulation time 28944451642 ps
CPU time 397.6 seconds
Started Jul 10 04:55:29 PM PDT 24
Finished Jul 10 05:02:08 PM PDT 24
Peak memory 199744 kb
Host smart-2524f573-b24a-4966-b2fa-7b301399c3de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727265117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1727265117
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.66605427
Short name T559
Test name
Test status
Simulation time 4435749835 ps
CPU time 8.99 seconds
Started Jul 10 04:55:20 PM PDT 24
Finished Jul 10 04:55:30 PM PDT 24
Peak memory 198576 kb
Host smart-b0df9f62-2b32-427f-83ed-2a439d3c19a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66605427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.66605427
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3095059312
Short name T851
Test name
Test status
Simulation time 112632837442 ps
CPU time 151.06 seconds
Started Jul 10 04:55:22 PM PDT 24
Finished Jul 10 04:57:54 PM PDT 24
Peak memory 199272 kb
Host smart-4195b830-eafd-47bd-88aa-9803e33fe303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095059312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3095059312
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1624720180
Short name T1
Test name
Test status
Simulation time 25628221020 ps
CPU time 34.16 seconds
Started Jul 10 04:55:19 PM PDT 24
Finished Jul 10 04:55:53 PM PDT 24
Peak memory 195876 kb
Host smart-5651e31d-5403-46ae-9cd9-b396316e7b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624720180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1624720180
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3783943423
Short name T1059
Test name
Test status
Simulation time 697365513 ps
CPU time 1.27 seconds
Started Jul 10 04:55:20 PM PDT 24
Finished Jul 10 04:55:23 PM PDT 24
Peak memory 198588 kb
Host smart-493e793d-df07-4296-8930-3910916dbaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783943423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3783943423
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3876821019
Short name T266
Test name
Test status
Simulation time 173113243859 ps
CPU time 727.21 seconds
Started Jul 10 04:55:30 PM PDT 24
Finished Jul 10 05:07:38 PM PDT 24
Peak memory 199740 kb
Host smart-096a3b62-a9cc-4ad1-8cf4-34bccd8ba5c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876821019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3876821019
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1690007052
Short name T735
Test name
Test status
Simulation time 20668128273 ps
CPU time 238.66 seconds
Started Jul 10 04:55:29 PM PDT 24
Finished Jul 10 04:59:29 PM PDT 24
Peak memory 212432 kb
Host smart-cb51ed5b-e4fd-4510-b1e9-f5a03ae3ef90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690007052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1690007052
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3281799932
Short name T724
Test name
Test status
Simulation time 1641810667 ps
CPU time 3.55 seconds
Started Jul 10 04:55:30 PM PDT 24
Finished Jul 10 04:55:35 PM PDT 24
Peak memory 199464 kb
Host smart-a8ca72d5-be6f-4557-9b1d-14a65ba64977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281799932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3281799932
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2478779277
Short name T1104
Test name
Test status
Simulation time 108909755031 ps
CPU time 189.31 seconds
Started Jul 10 04:55:19 PM PDT 24
Finished Jul 10 04:58:30 PM PDT 24
Peak memory 199912 kb
Host smart-ed9d79da-1d68-45c0-9f25-831fea79b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478779277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2478779277
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2099718899
Short name T1127
Test name
Test status
Simulation time 30852699 ps
CPU time 0.62 seconds
Started Jul 10 04:55:38 PM PDT 24
Finished Jul 10 04:55:41 PM PDT 24
Peak memory 195400 kb
Host smart-3d38465f-dccf-4ece-9509-8eda708f5785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099718899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2099718899
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1874851623
Short name T1161
Test name
Test status
Simulation time 32244665415 ps
CPU time 25.89 seconds
Started Jul 10 04:55:29 PM PDT 24
Finished Jul 10 04:55:55 PM PDT 24
Peak memory 199800 kb
Host smart-e55f011d-c070-4045-96a0-446a019b79fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874851623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1874851623
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.144624913
Short name T370
Test name
Test status
Simulation time 126783434207 ps
CPU time 213.16 seconds
Started Jul 10 04:55:31 PM PDT 24
Finished Jul 10 04:59:05 PM PDT 24
Peak memory 199852 kb
Host smart-6a148d79-448e-429a-be72-8570f2755fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144624913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.144624913
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.4166437869
Short name T574
Test name
Test status
Simulation time 25238000655 ps
CPU time 5.14 seconds
Started Jul 10 04:55:30 PM PDT 24
Finished Jul 10 04:55:37 PM PDT 24
Peak memory 199636 kb
Host smart-ec70072f-def4-4cab-b16c-f8a9c024cece
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166437869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.4166437869
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.713490444
Short name T958
Test name
Test status
Simulation time 116027755119 ps
CPU time 393.46 seconds
Started Jul 10 04:55:39 PM PDT 24
Finished Jul 10 05:02:14 PM PDT 24
Peak memory 199816 kb
Host smart-ce697d31-dc63-432d-873f-f82005a1d977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713490444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.713490444
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1658611746
Short name T631
Test name
Test status
Simulation time 4804041609 ps
CPU time 2.86 seconds
Started Jul 10 04:55:38 PM PDT 24
Finished Jul 10 04:55:43 PM PDT 24
Peak memory 198700 kb
Host smart-1fcd20d4-a413-4d71-bfa9-076bca18ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658611746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1658611746
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1721818496
Short name T924
Test name
Test status
Simulation time 151768418114 ps
CPU time 68.74 seconds
Started Jul 10 04:55:30 PM PDT 24
Finished Jul 10 04:56:40 PM PDT 24
Peak memory 199944 kb
Host smart-c966ebd7-3b3b-4691-9ca2-edbb9c4f3805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721818496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1721818496
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3408317811
Short name T322
Test name
Test status
Simulation time 22546355055 ps
CPU time 140 seconds
Started Jul 10 04:55:37 PM PDT 24
Finished Jul 10 04:57:58 PM PDT 24
Peak memory 200188 kb
Host smart-e3b942e4-4790-4406-8730-d0b8fc72d94e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408317811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3408317811
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2058662836
Short name T345
Test name
Test status
Simulation time 6224478739 ps
CPU time 28.06 seconds
Started Jul 10 04:55:29 PM PDT 24
Finished Jul 10 04:55:58 PM PDT 24
Peak memory 199136 kb
Host smart-1a533298-1032-4a36-a77d-dc58d07523e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058662836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2058662836
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.508311396
Short name T944
Test name
Test status
Simulation time 128938410343 ps
CPU time 80.76 seconds
Started Jul 10 04:55:38 PM PDT 24
Finished Jul 10 04:57:00 PM PDT 24
Peak memory 199780 kb
Host smart-3f8aa54c-5978-4ba5-8fb2-943083a4915a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508311396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.508311396
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.557843412
Short name T371
Test name
Test status
Simulation time 2872870243 ps
CPU time 5 seconds
Started Jul 10 04:55:30 PM PDT 24
Finished Jul 10 04:55:36 PM PDT 24
Peak memory 196320 kb
Host smart-012f0549-024e-45d3-a188-ce123921be7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557843412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.557843412
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1424232916
Short name T391
Test name
Test status
Simulation time 456341292 ps
CPU time 1.21 seconds
Started Jul 10 04:55:30 PM PDT 24
Finished Jul 10 04:55:32 PM PDT 24
Peak memory 199228 kb
Host smart-c1d1bc06-434e-43c3-b279-a1d2856b911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424232916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1424232916
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3263938776
Short name T957
Test name
Test status
Simulation time 46294551969 ps
CPU time 75.59 seconds
Started Jul 10 04:55:40 PM PDT 24
Finished Jul 10 04:56:57 PM PDT 24
Peak memory 208144 kb
Host smart-eaeccd29-7208-4bb0-83df-12a4f5849916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263938776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3263938776
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.689385643
Short name T642
Test name
Test status
Simulation time 5239445909 ps
CPU time 2.71 seconds
Started Jul 10 04:55:41 PM PDT 24
Finished Jul 10 04:55:45 PM PDT 24
Peak memory 199128 kb
Host smart-c50be55a-652c-4034-871e-c1d6a34e7b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689385643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.689385643
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2299847691
Short name T492
Test name
Test status
Simulation time 67586199355 ps
CPU time 16.41 seconds
Started Jul 10 04:55:29 PM PDT 24
Finished Jul 10 04:55:47 PM PDT 24
Peak memory 199812 kb
Host smart-4bb2352a-8ac4-4d0f-ac69-760efa90e408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299847691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2299847691
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2753934822
Short name T816
Test name
Test status
Simulation time 106803045 ps
CPU time 0.58 seconds
Started Jul 10 04:55:38 PM PDT 24
Finished Jul 10 04:55:40 PM PDT 24
Peak memory 195156 kb
Host smart-261e5f3b-e894-419f-be5d-041ab08d05f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753934822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2753934822
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3607122105
Short name T677
Test name
Test status
Simulation time 18701511155 ps
CPU time 16.9 seconds
Started Jul 10 04:55:40 PM PDT 24
Finished Jul 10 04:55:59 PM PDT 24
Peak memory 199900 kb
Host smart-7d0b33e9-0b6b-4740-ad82-eefc4d820bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607122105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3607122105
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1057846827
Short name T169
Test name
Test status
Simulation time 44837576098 ps
CPU time 28.62 seconds
Started Jul 10 04:55:37 PM PDT 24
Finished Jul 10 04:56:07 PM PDT 24
Peak memory 199584 kb
Host smart-014114b2-d426-4ad6-b648-beb407bc83ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057846827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1057846827
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2094987141
Short name T210
Test name
Test status
Simulation time 116440628496 ps
CPU time 191.69 seconds
Started Jul 10 04:55:42 PM PDT 24
Finished Jul 10 04:58:54 PM PDT 24
Peak memory 199800 kb
Host smart-1266c245-04f3-43f8-bef2-91e658c080ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094987141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2094987141
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.606076961
Short name T20
Test name
Test status
Simulation time 35520288528 ps
CPU time 14.75 seconds
Started Jul 10 04:55:41 PM PDT 24
Finished Jul 10 04:55:57 PM PDT 24
Peak memory 199824 kb
Host smart-99069aaa-eca7-41b8-ad56-72fcebd13c83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606076961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.606076961
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2225779493
Short name T77
Test name
Test status
Simulation time 151922691031 ps
CPU time 463.22 seconds
Started Jul 10 04:55:38 PM PDT 24
Finished Jul 10 05:03:22 PM PDT 24
Peak memory 199812 kb
Host smart-1f1edc27-5a56-4629-9ea6-90fbfb745d65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225779493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2225779493
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2193996816
Short name T826
Test name
Test status
Simulation time 1257054715 ps
CPU time 3.58 seconds
Started Jul 10 04:55:39 PM PDT 24
Finished Jul 10 04:55:45 PM PDT 24
Peak memory 198736 kb
Host smart-96689337-7893-4426-9587-ff73aaf606c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193996816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2193996816
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3919134390
Short name T510
Test name
Test status
Simulation time 63769348531 ps
CPU time 103.33 seconds
Started Jul 10 04:55:39 PM PDT 24
Finished Jul 10 04:57:24 PM PDT 24
Peak memory 199208 kb
Host smart-7efb8a26-4c0a-4d6a-a842-76a1f8b11388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919134390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3919134390
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.540592808
Short name T935
Test name
Test status
Simulation time 18481055019 ps
CPU time 921.51 seconds
Started Jul 10 04:55:37 PM PDT 24
Finished Jul 10 05:11:00 PM PDT 24
Peak memory 199740 kb
Host smart-ec1e879a-1da6-4ee5-b91d-0b9657bdd0d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540592808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.540592808
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3545440802
Short name T859
Test name
Test status
Simulation time 1177813273 ps
CPU time 1.52 seconds
Started Jul 10 04:55:40 PM PDT 24
Finished Jul 10 04:55:43 PM PDT 24
Peak memory 196620 kb
Host smart-c70e1543-4d8b-4f83-8f36-39e56ed07db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545440802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3545440802
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.985834604
Short name T141
Test name
Test status
Simulation time 214419899707 ps
CPU time 189.04 seconds
Started Jul 10 04:55:39 PM PDT 24
Finished Jul 10 04:58:50 PM PDT 24
Peak memory 199792 kb
Host smart-86936e43-8ab8-4d61-a27d-5d290aeeb0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985834604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.985834604
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.4046564461
Short name T563
Test name
Test status
Simulation time 4674878113 ps
CPU time 1.55 seconds
Started Jul 10 04:55:38 PM PDT 24
Finished Jul 10 04:55:41 PM PDT 24
Peak memory 196076 kb
Host smart-b55718f1-9d17-4ba9-b204-a85eaf8a4003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046564461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4046564461
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2787919317
Short name T841
Test name
Test status
Simulation time 5870116684 ps
CPU time 17.08 seconds
Started Jul 10 04:55:37 PM PDT 24
Finished Jul 10 04:55:56 PM PDT 24
Peak memory 199824 kb
Host smart-108812f5-6e27-4792-bfb6-cdfa008161c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787919317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2787919317
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1275091895
Short name T114
Test name
Test status
Simulation time 8451996490 ps
CPU time 75.69 seconds
Started Jul 10 04:55:39 PM PDT 24
Finished Jul 10 04:56:57 PM PDT 24
Peak memory 208172 kb
Host smart-c9b29789-1cde-45c4-9e15-11d1bff89774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275091895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1275091895
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.844898580
Short name T921
Test name
Test status
Simulation time 1422554222 ps
CPU time 2.05 seconds
Started Jul 10 04:55:39 PM PDT 24
Finished Jul 10 04:55:43 PM PDT 24
Peak memory 198524 kb
Host smart-cb1c752f-188c-44a3-acc1-895c1cb4da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844898580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.844898580
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1650784712
Short name T493
Test name
Test status
Simulation time 22775844157 ps
CPU time 34.8 seconds
Started Jul 10 04:55:38 PM PDT 24
Finished Jul 10 04:56:14 PM PDT 24
Peak memory 199764 kb
Host smart-be9a19a4-787a-4a85-8c28-b0c902e1f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650784712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1650784712
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.593584669
Short name T721
Test name
Test status
Simulation time 19548799 ps
CPU time 0.55 seconds
Started Jul 10 04:55:49 PM PDT 24
Finished Jul 10 04:55:50 PM PDT 24
Peak memory 194132 kb
Host smart-3da1dc35-8d2c-4571-98aa-ee83e335371a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593584669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.593584669
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2514461125
Short name T611
Test name
Test status
Simulation time 150276656208 ps
CPU time 61.28 seconds
Started Jul 10 04:55:39 PM PDT 24
Finished Jul 10 04:56:42 PM PDT 24
Peak memory 199804 kb
Host smart-d88cc1c6-61ed-4cc4-b69f-95fae981f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514461125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2514461125
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2950313422
Short name T1141
Test name
Test status
Simulation time 14115678131 ps
CPU time 25.29 seconds
Started Jul 10 04:55:47 PM PDT 24
Finished Jul 10 04:56:14 PM PDT 24
Peak memory 199764 kb
Host smart-5088a39d-e506-4183-a518-e90793946e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950313422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2950313422
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2230385001
Short name T222
Test name
Test status
Simulation time 58209774831 ps
CPU time 22.93 seconds
Started Jul 10 04:55:47 PM PDT 24
Finished Jul 10 04:56:12 PM PDT 24
Peak memory 199776 kb
Host smart-7af04a7e-9f87-4097-9a0e-bc2ccdab5fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230385001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2230385001
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.4253972035
Short name T644
Test name
Test status
Simulation time 10916141523 ps
CPU time 5.55 seconds
Started Jul 10 04:55:47 PM PDT 24
Finished Jul 10 04:55:54 PM PDT 24
Peak memory 196728 kb
Host smart-1d072a15-32f2-4445-93ae-52bffe196c23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253972035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.4253972035
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2671528415
Short name T464
Test name
Test status
Simulation time 38736974268 ps
CPU time 121.2 seconds
Started Jul 10 04:55:47 PM PDT 24
Finished Jul 10 04:57:50 PM PDT 24
Peak memory 199792 kb
Host smart-0dd20234-1869-467d-bfae-67a5d536db93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671528415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2671528415
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1229715114
Short name T663
Test name
Test status
Simulation time 5374950847 ps
CPU time 12.56 seconds
Started Jul 10 04:55:46 PM PDT 24
Finished Jul 10 04:55:59 PM PDT 24
Peak memory 199564 kb
Host smart-1b9130d0-c312-4f69-8c64-9a999ce1c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229715114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1229715114
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2074158938
Short name T575
Test name
Test status
Simulation time 46859204402 ps
CPU time 99.75 seconds
Started Jul 10 04:55:50 PM PDT 24
Finished Jul 10 04:57:31 PM PDT 24
Peak memory 198940 kb
Host smart-7c3a2e02-02d3-4b4b-8754-b1997ad9b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074158938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2074158938
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.937429577
Short name T845
Test name
Test status
Simulation time 17891694366 ps
CPU time 246.54 seconds
Started Jul 10 04:55:46 PM PDT 24
Finished Jul 10 04:59:55 PM PDT 24
Peak memory 199660 kb
Host smart-ffe51a69-f0e7-4637-8271-34608c55959c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937429577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.937429577
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2360788318
Short name T628
Test name
Test status
Simulation time 5184755763 ps
CPU time 10.04 seconds
Started Jul 10 04:55:49 PM PDT 24
Finished Jul 10 04:56:00 PM PDT 24
Peak memory 198580 kb
Host smart-d560f243-6184-4a34-bf74-4f9406f814f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360788318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2360788318
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.4038929946
Short name T1014
Test name
Test status
Simulation time 51548461764 ps
CPU time 82.94 seconds
Started Jul 10 04:55:48 PM PDT 24
Finished Jul 10 04:57:12 PM PDT 24
Peak memory 199800 kb
Host smart-c8090ab8-fb36-4624-b974-446e5ae65416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038929946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.4038929946
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2446012176
Short name T359
Test name
Test status
Simulation time 2867380717 ps
CPU time 1.76 seconds
Started Jul 10 04:55:49 PM PDT 24
Finished Jul 10 04:55:52 PM PDT 24
Peak memory 196220 kb
Host smart-8290d856-15ee-4d95-bfde-c16c91ac868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446012176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2446012176
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1735354727
Short name T888
Test name
Test status
Simulation time 6169806857 ps
CPU time 7.81 seconds
Started Jul 10 04:55:38 PM PDT 24
Finished Jul 10 04:55:47 PM PDT 24
Peak memory 199688 kb
Host smart-10bfc111-ec23-4d04-bafa-d91a47362a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735354727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1735354727
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2178561304
Short name T350
Test name
Test status
Simulation time 270037483816 ps
CPU time 206.8 seconds
Started Jul 10 04:55:47 PM PDT 24
Finished Jul 10 04:59:16 PM PDT 24
Peak memory 215900 kb
Host smart-532fe1c2-8e4b-47bf-98e8-e7983e035e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178561304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2178561304
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4273917667
Short name T385
Test name
Test status
Simulation time 556272489 ps
CPU time 2.19 seconds
Started Jul 10 04:55:50 PM PDT 24
Finished Jul 10 04:55:53 PM PDT 24
Peak memory 198240 kb
Host smart-d3d98449-e95d-4275-8a20-b73a5e1df3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273917667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4273917667
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.667379342
Short name T1175
Test name
Test status
Simulation time 29278041812 ps
CPU time 52.18 seconds
Started Jul 10 04:55:39 PM PDT 24
Finished Jul 10 04:56:33 PM PDT 24
Peak memory 199844 kb
Host smart-39da6f66-451c-4f96-a3b5-5af14b7777dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667379342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.667379342
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2008955268
Short name T609
Test name
Test status
Simulation time 10166739 ps
CPU time 0.55 seconds
Started Jul 10 04:55:55 PM PDT 24
Finished Jul 10 04:55:57 PM PDT 24
Peak memory 194420 kb
Host smart-311ed77d-8493-4b86-b96f-380294878013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008955268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2008955268
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3680753497
Short name T829
Test name
Test status
Simulation time 233993541683 ps
CPU time 368.13 seconds
Started Jul 10 04:55:47 PM PDT 24
Finished Jul 10 05:01:57 PM PDT 24
Peak memory 199840 kb
Host smart-00187510-fa4d-43ba-a17a-c221979590d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680753497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3680753497
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2049424003
Short name T183
Test name
Test status
Simulation time 46105203594 ps
CPU time 47.11 seconds
Started Jul 10 04:55:47 PM PDT 24
Finished Jul 10 04:56:35 PM PDT 24
Peak memory 199808 kb
Host smart-9f8a613b-b2ac-4a43-8c1d-8ce54e294167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049424003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2049424003
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3159536864
Short name T461
Test name
Test status
Simulation time 16368795575 ps
CPU time 22.08 seconds
Started Jul 10 04:55:46 PM PDT 24
Finished Jul 10 04:56:09 PM PDT 24
Peak memory 199824 kb
Host smart-acd737e1-eeaa-4485-b6ba-a7695d9dc5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159536864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3159536864
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1208207151
Short name T1034
Test name
Test status
Simulation time 254543276620 ps
CPU time 211.18 seconds
Started Jul 10 04:55:54 PM PDT 24
Finished Jul 10 04:59:27 PM PDT 24
Peak memory 199100 kb
Host smart-8bd98a4e-1d21-4ee0-8f1a-95b4321d5256
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208207151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1208207151
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.4247975951
Short name T756
Test name
Test status
Simulation time 48427854628 ps
CPU time 353.49 seconds
Started Jul 10 04:55:54 PM PDT 24
Finished Jul 10 05:01:48 PM PDT 24
Peak memory 199744 kb
Host smart-cdd2b5c8-f168-478a-87f9-eacd00dd15a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247975951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.4247975951
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1693898342
Short name T618
Test name
Test status
Simulation time 5499107362 ps
CPU time 9.55 seconds
Started Jul 10 04:55:56 PM PDT 24
Finished Jul 10 04:56:07 PM PDT 24
Peak memory 199644 kb
Host smart-ec7a4232-6d77-44b5-9d2a-94356453e046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693898342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1693898342
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.438657558
Short name T541
Test name
Test status
Simulation time 11936665569 ps
CPU time 20.34 seconds
Started Jul 10 04:55:54 PM PDT 24
Finished Jul 10 04:56:17 PM PDT 24
Peak memory 196164 kb
Host smart-f423caf1-1987-4cdc-ae26-9bee59e79fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438657558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.438657558
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1728641200
Short name T994
Test name
Test status
Simulation time 21688225524 ps
CPU time 530.48 seconds
Started Jul 10 04:55:54 PM PDT 24
Finished Jul 10 05:04:46 PM PDT 24
Peak memory 199808 kb
Host smart-302d8570-5d01-4eca-875a-1b86d4970cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728641200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1728641200
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.485891594
Short name T616
Test name
Test status
Simulation time 7058247993 ps
CPU time 18.03 seconds
Started Jul 10 04:55:46 PM PDT 24
Finished Jul 10 04:56:05 PM PDT 24
Peak memory 199804 kb
Host smart-5c0004f3-2453-4de0-a4d4-858b31fb2e2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485891594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.485891594
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1165076862
Short name T296
Test name
Test status
Simulation time 19837303656 ps
CPU time 27.38 seconds
Started Jul 10 04:55:55 PM PDT 24
Finished Jul 10 04:56:24 PM PDT 24
Peak memory 199756 kb
Host smart-6a1abaa9-eac8-446f-97e3-05e0a85bf582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165076862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1165076862
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3512540967
Short name T1140
Test name
Test status
Simulation time 6753627144 ps
CPU time 10.94 seconds
Started Jul 10 04:55:55 PM PDT 24
Finished Jul 10 04:56:08 PM PDT 24
Peak memory 195896 kb
Host smart-9260abdc-5560-4b56-a910-fb0af723f251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512540967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3512540967
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.535990144
Short name T299
Test name
Test status
Simulation time 691233544 ps
CPU time 1.83 seconds
Started Jul 10 04:55:47 PM PDT 24
Finished Jul 10 04:55:50 PM PDT 24
Peak memory 199420 kb
Host smart-2939a2de-0aa8-4de1-bdcd-b69871abac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535990144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.535990144
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3937095599
Short name T1050
Test name
Test status
Simulation time 258420882881 ps
CPU time 709.68 seconds
Started Jul 10 04:55:55 PM PDT 24
Finished Jul 10 05:07:47 PM PDT 24
Peak memory 199812 kb
Host smart-796c0b7e-e62c-46c4-8918-e1c11e974bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937095599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3937095599
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2392226435
Short name T373
Test name
Test status
Simulation time 67086925611 ps
CPU time 207.12 seconds
Started Jul 10 04:55:53 PM PDT 24
Finished Jul 10 04:59:21 PM PDT 24
Peak memory 208284 kb
Host smart-f6409d99-7567-4a53-bad8-b3f5675aae56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392226435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2392226435
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2750164375
Short name T1003
Test name
Test status
Simulation time 6700063516 ps
CPU time 23.97 seconds
Started Jul 10 04:55:58 PM PDT 24
Finished Jul 10 04:56:23 PM PDT 24
Peak memory 199804 kb
Host smart-d8c24bd7-a6f0-4314-85c6-14e7ea9f7f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750164375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2750164375
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1816377680
Short name T1083
Test name
Test status
Simulation time 90048116317 ps
CPU time 45.54 seconds
Started Jul 10 04:55:46 PM PDT 24
Finished Jul 10 04:56:32 PM PDT 24
Peak memory 199856 kb
Host smart-99af66bb-5ff7-45c2-980d-f3842e9eb9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816377680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1816377680
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.211996385
Short name T916
Test name
Test status
Simulation time 65109185 ps
CPU time 0.61 seconds
Started Jul 10 04:56:02 PM PDT 24
Finished Jul 10 04:56:03 PM PDT 24
Peak memory 195156 kb
Host smart-5655b829-a775-4f3c-b468-bc953e6838a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211996385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.211996385
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.4285757407
Short name T1049
Test name
Test status
Simulation time 53481122894 ps
CPU time 82.83 seconds
Started Jul 10 04:55:55 PM PDT 24
Finished Jul 10 04:57:20 PM PDT 24
Peak memory 199780 kb
Host smart-1e909592-5406-4430-919f-eba76bad89c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285757407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4285757407
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3154669167
Short name T1090
Test name
Test status
Simulation time 180672669850 ps
CPU time 65.73 seconds
Started Jul 10 04:55:52 PM PDT 24
Finished Jul 10 04:56:59 PM PDT 24
Peak memory 199912 kb
Host smart-d3dcdadd-fdb0-4904-8dd8-2e22c3398e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154669167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3154669167
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2210541420
Short name T702
Test name
Test status
Simulation time 125140444517 ps
CPU time 98.81 seconds
Started Jul 10 04:55:53 PM PDT 24
Finished Jul 10 04:57:33 PM PDT 24
Peak memory 199744 kb
Host smart-efd36185-37e8-4cce-9d1b-342bcb7c8c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210541420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2210541420
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.144221502
Short name T882
Test name
Test status
Simulation time 68397050404 ps
CPU time 52.07 seconds
Started Jul 10 04:56:03 PM PDT 24
Finished Jul 10 04:56:55 PM PDT 24
Peak memory 198812 kb
Host smart-1bf5d2cc-cc6d-4982-a5db-ac5dff9b911f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144221502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.144221502
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1680389833
Short name T891
Test name
Test status
Simulation time 154154180051 ps
CPU time 729.71 seconds
Started Jul 10 04:56:03 PM PDT 24
Finished Jul 10 05:08:13 PM PDT 24
Peak memory 199724 kb
Host smart-72587c54-4fa4-4149-a121-c5249ffbab18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1680389833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1680389833
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.775161371
Short name T931
Test name
Test status
Simulation time 11810536609 ps
CPU time 3.4 seconds
Started Jul 10 04:56:01 PM PDT 24
Finished Jul 10 04:56:06 PM PDT 24
Peak memory 199776 kb
Host smart-89d95efc-f2e7-484e-9b34-391fde5a88a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775161371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.775161371
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.97219080
Short name T745
Test name
Test status
Simulation time 82204009280 ps
CPU time 134.11 seconds
Started Jul 10 04:56:03 PM PDT 24
Finished Jul 10 04:58:17 PM PDT 24
Peak memory 198628 kb
Host smart-1ddb4427-3c36-44e9-8a5b-5869d807d59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97219080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.97219080
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2966361787
Short name T591
Test name
Test status
Simulation time 5596654783 ps
CPU time 80.93 seconds
Started Jul 10 04:56:01 PM PDT 24
Finished Jul 10 04:57:23 PM PDT 24
Peak memory 199808 kb
Host smart-135506bd-30cc-4d21-b10e-f76b2c5c5614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966361787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2966361787
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2618310528
Short name T671
Test name
Test status
Simulation time 5532811595 ps
CPU time 9.45 seconds
Started Jul 10 04:56:03 PM PDT 24
Finished Jul 10 04:56:13 PM PDT 24
Peak memory 198888 kb
Host smart-580bc7e8-edf3-422a-8e80-4c3d70c68716
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618310528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2618310528
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1784493875
Short name T376
Test name
Test status
Simulation time 131547538564 ps
CPU time 111.2 seconds
Started Jul 10 04:56:02 PM PDT 24
Finished Jul 10 04:57:54 PM PDT 24
Peak memory 199820 kb
Host smart-34462507-bdb6-4e09-8d75-b8f678ffbb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784493875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1784493875
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.725338675
Short name T689
Test name
Test status
Simulation time 3137367740 ps
CPU time 2.54 seconds
Started Jul 10 04:56:02 PM PDT 24
Finished Jul 10 04:56:05 PM PDT 24
Peak memory 195836 kb
Host smart-87b2adce-fb17-450e-acb9-c4c41bd49d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725338675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.725338675
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1240408438
Short name T1060
Test name
Test status
Simulation time 6086233131 ps
CPU time 7.77 seconds
Started Jul 10 04:55:55 PM PDT 24
Finished Jul 10 04:56:05 PM PDT 24
Peak memory 199792 kb
Host smart-9fa3dd97-1608-4c36-bb97-6862584e2c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240408438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1240408438
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2806131946
Short name T786
Test name
Test status
Simulation time 184407407981 ps
CPU time 277.53 seconds
Started Jul 10 04:56:02 PM PDT 24
Finished Jul 10 05:00:40 PM PDT 24
Peak memory 208140 kb
Host smart-d67e9375-3548-467d-955e-104c33e81252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806131946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2806131946
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3985440675
Short name T538
Test name
Test status
Simulation time 91854931284 ps
CPU time 498.77 seconds
Started Jul 10 04:56:02 PM PDT 24
Finished Jul 10 05:04:21 PM PDT 24
Peak memory 216484 kb
Host smart-b8c5c24b-5b3a-4665-b18f-99e958549105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985440675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3985440675
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2212011333
Short name T878
Test name
Test status
Simulation time 7904666411 ps
CPU time 13.89 seconds
Started Jul 10 04:56:01 PM PDT 24
Finished Jul 10 04:56:15 PM PDT 24
Peak memory 199732 kb
Host smart-912a29b6-269d-4b81-8792-e83a38aa7ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212011333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2212011333
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.752414603
Short name T970
Test name
Test status
Simulation time 114626038131 ps
CPU time 47.62 seconds
Started Jul 10 04:55:54 PM PDT 24
Finished Jul 10 04:56:43 PM PDT 24
Peak memory 199828 kb
Host smart-a9f69231-cd8b-4f75-a5b6-538ee10c10fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752414603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.752414603
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4030157250
Short name T497
Test name
Test status
Simulation time 40490188 ps
CPU time 0.58 seconds
Started Jul 10 04:56:11 PM PDT 24
Finished Jul 10 04:56:13 PM PDT 24
Peak memory 195156 kb
Host smart-dc0d489f-2cda-49da-b7f5-173fd52ee3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030157250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4030157250
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.819908768
Short name T580
Test name
Test status
Simulation time 48908599990 ps
CPU time 20.91 seconds
Started Jul 10 04:56:08 PM PDT 24
Finished Jul 10 04:56:30 PM PDT 24
Peak memory 199832 kb
Host smart-3baace45-4d7b-4cb6-b662-8f934f72189e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819908768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.819908768
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3277537681
Short name T1177
Test name
Test status
Simulation time 42380012597 ps
CPU time 9.51 seconds
Started Jul 10 04:56:10 PM PDT 24
Finished Jul 10 04:56:22 PM PDT 24
Peak memory 198688 kb
Host smart-650de4e6-196f-4387-ba6a-03400f1e2bc6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277537681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3277537681
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3212368593
Short name T761
Test name
Test status
Simulation time 124488441807 ps
CPU time 1054.43 seconds
Started Jul 10 04:56:10 PM PDT 24
Finished Jul 10 05:13:46 PM PDT 24
Peak memory 199784 kb
Host smart-1742cf2e-5b0a-4c1d-9dec-1a0c3b219f47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212368593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3212368593
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4274717220
Short name T1068
Test name
Test status
Simulation time 12020099832 ps
CPU time 15.06 seconds
Started Jul 10 04:56:09 PM PDT 24
Finished Jul 10 04:56:24 PM PDT 24
Peak memory 198344 kb
Host smart-c4138396-e136-406a-bc8d-bc052d1d0f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274717220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4274717220
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1264410236
Short name T473
Test name
Test status
Simulation time 120274644162 ps
CPU time 99.79 seconds
Started Jul 10 04:56:10 PM PDT 24
Finished Jul 10 04:57:51 PM PDT 24
Peak memory 200004 kb
Host smart-e690b91b-2da3-4136-a08d-deaf6aff0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264410236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1264410236
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1381455068
Short name T333
Test name
Test status
Simulation time 22723881657 ps
CPU time 185.52 seconds
Started Jul 10 04:56:09 PM PDT 24
Finished Jul 10 04:59:15 PM PDT 24
Peak memory 199808 kb
Host smart-90b45fb7-45c9-4fa4-abf4-a281fd383659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381455068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1381455068
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.16260119
Short name T665
Test name
Test status
Simulation time 7075561460 ps
CPU time 15.7 seconds
Started Jul 10 04:56:11 PM PDT 24
Finished Jul 10 04:56:28 PM PDT 24
Peak memory 198012 kb
Host smart-301abc24-43db-46a0-bd1c-9f706b727554
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16260119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.16260119
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2495536683
Short name T193
Test name
Test status
Simulation time 125324411304 ps
CPU time 54.31 seconds
Started Jul 10 04:56:11 PM PDT 24
Finished Jul 10 04:57:07 PM PDT 24
Peak memory 199780 kb
Host smart-93629940-2483-40d9-8eb6-aa06f5319912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495536683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2495536683
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2298392907
Short name T552
Test name
Test status
Simulation time 32922102184 ps
CPU time 26.56 seconds
Started Jul 10 04:56:10 PM PDT 24
Finished Jul 10 04:56:38 PM PDT 24
Peak memory 195872 kb
Host smart-a5e5807e-6f66-4a67-8eb6-78a993cc0192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298392907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2298392907
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3216890676
Short name T943
Test name
Test status
Simulation time 908379593 ps
CPU time 1.82 seconds
Started Jul 10 04:56:03 PM PDT 24
Finished Jul 10 04:56:05 PM PDT 24
Peak memory 198304 kb
Host smart-cbf020fa-c78c-497d-a81c-c3aee56d00f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216890676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3216890676
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2842391177
Short name T124
Test name
Test status
Simulation time 26322587605 ps
CPU time 49.93 seconds
Started Jul 10 04:56:08 PM PDT 24
Finished Jul 10 04:56:58 PM PDT 24
Peak memory 199764 kb
Host smart-1299d49b-da3a-4c72-a1c1-9f0500d2172d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842391177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2842391177
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.4272750672
Short name T188
Test name
Test status
Simulation time 251187132078 ps
CPU time 1116.29 seconds
Started Jul 10 04:56:09 PM PDT 24
Finished Jul 10 05:14:47 PM PDT 24
Peak memory 226056 kb
Host smart-e394a7b4-d591-479c-9c52-8ec5a23a04d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272750672 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.4272750672
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2632908378
Short name T747
Test name
Test status
Simulation time 2256099494 ps
CPU time 1.5 seconds
Started Jul 10 04:56:10 PM PDT 24
Finished Jul 10 04:56:14 PM PDT 24
Peak memory 199076 kb
Host smart-17daeba8-4110-4e1c-9ffe-d6f64c463e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632908378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2632908378
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1315236589
Short name T265
Test name
Test status
Simulation time 155411754269 ps
CPU time 157.7 seconds
Started Jul 10 04:56:11 PM PDT 24
Finished Jul 10 04:58:50 PM PDT 24
Peak memory 199784 kb
Host smart-eae5f64f-3d2c-460b-b451-8680399ebd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315236589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1315236589
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.4235135040
Short name T874
Test name
Test status
Simulation time 17068831 ps
CPU time 0.57 seconds
Started Jul 10 04:56:20 PM PDT 24
Finished Jul 10 04:56:22 PM PDT 24
Peak memory 195132 kb
Host smart-87a5431a-f0f3-4135-81a6-6c448a3af134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235135040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4235135040
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.458366772
Short name T604
Test name
Test status
Simulation time 21483135602 ps
CPU time 31.73 seconds
Started Jul 10 04:56:11 PM PDT 24
Finished Jul 10 04:56:44 PM PDT 24
Peak memory 199828 kb
Host smart-d3f49f8e-f95a-4e07-9243-a237622e3630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458366772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.458366772
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.253056558
Short name T968
Test name
Test status
Simulation time 244553504940 ps
CPU time 28.89 seconds
Started Jul 10 04:56:09 PM PDT 24
Finished Jul 10 04:56:38 PM PDT 24
Peak memory 199728 kb
Host smart-d03dc89b-a7a7-4449-a89e-f52b45fd0e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253056558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.253056558
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.3471163868
Short name T1046
Test name
Test status
Simulation time 11228068951 ps
CPU time 8.54 seconds
Started Jul 10 04:56:17 PM PDT 24
Finished Jul 10 04:56:26 PM PDT 24
Peak memory 196224 kb
Host smart-e8bad914-c8a5-42db-95c1-b3e1bd6bb5e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471163868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3471163868
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2723440845
Short name T403
Test name
Test status
Simulation time 96841128706 ps
CPU time 624.04 seconds
Started Jul 10 04:56:18 PM PDT 24
Finished Jul 10 05:06:43 PM PDT 24
Peak memory 199792 kb
Host smart-a1b865be-42b5-4bbc-b3c6-ea426a2c4baa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723440845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2723440845
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4280391163
Short name T518
Test name
Test status
Simulation time 2614788598 ps
CPU time 6.27 seconds
Started Jul 10 04:56:20 PM PDT 24
Finished Jul 10 04:56:28 PM PDT 24
Peak memory 198560 kb
Host smart-22cc5436-271c-43b5-9e53-167415e2d295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280391163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4280391163
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.553173637
Short name T737
Test name
Test status
Simulation time 96717377164 ps
CPU time 118.86 seconds
Started Jul 10 04:56:16 PM PDT 24
Finished Jul 10 04:58:16 PM PDT 24
Peak memory 199988 kb
Host smart-27d39f12-b465-4fcb-b544-db6f0f218916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553173637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.553173637
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.483208066
Short name T287
Test name
Test status
Simulation time 11908886581 ps
CPU time 689.73 seconds
Started Jul 10 04:56:16 PM PDT 24
Finished Jul 10 05:07:47 PM PDT 24
Peak memory 199760 kb
Host smart-3fae898a-7762-4345-b8e6-e0ad39a2a0dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483208066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.483208066
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1042655381
Short name T9
Test name
Test status
Simulation time 2548245031 ps
CPU time 3.87 seconds
Started Jul 10 04:56:16 PM PDT 24
Finished Jul 10 04:56:21 PM PDT 24
Peak memory 198716 kb
Host smart-4b328739-81a6-4af6-929d-95a3e99b5490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042655381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1042655381
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.4222251083
Short name T282
Test name
Test status
Simulation time 52259154315 ps
CPU time 69.77 seconds
Started Jul 10 04:56:15 PM PDT 24
Finished Jul 10 04:57:25 PM PDT 24
Peak memory 199844 kb
Host smart-7f9e434b-63d1-4034-b7e2-ab3d0bf60a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222251083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.4222251083
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1168830133
Short name T33
Test name
Test status
Simulation time 5516508603 ps
CPU time 4.3 seconds
Started Jul 10 04:56:15 PM PDT 24
Finished Jul 10 04:56:20 PM PDT 24
Peak memory 195940 kb
Host smart-27f93f9f-0c75-4126-a321-e563b4b84b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168830133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1168830133
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2027812695
Short name T331
Test name
Test status
Simulation time 522604974 ps
CPU time 1.27 seconds
Started Jul 10 04:56:13 PM PDT 24
Finished Jul 10 04:56:15 PM PDT 24
Peak memory 198488 kb
Host smart-1374a3c7-0ebd-4f75-87a9-4e5425295534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027812695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2027812695
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3732682709
Short name T321
Test name
Test status
Simulation time 167229407232 ps
CPU time 290.84 seconds
Started Jul 10 04:56:17 PM PDT 24
Finished Jul 10 05:01:09 PM PDT 24
Peak memory 199808 kb
Host smart-00ae94b6-dbbf-42a8-aa00-d77a314918da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732682709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3732682709
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.722489353
Short name T54
Test name
Test status
Simulation time 125547244048 ps
CPU time 289.46 seconds
Started Jul 10 04:56:17 PM PDT 24
Finished Jul 10 05:01:07 PM PDT 24
Peak memory 216704 kb
Host smart-63cf19cf-db83-4436-bc2a-402567c708e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722489353 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.722489353
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.125042509
Short name T19
Test name
Test status
Simulation time 653503061 ps
CPU time 2.69 seconds
Started Jul 10 04:56:16 PM PDT 24
Finished Jul 10 04:56:20 PM PDT 24
Peak memory 199788 kb
Host smart-d41b1b4b-7f66-4b9b-9c09-22415ce6d333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125042509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.125042509
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1522489242
Short name T733
Test name
Test status
Simulation time 70648281018 ps
CPU time 210.59 seconds
Started Jul 10 04:56:11 PM PDT 24
Finished Jul 10 04:59:43 PM PDT 24
Peak memory 199832 kb
Host smart-6cbc8514-f068-4de8-87d5-da733a028f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522489242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1522489242
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1108785161
Short name T813
Test name
Test status
Simulation time 45147960 ps
CPU time 0.56 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:52:01 PM PDT 24
Peak memory 194604 kb
Host smart-a8d9ba5d-efe4-4de8-88c0-ec10cc7a5c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108785161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1108785161
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2252663919
Short name T293
Test name
Test status
Simulation time 47388085367 ps
CPU time 19.49 seconds
Started Jul 10 04:52:03 PM PDT 24
Finished Jul 10 04:52:23 PM PDT 24
Peak memory 198892 kb
Host smart-a217b0d4-a108-4edc-99d7-2985c625cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252663919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2252663919
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3194137282
Short name T276
Test name
Test status
Simulation time 85128727911 ps
CPU time 155.71 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:54:36 PM PDT 24
Peak memory 199836 kb
Host smart-c98351fa-4f5a-4327-9950-daa1a49e7c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194137282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3194137282
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.709964799
Short name T676
Test name
Test status
Simulation time 79407615773 ps
CPU time 108.7 seconds
Started Jul 10 04:52:00 PM PDT 24
Finished Jul 10 04:53:50 PM PDT 24
Peak memory 199776 kb
Host smart-220df7a7-e32f-44e7-b088-8c5cba95133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709964799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.709964799
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.171478657
Short name T130
Test name
Test status
Simulation time 32873304521 ps
CPU time 13.83 seconds
Started Jul 10 04:52:01 PM PDT 24
Finished Jul 10 04:52:16 PM PDT 24
Peak memory 200108 kb
Host smart-95d9e5ab-22b7-490d-85a7-e81d389b49fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171478657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.171478657
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2742083166
Short name T291
Test name
Test status
Simulation time 217691299676 ps
CPU time 425.84 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:59:06 PM PDT 24
Peak memory 199800 kb
Host smart-e0aa1de2-8b36-4449-94cc-266b9dec77d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742083166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2742083166
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.564237336
Short name T1163
Test name
Test status
Simulation time 9502196627 ps
CPU time 18.65 seconds
Started Jul 10 04:52:01 PM PDT 24
Finished Jul 10 04:52:21 PM PDT 24
Peak memory 199732 kb
Host smart-4f33f2dc-1b8d-4f00-a9e0-099eb83277f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564237336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.564237336
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1845067430
Short name T679
Test name
Test status
Simulation time 75856634940 ps
CPU time 34.75 seconds
Started Jul 10 04:52:00 PM PDT 24
Finished Jul 10 04:52:36 PM PDT 24
Peak memory 199748 kb
Host smart-1f14f076-4d37-4b62-ae2f-86fb09a94909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845067430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1845067430
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3509811905
Short name T547
Test name
Test status
Simulation time 12859088921 ps
CPU time 176.94 seconds
Started Jul 10 04:52:02 PM PDT 24
Finished Jul 10 04:55:00 PM PDT 24
Peak memory 199784 kb
Host smart-db39f1bb-c66c-4f29-bbe2-be03cb15c789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509811905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3509811905
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1896919081
Short name T770
Test name
Test status
Simulation time 6475261980 ps
CPU time 14.38 seconds
Started Jul 10 04:52:00 PM PDT 24
Finished Jul 10 04:52:16 PM PDT 24
Peak memory 198088 kb
Host smart-c5b6a97a-b2e4-4f63-885e-c5060565ab6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896919081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1896919081
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.4221286204
Short name T768
Test name
Test status
Simulation time 83501479563 ps
CPU time 132.5 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:54:13 PM PDT 24
Peak memory 199828 kb
Host smart-aae3c633-c0bb-46ee-a9ad-332be12f5f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221286204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.4221286204
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2813248620
Short name T454
Test name
Test status
Simulation time 31262381853 ps
CPU time 43.91 seconds
Started Jul 10 04:52:03 PM PDT 24
Finished Jul 10 04:52:48 PM PDT 24
Peak memory 196232 kb
Host smart-0c600249-b0af-428c-ac4a-68fcb0d7e748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813248620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2813248620
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3223337934
Short name T31
Test name
Test status
Simulation time 80916138 ps
CPU time 0.85 seconds
Started Jul 10 04:52:00 PM PDT 24
Finished Jul 10 04:52:02 PM PDT 24
Peak memory 218080 kb
Host smart-58a47cee-4d64-47eb-b0c5-8b74de3c799c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223337934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3223337934
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1953753072
Short name T40
Test name
Test status
Simulation time 440581075 ps
CPU time 1.69 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:52:02 PM PDT 24
Peak memory 199396 kb
Host smart-7c2f0b8c-7509-4e93-b307-e62caf05fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953753072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1953753072
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1322125699
Short name T620
Test name
Test status
Simulation time 588216497644 ps
CPU time 78.5 seconds
Started Jul 10 04:52:01 PM PDT 24
Finished Jul 10 04:53:21 PM PDT 24
Peak memory 199784 kb
Host smart-696a4923-b96c-42d6-b870-fab9a096f8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322125699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1322125699
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1860992433
Short name T751
Test name
Test status
Simulation time 28587059995 ps
CPU time 229.72 seconds
Started Jul 10 04:51:59 PM PDT 24
Finished Jul 10 04:55:50 PM PDT 24
Peak memory 216544 kb
Host smart-23ee4921-9adb-45a7-be26-e4e406c4e4f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860992433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1860992433
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2509129683
Short name T624
Test name
Test status
Simulation time 966558270 ps
CPU time 3.56 seconds
Started Jul 10 04:51:58 PM PDT 24
Finished Jul 10 04:52:03 PM PDT 24
Peak memory 198128 kb
Host smart-e0a4147c-d31b-4585-933e-36dc91649762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509129683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2509129683
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2004466235
Short name T712
Test name
Test status
Simulation time 69768330184 ps
CPU time 14.7 seconds
Started Jul 10 04:51:58 PM PDT 24
Finished Jul 10 04:52:14 PM PDT 24
Peak memory 199824 kb
Host smart-1de11e49-6615-4c67-a43b-012ead61d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004466235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2004466235
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.459228103
Short name T1093
Test name
Test status
Simulation time 12420884 ps
CPU time 0.55 seconds
Started Jul 10 04:56:24 PM PDT 24
Finished Jul 10 04:56:26 PM PDT 24
Peak memory 195144 kb
Host smart-4e5471c8-8d12-43af-a75b-93be5b4264bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459228103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.459228103
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3596347438
Short name T839
Test name
Test status
Simulation time 43080526128 ps
CPU time 65.69 seconds
Started Jul 10 04:56:16 PM PDT 24
Finished Jul 10 04:57:24 PM PDT 24
Peak memory 199748 kb
Host smart-50f2d170-7ee8-4491-ac41-ae583068937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596347438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3596347438
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.717681201
Short name T458
Test name
Test status
Simulation time 15878048136 ps
CPU time 24.42 seconds
Started Jul 10 04:56:14 PM PDT 24
Finished Jul 10 04:56:40 PM PDT 24
Peak memory 198996 kb
Host smart-032e7008-0e55-45e0-b401-b3bd6463aa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717681201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.717681201
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2316911509
Short name T718
Test name
Test status
Simulation time 34236751060 ps
CPU time 15.56 seconds
Started Jul 10 04:56:20 PM PDT 24
Finished Jul 10 04:56:37 PM PDT 24
Peak memory 199800 kb
Host smart-7c889ba9-52be-44b1-8a46-94bd8c1072b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316911509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2316911509
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2075350885
Short name T865
Test name
Test status
Simulation time 139819653638 ps
CPU time 519.2 seconds
Started Jul 10 04:56:24 PM PDT 24
Finished Jul 10 05:05:04 PM PDT 24
Peak memory 199752 kb
Host smart-fe438da5-b829-4bb1-b1e5-296bee26a41b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075350885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2075350885
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3960432441
Short name T990
Test name
Test status
Simulation time 9467064294 ps
CPU time 2.7 seconds
Started Jul 10 04:56:26 PM PDT 24
Finished Jul 10 04:56:30 PM PDT 24
Peak memory 198812 kb
Host smart-d6ccc7d9-aca3-4962-97ff-c0bfc0a471ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960432441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3960432441
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2544329094
Short name T328
Test name
Test status
Simulation time 74362663582 ps
CPU time 33.11 seconds
Started Jul 10 04:56:23 PM PDT 24
Finished Jul 10 04:56:56 PM PDT 24
Peak memory 200004 kb
Host smart-ef7ae256-1dd4-4cae-a29e-0ae8782a3704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544329094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2544329094
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.376779756
Short name T760
Test name
Test status
Simulation time 13715180604 ps
CPU time 706.83 seconds
Started Jul 10 04:56:24 PM PDT 24
Finished Jul 10 05:08:12 PM PDT 24
Peak memory 199792 kb
Host smart-b653fc89-0713-41b6-9aa4-545aa9bee271
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376779756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.376779756
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.725156405
Short name T102
Test name
Test status
Simulation time 6829157048 ps
CPU time 64.13 seconds
Started Jul 10 04:56:16 PM PDT 24
Finished Jul 10 04:57:22 PM PDT 24
Peak memory 197912 kb
Host smart-99a8578b-b969-49fc-b272-1c971875de37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725156405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.725156405
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.4173313741
Short name T155
Test name
Test status
Simulation time 27364664463 ps
CPU time 14.03 seconds
Started Jul 10 04:56:24 PM PDT 24
Finished Jul 10 04:56:38 PM PDT 24
Peak memory 199844 kb
Host smart-121f2e02-5df4-4281-b770-a9df67d85579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173313741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.4173313741
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2696794880
Short name T1096
Test name
Test status
Simulation time 2121406025 ps
CPU time 3.88 seconds
Started Jul 10 04:56:25 PM PDT 24
Finished Jul 10 04:56:30 PM PDT 24
Peak memory 195276 kb
Host smart-4037d910-5e28-4f4e-85ca-b1660fd614f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696794880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2696794880
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2474484359
Short name T1126
Test name
Test status
Simulation time 630449884 ps
CPU time 2.7 seconds
Started Jul 10 04:56:17 PM PDT 24
Finished Jul 10 04:56:21 PM PDT 24
Peak memory 198756 kb
Host smart-a525e794-6f4b-4a5b-ba3c-ec6b1d22b5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474484359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2474484359
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3811766789
Short name T425
Test name
Test status
Simulation time 108221556054 ps
CPU time 62.6 seconds
Started Jul 10 04:56:26 PM PDT 24
Finished Jul 10 04:57:29 PM PDT 24
Peak memory 199812 kb
Host smart-eb093829-b7d3-45ab-8865-f30ce0871bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811766789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3811766789
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2180047184
Short name T897
Test name
Test status
Simulation time 375705266381 ps
CPU time 1025.87 seconds
Started Jul 10 04:56:24 PM PDT 24
Finished Jul 10 05:13:31 PM PDT 24
Peak memory 224672 kb
Host smart-ea6038c0-5d2b-48dd-ad37-c5f9833191b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180047184 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2180047184
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1852946194
Short name T332
Test name
Test status
Simulation time 7552216006 ps
CPU time 4.59 seconds
Started Jul 10 04:56:25 PM PDT 24
Finished Jul 10 04:56:30 PM PDT 24
Peak memory 199236 kb
Host smart-20a101ae-9758-4093-a799-9c4ecd9e1e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852946194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1852946194
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3002519897
Short name T530
Test name
Test status
Simulation time 7398217846 ps
CPU time 21.67 seconds
Started Jul 10 04:56:16 PM PDT 24
Finished Jul 10 04:56:39 PM PDT 24
Peak memory 199836 kb
Host smart-e998ca6c-9f89-4c6c-9912-746d8dae29b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002519897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3002519897
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3094403042
Short name T595
Test name
Test status
Simulation time 37492495 ps
CPU time 0.55 seconds
Started Jul 10 04:56:35 PM PDT 24
Finished Jul 10 04:56:37 PM PDT 24
Peak memory 195156 kb
Host smart-27d88467-cafe-4074-8644-36c8fedc0c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094403042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3094403042
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2038830420
Short name T143
Test name
Test status
Simulation time 18820485859 ps
CPU time 27.63 seconds
Started Jul 10 04:56:26 PM PDT 24
Finished Jul 10 04:56:54 PM PDT 24
Peak memory 199840 kb
Host smart-180bee67-ad62-42ab-b632-6d715ad257ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038830420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2038830420
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1985224232
Short name T640
Test name
Test status
Simulation time 21850765401 ps
CPU time 17.84 seconds
Started Jul 10 04:56:25 PM PDT 24
Finished Jul 10 04:56:44 PM PDT 24
Peak memory 199804 kb
Host smart-4a0b39a8-37c9-4f90-825c-0107964f9bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985224232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1985224232
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1081804547
Short name T471
Test name
Test status
Simulation time 28706114288 ps
CPU time 23.39 seconds
Started Jul 10 04:56:27 PM PDT 24
Finished Jul 10 04:56:51 PM PDT 24
Peak memory 199840 kb
Host smart-c57f0e16-3328-4600-ad77-3bb7ddd60d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081804547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1081804547
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2532397663
Short name T587
Test name
Test status
Simulation time 18654718513 ps
CPU time 30.84 seconds
Started Jul 10 04:56:27 PM PDT 24
Finished Jul 10 04:56:58 PM PDT 24
Peak memory 199584 kb
Host smart-75c01f02-7ba6-4938-9400-1a454e0643c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532397663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2532397663
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.906072647
Short name T467
Test name
Test status
Simulation time 100189240123 ps
CPU time 410.88 seconds
Started Jul 10 04:56:35 PM PDT 24
Finished Jul 10 05:03:27 PM PDT 24
Peak memory 199796 kb
Host smart-7436bcf0-4d89-4621-b907-e980a27948ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906072647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.906072647
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3617248694
Short name T629
Test name
Test status
Simulation time 13867181303 ps
CPU time 5.06 seconds
Started Jul 10 04:56:36 PM PDT 24
Finished Jul 10 04:56:42 PM PDT 24
Peak memory 199796 kb
Host smart-cf483bfe-c9c3-4e3a-b6d5-455d2b2200c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617248694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3617248694
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3587850959
Short name T969
Test name
Test status
Simulation time 362758664880 ps
CPU time 52.28 seconds
Started Jul 10 04:56:25 PM PDT 24
Finished Jul 10 04:57:18 PM PDT 24
Peak memory 208172 kb
Host smart-a60769fe-be09-4826-86ef-263791528721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587850959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3587850959
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3105440656
Short name T899
Test name
Test status
Simulation time 9744173755 ps
CPU time 584.12 seconds
Started Jul 10 04:56:35 PM PDT 24
Finished Jul 10 05:06:20 PM PDT 24
Peak memory 199748 kb
Host smart-56b18a6d-e34e-4edf-931c-cdd5b6a114e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105440656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3105440656
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.619247132
Short name T986
Test name
Test status
Simulation time 4735042128 ps
CPU time 10.54 seconds
Started Jul 10 04:56:24 PM PDT 24
Finished Jul 10 04:56:36 PM PDT 24
Peak memory 198024 kb
Host smart-06da7941-7789-49ac-8032-b0e32c5a7da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619247132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.619247132
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3494225955
Short name T999
Test name
Test status
Simulation time 465902918849 ps
CPU time 57.04 seconds
Started Jul 10 04:56:35 PM PDT 24
Finished Jul 10 04:57:33 PM PDT 24
Peak memory 199760 kb
Host smart-2b0f1c8c-8b40-4b3c-96c6-8692f6c03209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494225955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3494225955
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.4290688060
Short name T872
Test name
Test status
Simulation time 31040168096 ps
CPU time 23.19 seconds
Started Jul 10 04:56:36 PM PDT 24
Finished Jul 10 04:57:00 PM PDT 24
Peak memory 195968 kb
Host smart-e1ff08bd-d289-4ec1-bee3-f780a177c965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290688060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.4290688060
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3028162354
Short name T1040
Test name
Test status
Simulation time 100231320 ps
CPU time 0.91 seconds
Started Jul 10 04:56:24 PM PDT 24
Finished Jul 10 04:56:25 PM PDT 24
Peak memory 198144 kb
Host smart-149eae92-789e-4bc0-b019-7b2d8ba44b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028162354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3028162354
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2485377100
Short name T655
Test name
Test status
Simulation time 75488090861 ps
CPU time 76.11 seconds
Started Jul 10 04:56:35 PM PDT 24
Finished Jul 10 04:57:52 PM PDT 24
Peak memory 215420 kb
Host smart-dec0578a-c45b-43bb-a09a-7b50cb616890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485377100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2485377100
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1787794623
Short name T578
Test name
Test status
Simulation time 261172914826 ps
CPU time 1159.47 seconds
Started Jul 10 04:56:34 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 222664 kb
Host smart-814c84a9-440a-491a-bbfa-1a141b95d5e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787794623 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1787794623
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3033835321
Short name T1023
Test name
Test status
Simulation time 7051134656 ps
CPU time 27.4 seconds
Started Jul 10 04:56:34 PM PDT 24
Finished Jul 10 04:57:03 PM PDT 24
Peak memory 199820 kb
Host smart-78f2a496-0e7e-4429-a961-b414e7dc94f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033835321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3033835321
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.582504863
Short name T477
Test name
Test status
Simulation time 114632287433 ps
CPU time 64.41 seconds
Started Jul 10 04:56:26 PM PDT 24
Finished Jul 10 04:57:32 PM PDT 24
Peak memory 199820 kb
Host smart-ea9e9a28-9ded-4c2d-bcdf-eede14ab1790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582504863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.582504863
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2131830938
Short name T1037
Test name
Test status
Simulation time 16403164 ps
CPU time 0.54 seconds
Started Jul 10 04:56:42 PM PDT 24
Finished Jul 10 04:56:45 PM PDT 24
Peak memory 194200 kb
Host smart-c492ef9b-f675-442a-ad1f-e36a8fd8f614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131830938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2131830938
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3561374957
Short name T862
Test name
Test status
Simulation time 177669608491 ps
CPU time 222.85 seconds
Started Jul 10 04:56:34 PM PDT 24
Finished Jul 10 05:00:18 PM PDT 24
Peak memory 199768 kb
Host smart-b9538fda-466c-41ab-a2f0-717bcad618fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561374957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3561374957
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1139500784
Short name T192
Test name
Test status
Simulation time 119534090997 ps
CPU time 102.67 seconds
Started Jul 10 04:56:36 PM PDT 24
Finished Jul 10 04:58:19 PM PDT 24
Peak memory 199828 kb
Host smart-229e6de9-523c-48bc-a750-2f096a9319ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139500784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1139500784
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2369611552
Short name T234
Test name
Test status
Simulation time 135575139289 ps
CPU time 21.84 seconds
Started Jul 10 04:56:34 PM PDT 24
Finished Jul 10 04:56:58 PM PDT 24
Peak memory 199704 kb
Host smart-20a4389b-0e8f-4518-9195-b429252e865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369611552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2369611552
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1024191722
Short name T929
Test name
Test status
Simulation time 38493545791 ps
CPU time 54.89 seconds
Started Jul 10 04:56:42 PM PDT 24
Finished Jul 10 04:57:39 PM PDT 24
Peak memory 199820 kb
Host smart-893e0868-f1bd-49cc-b804-b300ce1d0ab4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024191722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1024191722
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2240011880
Short name T1115
Test name
Test status
Simulation time 107417418009 ps
CPU time 886.76 seconds
Started Jul 10 04:56:42 PM PDT 24
Finished Jul 10 05:11:30 PM PDT 24
Peak memory 199752 kb
Host smart-768fc973-16f9-4f09-8906-7fba940a0e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240011880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2240011880
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3252561269
Short name T24
Test name
Test status
Simulation time 3570301981 ps
CPU time 7.75 seconds
Started Jul 10 04:56:44 PM PDT 24
Finished Jul 10 04:56:53 PM PDT 24
Peak memory 199540 kb
Host smart-708863f9-d79c-4293-88e3-9af83a99936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252561269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3252561269
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.283905616
Short name T932
Test name
Test status
Simulation time 168941793865 ps
CPU time 84.32 seconds
Started Jul 10 04:56:43 PM PDT 24
Finished Jul 10 04:58:09 PM PDT 24
Peak memory 198500 kb
Host smart-02c09b47-664f-4280-821d-37b2d85678c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283905616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.283905616
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1840369734
Short name T610
Test name
Test status
Simulation time 18557877504 ps
CPU time 896.09 seconds
Started Jul 10 04:56:42 PM PDT 24
Finished Jul 10 05:11:40 PM PDT 24
Peak memory 199780 kb
Host smart-aef53e65-6c86-4d3f-923d-584ee5bb5d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840369734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1840369734
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.449252247
Short name T507
Test name
Test status
Simulation time 5412138845 ps
CPU time 47.78 seconds
Started Jul 10 04:56:36 PM PDT 24
Finished Jul 10 04:57:25 PM PDT 24
Peak memory 197952 kb
Host smart-98f672f5-1994-47b9-908a-5d1e3b5cce37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449252247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.449252247
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1859547563
Short name T569
Test name
Test status
Simulation time 133690810386 ps
CPU time 161.02 seconds
Started Jul 10 04:56:42 PM PDT 24
Finished Jul 10 04:59:25 PM PDT 24
Peak memory 199836 kb
Host smart-49761dbd-b93a-4f13-919d-e82aa86b07de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859547563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1859547563
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3609302555
Short name T430
Test name
Test status
Simulation time 37021543024 ps
CPU time 4.36 seconds
Started Jul 10 04:56:43 PM PDT 24
Finished Jul 10 04:56:49 PM PDT 24
Peak memory 195852 kb
Host smart-ef08ff8a-6c5f-4fc1-95f7-9a15136bdf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609302555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3609302555
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3942329452
Short name T1178
Test name
Test status
Simulation time 939278285 ps
CPU time 4.17 seconds
Started Jul 10 04:56:34 PM PDT 24
Finished Jul 10 04:56:40 PM PDT 24
Peak memory 199656 kb
Host smart-f5af44f1-26c9-4bc3-a2e6-a0b247ace3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942329452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3942329452
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.289574356
Short name T180
Test name
Test status
Simulation time 510424270035 ps
CPU time 127.76 seconds
Started Jul 10 04:56:43 PM PDT 24
Finished Jul 10 04:58:52 PM PDT 24
Peak memory 200096 kb
Host smart-77537beb-1b05-4631-8a55-f59b72f081ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289574356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.289574356
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2839894533
Short name T742
Test name
Test status
Simulation time 370788379844 ps
CPU time 364.53 seconds
Started Jul 10 04:56:43 PM PDT 24
Finished Jul 10 05:02:49 PM PDT 24
Peak memory 216348 kb
Host smart-2de5f434-31c2-48d1-8be8-ce945a7515e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839894533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2839894533
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.27542188
Short name T1085
Test name
Test status
Simulation time 12449570680 ps
CPU time 34.4 seconds
Started Jul 10 04:56:43 PM PDT 24
Finished Jul 10 04:57:19 PM PDT 24
Peak memory 199844 kb
Host smart-90fe2a3f-273c-4e63-bf04-9e48a752c017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27542188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.27542188
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.301450409
Short name T1026
Test name
Test status
Simulation time 53926043684 ps
CPU time 17.78 seconds
Started Jul 10 04:56:34 PM PDT 24
Finished Jul 10 04:56:53 PM PDT 24
Peak memory 199788 kb
Host smart-443b7d33-e697-4305-938d-660b5429eccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301450409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.301450409
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3516488836
Short name T885
Test name
Test status
Simulation time 33306967 ps
CPU time 0.56 seconds
Started Jul 10 04:56:53 PM PDT 24
Finished Jul 10 04:56:54 PM PDT 24
Peak memory 195148 kb
Host smart-d1baac21-950f-4820-97b6-ccc14eb73e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516488836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3516488836
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1598113354
Short name T483
Test name
Test status
Simulation time 34200902991 ps
CPU time 51.55 seconds
Started Jul 10 04:56:42 PM PDT 24
Finished Jul 10 04:57:36 PM PDT 24
Peak memory 199828 kb
Host smart-0a0b1156-9c45-4d87-bcf0-d7750b8f28ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598113354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1598113354
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3310448210
Short name T596
Test name
Test status
Simulation time 138563145849 ps
CPU time 229.95 seconds
Started Jul 10 04:56:41 PM PDT 24
Finished Jul 10 05:00:32 PM PDT 24
Peak memory 199832 kb
Host smart-9b7949b2-f6b5-4645-b2d3-e0079b5ea635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310448210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3310448210
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.785603916
Short name T436
Test name
Test status
Simulation time 139586162732 ps
CPU time 81.69 seconds
Started Jul 10 04:56:46 PM PDT 24
Finished Jul 10 04:58:08 PM PDT 24
Peak memory 199844 kb
Host smart-faf08de0-1af5-484f-9b66-ac3618616d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785603916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.785603916
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.531642348
Short name T412
Test name
Test status
Simulation time 12080856018 ps
CPU time 18.26 seconds
Started Jul 10 04:56:45 PM PDT 24
Finished Jul 10 04:57:04 PM PDT 24
Peak memory 196260 kb
Host smart-38bb1f80-e34a-4c84-906d-2818e5c73711
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531642348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.531642348
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4065597038
Short name T738
Test name
Test status
Simulation time 112636800490 ps
CPU time 406.97 seconds
Started Jul 10 04:56:54 PM PDT 24
Finished Jul 10 05:03:42 PM PDT 24
Peak memory 199728 kb
Host smart-390418f5-740d-4578-b9f5-2e09eaaccf07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065597038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4065597038
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2846378025
Short name T522
Test name
Test status
Simulation time 2276158164 ps
CPU time 2.51 seconds
Started Jul 10 04:56:54 PM PDT 24
Finished Jul 10 04:56:57 PM PDT 24
Peak memory 199660 kb
Host smart-f5a1a2a7-6dd5-49c1-b16b-4ec9d0711a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846378025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2846378025
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2617462682
Short name T1124
Test name
Test status
Simulation time 161874397474 ps
CPU time 79.89 seconds
Started Jul 10 04:56:43 PM PDT 24
Finished Jul 10 04:58:05 PM PDT 24
Peak memory 199484 kb
Host smart-b911eb80-ae06-424a-8feb-993f26a5aac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617462682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2617462682
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1460689802
Short name T46
Test name
Test status
Simulation time 16804606778 ps
CPU time 88.21 seconds
Started Jul 10 04:56:55 PM PDT 24
Finished Jul 10 04:58:24 PM PDT 24
Peak memory 199708 kb
Host smart-96534b18-0ca0-4bc9-bbbc-19c0281b8aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1460689802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1460689802
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1712970489
Short name T1181
Test name
Test status
Simulation time 2861210615 ps
CPU time 8.49 seconds
Started Jul 10 04:56:44 PM PDT 24
Finished Jul 10 04:56:53 PM PDT 24
Peak memory 199052 kb
Host smart-76445034-c415-4e66-9f8b-9a1e6b6ad8a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712970489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1712970489
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2060133287
Short name T799
Test name
Test status
Simulation time 83067887108 ps
CPU time 83.02 seconds
Started Jul 10 04:56:53 PM PDT 24
Finished Jul 10 04:58:17 PM PDT 24
Peak memory 199800 kb
Host smart-6e3c0662-5245-4b22-ba04-ca7d03fb3707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060133287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2060133287
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3260917005
Short name T474
Test name
Test status
Simulation time 2284240411 ps
CPU time 4 seconds
Started Jul 10 04:56:42 PM PDT 24
Finished Jul 10 04:56:47 PM PDT 24
Peak memory 195300 kb
Host smart-5cc4504c-4db7-4880-b658-d063483e18d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260917005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3260917005
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2017944500
Short name T1044
Test name
Test status
Simulation time 5762249614 ps
CPU time 24.89 seconds
Started Jul 10 04:56:43 PM PDT 24
Finished Jul 10 04:57:09 PM PDT 24
Peak memory 199104 kb
Host smart-a6cfe7ff-9911-4d8d-8750-ac80ac76c606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017944500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2017944500
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1413589939
Short name T568
Test name
Test status
Simulation time 524943906825 ps
CPU time 337.75 seconds
Started Jul 10 04:56:55 PM PDT 24
Finished Jul 10 05:02:34 PM PDT 24
Peak memory 199776 kb
Host smart-5c77af31-9463-4f3d-a3d0-4a918374fcfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413589939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1413589939
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2438702001
Short name T775
Test name
Test status
Simulation time 121924661140 ps
CPU time 663.13 seconds
Started Jul 10 04:56:55 PM PDT 24
Finished Jul 10 05:07:59 PM PDT 24
Peak memory 216516 kb
Host smart-cf7f0b79-43fd-40f2-bf79-2c1f1aa8f4bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438702001 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2438702001
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2666548459
Short name T926
Test name
Test status
Simulation time 862053572 ps
CPU time 1.86 seconds
Started Jul 10 04:56:53 PM PDT 24
Finished Jul 10 04:56:55 PM PDT 24
Peak memory 197644 kb
Host smart-c7750ada-5571-4699-8c90-9c862d23e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666548459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2666548459
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.531673813
Short name T554
Test name
Test status
Simulation time 14896135487 ps
CPU time 32.36 seconds
Started Jul 10 04:56:42 PM PDT 24
Finished Jul 10 04:57:16 PM PDT 24
Peak memory 199840 kb
Host smart-71eddcb3-e791-45db-b625-1c705089feb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531673813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.531673813
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.714135036
Short name T108
Test name
Test status
Simulation time 88256177 ps
CPU time 0.57 seconds
Started Jul 10 04:57:02 PM PDT 24
Finished Jul 10 04:57:04 PM PDT 24
Peak memory 195052 kb
Host smart-b9e008ac-edc1-4aa0-b78e-e6476c73ceec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714135036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.714135036
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.966227493
Short name T976
Test name
Test status
Simulation time 66084572868 ps
CPU time 86.38 seconds
Started Jul 10 04:56:54 PM PDT 24
Finished Jul 10 04:58:21 PM PDT 24
Peak memory 200120 kb
Host smart-d2df0d9f-a9a4-4067-bf3f-8f80bedd9740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966227493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.966227493
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3073207886
Short name T182
Test name
Test status
Simulation time 51107112897 ps
CPU time 38.87 seconds
Started Jul 10 04:56:52 PM PDT 24
Finished Jul 10 04:57:31 PM PDT 24
Peak memory 199812 kb
Host smart-d0a56d22-6ea1-499e-8c6b-9fb243f29e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073207886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3073207886
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1676633933
Short name T548
Test name
Test status
Simulation time 132682103734 ps
CPU time 57.63 seconds
Started Jul 10 04:56:53 PM PDT 24
Finished Jul 10 04:57:52 PM PDT 24
Peak memory 199820 kb
Host smart-89b8fade-966b-45a4-b15f-836c1f61c929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676633933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1676633933
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.750549178
Short name T348
Test name
Test status
Simulation time 45848919830 ps
CPU time 21.34 seconds
Started Jul 10 04:57:01 PM PDT 24
Finished Jul 10 04:57:23 PM PDT 24
Peak memory 199784 kb
Host smart-a5e4b04a-1f73-4f18-b3e7-dd72cb541ea7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750549178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.750549178
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1486647398
Short name T857
Test name
Test status
Simulation time 173567942207 ps
CPU time 1235.39 seconds
Started Jul 10 04:57:02 PM PDT 24
Finished Jul 10 05:17:39 PM PDT 24
Peak memory 199788 kb
Host smart-3f0a9547-c660-4a88-ab5f-87a62fa1b8f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486647398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1486647398
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2837514601
Short name T776
Test name
Test status
Simulation time 1056017081 ps
CPU time 1.28 seconds
Started Jul 10 04:56:59 PM PDT 24
Finished Jul 10 04:57:01 PM PDT 24
Peak memory 198524 kb
Host smart-f5c9323e-d8a1-408d-9680-7a8871eea47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837514601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2837514601
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.82475518
Short name T873
Test name
Test status
Simulation time 114294880322 ps
CPU time 107.34 seconds
Started Jul 10 04:57:05 PM PDT 24
Finished Jul 10 04:58:53 PM PDT 24
Peak memory 199884 kb
Host smart-4659b5d4-e1fc-4f5d-b5b1-08d4256ec5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82475518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.82475518
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3563250151
Short name T446
Test name
Test status
Simulation time 18776065770 ps
CPU time 527.16 seconds
Started Jul 10 04:57:02 PM PDT 24
Finished Jul 10 05:05:50 PM PDT 24
Peak memory 199792 kb
Host smart-5fe16d1f-b64b-4b8c-8ab7-e285560ba1d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563250151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3563250151
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.374563840
Short name T1129
Test name
Test status
Simulation time 4968757507 ps
CPU time 11.23 seconds
Started Jul 10 04:57:00 PM PDT 24
Finished Jul 10 04:57:12 PM PDT 24
Peak memory 198556 kb
Host smart-689a1dd9-073a-4e2e-9d7a-00f334f2868a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374563840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.374563840
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2522847970
Short name T140
Test name
Test status
Simulation time 21426397654 ps
CPU time 6.44 seconds
Started Jul 10 04:57:00 PM PDT 24
Finished Jul 10 04:57:07 PM PDT 24
Peak memory 198340 kb
Host smart-3d6fc191-3e86-4d7c-898a-c275a12431fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522847970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2522847970
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2459452208
Short name T900
Test name
Test status
Simulation time 3980898239 ps
CPU time 6.89 seconds
Started Jul 10 04:57:01 PM PDT 24
Finished Jul 10 04:57:09 PM PDT 24
Peak memory 196076 kb
Host smart-f79d0963-d86b-4624-b885-1af96e2e3f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459452208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2459452208
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3814036802
Short name T337
Test name
Test status
Simulation time 905293204 ps
CPU time 1.9 seconds
Started Jul 10 04:56:53 PM PDT 24
Finished Jul 10 04:56:56 PM PDT 24
Peak memory 198644 kb
Host smart-bbed37ac-b083-4f63-8345-763966d48179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814036802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3814036802
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.584919155
Short name T206
Test name
Test status
Simulation time 139992512330 ps
CPU time 384.32 seconds
Started Jul 10 04:57:06 PM PDT 24
Finished Jul 10 05:03:31 PM PDT 24
Peak memory 216076 kb
Host smart-ea0dd645-0460-4cbb-8768-46fe9d4ad360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584919155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.584919155
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3056866711
Short name T57
Test name
Test status
Simulation time 138514233000 ps
CPU time 799.04 seconds
Started Jul 10 04:57:01 PM PDT 24
Finished Jul 10 05:10:21 PM PDT 24
Peak memory 216484 kb
Host smart-7a9bf485-0815-46aa-a4fe-e4f0548a7f52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056866711 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3056866711
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2791916865
Short name T122
Test name
Test status
Simulation time 394771270 ps
CPU time 0.95 seconds
Started Jul 10 04:57:00 PM PDT 24
Finished Jul 10 04:57:02 PM PDT 24
Peak memory 196480 kb
Host smart-44107b5f-6034-4d10-8780-dfa122cb1065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791916865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2791916865
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3474637979
Short name T513
Test name
Test status
Simulation time 33629827664 ps
CPU time 53.16 seconds
Started Jul 10 04:56:53 PM PDT 24
Finished Jul 10 04:57:47 PM PDT 24
Peak memory 199860 kb
Host smart-5fef561e-38a3-4ab7-8002-6ebfe4054dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474637979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3474637979
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.895404284
Short name T380
Test name
Test status
Simulation time 44845464 ps
CPU time 0.54 seconds
Started Jul 10 04:57:15 PM PDT 24
Finished Jul 10 04:57:17 PM PDT 24
Peak memory 195452 kb
Host smart-7dbf4ee0-d638-4d8c-b44b-b689de3092dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895404284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.895404284
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.871917364
Short name T520
Test name
Test status
Simulation time 46589650031 ps
CPU time 68.88 seconds
Started Jul 10 04:57:00 PM PDT 24
Finished Jul 10 04:58:10 PM PDT 24
Peak memory 199756 kb
Host smart-e89f3717-919a-48d1-b99a-63e0751ec9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871917364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.871917364
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2598497850
Short name T952
Test name
Test status
Simulation time 25423549852 ps
CPU time 29.31 seconds
Started Jul 10 04:57:05 PM PDT 24
Finished Jul 10 04:57:35 PM PDT 24
Peak memory 199852 kb
Host smart-05d3009d-fbe4-4412-8abf-7f21d2081e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598497850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2598497850
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2451155896
Short name T355
Test name
Test status
Simulation time 16034694523 ps
CPU time 30.05 seconds
Started Jul 10 04:57:00 PM PDT 24
Finished Jul 10 04:57:31 PM PDT 24
Peak memory 199792 kb
Host smart-1a2f4da2-1c8c-4e79-8cbb-01f86a7c9f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451155896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2451155896
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1211829530
Short name T901
Test name
Test status
Simulation time 38501630591 ps
CPU time 17.02 seconds
Started Jul 10 04:57:05 PM PDT 24
Finished Jul 10 04:57:23 PM PDT 24
Peak memory 199760 kb
Host smart-4d9d9599-7ef0-47c8-be48-c7b99c0c72e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211829530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1211829530
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1603236478
Short name T934
Test name
Test status
Simulation time 111676116872 ps
CPU time 93.3 seconds
Started Jul 10 04:57:15 PM PDT 24
Finished Jul 10 04:58:50 PM PDT 24
Peak memory 199836 kb
Host smart-56a96a39-0edf-4f9c-a9ee-94b75c13326c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603236478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1603236478
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.443798870
Short name T1092
Test name
Test status
Simulation time 2819179263 ps
CPU time 3.71 seconds
Started Jul 10 04:57:09 PM PDT 24
Finished Jul 10 04:57:14 PM PDT 24
Peak memory 199120 kb
Host smart-63863ad1-b861-48ca-abfa-9527f386879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443798870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.443798870
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2874984210
Short name T1135
Test name
Test status
Simulation time 17765896786 ps
CPU time 13.99 seconds
Started Jul 10 04:57:01 PM PDT 24
Finished Jul 10 04:57:16 PM PDT 24
Peak memory 198912 kb
Host smart-637909e1-cf5a-4537-89e4-0e9270b84ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874984210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2874984210
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3416690037
Short name T500
Test name
Test status
Simulation time 19330626405 ps
CPU time 212.43 seconds
Started Jul 10 04:57:09 PM PDT 24
Finished Jul 10 05:00:42 PM PDT 24
Peak memory 199828 kb
Host smart-a502e4cf-c617-4a9c-afb6-0451f8583f97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3416690037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3416690037
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.744370659
Short name T365
Test name
Test status
Simulation time 2534029485 ps
CPU time 3.14 seconds
Started Jul 10 04:57:02 PM PDT 24
Finished Jul 10 04:57:07 PM PDT 24
Peak memory 197880 kb
Host smart-7ed8d17c-40f1-4541-86a0-2e0954408c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744370659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.744370659
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2335076544
Short name T942
Test name
Test status
Simulation time 27460027819 ps
CPU time 49.53 seconds
Started Jul 10 04:57:01 PM PDT 24
Finished Jul 10 04:57:51 PM PDT 24
Peak memory 199788 kb
Host smart-f6729ae0-b9e7-4256-913b-c3c55852021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335076544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2335076544
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.995493306
Short name T692
Test name
Test status
Simulation time 3051103199 ps
CPU time 5.1 seconds
Started Jul 10 04:57:04 PM PDT 24
Finished Jul 10 04:57:09 PM PDT 24
Peak memory 195692 kb
Host smart-57d01d0a-3d2f-4588-ae23-6e7eb78ad6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995493306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.995493306
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1460319806
Short name T767
Test name
Test status
Simulation time 670443960 ps
CPU time 1.72 seconds
Started Jul 10 04:56:59 PM PDT 24
Finished Jul 10 04:57:02 PM PDT 24
Peak memory 199768 kb
Host smart-82f1d703-9afe-4055-b779-3a3083df15cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460319806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1460319806
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1510241120
Short name T855
Test name
Test status
Simulation time 11219475729 ps
CPU time 128.4 seconds
Started Jul 10 04:57:09 PM PDT 24
Finished Jul 10 04:59:18 PM PDT 24
Peak memory 216580 kb
Host smart-32ca1606-b09f-4be2-ba64-95cd17ab0a8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510241120 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1510241120
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2072529796
Short name T791
Test name
Test status
Simulation time 455498941 ps
CPU time 1.67 seconds
Started Jul 10 04:57:09 PM PDT 24
Finished Jul 10 04:57:11 PM PDT 24
Peak memory 198200 kb
Host smart-b2032b9a-8e92-4584-b4c0-95787d16a5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072529796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2072529796
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3995528755
Short name T680
Test name
Test status
Simulation time 48852829122 ps
CPU time 91.9 seconds
Started Jul 10 04:57:02 PM PDT 24
Finished Jul 10 04:58:35 PM PDT 24
Peak memory 199848 kb
Host smart-cd3d8753-f143-42c3-a916-ee9f91aadf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995528755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3995528755
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2187482221
Short name T599
Test name
Test status
Simulation time 13794989 ps
CPU time 0.57 seconds
Started Jul 10 04:57:16 PM PDT 24
Finished Jul 10 04:57:18 PM PDT 24
Peak memory 195152 kb
Host smart-283c3d8d-3917-48c0-be6c-c951ba04eb14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187482221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2187482221
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.4271675308
Short name T821
Test name
Test status
Simulation time 19941552483 ps
CPU time 17.05 seconds
Started Jul 10 04:57:08 PM PDT 24
Finished Jul 10 04:57:26 PM PDT 24
Peak memory 199880 kb
Host smart-83cd31b0-c7ae-41b8-a33d-0f5ce2157d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271675308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.4271675308
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1962639673
Short name T323
Test name
Test status
Simulation time 57172225969 ps
CPU time 36.43 seconds
Started Jul 10 04:57:06 PM PDT 24
Finished Jul 10 04:57:43 PM PDT 24
Peak memory 199864 kb
Host smart-169cdfeb-6010-4efc-aac7-5c42b81ab1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962639673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1962639673
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1035081318
Short name T607
Test name
Test status
Simulation time 23439576041 ps
CPU time 37.85 seconds
Started Jul 10 04:57:07 PM PDT 24
Finished Jul 10 04:57:46 PM PDT 24
Peak memory 197992 kb
Host smart-58de9cb6-a940-43c7-8b23-ef8033e2cbde
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035081318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1035081318
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1774241818
Short name T271
Test name
Test status
Simulation time 72205893673 ps
CPU time 284.64 seconds
Started Jul 10 04:57:19 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 199836 kb
Host smart-4d634c85-0e98-49ce-b77b-08aab5d95545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774241818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1774241818
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3129204442
Short name T73
Test name
Test status
Simulation time 5314603195 ps
CPU time 3.71 seconds
Started Jul 10 04:57:16 PM PDT 24
Finished Jul 10 04:57:21 PM PDT 24
Peak memory 198948 kb
Host smart-f918ca30-3e07-45ae-a546-dba1b3dc0d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129204442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3129204442
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4232173668
Short name T668
Test name
Test status
Simulation time 30516048381 ps
CPU time 44.16 seconds
Started Jul 10 04:57:07 PM PDT 24
Finished Jul 10 04:57:52 PM PDT 24
Peak memory 198284 kb
Host smart-17d564d3-4e7e-4fc8-a1be-2218566d38e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232173668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4232173668
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.4041724946
Short name T440
Test name
Test status
Simulation time 15059423008 ps
CPU time 723.29 seconds
Started Jul 10 04:57:14 PM PDT 24
Finished Jul 10 05:09:18 PM PDT 24
Peak memory 199768 kb
Host smart-02dffe45-0d3d-4d47-89da-10dcffbb5f76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041724946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4041724946
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3822900792
Short name T715
Test name
Test status
Simulation time 4133873837 ps
CPU time 7.91 seconds
Started Jul 10 04:57:10 PM PDT 24
Finished Jul 10 04:57:19 PM PDT 24
Peak memory 198972 kb
Host smart-d96c67da-a35f-4193-a65d-9ed1ef90b50c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822900792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3822900792
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3731690243
Short name T308
Test name
Test status
Simulation time 157663107259 ps
CPU time 33.83 seconds
Started Jul 10 04:57:18 PM PDT 24
Finished Jul 10 04:57:53 PM PDT 24
Peak memory 199764 kb
Host smart-20dd0454-b6aa-4302-9569-fd98d424fdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731690243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3731690243
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.175457332
Short name T884
Test name
Test status
Simulation time 4406972975 ps
CPU time 2.21 seconds
Started Jul 10 04:57:17 PM PDT 24
Finished Jul 10 04:57:20 PM PDT 24
Peak memory 195912 kb
Host smart-2aa1fa94-44c3-41bb-af30-678a05af875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175457332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.175457332
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1126769663
Short name T463
Test name
Test status
Simulation time 306304599 ps
CPU time 1.63 seconds
Started Jul 10 04:57:09 PM PDT 24
Finished Jul 10 04:57:12 PM PDT 24
Peak memory 199528 kb
Host smart-303f8eed-aba1-4f86-bc7f-0d47751ca843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126769663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1126769663
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2239856919
Short name T53
Test name
Test status
Simulation time 265421822808 ps
CPU time 698.11 seconds
Started Jul 10 04:57:16 PM PDT 24
Finished Jul 10 05:08:56 PM PDT 24
Peak memory 216512 kb
Host smart-3e5cf1ec-5b9b-49ae-b11d-d353c2e2f2ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239856919 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2239856919
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3724641878
Short name T1105
Test name
Test status
Simulation time 1923614017 ps
CPU time 2.13 seconds
Started Jul 10 04:57:17 PM PDT 24
Finished Jul 10 04:57:20 PM PDT 24
Peak memory 198600 kb
Host smart-1dd6e8b2-2310-488f-acfd-c0054757edea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724641878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3724641878
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1146185805
Short name T1057
Test name
Test status
Simulation time 116365579667 ps
CPU time 69.78 seconds
Started Jul 10 04:57:09 PM PDT 24
Finished Jul 10 04:58:19 PM PDT 24
Peak memory 199872 kb
Host smart-a9451c1d-9dff-4120-869f-828020b4c1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146185805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1146185805
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2768959766
Short name T521
Test name
Test status
Simulation time 86493142 ps
CPU time 0.54 seconds
Started Jul 10 04:57:22 PM PDT 24
Finished Jul 10 04:57:24 PM PDT 24
Peak memory 194132 kb
Host smart-29876098-ec6d-4a89-ae4a-0082cd4adf1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768959766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2768959766
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3018834108
Short name T818
Test name
Test status
Simulation time 218825974696 ps
CPU time 167.84 seconds
Started Jul 10 04:57:17 PM PDT 24
Finished Jul 10 05:00:06 PM PDT 24
Peak memory 199900 kb
Host smart-f23d7db4-60cf-4bff-866a-72d0d53aed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018834108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3018834108
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2738231607
Short name T153
Test name
Test status
Simulation time 115698089924 ps
CPU time 96.31 seconds
Started Jul 10 04:57:16 PM PDT 24
Finished Jul 10 04:58:53 PM PDT 24
Peak memory 199752 kb
Host smart-2584a4ba-39a5-4092-926b-f658cebfd483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738231607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2738231607
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.4030526277
Short name T235
Test name
Test status
Simulation time 26294426563 ps
CPU time 47.39 seconds
Started Jul 10 04:57:23 PM PDT 24
Finished Jul 10 04:58:12 PM PDT 24
Peak memory 199764 kb
Host smart-64b61aae-b1f0-47d1-8d43-915ad24c2ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030526277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.4030526277
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.665083866
Short name T866
Test name
Test status
Simulation time 50853509340 ps
CPU time 81.81 seconds
Started Jul 10 04:57:25 PM PDT 24
Finished Jul 10 04:58:47 PM PDT 24
Peak memory 199756 kb
Host smart-c2c3be7b-b027-428c-a05d-ff305253c8b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665083866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.665083866
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.639935186
Short name T856
Test name
Test status
Simulation time 88286001207 ps
CPU time 621.1 seconds
Started Jul 10 04:57:23 PM PDT 24
Finished Jul 10 05:07:46 PM PDT 24
Peak memory 199772 kb
Host smart-aa484223-a204-4efb-ad2d-41435f13ee9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639935186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.639935186
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.700605850
Short name T23
Test name
Test status
Simulation time 3562250188 ps
CPU time 6.51 seconds
Started Jul 10 04:57:22 PM PDT 24
Finished Jul 10 04:57:29 PM PDT 24
Peak memory 198508 kb
Host smart-e123f65d-fe1d-4765-abad-16a840f849fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700605850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.700605850
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.670752711
Short name T360
Test name
Test status
Simulation time 29373613800 ps
CPU time 12.19 seconds
Started Jul 10 04:57:26 PM PDT 24
Finished Jul 10 04:57:39 PM PDT 24
Peak memory 195964 kb
Host smart-6f5e286a-c422-40a3-bc6c-db77ef4db8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670752711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.670752711
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2371578672
Short name T1098
Test name
Test status
Simulation time 11729389892 ps
CPU time 584.37 seconds
Started Jul 10 04:57:22 PM PDT 24
Finished Jul 10 05:07:08 PM PDT 24
Peak memory 199784 kb
Host smart-2368a7f5-18f1-4ff8-a488-1e88d1dec101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371578672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2371578672
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1801134327
Short name T904
Test name
Test status
Simulation time 7911388001 ps
CPU time 67.12 seconds
Started Jul 10 04:57:22 PM PDT 24
Finished Jul 10 04:58:31 PM PDT 24
Peak memory 199012 kb
Host smart-1a8bafe5-c89c-44c7-85ab-ccbb50efeafb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801134327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1801134327
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2654421979
Short name T802
Test name
Test status
Simulation time 3340158391 ps
CPU time 6.06 seconds
Started Jul 10 04:57:23 PM PDT 24
Finished Jul 10 04:57:31 PM PDT 24
Peak memory 196328 kb
Host smart-b8e47e8b-222b-4b65-adfd-038abeada4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654421979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2654421979
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1111457434
Short name T1179
Test name
Test status
Simulation time 5626870892 ps
CPU time 13.53 seconds
Started Jul 10 04:57:14 PM PDT 24
Finished Jul 10 04:57:28 PM PDT 24
Peak memory 198988 kb
Host smart-e4bcb564-c692-457a-b110-75669be3706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111457434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1111457434
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2654279299
Short name T189
Test name
Test status
Simulation time 476755448618 ps
CPU time 254.34 seconds
Started Jul 10 04:57:26 PM PDT 24
Finished Jul 10 05:01:41 PM PDT 24
Peak memory 199800 kb
Host smart-daca06f5-629e-407d-a11d-51046fcf28e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654279299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2654279299
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2268496610
Short name T131
Test name
Test status
Simulation time 160933748236 ps
CPU time 416.99 seconds
Started Jul 10 04:57:22 PM PDT 24
Finished Jul 10 05:04:21 PM PDT 24
Peak memory 216316 kb
Host smart-5e17e108-cd3d-4a80-bcfa-1e03c9eeaafc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268496610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2268496610
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2303756021
Short name T523
Test name
Test status
Simulation time 7145594895 ps
CPU time 24.99 seconds
Started Jul 10 04:57:23 PM PDT 24
Finished Jul 10 04:57:50 PM PDT 24
Peak memory 199768 kb
Host smart-1299e274-f014-4707-964d-5d0bac58aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303756021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2303756021
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1990027128
Short name T462
Test name
Test status
Simulation time 10321664395 ps
CPU time 17.92 seconds
Started Jul 10 04:57:18 PM PDT 24
Finished Jul 10 04:57:37 PM PDT 24
Peak memory 199776 kb
Host smart-fa915bbf-e1fc-46ae-8c6a-97239f845ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990027128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1990027128
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2704018954
Short name T506
Test name
Test status
Simulation time 15030439 ps
CPU time 0.57 seconds
Started Jul 10 04:57:35 PM PDT 24
Finished Jul 10 04:57:37 PM PDT 24
Peak memory 194132 kb
Host smart-3d3b89d9-1719-4275-97da-e5a307a46fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704018954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2704018954
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3488842639
Short name T526
Test name
Test status
Simulation time 26829054781 ps
CPU time 40.07 seconds
Started Jul 10 04:57:30 PM PDT 24
Finished Jul 10 04:58:10 PM PDT 24
Peak memory 199760 kb
Host smart-9ab12747-3b78-44d2-85ff-3caddef7d43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488842639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3488842639
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3269554907
Short name T1173
Test name
Test status
Simulation time 130116287471 ps
CPU time 21.26 seconds
Started Jul 10 04:57:30 PM PDT 24
Finished Jul 10 04:57:52 PM PDT 24
Peak memory 199748 kb
Host smart-cfc48428-9558-451d-9e4f-2193471870bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269554907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3269554907
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.461976943
Short name T961
Test name
Test status
Simulation time 14983026079 ps
CPU time 25.11 seconds
Started Jul 10 04:57:32 PM PDT 24
Finished Jul 10 04:57:58 PM PDT 24
Peak memory 199732 kb
Host smart-d87bf8dd-e81c-4765-9a88-4c4558378b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461976943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.461976943
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1854303984
Short name T787
Test name
Test status
Simulation time 6894906482 ps
CPU time 2.31 seconds
Started Jul 10 04:57:29 PM PDT 24
Finished Jul 10 04:57:32 PM PDT 24
Peak memory 196264 kb
Host smart-4393b3d7-30ec-4b55-b8b7-663910416ba7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854303984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1854303984
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.4091673656
Short name T378
Test name
Test status
Simulation time 110518410813 ps
CPU time 414.03 seconds
Started Jul 10 04:57:33 PM PDT 24
Finished Jul 10 05:04:27 PM PDT 24
Peak memory 199704 kb
Host smart-1a8e6976-2658-43c1-83d8-7b5c399685ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091673656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4091673656
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1063271416
Short name T1149
Test name
Test status
Simulation time 3926161083 ps
CPU time 2.26 seconds
Started Jul 10 04:57:30 PM PDT 24
Finished Jul 10 04:57:34 PM PDT 24
Peak memory 197220 kb
Host smart-94616a5b-ea5d-4013-9774-6835af8982d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063271416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1063271416
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1030683082
Short name T324
Test name
Test status
Simulation time 102436489856 ps
CPU time 27.65 seconds
Started Jul 10 04:57:30 PM PDT 24
Finished Jul 10 04:57:58 PM PDT 24
Peak memory 200048 kb
Host smart-80f3949d-ec8f-4738-bffc-3e9f1391653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030683082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1030683082
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.914018728
Short name T757
Test name
Test status
Simulation time 14770004306 ps
CPU time 649.49 seconds
Started Jul 10 04:57:31 PM PDT 24
Finished Jul 10 05:08:21 PM PDT 24
Peak memory 199760 kb
Host smart-96a52814-147a-4ae1-8e8e-291a172c8c32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914018728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.914018728
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3706514611
Short name T723
Test name
Test status
Simulation time 5454115132 ps
CPU time 13.64 seconds
Started Jul 10 04:57:28 PM PDT 24
Finished Jul 10 04:57:43 PM PDT 24
Peak memory 199232 kb
Host smart-499dc413-70ec-4222-863d-9af4e7df6421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706514611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3706514611
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1828250903
Short name T117
Test name
Test status
Simulation time 252035007423 ps
CPU time 107.2 seconds
Started Jul 10 04:57:29 PM PDT 24
Finished Jul 10 04:59:17 PM PDT 24
Peak memory 199840 kb
Host smart-260c3f34-2adb-4e63-81dc-33455c905f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828250903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1828250903
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.20525103
Short name T753
Test name
Test status
Simulation time 41342743930 ps
CPU time 31.04 seconds
Started Jul 10 04:57:29 PM PDT 24
Finished Jul 10 04:58:01 PM PDT 24
Peak memory 195660 kb
Host smart-24397bcb-ffd5-489c-863e-f7c2848ac35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20525103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.20525103
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3082837357
Short name T930
Test name
Test status
Simulation time 11050304267 ps
CPU time 39.61 seconds
Started Jul 10 04:57:23 PM PDT 24
Finished Jul 10 04:58:04 PM PDT 24
Peak memory 199764 kb
Host smart-8750b8e4-d8db-4b0c-8762-46e2cf0b619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082837357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3082837357
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1045053805
Short name T232
Test name
Test status
Simulation time 302796626959 ps
CPU time 532.33 seconds
Started Jul 10 04:57:37 PM PDT 24
Finished Jul 10 05:06:30 PM PDT 24
Peak memory 199880 kb
Host smart-4f4bfc03-d29d-49ed-aace-821c13a49839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045053805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1045053805
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2601977653
Short name T763
Test name
Test status
Simulation time 202207132700 ps
CPU time 1328.84 seconds
Started Jul 10 04:57:37 PM PDT 24
Finished Jul 10 05:19:47 PM PDT 24
Peak memory 225304 kb
Host smart-d739b04c-7960-4671-b998-e3d628b1305f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601977653 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2601977653
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2761309530
Short name T516
Test name
Test status
Simulation time 7398037260 ps
CPU time 12.64 seconds
Started Jul 10 04:57:29 PM PDT 24
Finished Jul 10 04:57:43 PM PDT 24
Peak memory 199240 kb
Host smart-ad84895f-a0b5-4330-a8ad-e46532671907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761309530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2761309530
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3772578204
Short name T452
Test name
Test status
Simulation time 755241115 ps
CPU time 1.19 seconds
Started Jul 10 04:57:22 PM PDT 24
Finished Jul 10 04:57:25 PM PDT 24
Peak memory 196196 kb
Host smart-5749d425-5bf8-48ba-95f8-2efb2d8a1273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772578204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3772578204
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.337208563
Short name T732
Test name
Test status
Simulation time 31966746 ps
CPU time 0.55 seconds
Started Jul 10 04:57:44 PM PDT 24
Finished Jul 10 04:57:45 PM PDT 24
Peak memory 194708 kb
Host smart-7483f7cb-08aa-4d2c-befe-5e1b1f776b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337208563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.337208563
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3290720145
Short name T1065
Test name
Test status
Simulation time 29601116819 ps
CPU time 37.84 seconds
Started Jul 10 04:57:38 PM PDT 24
Finished Jul 10 04:58:17 PM PDT 24
Peak memory 199776 kb
Host smart-fcbb8e30-d41d-4137-8bd5-ddff31a258b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290720145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3290720145
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3777053905
Short name T292
Test name
Test status
Simulation time 59501919994 ps
CPU time 92.72 seconds
Started Jul 10 04:57:36 PM PDT 24
Finished Jul 10 04:59:10 PM PDT 24
Peak memory 199676 kb
Host smart-b19a2beb-047f-41cd-8558-95c07795ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777053905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3777053905
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.873570900
Short name T817
Test name
Test status
Simulation time 154433200641 ps
CPU time 88.81 seconds
Started Jul 10 04:57:36 PM PDT 24
Finished Jul 10 04:59:06 PM PDT 24
Peak memory 199836 kb
Host smart-ffbbfe5e-2045-4dee-8062-9c97efa4a788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873570900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.873570900
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1362746700
Short name T946
Test name
Test status
Simulation time 13187273913 ps
CPU time 4.98 seconds
Started Jul 10 04:57:36 PM PDT 24
Finished Jul 10 04:57:42 PM PDT 24
Peak memory 197780 kb
Host smart-abfc9191-687b-450b-ac00-f001b3856569
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362746700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1362746700
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3602783298
Short name T553
Test name
Test status
Simulation time 77902145377 ps
CPU time 772.4 seconds
Started Jul 10 04:57:43 PM PDT 24
Finished Jul 10 05:10:37 PM PDT 24
Peak memory 199788 kb
Host smart-38225190-a780-437e-a61a-56a11117b920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602783298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3602783298
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2050825769
Short name T706
Test name
Test status
Simulation time 2914647655 ps
CPU time 2.98 seconds
Started Jul 10 04:57:35 PM PDT 24
Finished Jul 10 04:57:39 PM PDT 24
Peak memory 199140 kb
Host smart-5d0693c9-af48-4981-b46e-15644caba53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050825769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2050825769
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1908823293
Short name T313
Test name
Test status
Simulation time 46258433214 ps
CPU time 75.12 seconds
Started Jul 10 04:57:36 PM PDT 24
Finished Jul 10 04:58:52 PM PDT 24
Peak memory 200004 kb
Host smart-c5733f4f-094c-4b92-9352-20ddb51f7db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908823293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1908823293
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3693814651
Short name T701
Test name
Test status
Simulation time 11481952755 ps
CPU time 158.67 seconds
Started Jul 10 04:57:45 PM PDT 24
Finished Jul 10 05:00:24 PM PDT 24
Peak memory 199760 kb
Host smart-f875b2f3-36f1-4b69-a009-98aae84d78af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693814651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3693814651
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1823381293
Short name T1121
Test name
Test status
Simulation time 5041179526 ps
CPU time 23.75 seconds
Started Jul 10 04:57:36 PM PDT 24
Finished Jul 10 04:58:00 PM PDT 24
Peak memory 198668 kb
Host smart-0611ec26-54d1-48e1-bc7a-9bf4ef34381e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823381293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1823381293
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3262890980
Short name T623
Test name
Test status
Simulation time 48835982900 ps
CPU time 77.9 seconds
Started Jul 10 04:57:37 PM PDT 24
Finished Jul 10 04:58:56 PM PDT 24
Peak memory 199804 kb
Host smart-e5b0b197-3686-499e-81c8-36da004f8e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262890980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3262890980
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1882821086
Short name T415
Test name
Test status
Simulation time 566907929 ps
CPU time 1.36 seconds
Started Jul 10 04:57:37 PM PDT 24
Finished Jul 10 04:57:39 PM PDT 24
Peak memory 195420 kb
Host smart-9365f1e9-47a5-4af9-b7bb-7d50d7b0449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882821086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1882821086
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.825877028
Short name T395
Test name
Test status
Simulation time 853034385 ps
CPU time 2.41 seconds
Started Jul 10 04:57:37 PM PDT 24
Finished Jul 10 04:57:40 PM PDT 24
Peak memory 198668 kb
Host smart-3d9c7736-a6d0-4837-96f7-e73b4c34084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825877028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.825877028
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3629851217
Short name T125
Test name
Test status
Simulation time 80459493178 ps
CPU time 147.97 seconds
Started Jul 10 04:57:43 PM PDT 24
Finished Jul 10 05:00:11 PM PDT 24
Peak memory 199792 kb
Host smart-790e1068-cc5b-44d9-a256-2c736b8fbb93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629851217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3629851217
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2349359869
Short name T120
Test name
Test status
Simulation time 802198588 ps
CPU time 3.28 seconds
Started Jul 10 04:57:38 PM PDT 24
Finished Jul 10 04:57:43 PM PDT 24
Peak memory 199728 kb
Host smart-63daba56-f35e-4e2b-b991-833eadf8d3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349359869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2349359869
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.337423982
Short name T697
Test name
Test status
Simulation time 12434690451 ps
CPU time 13.84 seconds
Started Jul 10 04:57:37 PM PDT 24
Finished Jul 10 04:57:52 PM PDT 24
Peak memory 199828 kb
Host smart-17f1df1c-029c-4819-8630-e1a6d38ec669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337423982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.337423982
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1294165247
Short name T621
Test name
Test status
Simulation time 12846205 ps
CPU time 0.56 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:52:20 PM PDT 24
Peak memory 194128 kb
Host smart-8e46f7fe-5385-4941-adb0-6f502c881622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294165247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1294165247
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1457717676
Short name T1144
Test name
Test status
Simulation time 37054580894 ps
CPU time 62.83 seconds
Started Jul 10 04:52:20 PM PDT 24
Finished Jul 10 04:53:25 PM PDT 24
Peak memory 199780 kb
Host smart-b6b2fe56-905d-46d0-9443-5c57520b29f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457717676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1457717676
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.287011401
Short name T594
Test name
Test status
Simulation time 63466509717 ps
CPU time 61.26 seconds
Started Jul 10 04:52:17 PM PDT 24
Finished Jul 10 04:53:19 PM PDT 24
Peak memory 199776 kb
Host smart-75c7102f-0342-412f-ad83-dd0ba0eadada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287011401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.287011401
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.217054306
Short name T453
Test name
Test status
Simulation time 13125581406 ps
CPU time 5.29 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:52:25 PM PDT 24
Peak memory 195984 kb
Host smart-18b136b4-2510-4791-9363-b772cf685bea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217054306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.217054306
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.601184578
Short name T1067
Test name
Test status
Simulation time 132944576674 ps
CPU time 628.1 seconds
Started Jul 10 04:52:18 PM PDT 24
Finished Jul 10 05:02:47 PM PDT 24
Peak memory 199816 kb
Host smart-fe04ee4e-65fd-4818-b6da-ac9a40103148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601184578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.601184578
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1755786935
Short name T909
Test name
Test status
Simulation time 8160889893 ps
CPU time 17.07 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:52:37 PM PDT 24
Peak memory 199280 kb
Host smart-92827c89-0d02-42d2-8e4a-526a48baf08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755786935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1755786935
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1271210097
Short name T283
Test name
Test status
Simulation time 143389828266 ps
CPU time 60.76 seconds
Started Jul 10 04:52:18 PM PDT 24
Finished Jul 10 04:53:19 PM PDT 24
Peak memory 199048 kb
Host smart-d21ab5ae-e74c-4f45-a159-4cf6d04b83c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271210097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1271210097
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2289224399
Short name T409
Test name
Test status
Simulation time 14623510133 ps
CPU time 426.36 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:59:27 PM PDT 24
Peak memory 199828 kb
Host smart-c6868dfd-077e-4502-82dc-26300a94bda5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2289224399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2289224399
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1694285825
Short name T389
Test name
Test status
Simulation time 4522781172 ps
CPU time 38.27 seconds
Started Jul 10 04:52:18 PM PDT 24
Finished Jul 10 04:52:57 PM PDT 24
Peak memory 199792 kb
Host smart-9e1a55ea-2373-434f-ace3-2016b247aec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694285825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1694285825
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2717513653
Short name T281
Test name
Test status
Simulation time 103140261993 ps
CPU time 156.86 seconds
Started Jul 10 04:52:20 PM PDT 24
Finished Jul 10 04:54:58 PM PDT 24
Peak memory 199860 kb
Host smart-5dd6d32a-acc1-4406-a983-37ae5ae21925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717513653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2717513653
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1829483643
Short name T1071
Test name
Test status
Simulation time 34862353737 ps
CPU time 47.66 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:53:07 PM PDT 24
Peak memory 195840 kb
Host smart-78f1dffa-cfb1-4889-9f68-90fd2cc3788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829483643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1829483643
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3660477846
Short name T1013
Test name
Test status
Simulation time 570582310 ps
CPU time 1.6 seconds
Started Jul 10 04:51:58 PM PDT 24
Finished Jul 10 04:52:01 PM PDT 24
Peak memory 199748 kb
Host smart-d180ff9a-13d4-4dd1-8d5d-06d7959edada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660477846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3660477846
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1095151876
Short name T1035
Test name
Test status
Simulation time 470527212888 ps
CPU time 247.51 seconds
Started Jul 10 04:52:20 PM PDT 24
Finished Jul 10 04:56:29 PM PDT 24
Peak memory 200076 kb
Host smart-a616b44a-b36f-4129-81b3-04e61f1874fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095151876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1095151876
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2281895408
Short name T116
Test name
Test status
Simulation time 171955381342 ps
CPU time 843.01 seconds
Started Jul 10 04:52:20 PM PDT 24
Finished Jul 10 05:06:25 PM PDT 24
Peak memory 224652 kb
Host smart-35e34e6f-29ed-4981-bbb4-39111339bc93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281895408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2281895408
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.4273542209
Short name T1045
Test name
Test status
Simulation time 15609501032 ps
CPU time 5.04 seconds
Started Jul 10 04:52:17 PM PDT 24
Finished Jul 10 04:52:22 PM PDT 24
Peak memory 199864 kb
Host smart-dc6496db-5c7b-446c-8e98-8ff06812ce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273542209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.4273542209
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3961838805
Short name T617
Test name
Test status
Simulation time 1365143330 ps
CPU time 0.94 seconds
Started Jul 10 04:52:21 PM PDT 24
Finished Jul 10 04:52:23 PM PDT 24
Peak memory 196216 kb
Host smart-4cedd059-12aa-4ca4-8688-1c7b3bfcac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961838805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3961838805
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1612689707
Short name T1021
Test name
Test status
Simulation time 18914472419 ps
CPU time 19.06 seconds
Started Jul 10 04:57:42 PM PDT 24
Finished Jul 10 04:58:02 PM PDT 24
Peak memory 199840 kb
Host smart-13256909-17af-4faa-af31-9e4e2a666559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612689707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1612689707
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4056323555
Short name T151
Test name
Test status
Simulation time 154901367785 ps
CPU time 973.93 seconds
Started Jul 10 04:57:43 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 215696 kb
Host smart-25577468-c93a-42cd-9032-95efc4d4f773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056323555 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4056323555
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.411637737
Short name T1153
Test name
Test status
Simulation time 92399805747 ps
CPU time 159.55 seconds
Started Jul 10 04:57:45 PM PDT 24
Finished Jul 10 05:00:25 PM PDT 24
Peak memory 199828 kb
Host smart-fbebc5a0-f87c-422e-8f7d-7426a473a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411637737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.411637737
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3322949422
Short name T982
Test name
Test status
Simulation time 177912767427 ps
CPU time 518.59 seconds
Started Jul 10 04:57:43 PM PDT 24
Finished Jul 10 05:06:23 PM PDT 24
Peak memory 224684 kb
Host smart-a957d9b7-5dd5-4026-b55a-777a20746e01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322949422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3322949422
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3515313577
Short name T762
Test name
Test status
Simulation time 248772487142 ps
CPU time 140.84 seconds
Started Jul 10 04:57:43 PM PDT 24
Finished Jul 10 05:00:05 PM PDT 24
Peak memory 199860 kb
Host smart-3879657f-0070-4570-a069-b37d858b37bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515313577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3515313577
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2794826467
Short name T844
Test name
Test status
Simulation time 63053041668 ps
CPU time 347.5 seconds
Started Jul 10 04:57:43 PM PDT 24
Finished Jul 10 05:03:31 PM PDT 24
Peak memory 208088 kb
Host smart-983b86fb-4699-4601-af45-d1fbef6f42dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794826467 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2794826467
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2323793332
Short name T435
Test name
Test status
Simulation time 38964632618 ps
CPU time 60.08 seconds
Started Jul 10 04:57:42 PM PDT 24
Finished Jul 10 04:58:43 PM PDT 24
Peak memory 199744 kb
Host smart-84f7140d-d4f8-4cef-a0f7-3a14d2c05839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323793332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2323793332
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2334211264
Short name T1030
Test name
Test status
Simulation time 70564691146 ps
CPU time 908.77 seconds
Started Jul 10 04:57:42 PM PDT 24
Finished Jul 10 05:12:51 PM PDT 24
Peak memory 224712 kb
Host smart-b320d0c7-fed8-47b1-8f0a-5096b6a3f5ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334211264 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2334211264
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.572007321
Short name T652
Test name
Test status
Simulation time 81861414111 ps
CPU time 29.65 seconds
Started Jul 10 04:57:49 PM PDT 24
Finished Jul 10 04:58:20 PM PDT 24
Peak memory 199776 kb
Host smart-00ee3861-4844-4436-b905-925a38ab72c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572007321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.572007321
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3870155094
Short name T1119
Test name
Test status
Simulation time 56415276513 ps
CPU time 135.14 seconds
Started Jul 10 04:57:49 PM PDT 24
Finished Jul 10 05:00:06 PM PDT 24
Peak memory 199796 kb
Host smart-4eef2859-f833-41ec-b9c3-583ec8f32d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870155094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3870155094
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3829455784
Short name T993
Test name
Test status
Simulation time 263021960240 ps
CPU time 356.65 seconds
Started Jul 10 04:57:52 PM PDT 24
Finished Jul 10 05:03:50 PM PDT 24
Peak memory 216264 kb
Host smart-1d9be0e4-ceee-43ec-ad27-3bf1a3d4eb56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829455784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3829455784
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.883349549
Short name T136
Test name
Test status
Simulation time 84195236887 ps
CPU time 123.88 seconds
Started Jul 10 04:57:51 PM PDT 24
Finished Jul 10 04:59:56 PM PDT 24
Peak memory 199852 kb
Host smart-37737e52-8037-43c4-8d46-a2dd250601fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883349549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.883349549
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2316572241
Short name T685
Test name
Test status
Simulation time 36968384158 ps
CPU time 439.82 seconds
Started Jul 10 04:57:51 PM PDT 24
Finished Jul 10 05:05:12 PM PDT 24
Peak memory 216568 kb
Host smart-f4080a22-6d34-4b7d-a3fd-457a0b9ff332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316572241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2316572241
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2276444287
Short name T1007
Test name
Test status
Simulation time 70202152236 ps
CPU time 1360.56 seconds
Started Jul 10 04:57:49 PM PDT 24
Finished Jul 10 05:20:30 PM PDT 24
Peak memory 224768 kb
Host smart-ba2da7df-3374-448b-8480-d18d0ed58948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276444287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2276444287
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3813126328
Short name T457
Test name
Test status
Simulation time 43700159745 ps
CPU time 20.86 seconds
Started Jul 10 04:57:51 PM PDT 24
Finished Jul 10 04:58:13 PM PDT 24
Peak memory 199836 kb
Host smart-54e94e60-42f4-4033-abfb-d3442b06bf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813126328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3813126328
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.758670712
Short name T809
Test name
Test status
Simulation time 59369021083 ps
CPU time 315.18 seconds
Started Jul 10 04:57:50 PM PDT 24
Finished Jul 10 05:03:06 PM PDT 24
Peak memory 216344 kb
Host smart-d4ffb850-436d-4b08-828a-140caa88dea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758670712 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.758670712
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3377855682
Short name T340
Test name
Test status
Simulation time 23922457256 ps
CPU time 31.22 seconds
Started Jul 10 04:57:49 PM PDT 24
Finished Jul 10 04:58:21 PM PDT 24
Peak memory 199780 kb
Host smart-7c47dddc-9ede-439e-850d-1701440c01bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377855682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3377855682
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3933360399
Short name T300
Test name
Test status
Simulation time 88918826243 ps
CPU time 1013.63 seconds
Started Jul 10 04:57:48 PM PDT 24
Finished Jul 10 05:14:42 PM PDT 24
Peak memory 232872 kb
Host smart-d9057526-f507-49f3-9b4b-29e699363c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933360399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3933360399
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.434158897
Short name T27
Test name
Test status
Simulation time 14666491 ps
CPU time 0.58 seconds
Started Jul 10 04:52:25 PM PDT 24
Finished Jul 10 04:52:27 PM PDT 24
Peak memory 195380 kb
Host smart-d5e650e1-7fc9-451e-99d1-a3f3e0cccf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434158897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.434158897
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.26282670
Short name T853
Test name
Test status
Simulation time 58989039279 ps
CPU time 26.43 seconds
Started Jul 10 04:52:18 PM PDT 24
Finished Jul 10 04:52:45 PM PDT 24
Peak memory 199784 kb
Host smart-cc6a2c5a-3165-4b07-b168-47cca9af4a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26282670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.26282670
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2357890366
Short name T270
Test name
Test status
Simulation time 6485102743 ps
CPU time 9.38 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:52:29 PM PDT 24
Peak memory 198976 kb
Host smart-65160c94-9178-4e28-8a63-7a91c4f24a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357890366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2357890366
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.324107223
Short name T910
Test name
Test status
Simulation time 191773633471 ps
CPU time 17.6 seconds
Started Jul 10 04:52:22 PM PDT 24
Finished Jul 10 04:52:40 PM PDT 24
Peak memory 199444 kb
Host smart-bafcbcee-935f-47c3-a509-34e71f33426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324107223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.324107223
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2373882256
Short name T556
Test name
Test status
Simulation time 50740135089 ps
CPU time 81.08 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:53:42 PM PDT 24
Peak memory 199732 kb
Host smart-d9612611-6391-4ff8-bb21-f20b5520f5fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373882256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2373882256
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.644188937
Short name T485
Test name
Test status
Simulation time 58136879761 ps
CPU time 109.78 seconds
Started Jul 10 04:52:25 PM PDT 24
Finished Jul 10 04:54:16 PM PDT 24
Peak memory 199824 kb
Host smart-44f50ae5-b8d6-4e72-9f96-870ba3fb93a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=644188937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.644188937
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1101356299
Short name T670
Test name
Test status
Simulation time 5801466711 ps
CPU time 5.12 seconds
Started Jul 10 04:52:25 PM PDT 24
Finished Jul 10 04:52:31 PM PDT 24
Peak memory 198440 kb
Host smart-e935f1d0-7460-4890-9ab7-781623f2c569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101356299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1101356299
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1030955831
Short name T1012
Test name
Test status
Simulation time 143699745826 ps
CPU time 113.31 seconds
Started Jul 10 04:52:21 PM PDT 24
Finished Jul 10 04:54:15 PM PDT 24
Peak memory 199912 kb
Host smart-1ef96fdf-4eed-405c-b4b2-9b9b1bba58cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030955831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1030955831
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.172997485
Short name T790
Test name
Test status
Simulation time 20945725595 ps
CPU time 1041.91 seconds
Started Jul 10 04:52:25 PM PDT 24
Finished Jul 10 05:09:47 PM PDT 24
Peak memory 199768 kb
Host smart-de8ca59d-68d3-4084-84ac-dc95d34c628d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172997485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.172997485
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1096823356
Short name T1108
Test name
Test status
Simulation time 1469603904 ps
CPU time 5.2 seconds
Started Jul 10 04:52:21 PM PDT 24
Finished Jul 10 04:52:27 PM PDT 24
Peak memory 198316 kb
Host smart-4d2375af-69b4-4d65-8486-3f3c1c75aaf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096823356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1096823356
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3284989416
Short name T744
Test name
Test status
Simulation time 73575668626 ps
CPU time 182.06 seconds
Started Jul 10 04:52:20 PM PDT 24
Finished Jul 10 04:55:23 PM PDT 24
Peak memory 199796 kb
Host smart-6024e6cd-9dfb-431f-a3d5-82ab542178e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284989416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3284989416
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1073957749
Short name T1080
Test name
Test status
Simulation time 5599616327 ps
CPU time 1.83 seconds
Started Jul 10 04:52:21 PM PDT 24
Finished Jul 10 04:52:24 PM PDT 24
Peak memory 195952 kb
Host smart-c694703a-6550-42a6-8b69-5940ef650dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073957749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1073957749
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2404109010
Short name T442
Test name
Test status
Simulation time 303641023 ps
CPU time 1.32 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:52:22 PM PDT 24
Peak memory 198552 kb
Host smart-6691fe09-c5db-48cd-be81-ee76462fae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404109010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2404109010
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.916324049
Short name T512
Test name
Test status
Simulation time 147781002088 ps
CPU time 209.5 seconds
Started Jul 10 04:52:27 PM PDT 24
Finished Jul 10 04:55:58 PM PDT 24
Peak memory 199816 kb
Host smart-3757afca-70ec-4253-b4a5-18a0f58ceab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916324049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.916324049
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3103375247
Short name T662
Test name
Test status
Simulation time 336193339473 ps
CPU time 1106.34 seconds
Started Jul 10 04:52:25 PM PDT 24
Finished Jul 10 05:10:52 PM PDT 24
Peak memory 224712 kb
Host smart-aefaf187-1a97-4491-9c53-dfe928a2e153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103375247 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3103375247
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.971317277
Short name T47
Test name
Test status
Simulation time 6695335068 ps
CPU time 30.46 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:52:50 PM PDT 24
Peak memory 199844 kb
Host smart-0f7c8c40-1d9f-4006-871c-ef525d41eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971317277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.971317277
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.989389561
Short name T691
Test name
Test status
Simulation time 373245852705 ps
CPU time 46.93 seconds
Started Jul 10 04:52:19 PM PDT 24
Finished Jul 10 04:53:08 PM PDT 24
Peak memory 199828 kb
Host smart-02d030d6-4c51-4795-bace-898e0a540c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989389561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.989389561
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2293358560
Short name T6
Test name
Test status
Simulation time 52945467483 ps
CPU time 26.88 seconds
Started Jul 10 04:57:50 PM PDT 24
Finished Jul 10 04:58:18 PM PDT 24
Peak memory 199776 kb
Host smart-804b0452-8a3d-4c6f-a8d0-bfee7441b5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293358560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2293358560
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.995452860
Short name T602
Test name
Test status
Simulation time 483208454114 ps
CPU time 1526.95 seconds
Started Jul 10 04:57:52 PM PDT 24
Finished Jul 10 05:23:20 PM PDT 24
Peak memory 232556 kb
Host smart-9dadb18c-0e85-4ac7-81ff-db31fa3b7d2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995452860 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.995452860
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2286659699
Short name T207
Test name
Test status
Simulation time 26423566069 ps
CPU time 21.01 seconds
Started Jul 10 04:57:50 PM PDT 24
Finished Jul 10 04:58:12 PM PDT 24
Peak memory 199852 kb
Host smart-6a37894e-3b57-4360-b0e4-14289e35709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286659699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2286659699
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3392417097
Short name T251
Test name
Test status
Simulation time 59367305319 ps
CPU time 1366.37 seconds
Started Jul 10 04:57:58 PM PDT 24
Finished Jul 10 05:20:45 PM PDT 24
Peak memory 224752 kb
Host smart-cd7fae55-292b-48f5-b437-37d2b9f42ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392417097 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3392417097
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3986134048
Short name T647
Test name
Test status
Simulation time 74135859219 ps
CPU time 55.38 seconds
Started Jul 10 04:57:56 PM PDT 24
Finished Jul 10 04:58:52 PM PDT 24
Peak memory 199776 kb
Host smart-ba13310e-5932-45d3-aa2a-d355f7002de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986134048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3986134048
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3317784135
Short name T1078
Test name
Test status
Simulation time 197736653446 ps
CPU time 330.04 seconds
Started Jul 10 04:57:59 PM PDT 24
Finished Jul 10 05:03:30 PM PDT 24
Peak memory 216524 kb
Host smart-ed217467-389a-40c0-896d-ca75eb33345a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317784135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3317784135
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.576770757
Short name T695
Test name
Test status
Simulation time 23476530344 ps
CPU time 15.42 seconds
Started Jul 10 04:58:00 PM PDT 24
Finished Jul 10 04:58:16 PM PDT 24
Peak memory 199832 kb
Host smart-06613b38-8fdf-43a2-b83c-f052d39b88d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576770757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.576770757
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3150394356
Short name T56
Test name
Test status
Simulation time 63665245605 ps
CPU time 366.65 seconds
Started Jul 10 04:57:57 PM PDT 24
Finished Jul 10 05:04:05 PM PDT 24
Peak memory 216528 kb
Host smart-948ff2a3-eb6e-4b88-83ed-d5484fba9fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150394356 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3150394356
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4104490591
Short name T243
Test name
Test status
Simulation time 43911447877 ps
CPU time 20.82 seconds
Started Jul 10 04:58:00 PM PDT 24
Finished Jul 10 04:58:22 PM PDT 24
Peak memory 199828 kb
Host smart-35bf5d8d-a118-4629-a506-dc190abcb45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104490591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4104490591
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2608821404
Short name T836
Test name
Test status
Simulation time 72859335162 ps
CPU time 215.18 seconds
Started Jul 10 04:57:55 PM PDT 24
Finished Jul 10 05:01:31 PM PDT 24
Peak memory 208644 kb
Host smart-83f690ec-2f14-45b7-a08c-4901174272b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608821404 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2608821404
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3062065510
Short name T246
Test name
Test status
Simulation time 27113285857 ps
CPU time 10.15 seconds
Started Jul 10 04:57:57 PM PDT 24
Finished Jul 10 04:58:08 PM PDT 24
Peak memory 199776 kb
Host smart-dced01a6-bee3-4fa5-bc40-06f74e92289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062065510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3062065510
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.233142166
Short name T37
Test name
Test status
Simulation time 25992724312 ps
CPU time 152.68 seconds
Started Jul 10 04:57:56 PM PDT 24
Finished Jul 10 05:00:30 PM PDT 24
Peak memory 215672 kb
Host smart-82dedbed-2169-4017-9f42-c2414d759629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233142166 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.233142166
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2210643608
Short name T1024
Test name
Test status
Simulation time 73603493813 ps
CPU time 23.68 seconds
Started Jul 10 04:57:57 PM PDT 24
Finished Jul 10 04:58:22 PM PDT 24
Peak memory 199780 kb
Host smart-8b785ae6-37f1-409a-ae59-58025b32089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210643608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2210643608
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3689531278
Short name T998
Test name
Test status
Simulation time 109475302043 ps
CPU time 789.04 seconds
Started Jul 10 04:57:56 PM PDT 24
Finished Jul 10 05:11:06 PM PDT 24
Peak memory 228404 kb
Host smart-88c702b9-1c7b-4835-8830-99bb7890cf95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689531278 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3689531278
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.4057378330
Short name T212
Test name
Test status
Simulation time 28871136402 ps
CPU time 13.5 seconds
Started Jul 10 04:57:57 PM PDT 24
Finished Jul 10 04:58:11 PM PDT 24
Peak memory 200040 kb
Host smart-a14aa76d-1ce6-4515-8c9f-9c870f0e2fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057378330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4057378330
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.288658297
Short name T1113
Test name
Test status
Simulation time 49461433134 ps
CPU time 964.26 seconds
Started Jul 10 04:58:08 PM PDT 24
Finished Jul 10 05:14:13 PM PDT 24
Peak memory 224676 kb
Host smart-9a757d1f-9595-49de-ac32-fb64467aed25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288658297 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.288658297
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3358828260
Short name T239
Test name
Test status
Simulation time 104931686852 ps
CPU time 116.58 seconds
Started Jul 10 04:58:06 PM PDT 24
Finished Jul 10 05:00:04 PM PDT 24
Peak memory 199840 kb
Host smart-0a3860c5-3170-483a-84da-a622566af281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358828260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3358828260
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.4015798519
Short name T638
Test name
Test status
Simulation time 58026863568 ps
CPU time 699.38 seconds
Started Jul 10 04:58:06 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 213032 kb
Host smart-b7554a22-dd59-4f4b-8fe8-3198d4e86a3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015798519 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.4015798519
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.4073936861
Short name T358
Test name
Test status
Simulation time 15312117 ps
CPU time 0.57 seconds
Started Jul 10 04:52:38 PM PDT 24
Finished Jul 10 04:52:39 PM PDT 24
Peak memory 195140 kb
Host smart-8a655bd6-03b1-4d0e-bf5b-5ab777bd5725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073936861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.4073936861
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2568818961
Short name T558
Test name
Test status
Simulation time 52729072988 ps
CPU time 43.6 seconds
Started Jul 10 04:52:25 PM PDT 24
Finished Jul 10 04:53:10 PM PDT 24
Peak memory 199756 kb
Host smart-636b0d04-0d39-4b87-a2f3-79f84649b2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568818961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2568818961
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3372624364
Short name T741
Test name
Test status
Simulation time 207664585724 ps
CPU time 85.07 seconds
Started Jul 10 04:52:26 PM PDT 24
Finished Jul 10 04:53:52 PM PDT 24
Peak memory 200096 kb
Host smart-54c95414-af3f-4412-a3e5-22989c3e7652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372624364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3372624364
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1756179265
Short name T335
Test name
Test status
Simulation time 52878467060 ps
CPU time 38.79 seconds
Started Jul 10 04:52:24 PM PDT 24
Finished Jul 10 04:53:04 PM PDT 24
Peak memory 199776 kb
Host smart-86ff90ec-067d-4cc4-954e-3b08cd9a9b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756179265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1756179265
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2419882826
Short name T606
Test name
Test status
Simulation time 34688417152 ps
CPU time 30.98 seconds
Started Jul 10 04:52:26 PM PDT 24
Finished Jul 10 04:52:58 PM PDT 24
Peak memory 199756 kb
Host smart-29bf179e-c028-4016-b434-2fa85b60222f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419882826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2419882826
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2066309021
Short name T1079
Test name
Test status
Simulation time 54187088262 ps
CPU time 77.85 seconds
Started Jul 10 04:52:33 PM PDT 24
Finished Jul 10 04:53:52 PM PDT 24
Peak memory 199796 kb
Host smart-1fff7f16-7c62-4ecd-8981-4166c781e310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066309021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2066309021
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.840235595
Short name T1107
Test name
Test status
Simulation time 5766588225 ps
CPU time 8.74 seconds
Started Jul 10 04:52:37 PM PDT 24
Finished Jul 10 04:52:46 PM PDT 24
Peak memory 197684 kb
Host smart-4e0b1a82-01ff-44a9-9869-6974457f68c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840235595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.840235595
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.444187130
Short name T286
Test name
Test status
Simulation time 141789942794 ps
CPU time 75.28 seconds
Started Jul 10 04:52:31 PM PDT 24
Finished Jul 10 04:53:46 PM PDT 24
Peak memory 199396 kb
Host smart-66604527-4ec5-427f-85b7-96d7916e533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444187130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.444187130
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2656865151
Short name T798
Test name
Test status
Simulation time 17172896169 ps
CPU time 702.67 seconds
Started Jul 10 04:52:34 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 200084 kb
Host smart-bfc86fef-516c-429f-a239-db84984922fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656865151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2656865151
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3691564349
Short name T362
Test name
Test status
Simulation time 4894800602 ps
CPU time 11.11 seconds
Started Jul 10 04:52:30 PM PDT 24
Finished Jul 10 04:52:42 PM PDT 24
Peak memory 197696 kb
Host smart-277dd24c-bd69-4458-bf3f-e5ae18aa9cae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691564349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3691564349
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3861862298
Short name T303
Test name
Test status
Simulation time 50660655068 ps
CPU time 76.5 seconds
Started Jul 10 04:52:24 PM PDT 24
Finished Jul 10 04:53:41 PM PDT 24
Peak memory 199852 kb
Host smart-fea7d3e7-4612-45e6-9fee-3c6f5a5b401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861862298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3861862298
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1865101480
Short name T451
Test name
Test status
Simulation time 2632516034 ps
CPU time 3.05 seconds
Started Jul 10 04:52:31 PM PDT 24
Finished Jul 10 04:52:35 PM PDT 24
Peak memory 195588 kb
Host smart-2febc58d-331e-4f16-918e-e5f67bd66e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865101480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1865101480
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2763398647
Short name T1132
Test name
Test status
Simulation time 761912838 ps
CPU time 1.67 seconds
Started Jul 10 04:52:26 PM PDT 24
Finished Jul 10 04:52:28 PM PDT 24
Peak memory 199324 kb
Host smart-cc1268ce-8442-48c3-8096-766de82ab639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763398647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2763398647
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1455484991
Short name T1155
Test name
Test status
Simulation time 435012522627 ps
CPU time 178.46 seconds
Started Jul 10 04:52:32 PM PDT 24
Finished Jul 10 04:55:32 PM PDT 24
Peak memory 199816 kb
Host smart-2562261c-122b-46c9-8254-2027888ff375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455484991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1455484991
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1071000995
Short name T529
Test name
Test status
Simulation time 290559360421 ps
CPU time 1135.29 seconds
Started Jul 10 04:52:32 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 224696 kb
Host smart-8a069b27-b4fc-44e0-8f33-a3360a1de7cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071000995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1071000995
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2849212813
Short name T683
Test name
Test status
Simulation time 1226463133 ps
CPU time 4.04 seconds
Started Jul 10 04:52:34 PM PDT 24
Finished Jul 10 04:52:39 PM PDT 24
Peak memory 199184 kb
Host smart-1bae1dec-ce89-49a7-9894-23f042785926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849212813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2849212813
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2555592706
Short name T1036
Test name
Test status
Simulation time 8328835773 ps
CPU time 7.52 seconds
Started Jul 10 04:52:26 PM PDT 24
Finished Jul 10 04:52:35 PM PDT 24
Peak memory 199628 kb
Host smart-72ad8dd4-d23b-4fac-a974-cb1b753e06a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555592706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2555592706
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.4180506442
Short name T211
Test name
Test status
Simulation time 36698406751 ps
CPU time 26.62 seconds
Started Jul 10 04:58:07 PM PDT 24
Finished Jul 10 04:58:35 PM PDT 24
Peak memory 199784 kb
Host smart-56f74cd0-f8be-432f-aa25-02ad69573744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180506442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.4180506442
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3068390651
Short name T898
Test name
Test status
Simulation time 76729912569 ps
CPU time 310.8 seconds
Started Jul 10 04:58:07 PM PDT 24
Finished Jul 10 05:03:19 PM PDT 24
Peak memory 216512 kb
Host smart-52dbafba-786a-4bdd-8d22-8d86443e3cff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068390651 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3068390651
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3389478666
Short name T831
Test name
Test status
Simulation time 87508311236 ps
CPU time 125.81 seconds
Started Jul 10 04:58:07 PM PDT 24
Finished Jul 10 05:00:14 PM PDT 24
Peak memory 199864 kb
Host smart-320d6fd8-fc82-4464-a281-1bb62d7a459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389478666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3389478666
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2377679503
Short name T1134
Test name
Test status
Simulation time 53817409171 ps
CPU time 471.99 seconds
Started Jul 10 04:58:06 PM PDT 24
Finished Jul 10 05:05:59 PM PDT 24
Peak memory 215976 kb
Host smart-80b5407e-d346-4b24-80ab-59a5323044de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377679503 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2377679503
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.292180378
Short name T988
Test name
Test status
Simulation time 13748736809 ps
CPU time 24.04 seconds
Started Jul 10 04:58:07 PM PDT 24
Finished Jul 10 04:58:32 PM PDT 24
Peak memory 199832 kb
Host smart-c0823a7e-bba4-4e36-94d4-ff6862ba543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292180378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.292180378
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1887656131
Short name T341
Test name
Test status
Simulation time 85508535976 ps
CPU time 592.6 seconds
Started Jul 10 04:58:07 PM PDT 24
Finished Jul 10 05:08:01 PM PDT 24
Peak memory 224632 kb
Host smart-857a2bb3-d523-45f7-9224-53db51992e33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887656131 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1887656131
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3674898340
Short name T226
Test name
Test status
Simulation time 46168031705 ps
CPU time 22.86 seconds
Started Jul 10 04:58:06 PM PDT 24
Finished Jul 10 04:58:30 PM PDT 24
Peak memory 199848 kb
Host smart-c28e2717-199d-436f-8965-4b4f91622cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674898340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3674898340
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.885312922
Short name T627
Test name
Test status
Simulation time 123019667164 ps
CPU time 578.79 seconds
Started Jul 10 04:58:06 PM PDT 24
Finished Jul 10 05:07:45 PM PDT 24
Peak memory 216532 kb
Host smart-049c86a3-573e-41ce-8fe2-7e806ee94909
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885312922 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.885312922
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2104934942
Short name T1156
Test name
Test status
Simulation time 37767575905 ps
CPU time 54.43 seconds
Started Jul 10 04:58:07 PM PDT 24
Finished Jul 10 04:59:02 PM PDT 24
Peak memory 199852 kb
Host smart-7a622db6-a4e3-4d66-8832-073644b926f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104934942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2104934942
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.318525757
Short name T406
Test name
Test status
Simulation time 33177903346 ps
CPU time 232.81 seconds
Started Jul 10 04:58:16 PM PDT 24
Finished Jul 10 05:02:10 PM PDT 24
Peak memory 208184 kb
Host smart-c84084b2-4e9b-4651-a81c-fded0c51ed1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318525757 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.318525757
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1323792705
Short name T242
Test name
Test status
Simulation time 84139023166 ps
CPU time 62.28 seconds
Started Jul 10 04:58:16 PM PDT 24
Finished Jul 10 04:59:19 PM PDT 24
Peak memory 199808 kb
Host smart-1a131135-f76a-46b0-ab6c-976d59f978c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323792705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1323792705
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2274109061
Short name T914
Test name
Test status
Simulation time 17280767729 ps
CPU time 27.64 seconds
Started Jul 10 04:58:17 PM PDT 24
Finished Jul 10 04:58:46 PM PDT 24
Peak memory 199824 kb
Host smart-615d9dc6-f8c1-4167-b435-ed8e55a42a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274109061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2274109061
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.500296483
Short name T681
Test name
Test status
Simulation time 56083998151 ps
CPU time 544.35 seconds
Started Jul 10 04:58:16 PM PDT 24
Finished Jul 10 05:07:21 PM PDT 24
Peak memory 215004 kb
Host smart-da50d257-9d09-4da1-a686-9239edc33330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500296483 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.500296483
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1158458645
Short name T249
Test name
Test status
Simulation time 19222125215 ps
CPU time 33.1 seconds
Started Jul 10 04:58:15 PM PDT 24
Finished Jul 10 04:58:49 PM PDT 24
Peak memory 199788 kb
Host smart-09e50cbb-5173-4f29-8868-8ef03bf43b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158458645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1158458645
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.677310056
Short name T797
Test name
Test status
Simulation time 107929944875 ps
CPU time 1454.73 seconds
Started Jul 10 04:58:18 PM PDT 24
Finished Jul 10 05:22:34 PM PDT 24
Peak memory 216340 kb
Host smart-0ef747dd-206e-4adc-9536-810905834dab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677310056 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.677310056
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2555573227
Short name T549
Test name
Test status
Simulation time 156007507334 ps
CPU time 135.35 seconds
Started Jul 10 04:58:17 PM PDT 24
Finished Jul 10 05:00:33 PM PDT 24
Peak memory 199780 kb
Host smart-da9860c8-ea21-4b02-8419-0fc568262c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555573227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2555573227
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2950848129
Short name T137
Test name
Test status
Simulation time 77630318098 ps
CPU time 34.9 seconds
Started Jul 10 04:58:18 PM PDT 24
Finished Jul 10 04:58:54 PM PDT 24
Peak memory 199596 kb
Host smart-cfe430f2-2c9d-470f-98b6-2c6563b1ff23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950848129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2950848129
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.4256697932
Short name T261
Test name
Test status
Simulation time 53185435043 ps
CPU time 867.85 seconds
Started Jul 10 04:58:18 PM PDT 24
Finished Jul 10 05:12:47 PM PDT 24
Peak memory 216344 kb
Host smart-5644da37-dd3f-4c61-b703-ec8313b06e27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256697932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4256697932
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1556299555
Short name T887
Test name
Test status
Simulation time 11787081 ps
CPU time 0.57 seconds
Started Jul 10 04:52:42 PM PDT 24
Finished Jul 10 04:52:44 PM PDT 24
Peak memory 195220 kb
Host smart-9fe3db03-a76f-4069-9aab-74b367a178c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556299555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1556299555
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.944105921
Short name T698
Test name
Test status
Simulation time 62209238373 ps
CPU time 49.71 seconds
Started Jul 10 04:52:32 PM PDT 24
Finished Jul 10 04:53:23 PM PDT 24
Peak memory 199840 kb
Host smart-023322f4-b20f-45fb-8d25-cf84cb4a6c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944105921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.944105921
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.4243369958
Short name T543
Test name
Test status
Simulation time 16057713537 ps
CPU time 22.26 seconds
Started Jul 10 04:52:32 PM PDT 24
Finished Jul 10 04:52:55 PM PDT 24
Peak memory 199724 kb
Host smart-c990150c-985b-464d-80ba-50fde56bfe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243369958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4243369958
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1665886467
Short name T481
Test name
Test status
Simulation time 111357477480 ps
CPU time 47.14 seconds
Started Jul 10 04:52:32 PM PDT 24
Finished Jul 10 04:53:21 PM PDT 24
Peak memory 199828 kb
Host smart-fdbfa655-a72e-4ff3-a9ec-4e78580175ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665886467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1665886467
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.914379745
Short name T336
Test name
Test status
Simulation time 13295729456 ps
CPU time 19.93 seconds
Started Jul 10 04:52:34 PM PDT 24
Finished Jul 10 04:52:55 PM PDT 24
Peak memory 196032 kb
Host smart-8e8aa352-0613-4c36-ad8b-d4150438ac1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914379745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.914379745
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1211335352
Short name T570
Test name
Test status
Simulation time 232341969701 ps
CPU time 177.47 seconds
Started Jul 10 04:52:33 PM PDT 24
Finished Jul 10 04:55:31 PM PDT 24
Peak memory 199840 kb
Host smart-c2fa96e5-71f2-4ea4-a8dd-f4b5cf4e983d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211335352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1211335352
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1253740764
Short name T121
Test name
Test status
Simulation time 272880989 ps
CPU time 1.25 seconds
Started Jul 10 04:52:33 PM PDT 24
Finished Jul 10 04:52:36 PM PDT 24
Peak memory 198024 kb
Host smart-ce2c64cb-d421-4ffb-895c-8931f7d38b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253740764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1253740764
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.94227781
Short name T367
Test name
Test status
Simulation time 74404741682 ps
CPU time 12.62 seconds
Started Jul 10 04:52:33 PM PDT 24
Finished Jul 10 04:52:47 PM PDT 24
Peak memory 199868 kb
Host smart-c87e6887-1af5-456c-8f6f-b6d374127c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94227781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.94227781
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3611995385
Short name T1000
Test name
Test status
Simulation time 12947469986 ps
CPU time 789.64 seconds
Started Jul 10 04:52:37 PM PDT 24
Finished Jul 10 05:05:48 PM PDT 24
Peak memory 199752 kb
Host smart-5bec0ed9-2660-4c52-bf15-a9ec852a1eaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611995385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3611995385
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.201904869
Short name T427
Test name
Test status
Simulation time 3579453787 ps
CPU time 26.07 seconds
Started Jul 10 04:52:32 PM PDT 24
Finished Jul 10 04:52:58 PM PDT 24
Peak memory 198220 kb
Host smart-d06f92c0-bfbc-4b23-a84a-e0b0e7c7699c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201904869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.201904869
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1599911894
Short name T161
Test name
Test status
Simulation time 51172792503 ps
CPU time 33.2 seconds
Started Jul 10 04:52:33 PM PDT 24
Finished Jul 10 04:53:07 PM PDT 24
Peak memory 199776 kb
Host smart-b4ab0c5f-c189-4d1c-b730-5c8b2120dcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599911894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1599911894
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2203610199
Short name T525
Test name
Test status
Simulation time 4682044270 ps
CPU time 1.63 seconds
Started Jul 10 04:52:33 PM PDT 24
Finished Jul 10 04:52:36 PM PDT 24
Peak memory 196320 kb
Host smart-2721f1b6-d561-4c5c-953d-ffac6a26e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203610199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2203610199
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3200957522
Short name T842
Test name
Test status
Simulation time 1043959180 ps
CPU time 1.45 seconds
Started Jul 10 04:52:35 PM PDT 24
Finished Jul 10 04:52:37 PM PDT 24
Peak memory 199740 kb
Host smart-c58a4ef9-db07-4145-84a4-f8758449e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200957522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3200957522
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1311709650
Short name T284
Test name
Test status
Simulation time 88467519923 ps
CPU time 129.85 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:54:52 PM PDT 24
Peak memory 199840 kb
Host smart-928fd933-073f-40e1-a1ad-34208f82414b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311709650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1311709650
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3515861412
Short name T555
Test name
Test status
Simulation time 242579552625 ps
CPU time 1900.64 seconds
Started Jul 10 04:52:37 PM PDT 24
Finished Jul 10 05:24:19 PM PDT 24
Peak memory 225172 kb
Host smart-4b3b8521-7344-4a1c-8bdb-fc01368f2d44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515861412 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3515861412
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3566208803
Short name T361
Test name
Test status
Simulation time 1453979137 ps
CPU time 1.44 seconds
Started Jul 10 04:52:32 PM PDT 24
Finished Jul 10 04:52:35 PM PDT 24
Peak memory 198172 kb
Host smart-34fb2c5b-db90-4f1c-9dae-192486c9b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566208803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3566208803
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3314297866
Short name T420
Test name
Test status
Simulation time 13914125237 ps
CPU time 6 seconds
Started Jul 10 04:52:33 PM PDT 24
Finished Jul 10 04:52:40 PM PDT 24
Peak memory 199764 kb
Host smart-88a50e9c-c293-4ad5-bb5e-df1fcdd6745a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314297866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3314297866
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2141997012
Short name T1158
Test name
Test status
Simulation time 22360730021 ps
CPU time 23.71 seconds
Started Jul 10 04:58:20 PM PDT 24
Finished Jul 10 04:58:45 PM PDT 24
Peak memory 199924 kb
Host smart-24e675ad-1e31-48e2-a11d-0c3a2fa864c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141997012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2141997012
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3971339206
Short name T896
Test name
Test status
Simulation time 106639213491 ps
CPU time 39.89 seconds
Started Jul 10 04:58:17 PM PDT 24
Finished Jul 10 04:58:57 PM PDT 24
Peak memory 199840 kb
Host smart-a2919fff-4a39-4552-a00b-18df62fec168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971339206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3971339206
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1047870884
Short name T58
Test name
Test status
Simulation time 42248831335 ps
CPU time 461.99 seconds
Started Jul 10 04:58:16 PM PDT 24
Finished Jul 10 05:05:59 PM PDT 24
Peak memory 216584 kb
Host smart-1bd4a6e8-23d8-420b-b641-33f460c68249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047870884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1047870884
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3456782958
Short name T687
Test name
Test status
Simulation time 56511454118 ps
CPU time 40.81 seconds
Started Jul 10 04:58:16 PM PDT 24
Finished Jul 10 04:58:57 PM PDT 24
Peak memory 199804 kb
Host smart-67372379-3ce9-44f4-b63f-63bb1e0d58c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456782958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3456782958
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3224092554
Short name T115
Test name
Test status
Simulation time 31804400688 ps
CPU time 327.01 seconds
Started Jul 10 04:58:20 PM PDT 24
Finished Jul 10 05:03:47 PM PDT 24
Peak memory 215932 kb
Host smart-0719edd9-d4e1-42d7-bccd-608def5309f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224092554 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3224092554
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1968743265
Short name T605
Test name
Test status
Simulation time 14164759508 ps
CPU time 27.42 seconds
Started Jul 10 04:58:16 PM PDT 24
Finished Jul 10 04:58:45 PM PDT 24
Peak memory 199868 kb
Host smart-cbaa54f5-0827-4d84-9f07-c09134db1eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968743265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1968743265
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3902108739
Short name T589
Test name
Test status
Simulation time 187841351087 ps
CPU time 756 seconds
Started Jul 10 04:58:16 PM PDT 24
Finished Jul 10 05:10:53 PM PDT 24
Peak memory 224804 kb
Host smart-2a0dd078-1c03-4162-ab26-ae77aaab7799
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902108739 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3902108739
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1222795130
Short name T105
Test name
Test status
Simulation time 257107647519 ps
CPU time 336.55 seconds
Started Jul 10 04:58:18 PM PDT 24
Finished Jul 10 05:03:55 PM PDT 24
Peak memory 199792 kb
Host smart-1bcaab5a-6957-469d-a6bd-0bb087b82097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222795130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1222795130
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2326242247
Short name T648
Test name
Test status
Simulation time 258053877939 ps
CPU time 1478.52 seconds
Started Jul 10 04:58:15 PM PDT 24
Finished Jul 10 05:22:54 PM PDT 24
Peak memory 230604 kb
Host smart-1b824829-5083-4fd1-bf48-433345267ede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326242247 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2326242247
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1263689299
Short name T893
Test name
Test status
Simulation time 123469799978 ps
CPU time 98.68 seconds
Started Jul 10 04:58:19 PM PDT 24
Finished Jul 10 04:59:59 PM PDT 24
Peak memory 199864 kb
Host smart-c2fef7be-f9d6-4486-91b3-63e75573baff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263689299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1263689299
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1711318831
Short name T1176
Test name
Test status
Simulation time 20286594838 ps
CPU time 225.82 seconds
Started Jul 10 04:58:24 PM PDT 24
Finished Jul 10 05:02:11 PM PDT 24
Peak memory 208064 kb
Host smart-ea363488-fa34-493c-892b-e539f8697bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711318831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1711318831
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2871303210
Short name T955
Test name
Test status
Simulation time 143716205695 ps
CPU time 256.39 seconds
Started Jul 10 04:58:25 PM PDT 24
Finished Jul 10 05:02:42 PM PDT 24
Peak memory 199840 kb
Host smart-50cdc184-57ff-4198-8533-35dd46f97131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871303210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2871303210
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3287034573
Short name T1028
Test name
Test status
Simulation time 159374834152 ps
CPU time 423.93 seconds
Started Jul 10 04:58:24 PM PDT 24
Finished Jul 10 05:05:29 PM PDT 24
Peak memory 216800 kb
Host smart-f622668f-9771-4887-bdc5-763c9d7a4fd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287034573 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3287034573
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4040043848
Short name T472
Test name
Test status
Simulation time 156213666649 ps
CPU time 72.66 seconds
Started Jul 10 04:58:24 PM PDT 24
Finished Jul 10 04:59:38 PM PDT 24
Peak memory 199776 kb
Host smart-10b4982a-4d35-41cf-b4ba-493c46c9d494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040043848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4040043848
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2716960223
Short name T785
Test name
Test status
Simulation time 6829414630 ps
CPU time 64.41 seconds
Started Jul 10 04:58:25 PM PDT 24
Finished Jul 10 04:59:31 PM PDT 24
Peak memory 215328 kb
Host smart-76130451-a441-42ae-9301-e91d7fddd3fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716960223 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2716960223
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2997065713
Short name T197
Test name
Test status
Simulation time 80081943244 ps
CPU time 122.22 seconds
Started Jul 10 04:58:24 PM PDT 24
Finished Jul 10 05:00:26 PM PDT 24
Peak memory 199828 kb
Host smart-e2181b75-023f-473f-b449-67a5ea43b1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997065713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2997065713
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1106331241
Short name T906
Test name
Test status
Simulation time 72785772413 ps
CPU time 698.72 seconds
Started Jul 10 04:58:25 PM PDT 24
Finished Jul 10 05:10:05 PM PDT 24
Peak memory 216492 kb
Host smart-99c64379-5ae0-4272-ac6a-165ba03948e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106331241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1106331241
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1445255517
Short name T12
Test name
Test status
Simulation time 68130157770 ps
CPU time 23.79 seconds
Started Jul 10 04:58:24 PM PDT 24
Finished Jul 10 04:58:49 PM PDT 24
Peak memory 199804 kb
Host smart-dc0c997b-0621-4248-bc0f-4119e53cf1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445255517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1445255517
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2136583125
Short name T881
Test name
Test status
Simulation time 19624294 ps
CPU time 0.58 seconds
Started Jul 10 04:52:44 PM PDT 24
Finished Jul 10 04:52:45 PM PDT 24
Peak memory 195220 kb
Host smart-4087f8fd-5f98-4834-9f7b-d0cc49eec42f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136583125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2136583125
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3586488908
Short name T486
Test name
Test status
Simulation time 23680803289 ps
CPU time 33.06 seconds
Started Jul 10 04:52:45 PM PDT 24
Finished Jul 10 04:53:19 PM PDT 24
Peak memory 199740 kb
Host smart-5a4680f2-d66e-4b56-a9b5-3c82dff776e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586488908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3586488908
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.479585213
Short name T146
Test name
Test status
Simulation time 60802986183 ps
CPU time 41.79 seconds
Started Jul 10 04:52:40 PM PDT 24
Finished Jul 10 04:53:23 PM PDT 24
Peak memory 199900 kb
Host smart-da85810a-77ac-4bde-a443-88efce26acb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479585213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.479585213
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3847151037
Short name T255
Test name
Test status
Simulation time 8202191313 ps
CPU time 12.57 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:52:55 PM PDT 24
Peak memory 199852 kb
Host smart-2c594387-dd71-424a-a96d-59c20f0a3c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847151037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3847151037
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3751053776
Short name T779
Test name
Test status
Simulation time 296904544961 ps
CPU time 209.39 seconds
Started Jul 10 04:52:42 PM PDT 24
Finished Jul 10 04:56:13 PM PDT 24
Peak memory 197912 kb
Host smart-a95ab4ef-a28c-4bbc-820c-cba739148aa7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751053776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3751053776
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1675673488
Short name T384
Test name
Test status
Simulation time 194050856195 ps
CPU time 236.98 seconds
Started Jul 10 04:52:40 PM PDT 24
Finished Jul 10 04:56:38 PM PDT 24
Peak memory 199840 kb
Host smart-cecbafe8-d5e7-42b5-95a4-09a0bf268de1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675673488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1675673488
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2150320583
Short name T390
Test name
Test status
Simulation time 10856909511 ps
CPU time 14.44 seconds
Started Jul 10 04:52:45 PM PDT 24
Finished Jul 10 04:53:00 PM PDT 24
Peak memory 199656 kb
Host smart-07ad1ac5-6264-4523-966f-127075c18f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150320583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2150320583
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2726751266
Short name T42
Test name
Test status
Simulation time 138010582038 ps
CPU time 139.4 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:55:01 PM PDT 24
Peak memory 199996 kb
Host smart-2c57b839-5933-4e07-b48a-82c1f65793ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726751266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2726751266
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2736951358
Short name T388
Test name
Test status
Simulation time 17251425878 ps
CPU time 361.18 seconds
Started Jul 10 04:52:45 PM PDT 24
Finished Jul 10 04:58:47 PM PDT 24
Peak memory 199748 kb
Host smart-47a37fa4-a681-4806-b69c-5326fdd14010
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736951358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2736951358
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2136945419
Short name T1047
Test name
Test status
Simulation time 5161151567 ps
CPU time 34.35 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:53:17 PM PDT 24
Peak memory 197676 kb
Host smart-f03c0d7f-0f45-4b0c-b913-df25307b2241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136945419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2136945419
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2558272615
Short name T25
Test name
Test status
Simulation time 190031594345 ps
CPU time 156.7 seconds
Started Jul 10 04:52:42 PM PDT 24
Finished Jul 10 04:55:20 PM PDT 24
Peak memory 199732 kb
Host smart-f11321bc-2ae1-4f30-bb9e-d713cf8b98ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558272615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2558272615
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2368270124
Short name T307
Test name
Test status
Simulation time 34386747421 ps
CPU time 12.65 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:52:55 PM PDT 24
Peak memory 196060 kb
Host smart-7e5c9146-57d8-4a90-ba78-8b5b68f05fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368270124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2368270124
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2282702503
Short name T305
Test name
Test status
Simulation time 5297555223 ps
CPU time 16.31 seconds
Started Jul 10 04:52:40 PM PDT 24
Finished Jul 10 04:52:57 PM PDT 24
Peak memory 199308 kb
Host smart-4e8bc5a9-928f-4f83-bbbd-9e4aad531a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282702503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2282702503
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3086795061
Short name T1084
Test name
Test status
Simulation time 269318559575 ps
CPU time 1019.2 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 05:09:42 PM PDT 24
Peak memory 225508 kb
Host smart-14ed3f34-e3bb-4ff3-844d-21a9c103d6cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086795061 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3086795061
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1390646980
Short name T838
Test name
Test status
Simulation time 2659418725 ps
CPU time 1.48 seconds
Started Jul 10 04:52:40 PM PDT 24
Finished Jul 10 04:52:42 PM PDT 24
Peak memory 198620 kb
Host smart-cbc95915-b105-4d03-98f9-3b2ca51d0eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390646980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1390646980
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.630480255
Short name T10
Test name
Test status
Simulation time 96358542802 ps
CPU time 211.12 seconds
Started Jul 10 04:52:41 PM PDT 24
Finished Jul 10 04:56:13 PM PDT 24
Peak memory 199820 kb
Host smart-3e74d7d4-1a8a-4b11-8ea2-4ff53327661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630480255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.630480255
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.375724596
Short name T889
Test name
Test status
Simulation time 48273971935 ps
CPU time 66.76 seconds
Started Jul 10 04:58:26 PM PDT 24
Finished Jul 10 04:59:34 PM PDT 24
Peak memory 199788 kb
Host smart-f19a04c1-20fb-4860-9a0d-574a37b223fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375724596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.375724596
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3547032198
Short name T394
Test name
Test status
Simulation time 17265749072 ps
CPU time 157.68 seconds
Started Jul 10 04:58:25 PM PDT 24
Finished Jul 10 05:01:04 PM PDT 24
Peak memory 211444 kb
Host smart-c50892fd-3ba6-4936-9ee9-e96e6526f914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547032198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3547032198
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2062807140
Short name T948
Test name
Test status
Simulation time 68688759681 ps
CPU time 25.43 seconds
Started Jul 10 04:58:26 PM PDT 24
Finished Jul 10 04:58:53 PM PDT 24
Peak memory 199828 kb
Host smart-cd0d4eb6-4f2e-47c0-840c-1d4f6fb99931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062807140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2062807140
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3667045631
Short name T1109
Test name
Test status
Simulation time 44456485406 ps
CPU time 171.26 seconds
Started Jul 10 04:58:24 PM PDT 24
Finished Jul 10 05:01:16 PM PDT 24
Peak memory 216488 kb
Host smart-fd5c6c64-305b-4c89-bcaa-420f85a17a73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667045631 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3667045631
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1528636245
Short name T965
Test name
Test status
Simulation time 21342537176 ps
CPU time 35.06 seconds
Started Jul 10 04:58:27 PM PDT 24
Finished Jul 10 04:59:03 PM PDT 24
Peak memory 199780 kb
Host smart-6d55d568-f71f-43c3-bed4-7c6fef0d416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528636245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1528636245
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2372130133
Short name T110
Test name
Test status
Simulation time 49900878504 ps
CPU time 250.78 seconds
Started Jul 10 04:58:25 PM PDT 24
Finished Jul 10 05:02:37 PM PDT 24
Peak memory 214516 kb
Host smart-fd8af673-a6a6-4cfa-b7b2-56e64addcece
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372130133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2372130133
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1733854178
Short name T509
Test name
Test status
Simulation time 431420372592 ps
CPU time 548.94 seconds
Started Jul 10 04:58:32 PM PDT 24
Finished Jul 10 05:07:42 PM PDT 24
Peak memory 216344 kb
Host smart-527a3720-b212-4836-a830-a9fdb7d76776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733854178 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1733854178
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.781839346
Short name T157
Test name
Test status
Simulation time 57453596235 ps
CPU time 100.46 seconds
Started Jul 10 04:58:32 PM PDT 24
Finished Jul 10 05:00:13 PM PDT 24
Peak memory 199804 kb
Host smart-731e79fa-349e-4bc9-9cf2-6a1385dbd9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781839346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.781839346
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2288209768
Short name T1053
Test name
Test status
Simulation time 118017609051 ps
CPU time 418.79 seconds
Started Jul 10 04:58:33 PM PDT 24
Finished Jul 10 05:05:33 PM PDT 24
Peak memory 225932 kb
Host smart-b8c6a84e-b653-4e7a-b0c0-3eabb79d79ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288209768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2288209768
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3212080255
Short name T824
Test name
Test status
Simulation time 25955566971 ps
CPU time 40.87 seconds
Started Jul 10 04:58:34 PM PDT 24
Finished Jul 10 04:59:16 PM PDT 24
Peak memory 199740 kb
Host smart-125156e7-e7c0-4185-9d4c-8b29a45e0e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212080255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3212080255
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2871649683
Short name T231
Test name
Test status
Simulation time 38513004342 ps
CPU time 32.29 seconds
Started Jul 10 04:58:35 PM PDT 24
Finished Jul 10 04:59:08 PM PDT 24
Peak memory 199864 kb
Host smart-7ef720a8-591e-4bb9-8562-631ee4913840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871649683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2871649683
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3713200309
Short name T972
Test name
Test status
Simulation time 108979423735 ps
CPU time 290.08 seconds
Started Jul 10 04:58:34 PM PDT 24
Finished Jul 10 05:03:26 PM PDT 24
Peak memory 216548 kb
Host smart-f4d8b00b-dea2-4c35-b281-921d2a579b1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713200309 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3713200309
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1498083094
Short name T402
Test name
Test status
Simulation time 40647877685 ps
CPU time 17.33 seconds
Started Jul 10 04:58:32 PM PDT 24
Finished Jul 10 04:58:50 PM PDT 24
Peak memory 199780 kb
Host smart-b591d5d7-14f5-4978-8b76-2d79bfcde108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498083094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1498083094
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3141651515
Short name T439
Test name
Test status
Simulation time 59687268787 ps
CPU time 774.89 seconds
Started Jul 10 04:58:33 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 224636 kb
Host smart-240ae731-9eb3-481f-a7ae-f457d7d3be25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141651515 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3141651515
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1534863778
Short name T795
Test name
Test status
Simulation time 241162563449 ps
CPU time 180.48 seconds
Started Jul 10 04:58:33 PM PDT 24
Finished Jul 10 05:01:35 PM PDT 24
Peak memory 199744 kb
Host smart-3830b797-8c79-4b10-a688-7cb44da368f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534863778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1534863778
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3195824592
Short name T780
Test name
Test status
Simulation time 10161102441 ps
CPU time 98.91 seconds
Started Jul 10 04:58:34 PM PDT 24
Finished Jul 10 05:00:15 PM PDT 24
Peak memory 215812 kb
Host smart-5abb16cc-8ad2-45d7-8885-a9cfa629fdb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195824592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3195824592
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2123334697
Short name T947
Test name
Test status
Simulation time 177057326686 ps
CPU time 141.89 seconds
Started Jul 10 04:58:34 PM PDT 24
Finished Jul 10 05:00:58 PM PDT 24
Peak memory 199840 kb
Host smart-9c0cb999-21d2-41ee-98f5-0dbd40c7ff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123334697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2123334697
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1188218182
Short name T1032
Test name
Test status
Simulation time 68584425586 ps
CPU time 193.51 seconds
Started Jul 10 04:58:32 PM PDT 24
Finished Jul 10 05:01:46 PM PDT 24
Peak memory 216532 kb
Host smart-04d727ae-b0ca-4970-9f76-1d184969dad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188218182 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1188218182
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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