Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98738	1			T1	18		T2	232		T3	11
all_values[1]	98738	1			T1	18		T2	232		T3	11
all_values[2]	98738	1			T1	18		T2	232		T3	11
all_values[3]	98738	1			T1	18		T2	232		T3	11
all_values[4]	98738	1			T1	18		T2	232		T3	11
all_values[5]	98738	1			T1	18		T2	232		T3	11
all_values[6]	98738	1			T1	18		T2	232		T3	11
all_values[7]	98738	1			T1	18		T2	232		T3	11
all_values[8]	98738	1			T1	18		T2	232		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

440903

1

T1

68

T2

1193

T3

50

auto[1]

447739

1

T1

94

T2

895

T3

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

802231

1

T1

147

T2

1727

T3

79

auto[1]

86411

1

T1

15

T2

361

T3

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29758	1			T2	21		T3	2		T4	8
all_values[0]	auto[0]	auto[1]	21685	1			T2	87		T3	5		T5	1
all_values[0]	auto[1]	auto[0]	26196	1			T1	12		T2	33		T3	2
all_values[0]	auto[1]	auto[1]	21099	1			T1	6		T2	91		T3	2
all_values[1]	auto[0]	auto[0]	45248	1			T1	16		T2	150		T3	9
all_values[1]	auto[0]	auto[1]	1512	1			T2	2		T10	4		T31	23
all_values[1]	auto[1]	auto[0]	50070	1			T1	2		T2	75		T4	8
all_values[1]	auto[1]	auto[1]	1908	1			T2	5		T3	2		T5	2
all_values[2]	auto[0]	auto[0]	43435	1			T1	3		T2	65		T3	1
all_values[2]	auto[0]	auto[1]	2650	1			T2	12		T3	1		T4	1
all_values[2]	auto[1]	auto[0]	50194	1			T1	12		T2	141		T3	6
all_values[2]	auto[1]	auto[1]	2459	1			T1	3		T2	14		T3	3
all_values[3]	auto[0]	auto[0]	48594	1			T1	5		T2	143		T3	7
all_values[3]	auto[0]	auto[1]	278	1			T2	1		T10	2		T12	2
all_values[3]	auto[1]	auto[0]	49584	1			T1	13		T2	87		T3	4
all_values[3]	auto[1]	auto[1]	282	1			T2	1		T10	1		T12	1
all_values[4]	auto[0]	auto[0]	48457	1			T1	13		T2	145		T3	7
all_values[4]	auto[0]	auto[1]	452	1			T25	3		T13	5		T14	7
all_values[4]	auto[1]	auto[0]	49251	1			T1	5		T2	75		T3	4
all_values[4]	auto[1]	auto[1]	578	1			T2	12		T10	3		T12	6
all_values[5]	auto[0]	auto[0]	50442	1			T1	13		T2	128		T3	2
all_values[5]	auto[0]	auto[1]	183	1			T10	1		T12	2		T24	2
all_values[5]	auto[1]	auto[0]	47929	1			T1	5		T2	104		T3	9
all_values[5]	auto[1]	auto[1]	184	1			T12	3		T25	4		T112	2
all_values[6]	auto[0]	auto[0]	50325	1			T1	12		T2	119		T4	4
all_values[6]	auto[0]	auto[1]	185	1			T24	2		T25	5		T112	1
all_values[6]	auto[1]	auto[0]	48088	1			T1	6		T2	113		T3	11
all_values[6]	auto[1]	auto[1]	140	1			T12	2		T25	2		T104	4
all_values[7]	auto[0]	auto[0]	47147	1			T1	4		T2	164		T3	9
all_values[7]	auto[0]	auto[1]	306	1			T4	1		T5	1		T12	1
all_values[7]	auto[1]	auto[0]	50910	1			T1	14		T2	64		T3	2
all_values[7]	auto[1]	auto[1]	375	1			T2	4		T10	2		T12	3
all_values[8]	auto[0]	auto[0]	34396	1			T1	1		T2	68		T4	8
all_values[8]	auto[0]	auto[1]	15850	1			T1	1		T2	88		T3	7
all_values[8]	auto[1]	auto[0]	32207	1			T1	11		T2	32		T3	4
all_values[8]	auto[1]	auto[1]	16285	1			T1	5		T2	44		T6	2