Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2568

1

T1

1

T2

5

T3

1

auto[UartRx]

2568

1

T1

1

T2

5

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4564	1			T1	2		T2	8		T3	2
values[1]	50	1			T24	1		T25	1		T111	2
values[2]	51	1			T23	1		T24	3		T28	1
values[3]	55	1			T9	1		T10	1		T12	1
values[4]	60	1			T2	1		T10	1		T25	1
values[5]	50	1			T9	1		T10	2		T23	2
values[6]	50	1			T23	1		T25	2		T26	3
values[7]	63	1			T10	1		T12	1		T23	1
values[8]	56	1			T26	2		T27	1		T28	1
values[9]	49	1			T10	2		T24	2		T102	3
values[10]	55	1			T9	1		T12	1		T24	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2398	1			T1	1		T2	4		T3	1
auto[UartTx]	values[1]	17	1			T24	1		T25	1		T312	1
auto[UartTx]	values[2]	14	1			T24	1		T102	1		T313	1
auto[UartTx]	values[3]	18	1			T9	1		T27	1		T103	1
auto[UartTx]	values[4]	13	1			T2	1		T26	1		T147	1
auto[UartTx]	values[5]	16	1			T314	1		T315	1		T316	1
auto[UartTx]	values[6]	21	1			T23	1		T26	1		T27	1
auto[UartTx]	values[7]	14	1			T25	1		T28	1		T42	1
auto[UartTx]	values[8]	22	1			T27	1		T111	1		T147	1
auto[UartTx]	values[9]	9	1			T10	1		T24	1		T113	1
auto[UartTx]	values[10]	16	1			T24	1		T42	1		T102	1
auto[UartRx]	values[0]	2166	1			T1	1		T2	4		T3	1
auto[UartRx]	values[1]	33	1			T111	2		T110	1		T314	1
auto[UartRx]	values[2]	37	1			T23	1		T24	2		T28	1
auto[UartRx]	values[3]	37	1			T10	1		T12	1		T24	1
auto[UartRx]	values[4]	47	1			T10	1		T25	1		T26	1
auto[UartRx]	values[5]	34	1			T9	1		T10	2		T23	2
auto[UartRx]	values[6]	29	1			T25	2		T26	2		T136	1
auto[UartRx]	values[7]	49	1			T10	1		T12	1		T23	1
auto[UartRx]	values[8]	34	1			T26	2		T28	1		T42	3
auto[UartRx]	values[9]	40	1			T10	1		T24	1		T102	3
auto[UartRx]	values[10]	39	1			T9	1		T12	1		T24	1