Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2465	1			T1	2		T2	7		T3	1
auto[BaudRate115200]	2059	1			T1	3		T2	15		T3	1
auto[BaudRate230400]	2174	1			T1	1		T2	7		T3	3
auto[BaudRate128Kbps]	2068	1			T2	9		T3	1		T5	1
auto[BaudRate256Kbps]	2424	1			T2	23		T3	1		T4	2
auto[BaudRate1Mbps]	1873	1			T1	3		T4	1		T7	2
auto[BaudRate1p5Mbps]	1379	1			T5	2		T9	6		T10	8

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1502	1			T9	49		T30	2		T16	33
freqs[25]	1458	1			T8	11		T32	6		T118	12
freqs[48]	797	1			T269	2		T253	7		T317	3
freqs[50]	688	1			T10	25		T29	7		T78	11
freqs[100]	1110	1			T31	10		T39	10		T11	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	252	1			T9	3		T16	3		T176	1
auto[BaudRate9600]	freqs[25]	253	1			T8	1		T318	3		T37	1
auto[BaudRate9600]	freqs[48]	111	1			T319	1		T303	3		T320	1
auto[BaudRate9600]	freqs[50]	127	1			T10	4		T29	1		T78	11
auto[BaudRate9600]	freqs[100]	167	1			T39	1		T267	1		T13	1
auto[BaudRate115200]	freqs[24]	220	1			T9	7		T16	3		T100	4
auto[BaudRate115200]	freqs[25]	197	1			T8	2		T32	1		T118	4
auto[BaudRate115200]	freqs[48]	117	1			T319	1		T321	1		T322	1
auto[BaudRate115200]	freqs[50]	100	1			T10	1		T29	2		T59	2
auto[BaudRate115200]	freqs[100]	148	1			T31	4		T39	3		T11	1
auto[BaudRate230400]	freqs[24]	261	1			T9	14		T30	1		T16	9
auto[BaudRate230400]	freqs[25]	216	1			T8	4		T32	2		T118	2
auto[BaudRate230400]	freqs[48]	99	1			T269	1		T317	1		T319	3
auto[BaudRate230400]	freqs[50]	85	1			T10	4		T29	2		T59	1
auto[BaudRate230400]	freqs[100]	164	1			T31	1		T39	1		T11	2
auto[BaudRate128Kbps]	freqs[24]	194	1			T9	1		T30	1		T16	9
auto[BaudRate128Kbps]	freqs[25]	222	1			T8	2		T32	3		T118	1
auto[BaudRate128Kbps]	freqs[48]	144	1			T269	1		T319	1		T303	2
auto[BaudRate128Kbps]	freqs[50]	87	1			T29	1		T59	2		T104	7
auto[BaudRate128Kbps]	freqs[100]	153	1			T39	1		T11	2		T121	2
auto[BaudRate256Kbps]	freqs[24]	240	1			T9	7		T16	3		T176	2
auto[BaudRate256Kbps]	freqs[25]	245	1			T8	1		T118	3		T34	5
auto[BaudRate256Kbps]	freqs[48]	117	1			T253	2		T317	1		T319	1
auto[BaudRate256Kbps]	freqs[50]	83	1			T10	4		T254	1		T104	5
auto[BaudRate256Kbps]	freqs[100]	162	1			T31	2		T39	2		T121	1
auto[BaudRate1Mbps]	freqs[24]	237	1			T9	11		T16	3		T176	1
auto[BaudRate1Mbps]	freqs[25]	222	1			T8	1		T118	1		T37	1
auto[BaudRate1Mbps]	freqs[48]	99	1			T253	3		T319	1		T323	2
auto[BaudRate1Mbps]	freqs[50]	116	1			T10	4		T254	7		T59	1
auto[BaudRate1Mbps]	freqs[100]	146	1			T31	1		T39	1		T11	2
auto[BaudRate1p5Mbps]	freqs[25]	103	1			T118	1		T34	1		T37	1
auto[BaudRate1p5Mbps]	freqs[48]	110	1			T253	2		T317	1		T320	1
auto[BaudRate1p5Mbps]	freqs[50]	90	1			T10	8		T29	1		T254	2
auto[BaudRate1p5Mbps]	freqs[100]	170	1			T31	2		T39	1		T11	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded