Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	26406493	1			T1	276		T2	40677		T3	33
all_levels[1]	195791	1			T1	13		T2	4264		T3	3
all_levels[2]	2521	1			T1	1		T2	22		T7	8
all_levels[3]	1111	1			T2	1		T3	1		T7	4
all_levels[4]	754	1			T3	1		T5	1		T8	3
all_levels[5]	499	1			T2	1		T5	1		T7	3
all_levels[6]	450	1			T2	1		T5	1		T7	1
all_levels[7]	371	1			T2	2		T7	1		T8	1
all_levels[8]	321	1			T7	1		T31	1		T117	1
all_levels[9]	227	1			T2	1		T31	2		T118	1
all_levels[10]	227	1			T5	1		T31	1		T23	2
all_levels[11]	207	1			T7	1		T31	3		T11	1
all_levels[12]	185	1			T5	1		T32	1		T40	1
all_levels[13]	152	1			T31	6		T11	2		T119	1
all_levels[14]	154	1			T23	1		T25	1		T120	1
all_levels[15]	144	1			T2	1		T4	1		T5	1
all_levels[16]	106	1			T2	1		T121	1		T106	1
all_levels[17]	96	1			T2	1		T9	2		T122	1
all_levels[18]	117	1			T11	1		T23	2		T121	1
all_levels[19]	98	1			T2	1		T3	1		T7	1
all_levels[20]	93	1			T4	1		T11	2		T23	1
all_levels[21]	85	1			T4	1		T5	1		T122	1
all_levels[22]	79	1			T11	1		T23	1		T106	1
all_levels[23]	72	1			T7	1		T9	1		T11	2
all_levels[24]	55	1			T123	1		T124	1		T42	1
all_levels[25]	62	1			T2	1		T122	1		T25	2
all_levels[26]	55	1			T125	1		T126	1		T127	1
all_levels[27]	52	1			T2	1		T123	1		T128	1
all_levels[28]	48	1			T2	1		T122	1		T34	4
all_levels[29]	41	1			T31	1		T11	1		T129	2
all_levels[30]	35	1			T2	1		T106	1		T25	1
all_levels[31]	24	1			T5	1		T32	1		T130	1
all_levels[32]	34	1			T108	1		T131	1		T132	2
all_levels[33]	37	1			T31	1		T33	1		T133	1
all_levels[34]	29	1			T31	1		T134	1		T135	1
all_levels[35]	22	1			T123	1		T136	1		T137	1
all_levels[36]	20	1			T7	2		T133	1		T138	1
all_levels[37]	35	1			T23	1		T105	1		T126	2
all_levels[38]	34	1			T33	1		T23	1		T105	1
all_levels[39]	22	1			T2	1		T31	1		T37	1
all_levels[40]	19	1			T133	1		T139	1		T140	4
all_levels[41]	13	1			T31	1		T141	1		T142	1
all_levels[42]	18	1			T133	1		T108	1		T66	1
all_levels[43]	20	1			T123	1		T136	1		T143	1
all_levels[44]	19	1			T23	1		T144	1		T145	1
all_levels[45]	19	1			T2	1		T146	1		T147	1
all_levels[46]	9	1			T144	1		T148	1		T149	1
all_levels[47]	21	1			T2	1		T31	1		T150	1
all_levels[48]	19	1			T31	1		T36	1		T139	2
all_levels[49]	14	1			T2	1		T23	1		T151	1
all_levels[50]	14	1			T4	1		T23	1		T105	2
all_levels[51]	25	1			T2	1		T4	1		T152	1
all_levels[52]	12	1			T25	1		T146	1		T153	1
all_levels[53]	7	1			T154	3		T155	1		T156	1
all_levels[54]	9	1			T2	1		T147	1		T157	1
all_levels[55]	16	1			T9	1		T135	1		T158	1
all_levels[56]	5	1			T159	1		T160	1		T48	1
all_levels[57]	8	1			T161	1		T162	1		T163	1
all_levels[58]	7	1			T164	1		T165	1		T166	1
all_levels[59]	6	1			T27	1		T167	1		T168	1
all_levels[60]	8	1			T11	1		T169	2		T170	1
all_levels[61]	4	1			T147	1		T171	1		T141	1
all_levels[62]	3	1			T162	1		T172	1		T173	1
all_levels[63]	10	1			T42	3		T174	1		T175	1
all_levels[64]	103	1			T2	2		T11	2		T176	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606357

1

T1

290

T2

44955

T3

39

auto[1]

5009

1

T2

30

T7

7

T9

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58] , all_levels[59]]	[auto[1]]	--	--	2
[all_levels[61] , all_levels[62]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	26401953	1			T1	276		T2	40647		T3	33
all_levels[0]	auto[1]	4540	1			T2	30		T7	4		T9	4
all_levels[1]	auto[0]	195717	1			T1	13		T2	4264		T3	3
all_levels[1]	auto[1]	74	1			T7	1		T117	1		T11	1
all_levels[2]	auto[0]	2505	1			T1	1		T2	22		T7	8
all_levels[2]	auto[1]	16	1			T177	1		T178	2		T161	1
all_levels[3]	auto[0]	1088	1			T2	1		T3	1		T7	3
all_levels[3]	auto[1]	23	1			T7	1		T39	2		T117	1
all_levels[4]	auto[0]	729	1			T3	1		T5	1		T8	3
all_levels[4]	auto[1]	25	1			T39	1		T179	1		T180	1
all_levels[5]	auto[0]	482	1			T2	1		T5	1		T7	3
all_levels[5]	auto[1]	17	1			T108	1		T63	1		T181	1
all_levels[6]	auto[0]	430	1			T2	1		T5	1		T7	1
all_levels[6]	auto[1]	20	1			T31	1		T182	1		T132	1
all_levels[7]	auto[0]	346	1			T2	2		T7	1		T8	1
all_levels[7]	auto[1]	25	1			T124	2		T183	2		T184	2
all_levels[8]	auto[0]	308	1			T7	1		T31	1		T117	1
all_levels[8]	auto[1]	13	1			T144	1		T185	1		T186	1
all_levels[9]	auto[0]	223	1			T2	1		T31	2		T118	1
all_levels[9]	auto[1]	4	1			T63	1		T187	1		T188	1
all_levels[10]	auto[0]	212	1			T5	1		T31	1		T23	2
all_levels[10]	auto[1]	15	1			T100	4		T189	1		T190	1
all_levels[11]	auto[0]	184	1			T7	1		T31	2		T11	1
all_levels[11]	auto[1]	23	1			T31	1		T191	1		T26	1
all_levels[12]	auto[0]	168	1			T5	1		T32	1		T40	1
all_levels[12]	auto[1]	17	1			T11	1		T192	1		T193	1
all_levels[13]	auto[0]	146	1			T31	5		T11	2		T119	1
all_levels[13]	auto[1]	6	1			T31	1		T134	1		T194	1
all_levels[14]	auto[0]	145	1			T23	1		T25	1		T120	1
all_levels[14]	auto[1]	9	1			T144	1		T195	2		T196	1
all_levels[15]	auto[0]	131	1			T2	1		T4	1		T5	1
all_levels[15]	auto[1]	13	1			T167	1		T197	1		T198	1
all_levels[16]	auto[0]	98	1			T2	1		T121	1		T106	1
all_levels[16]	auto[1]	8	1			T178	1		T199	1		T200	1
all_levels[17]	auto[0]	90	1			T2	1		T9	2		T122	1
all_levels[17]	auto[1]	6	1			T128	1		T201	2		T202	1
all_levels[18]	auto[0]	108	1			T11	1		T23	2		T121	1
all_levels[18]	auto[1]	9	1			T144	1		T203	1		T204	1
all_levels[19]	auto[0]	86	1			T2	1		T3	1		T7	1
all_levels[19]	auto[1]	12	1			T32	4		T205	1		T206	2
all_levels[20]	auto[0]	84	1			T4	1		T11	2		T23	1
all_levels[20]	auto[1]	9	1			T207	1		T208	2		T190	3
all_levels[21]	auto[0]	81	1			T4	1		T5	1		T122	1
all_levels[21]	auto[1]	4	1			T59	2		T209	1		T210	1
all_levels[22]	auto[0]	71	1			T11	1		T23	1		T106	1
all_levels[22]	auto[1]	8	1			T139	1		T211	1		T212	1
all_levels[23]	auto[0]	64	1			T7	1		T9	1		T11	1
all_levels[23]	auto[1]	8	1			T11	1		T36	1		T213	3
all_levels[24]	auto[0]	54	1			T123	1		T124	1		T42	1
all_levels[24]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[25]	auto[0]	55	1			T2	1		T122	1		T25	2
all_levels[25]	auto[1]	7	1			T215	1		T216	1		T217	1
all_levels[26]	auto[0]	49	1			T125	1		T126	1		T127	1
all_levels[26]	auto[1]	6	1			T174	1		T218	1		T219	1
all_levels[27]	auto[0]	51	1			T2	1		T123	1		T128	1
all_levels[27]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[28]	auto[0]	45	1			T2	1		T122	1		T34	1
all_levels[28]	auto[1]	3	1			T34	3		-	-		-	-
all_levels[29]	auto[0]	36	1			T31	1		T11	1		T129	1
all_levels[29]	auto[1]	5	1			T129	1		T221	1		T199	2
all_levels[30]	auto[0]	31	1			T2	1		T106	1		T25	1
all_levels[30]	auto[1]	4	1			T222	1		T223	1		T224	1
all_levels[31]	auto[0]	21	1			T5	1		T32	1		T130	1
all_levels[31]	auto[1]	3	1			T141	2		T225	1		-	-
all_levels[32]	auto[0]	31	1			T108	1		T131	1		T132	1
all_levels[32]	auto[1]	3	1			T132	1		T226	1		T227	1
all_levels[33]	auto[0]	36	1			T31	1		T33	1		T133	1
all_levels[33]	auto[1]	1	1			T196	1		-	-		-	-
all_levels[34]	auto[0]	26	1			T31	1		T134	1		T135	1
all_levels[34]	auto[1]	3	1			T102	2		T228	1		-	-
all_levels[35]	auto[0]	21	1			T123	1		T136	1		T137	1
all_levels[35]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[36]	auto[0]	19	1			T7	1		T133	1		T138	1
all_levels[36]	auto[1]	1	1			T7	1		-	-		-	-
all_levels[37]	auto[0]	32	1			T23	1		T105	1		T126	2
all_levels[37]	auto[1]	3	1			T140	1		T230	1		T231	1
all_levels[38]	auto[0]	28	1			T33	1		T23	1		T105	1
all_levels[38]	auto[1]	6	1			T232	1		T67	1		T233	3
all_levels[39]	auto[0]	21	1			T2	1		T31	1		T37	1
all_levels[39]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[40]	auto[0]	16	1			T133	1		T139	1		T140	1
all_levels[40]	auto[1]	3	1			T140	3		-	-		-	-
all_levels[41]	auto[0]	13	1			T31	1		T141	1		T142	1
all_levels[42]	auto[0]	16	1			T133	1		T108	1		T66	1
all_levels[42]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[43]	auto[0]	19	1			T123	1		T136	1		T143	1
all_levels[43]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[44]	auto[0]	17	1			T23	1		T144	1		T145	1
all_levels[44]	auto[1]	2	1			T237	1		T238	1		-	-
all_levels[45]	auto[0]	17	1			T2	1		T146	1		T147	1
all_levels[45]	auto[1]	2	1			T239	1		T240	1		-	-
all_levels[46]	auto[0]	9	1			T144	1		T148	1		T149	1
all_levels[47]	auto[0]	18	1			T2	1		T31	1		T150	1
all_levels[47]	auto[1]	3	1			T241	2		T242	1		-	-
all_levels[48]	auto[0]	15	1			T31	1		T36	1		T139	1
all_levels[48]	auto[1]	4	1			T139	1		T152	1		T136	2
all_levels[49]	auto[0]	13	1			T2	1		T23	1		T151	1
all_levels[49]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[50]	auto[0]	14	1			T4	1		T23	1		T105	2
all_levels[51]	auto[0]	18	1			T2	1		T4	1		T152	1
all_levels[51]	auto[1]	7	1			T244	1		T245	2		T246	3
all_levels[52]	auto[0]	11	1			T25	1		T146	1		T153	1
all_levels[52]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[53]	auto[0]	5	1			T154	1		T155	1		T156	1
all_levels[53]	auto[1]	2	1			T154	2		-	-		-	-
all_levels[54]	auto[0]	9	1			T2	1		T147	1		T157	1
all_levels[55]	auto[0]	13	1			T9	1		T135	1		T158	1
all_levels[55]	auto[1]	3	1			T248	1		T249	1		T250	1
all_levels[56]	auto[0]	5	1			T159	1		T160	1		T48	1
all_levels[57]	auto[0]	7	1			T161	1		T162	1		T163	1
all_levels[57]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[58]	auto[0]	7	1			T164	1		T165	1		T166	1
all_levels[59]	auto[0]	6	1			T27	1		T167	1		T168	1
all_levels[60]	auto[0]	7	1			T11	1		T169	1		T170	1
all_levels[60]	auto[1]	1	1			T169	1		-	-		-	-
all_levels[61]	auto[0]	4	1			T147	1		T171	1		T141	1
all_levels[62]	auto[0]	3	1			T162	1		T172	1		T173	1
all_levels[63]	auto[0]	7	1			T42	2		T174	1		T175	1
all_levels[63]	auto[1]	3	1			T42	1		T251	2		-	-
all_levels[64]	auto[0]	83	1			T2	2		T11	1		T176	1
all_levels[64]	auto[1]	20	1			T11	1		T152	2		T252	1