Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98738	1			T1	18		T2	232		T3	11
all_pins[1]	98738	1			T1	18		T2	232		T3	11
all_pins[2]	98738	1			T1	18		T2	232		T3	11
all_pins[3]	98738	1			T1	18		T2	232		T3	11
all_pins[4]	98738	1			T1	18		T2	232		T3	11
all_pins[5]	98738	1			T1	18		T2	232		T3	11
all_pins[6]	98738	1			T1	18		T2	232		T3	11
all_pins[7]	98738	1			T1	18		T2	232		T3	11
all_pins[8]	98738	1			T1	18		T2	232		T3	11

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	844422	1			T1	148		T2	1914		T3	92
values[0x1]	44220	1			T1	14		T2	174		T3	7
transitions[0x0=>0x1]	34896	1			T1	11		T2	144		T3	5
transitions[0x1=>0x0]	34698	1			T1	10		T2	143		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	77576	1			T1	12		T2	141		T3	9
all_pins[0]	values[0x1]	21162	1			T1	6		T2	91		T3	2
all_pins[0]	transitions[0x0=>0x1]	20448	1			T1	6		T2	89		T3	2
all_pins[0]	transitions[0x1=>0x0]	1191	1			T2	3		T3	2		T7	1
all_pins[1]	values[0x0]	96833	1			T1	18		T2	227		T3	9
all_pins[1]	values[0x1]	1905	1			T2	5		T3	2		T5	2
all_pins[1]	transitions[0x0=>0x1]	1774	1			T2	5		T5	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	2388	1			T1	3		T2	14		T3	1
all_pins[2]	values[0x0]	96219	1			T1	15		T2	218		T3	8
all_pins[2]	values[0x1]	2519	1			T1	3		T2	14		T3	3
all_pins[2]	transitions[0x0=>0x1]	2474	1			T1	3		T2	14		T3	3
all_pins[2]	transitions[0x1=>0x0]	237	1			T2	1		T10	1		T25	4
all_pins[3]	values[0x0]	98456	1			T1	18		T2	231		T3	11
all_pins[3]	values[0x1]	282	1			T2	1		T10	1		T12	1
all_pins[3]	transitions[0x0=>0x1]	235	1			T2	1		T11	1		T25	5
all_pins[3]	transitions[0x1=>0x0]	531	1			T2	12		T10	2		T12	5
all_pins[4]	values[0x0]	98160	1			T1	18		T2	220		T3	11
all_pins[4]	values[0x1]	578	1			T2	12		T10	3		T12	6
all_pins[4]	transitions[0x0=>0x1]	467	1			T2	12		T10	3		T12	3
all_pins[4]	transitions[0x1=>0x0]	150	1			T25	2		T13	1		T112	2
all_pins[5]	values[0x0]	98477	1			T1	18		T2	232		T3	11
all_pins[5]	values[0x1]	261	1			T12	3		T25	4		T13	4
all_pins[5]	transitions[0x0=>0x1]	225	1			T12	1		T25	4		T13	4
all_pins[5]	transitions[0x1=>0x0]	749	1			T2	3		T4	1		T118	6
all_pins[6]	values[0x0]	97953	1			T1	18		T2	229		T3	11
all_pins[6]	values[0x1]	785	1			T2	3		T4	1		T12	2
all_pins[6]	transitions[0x0=>0x1]	742	1			T2	3		T4	1		T118	6
all_pins[6]	transitions[0x1=>0x0]	332	1			T2	4		T10	2		T12	1
all_pins[7]	values[0x0]	98363	1			T1	18		T2	228		T3	11
all_pins[7]	values[0x1]	375	1			T2	4		T10	2		T12	3
all_pins[7]	transitions[0x0=>0x1]	248	1			T2	4		T10	1		T13	10
all_pins[7]	transitions[0x1=>0x0]	16226	1			T1	5		T2	44		T6	2
all_pins[8]	values[0x0]	82385	1			T1	13		T2	188		T3	11
all_pins[8]	values[0x1]	16353	1			T1	5		T2	44		T6	2
all_pins[8]	transitions[0x0=>0x1]	8283	1			T1	2		T2	16		T6	1
all_pins[8]	transitions[0x1=>0x0]	12894	1			T1	2		T2	62		T3	1