Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6084070	1			T1	112		T2	10764		T3	12
all_levels[1]	1901863	1			T1	5		T2	270		T3	6
all_levels[2]	286031	1			T1	8		T2	214		T5	8
all_levels[3]	199072	1			T1	6		T2	215		T4	1
all_levels[4]	303744	1			T1	7		T2	220		T4	4
all_levels[5]	211348	1			T1	3		T2	217		T5	6
all_levels[6]	205019	1			T1	5		T2	195		T4	9
all_levels[7]	412192	1			T1	4		T2	142		T4	2
all_levels[8]	363907	1			T2	141		T5	5		T6	24
all_levels[9]	165684	1			T1	1		T2	139		T5	5
all_levels[10]	289154	1			T2	120		T4	1		T5	8
all_levels[11]	150723	1			T2	344		T5	4		T6	24
all_levels[12]	151676	1			T1	3		T2	115		T6	26
all_levels[13]	257881	1			T1	3		T2	105		T4	1
all_levels[14]	320416	1			T1	123		T2	105		T5	6
all_levels[15]	187367	1			T1	2		T2	96		T4	2
all_levels[16]	204480	1			T2	108		T5	4		T6	23
all_levels[17]	129648	1			T2	125		T5	12		T6	28
all_levels[18]	200612	1			T2	118		T5	2		T6	28
all_levels[19]	171503	1			T1	9		T2	166		T4	3
all_levels[20]	292310	1			T2	169		T3	1		T5	10
all_levels[21]	169306	1			T2	137		T4	1		T5	3
all_levels[22]	131629	1			T2	147		T4	1		T5	6
all_levels[23]	226208	1			T2	149		T4	3		T5	1
all_levels[24]	147927	1			T2	145		T3	1		T5	6
all_levels[25]	143673	1			T2	148		T5	4		T6	34
all_levels[26]	294121	1			T2	202		T5	5		T6	26
all_levels[27]	120749	1			T2	160		T3	1		T4	1
all_levels[28]	139108	1			T2	150		T6	24		T9	8
all_levels[29]	263920	1			T2	155		T3	4		T5	1
all_levels[30]	304564	1			T2	168		T3	1		T5	4
all_levels[31]	701299	1			T2	1722		T3	4		T5	2
all_levels[32]	11479565	1			T2	27615		T3	9		T6	28094

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606357

1

T1

290

T2

44955

T3

39

auto[1]

4412

1

T1

1

T2

31

T4

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6081519	1			T1	112		T2	10763		T3	12
all_levels[0]	auto[1]	2551	1			T2	1		T7	5		T10	5
all_levels[1]	auto[0]	1901539	1			T1	5		T2	270		T3	6
all_levels[1]	auto[1]	324	1			T4	1		T29	4		T122	4
all_levels[2]	auto[0]	285989	1			T1	8		T2	214		T5	8
all_levels[2]	auto[1]	42	1			T34	3		T95	1		T298	1
all_levels[3]	auto[0]	198939	1			T1	6		T2	215		T4	1
all_levels[3]	auto[1]	133	1			T31	1		T13	1		T63	2
all_levels[4]	auto[0]	303728	1			T1	7		T2	220		T4	4
all_levels[4]	auto[1]	16	1			T97	1		T144	1		T325	1
all_levels[5]	auto[0]	211329	1			T1	3		T2	217		T5	6
all_levels[5]	auto[1]	19	1			T11	1		T27	1		T42	1
all_levels[6]	auto[0]	204987	1			T1	5		T2	195		T4	9
all_levels[6]	auto[1]	32	1			T191	1		T36	1		T274	3
all_levels[7]	auto[0]	412087	1			T1	4		T2	142		T4	2
all_levels[7]	auto[1]	105	1			T191	1		T13	6		T311	5
all_levels[8]	auto[0]	363881	1			T2	141		T5	5		T6	24
all_levels[8]	auto[1]	26	1			T259	1		T42	1		T326	1
all_levels[9]	auto[0]	165664	1			T1	1		T2	139		T5	5
all_levels[9]	auto[1]	20	1			T285	1		T327	1		T193	1
all_levels[10]	auto[0]	289113	1			T2	120		T4	1		T5	8
all_levels[10]	auto[1]	41	1			T125	2		T34	3		T95	3
all_levels[11]	auto[0]	150699	1			T2	343		T5	4		T6	24
all_levels[11]	auto[1]	24	1			T2	1		T7	1		T274	2
all_levels[12]	auto[0]	151664	1			T1	3		T2	115		T6	26
all_levels[12]	auto[1]	12	1			T64	1		T328	1		T329	1
all_levels[13]	auto[0]	257853	1			T1	3		T2	105		T4	1
all_levels[13]	auto[1]	28	1			T40	2		T25	1		T150	2
all_levels[14]	auto[0]	320398	1			T1	123		T2	105		T5	6
all_levels[14]	auto[1]	18	1			T37	1		T205	1		T111	1
all_levels[15]	auto[0]	187247	1			T1	2		T2	96		T4	2
all_levels[15]	auto[1]	120	1			T33	1		T26	1		T27	1
all_levels[16]	auto[0]	204453	1			T2	108		T5	4		T6	23
all_levels[16]	auto[1]	27	1			T259	2		T281	1		T325	1
all_levels[17]	auto[0]	129617	1			T2	125		T5	12		T6	28
all_levels[17]	auto[1]	31	1			T117	1		T33	1		T310	1
all_levels[18]	auto[0]	200587	1			T2	118		T5	2		T6	28
all_levels[18]	auto[1]	25	1			T31	1		T125	4		T260	1
all_levels[19]	auto[0]	171474	1			T1	8		T2	166		T4	3
all_levels[19]	auto[1]	29	1			T1	1		T11	1		T138	1
all_levels[20]	auto[0]	292279	1			T2	169		T3	1		T5	9
all_levels[20]	auto[1]	31	1			T5	1		T7	2		T120	2
all_levels[21]	auto[0]	169279	1			T2	137		T4	1		T5	3
all_levels[21]	auto[1]	27	1			T31	2		T122	2		T178	2
all_levels[22]	auto[0]	131610	1			T2	147		T4	1		T5	6
all_levels[22]	auto[1]	19	1			T35	1		T95	2		T178	2
all_levels[23]	auto[0]	226192	1			T2	149		T4	3		T5	1
all_levels[23]	auto[1]	16	1			T29	2		T26	1		T330	1
all_levels[24]	auto[0]	147899	1			T2	145		T3	1		T5	6
all_levels[24]	auto[1]	28	1			T106	2		T185	1		T331	1
all_levels[25]	auto[0]	143663	1			T2	148		T5	4		T6	34
all_levels[25]	auto[1]	10	1			T140	2		T328	1		T141	1
all_levels[26]	auto[0]	294098	1			T2	202		T5	5		T6	26
all_levels[26]	auto[1]	23	1			T129	1		T120	2		T319	1
all_levels[27]	auto[0]	120736	1			T2	160		T3	1		T4	1
all_levels[27]	auto[1]	13	1			T130	1		T42	1		T332	1
all_levels[28]	auto[0]	139091	1			T2	150		T6	24		T9	8
all_levels[28]	auto[1]	17	1			T333	2		T334	1		T141	1
all_levels[29]	auto[0]	263903	1			T2	155		T3	4		T5	1
all_levels[29]	auto[1]	17	1			T132	1		T134	1		T181	1
all_levels[30]	auto[0]	304547	1			T2	168		T3	1		T5	4
all_levels[30]	auto[1]	17	1			T182	2		T102	1		T180	1
all_levels[31]	auto[0]	701284	1			T2	1722		T3	4		T5	2
all_levels[31]	auto[1]	15	1			T107	1		T59	1		T335	1
all_levels[32]	auto[0]	11479009	1			T2	27586		T3	9		T6	28093
all_levels[32]	auto[1]	556	1			T2	29		T6	1		T7	1