Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	746	1			T10	4		T12	7		T24	7
all_values[1]	746	1			T10	4		T12	7		T24	7
all_values[2]	746	1			T10	4		T12	7		T24	7
all_values[3]	746	1			T10	4		T12	7		T24	7
all_values[4]	746	1			T10	4		T12	7		T24	7
all_values[5]	746	1			T10	4		T12	7		T24	7
all_values[6]	746	1			T10	4		T12	7		T24	7
all_values[7]	746	1			T10	4		T12	7		T24	7
all_values[8]	746	1			T10	4		T12	7		T24	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3665

1

T10

20

T12

29

T24

38

auto[1]

3049

1

T10

16

T12

34

T24

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2216

1

T10

14

T12

16

T24

25

auto[1]

4498

1

T10

22

T12

47

T24

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3936

1

T10

26

T12

33

T24

37

auto[1]

2778

1

T10

10

T12

30

T24

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	212	1			T10	3		T12	2		T24	2
all_values[0]	auto[0]	auto[1]	auto[1]	208	1			T24	1		T25	2		T112	2
all_values[0]	auto[1]	auto[0]	auto[1]	175	1			T10	1		T12	2		T24	4
all_values[0]	auto[1]	auto[1]	auto[1]	151	1			T12	3		T25	1		T104	1
all_values[1]	auto[0]	auto[0]	auto[0]	237	1			T10	2		T25	5		T104	1
all_values[1]	auto[0]	auto[1]	auto[0]	209	1			T12	4		T24	2		T25	2
all_values[1]	auto[1]	auto[0]	auto[1]	163	1			T10	2		T12	2		T24	1
all_values[1]	auto[1]	auto[1]	auto[1]	137	1			T12	1		T24	4		T25	3
all_values[2]	auto[0]	auto[0]	auto[0]	148	1			T12	1		T24	3		T25	6
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T10	1		T101	1		T113	3
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T10	2		T12	2		T25	1
all_values[2]	auto[0]	auto[1]	auto[1]	59	1			T12	1		T24	1		T101	1
all_values[2]	auto[1]	auto[0]	auto[1]	167	1			T24	2		T25	2		T112	2
all_values[2]	auto[1]	auto[1]	auto[1]	156	1			T10	1		T12	3		T24	1
all_values[3]	auto[0]	auto[0]	auto[0]	159	1			T10	1		T12	1		T24	1
all_values[3]	auto[0]	auto[0]	auto[1]	68	1			T10	1		T12	1		T24	1
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T12	1		T24	2		T104	1
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T25	2		T104	1		T101	1
all_values[3]	auto[1]	auto[0]	auto[1]	184	1			T10	1		T12	2		T25	3
all_values[3]	auto[1]	auto[1]	auto[1]	129	1			T10	1		T12	2		T24	3
all_values[4]	auto[0]	auto[0]	auto[0]	172	1			T12	1		T24	2		T25	2
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T25	2		T112	1		T102	2
all_values[4]	auto[0]	auto[1]	auto[0]	114	1			T10	1		T24	3		T25	2
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T10	2		T12	3		T24	1
all_values[4]	auto[1]	auto[0]	auto[1]	170	1			T25	3		T112	1		T104	1
all_values[4]	auto[1]	auto[1]	auto[1]	132	1			T10	1		T12	3		T24	1
all_values[5]	auto[0]	auto[0]	auto[0]	150	1			T10	2		T24	2		T25	2
all_values[5]	auto[0]	auto[0]	auto[1]	79	1			T12	2		T24	1		T25	1
all_values[5]	auto[0]	auto[1]	auto[0]	124	1			T10	1		T24	1		T25	1
all_values[5]	auto[0]	auto[1]	auto[1]	78	1			T12	1		T25	2		T112	1
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T10	1		T12	2		T24	3
all_values[5]	auto[1]	auto[1]	auto[1]	140	1			T12	2		T25	1		T104	3
all_values[6]	auto[0]	auto[0]	auto[0]	179	1			T10	2		T12	2		T24	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T25	2		T104	1		T42	1
all_values[6]	auto[0]	auto[1]	auto[0]	138	1			T10	2		T12	1		T24	1
all_values[6]	auto[0]	auto[1]	auto[1]	55	1			T12	1		T25	1		T104	1
all_values[6]	auto[1]	auto[0]	auto[1]	173	1			T12	1		T24	5		T25	4
all_values[6]	auto[1]	auto[1]	auto[1]	123	1			T12	2		T25	2		T104	4
all_values[7]	auto[0]	auto[0]	auto[0]	184	1			T12	3		T24	5		T25	2
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T25	1		T112	1		T42	1
all_values[7]	auto[0]	auto[1]	auto[0]	123	1			T10	1		T24	2		T25	4
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T10	1		T12	1		T25	1
all_values[7]	auto[1]	auto[0]	auto[1]	156	1			T12	2		T25	1		T42	2
all_values[7]	auto[1]	auto[1]	auto[1]	134	1			T10	2		T12	1		T25	2
all_values[8]	auto[0]	auto[0]	auto[1]	239	1			T10	3		T12	4		T24	4
all_values[8]	auto[0]	auto[1]	auto[1]	194	1			T10	1		T12	1		T24	1
all_values[8]	auto[1]	auto[0]	auto[1]	183	1			T12	1		T24	1		T25	2
all_values[8]	auto[1]	auto[1]	auto[1]	130	1			T12	1		T24	1		T25	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal