Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1318
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T1259 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.282730549 Jul 11 04:21:12 PM PDT 24 Jul 11 04:21:14 PM PDT 24 35254628 ps
T1260 /workspace/coverage/cover_reg_top/20.uart_intr_test.1408810721 Jul 11 04:26:47 PM PDT 24 Jul 11 04:26:51 PM PDT 24 17751000 ps
T1261 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3493474305 Jul 11 04:26:57 PM PDT 24 Jul 11 04:27:01 PM PDT 24 105135688 ps
T1262 /workspace/coverage/cover_reg_top/15.uart_tl_errors.128955458 Jul 11 04:26:31 PM PDT 24 Jul 11 04:26:35 PM PDT 24 46485080 ps
T1263 /workspace/coverage/cover_reg_top/33.uart_intr_test.1380685643 Jul 11 04:26:53 PM PDT 24 Jul 11 04:26:55 PM PDT 24 13727585 ps
T56 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3987232842 Jul 11 04:26:08 PM PDT 24 Jul 11 04:26:13 PM PDT 24 34329802 ps
T1264 /workspace/coverage/cover_reg_top/27.uart_intr_test.3059061171 Jul 11 04:25:06 PM PDT 24 Jul 11 04:25:08 PM PDT 24 31587216 ps
T1265 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.128831999 Jul 11 04:24:32 PM PDT 24 Jul 11 04:24:34 PM PDT 24 21944230 ps
T1266 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3684142821 Jul 11 04:26:55 PM PDT 24 Jul 11 04:26:57 PM PDT 24 41853066 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.343407453 Jul 11 04:24:55 PM PDT 24 Jul 11 04:24:58 PM PDT 24 18983516 ps
T57 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3521825058 Jul 11 04:26:10 PM PDT 24 Jul 11 04:26:14 PM PDT 24 15565929 ps
T1268 /workspace/coverage/cover_reg_top/48.uart_intr_test.3897376451 Jul 11 04:26:34 PM PDT 24 Jul 11 04:26:38 PM PDT 24 13160319 ps
T1269 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1940439639 Jul 11 04:26:29 PM PDT 24 Jul 11 04:26:32 PM PDT 24 252859432 ps
T1270 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2407735548 Jul 11 04:22:24 PM PDT 24 Jul 11 04:22:25 PM PDT 24 106525630 ps
T1271 /workspace/coverage/cover_reg_top/41.uart_intr_test.815684540 Jul 11 04:26:35 PM PDT 24 Jul 11 04:26:38 PM PDT 24 11233301 ps
T1272 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.653451444 Jul 11 04:26:07 PM PDT 24 Jul 11 04:26:11 PM PDT 24 19666641 ps
T116 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2601451172 Jul 11 04:26:06 PM PDT 24 Jul 11 04:26:12 PM PDT 24 147703270 ps
T1273 /workspace/coverage/cover_reg_top/18.uart_tl_errors.544547388 Jul 11 04:24:56 PM PDT 24 Jul 11 04:24:58 PM PDT 24 188470510 ps
T84 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.750104250 Jul 11 04:26:58 PM PDT 24 Jul 11 04:27:01 PM PDT 24 291381907 ps
T1274 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1915038787 Jul 11 04:26:23 PM PDT 24 Jul 11 04:26:27 PM PDT 24 958671395 ps
T1275 /workspace/coverage/cover_reg_top/46.uart_intr_test.1612719176 Jul 11 04:26:34 PM PDT 24 Jul 11 04:26:38 PM PDT 24 14002461 ps
T1276 /workspace/coverage/cover_reg_top/12.uart_csr_rw.199327240 Jul 11 04:26:32 PM PDT 24 Jul 11 04:26:35 PM PDT 24 50555496 ps
T85 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3248622252 Jul 11 04:25:30 PM PDT 24 Jul 11 04:25:34 PM PDT 24 331224850 ps
T1277 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4201766553 Jul 11 04:26:48 PM PDT 24 Jul 11 04:26:53 PM PDT 24 52771268 ps
T1278 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2054899123 Jul 11 04:25:47 PM PDT 24 Jul 11 04:25:49 PM PDT 24 25090047 ps
T1279 /workspace/coverage/cover_reg_top/7.uart_tl_errors.177021426 Jul 11 04:23:55 PM PDT 24 Jul 11 04:23:58 PM PDT 24 865507311 ps
T1280 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1855753458 Jul 11 04:27:24 PM PDT 24 Jul 11 04:27:27 PM PDT 24 86942698 ps
T1281 /workspace/coverage/cover_reg_top/14.uart_intr_test.3094640972 Jul 11 04:26:32 PM PDT 24 Jul 11 04:26:34 PM PDT 24 26003422 ps
T1282 /workspace/coverage/cover_reg_top/5.uart_intr_test.4170144946 Jul 11 04:26:43 PM PDT 24 Jul 11 04:26:47 PM PDT 24 12429199 ps
T1283 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2097903221 Jul 11 04:24:07 PM PDT 24 Jul 11 04:24:09 PM PDT 24 41100646 ps
T1284 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4212347001 Jul 11 04:24:23 PM PDT 24 Jul 11 04:24:25 PM PDT 24 19037062 ps
T89 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1154014334 Jul 11 04:26:48 PM PDT 24 Jul 11 04:26:53 PM PDT 24 595467151 ps
T1285 /workspace/coverage/cover_reg_top/44.uart_intr_test.1690665614 Jul 11 04:26:35 PM PDT 24 Jul 11 04:26:38 PM PDT 24 17743278 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2708507066 Jul 11 04:20:22 PM PDT 24 Jul 11 04:20:23 PM PDT 24 32226604 ps
T1287 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1280319384 Jul 11 04:26:48 PM PDT 24 Jul 11 04:26:54 PM PDT 24 131656978 ps
T1288 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1684346704 Jul 11 04:25:05 PM PDT 24 Jul 11 04:25:08 PM PDT 24 229244012 ps
T1289 /workspace/coverage/cover_reg_top/28.uart_intr_test.1560419593 Jul 11 04:25:29 PM PDT 24 Jul 11 04:25:32 PM PDT 24 22044199 ps
T1290 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2830265136 Jul 11 04:26:31 PM PDT 24 Jul 11 04:26:34 PM PDT 24 91642695 ps
T1291 /workspace/coverage/cover_reg_top/47.uart_intr_test.687756723 Jul 11 04:25:20 PM PDT 24 Jul 11 04:25:22 PM PDT 24 47390531 ps
T1292 /workspace/coverage/cover_reg_top/4.uart_intr_test.1220931103 Jul 11 04:23:51 PM PDT 24 Jul 11 04:23:52 PM PDT 24 16761456 ps
T1293 /workspace/coverage/cover_reg_top/23.uart_intr_test.3110711818 Jul 11 04:25:06 PM PDT 24 Jul 11 04:25:08 PM PDT 24 16606127 ps
T1294 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2822430892 Jul 11 04:26:33 PM PDT 24 Jul 11 04:26:38 PM PDT 24 535702403 ps
T1295 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1993424181 Jul 11 04:23:55 PM PDT 24 Jul 11 04:23:56 PM PDT 24 41934761 ps
T115 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2762873295 Jul 11 04:26:43 PM PDT 24 Jul 11 04:26:48 PM PDT 24 178339599 ps
T1296 /workspace/coverage/cover_reg_top/36.uart_intr_test.4130797837 Jul 11 04:26:50 PM PDT 24 Jul 11 04:26:54 PM PDT 24 15618618 ps
T1297 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.31534715 Jul 11 04:26:32 PM PDT 24 Jul 11 04:26:35 PM PDT 24 57111743 ps
T1298 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2404642780 Jul 11 04:25:51 PM PDT 24 Jul 11 04:25:52 PM PDT 24 40719641 ps
T1299 /workspace/coverage/cover_reg_top/4.uart_csr_rw.921766155 Jul 11 04:26:58 PM PDT 24 Jul 11 04:27:00 PM PDT 24 40528031 ps
T1300 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3726390274 Jul 11 04:26:23 PM PDT 24 Jul 11 04:26:26 PM PDT 24 57333454 ps
T1301 /workspace/coverage/cover_reg_top/14.uart_csr_rw.304137425 Jul 11 04:27:10 PM PDT 24 Jul 11 04:27:13 PM PDT 24 15404200 ps
T1302 /workspace/coverage/cover_reg_top/25.uart_intr_test.371104641 Jul 11 04:25:29 PM PDT 24 Jul 11 04:25:32 PM PDT 24 50762465 ps
T1303 /workspace/coverage/cover_reg_top/39.uart_intr_test.3174627685 Jul 11 04:26:37 PM PDT 24 Jul 11 04:26:41 PM PDT 24 14915084 ps
T1304 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3054085811 Jul 11 04:26:43 PM PDT 24 Jul 11 04:26:49 PM PDT 24 146250042 ps
T1305 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.451493314 Jul 11 04:26:47 PM PDT 24 Jul 11 04:26:52 PM PDT 24 97538111 ps
T1306 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4083322749 Jul 11 04:26:48 PM PDT 24 Jul 11 04:26:52 PM PDT 24 22933630 ps
T1307 /workspace/coverage/cover_reg_top/17.uart_intr_test.134798619 Jul 11 04:24:56 PM PDT 24 Jul 11 04:24:58 PM PDT 24 73352797 ps
T1308 /workspace/coverage/cover_reg_top/32.uart_intr_test.598515040 Jul 11 04:25:29 PM PDT 24 Jul 11 04:25:32 PM PDT 24 13604972 ps
T1309 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3411257370 Jul 11 04:26:57 PM PDT 24 Jul 11 04:27:00 PM PDT 24 10427631 ps
T58 /workspace/coverage/cover_reg_top/18.uart_csr_rw.2190092152 Jul 11 04:26:43 PM PDT 24 Jul 11 04:26:48 PM PDT 24 15589733 ps
T1310 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3966748871 Jul 11 04:24:12 PM PDT 24 Jul 11 04:24:14 PM PDT 24 46293263 ps
T1311 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1324779377 Jul 11 04:26:29 PM PDT 24 Jul 11 04:26:31 PM PDT 24 80658214 ps
T1312 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1099217149 Jul 11 04:26:43 PM PDT 24 Jul 11 04:26:48 PM PDT 24 24601833 ps
T1313 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.993143807 Jul 11 04:26:48 PM PDT 24 Jul 11 04:26:52 PM PDT 24 253985184 ps
T1314 /workspace/coverage/cover_reg_top/0.uart_intr_test.745568448 Jul 11 04:20:24 PM PDT 24 Jul 11 04:20:27 PM PDT 24 22031892 ps
T1315 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.341129013 Jul 11 04:26:56 PM PDT 24 Jul 11 04:26:58 PM PDT 24 45644157 ps
T1316 /workspace/coverage/cover_reg_top/15.uart_intr_test.436771581 Jul 11 04:26:27 PM PDT 24 Jul 11 04:26:29 PM PDT 24 38049789 ps
T1317 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2194999120 Jul 11 04:23:55 PM PDT 24 Jul 11 04:23:56 PM PDT 24 56545908 ps
T1318 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3508360656 Jul 11 04:25:30 PM PDT 24 Jul 11 04:25:33 PM PDT 24 16477702 ps

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.491675555
Short name T2
Test name
Test status
Simulation time 1778635798614 ps
CPU time 1231.32 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 05:10:42 PM PDT 24
Peak memory 216316 kb
Host smart-0923e35f-6201-4fae-8424-6a19572f00d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491675555 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.491675555
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1373745685
Short name T42
Test name
Test status
Simulation time 659428680813 ps
CPU time 1896.51 seconds
Started Jul 11 04:50:12 PM PDT 24
Finished Jul 11 05:21:53 PM PDT 24
Peak memory 232704 kb
Host smart-fd55aeb5-940d-4030-82be-b9506d95b786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373745685 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1373745685
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.125448120
Short name T23
Test name
Test status
Simulation time 176433569539 ps
CPU time 322.73 seconds
Started Jul 11 04:47:57 PM PDT 24
Finished Jul 11 04:53:26 PM PDT 24
Peak memory 211888 kb
Host smart-6c51630a-3ee1-4b57-bd5e-0e358dfdcccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125448120 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.125448120
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3552891872
Short name T254
Test name
Test status
Simulation time 59132432404 ps
CPU time 268.41 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:53:00 PM PDT 24
Peak memory 199864 kb
Host smart-d870c68c-4895-4efc-ba0b-a90d2da7a073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552891872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3552891872
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3837690122
Short name T26
Test name
Test status
Simulation time 172979729035 ps
CPU time 1648.8 seconds
Started Jul 11 04:50:28 PM PDT 24
Finished Jul 11 05:17:58 PM PDT 24
Peak memory 231680 kb
Host smart-6ce4cc05-5fe1-42f6-ae4f-da4b58688d88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837690122 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3837690122
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2686518383
Short name T25
Test name
Test status
Simulation time 683391396003 ps
CPU time 453.91 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 224772 kb
Host smart-012c9913-4c41-494c-8714-bb214fe58432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686518383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2686518383
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2174242571
Short name T20
Test name
Test status
Simulation time 168203114 ps
CPU time 0.87 seconds
Started Jul 11 04:47:50 PM PDT 24
Finished Jul 11 04:47:58 PM PDT 24
Peak memory 218096 kb
Host smart-92584823-188d-4f69-b61d-1ad5cf71f744
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174242571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2174242571
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/10.uart_stress_all.4129963706
Short name T65
Test name
Test status
Simulation time 184098510800 ps
CPU time 929.31 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 05:03:44 PM PDT 24
Peak memory 199868 kb
Host smart-15085e45-44cd-4309-ae03-ceeeafcdbfdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129963706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4129963706
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1124568261
Short name T36
Test name
Test status
Simulation time 98712212389 ps
CPU time 31.1 seconds
Started Jul 11 04:48:15 PM PDT 24
Finished Jul 11 04:48:50 PM PDT 24
Peak memory 199832 kb
Host smart-6afbf56b-b976-45d4-92b7-b5401372de1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124568261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1124568261
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3107814945
Short name T256
Test name
Test status
Simulation time 61913113884 ps
CPU time 147.11 seconds
Started Jul 11 04:48:39 PM PDT 24
Finished Jul 11 04:51:14 PM PDT 24
Peak memory 199896 kb
Host smart-945a309f-5dc7-4a27-966a-1fed1d2bd1b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107814945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3107814945
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2127783495
Short name T123
Test name
Test status
Simulation time 318321511598 ps
CPU time 118.75 seconds
Started Jul 11 04:48:32 PM PDT 24
Finished Jul 11 04:50:40 PM PDT 24
Peak memory 199784 kb
Host smart-b42e397e-9c4c-4762-9bbf-85f3689669d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127783495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2127783495
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.4181991512
Short name T141
Test name
Test status
Simulation time 938689097076 ps
CPU time 1601.67 seconds
Started Jul 11 04:50:06 PM PDT 24
Finished Jul 11 05:16:49 PM PDT 24
Peak memory 232956 kb
Host smart-9afdd645-6fc3-4840-9632-9b59c8273178
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181991512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.4181991512
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3148434627
Short name T105
Test name
Test status
Simulation time 114916751345 ps
CPU time 170.24 seconds
Started Jul 11 04:49:02 PM PDT 24
Finished Jul 11 04:52:00 PM PDT 24
Peak memory 199800 kb
Host smart-bc0b83a5-16df-4730-9665-e0474808d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148434627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3148434627
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.891997169
Short name T102
Test name
Test status
Simulation time 135085300220 ps
CPU time 449.34 seconds
Started Jul 11 04:50:06 PM PDT 24
Finished Jul 11 04:57:37 PM PDT 24
Peak memory 216312 kb
Host smart-6ffe7e41-9f96-4244-b032-7eee2682aa09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891997169 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.891997169
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2267028401
Short name T83
Test name
Test status
Simulation time 292695429 ps
CPU time 1.37 seconds
Started Jul 11 04:26:04 PM PDT 24
Finished Jul 11 04:26:08 PM PDT 24
Peak memory 199056 kb
Host smart-1b61db63-b963-4d81-9f21-faaff6316827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267028401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2267028401
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/45.uart_stress_all.2458803165
Short name T104
Test name
Test status
Simulation time 270538337879 ps
CPU time 292.56 seconds
Started Jul 11 04:49:50 PM PDT 24
Finished Jul 11 04:54:46 PM PDT 24
Peak memory 210348 kb
Host smart-fa30ac36-4939-4916-84d1-dc5b2e17ca04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458803165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2458803165
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2377987649
Short name T132
Test name
Test status
Simulation time 296123801790 ps
CPU time 81.36 seconds
Started Jul 11 04:50:41 PM PDT 24
Finished Jul 11 04:52:06 PM PDT 24
Peak memory 199880 kb
Host smart-391383da-79a2-4fba-880e-b2700aa60154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377987649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2377987649
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3495050358
Short name T18
Test name
Test status
Simulation time 56516666 ps
CPU time 0.53 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:48:30 PM PDT 24
Peak memory 195188 kb
Host smart-2e8b1f62-a3d5-486b-8639-a132642c39b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495050358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3495050358
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3238616208
Short name T50
Test name
Test status
Simulation time 22652380 ps
CPU time 0.59 seconds
Started Jul 11 04:26:07 PM PDT 24
Finished Jul 11 04:26:11 PM PDT 24
Peak memory 194748 kb
Host smart-a2af2ba6-7d29-42a7-b131-eaa7efede070
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238616208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3238616208
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3373608298
Short name T282
Test name
Test status
Simulation time 195733274665 ps
CPU time 450.75 seconds
Started Jul 11 04:49:06 PM PDT 24
Finished Jul 11 04:56:43 PM PDT 24
Peak memory 199776 kb
Host smart-7e714291-4b38-482a-9155-eb419362d2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373608298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3373608298
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4013589921
Short name T275
Test name
Test status
Simulation time 113055326079 ps
CPU time 80.99 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:49:51 PM PDT 24
Peak memory 199736 kb
Host smart-8ba846a7-ebed-4f7c-a567-631f42f61bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013589921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4013589921
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3374019466
Short name T32
Test name
Test status
Simulation time 77445453744 ps
CPU time 34.79 seconds
Started Jul 11 04:51:13 PM PDT 24
Finished Jul 11 04:51:51 PM PDT 24
Peak memory 199792 kb
Host smart-f66cff10-15a9-43e7-b679-4194dd78b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374019466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3374019466
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.487823225
Short name T31
Test name
Test status
Simulation time 26881347550 ps
CPU time 44.28 seconds
Started Jul 11 04:51:01 PM PDT 24
Finished Jul 11 04:51:49 PM PDT 24
Peak memory 199860 kb
Host smart-7fa5748e-fefd-4910-a3cb-db43f03b2757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487823225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.487823225
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3175315357
Short name T268
Test name
Test status
Simulation time 236341423709 ps
CPU time 182.92 seconds
Started Jul 11 04:48:59 PM PDT 24
Finished Jul 11 04:52:10 PM PDT 24
Peak memory 199836 kb
Host smart-020c33d4-287f-4d8c-89c6-fc5d7ac44001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175315357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3175315357
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3614356304
Short name T270
Test name
Test status
Simulation time 105225308212 ps
CPU time 79.02 seconds
Started Jul 11 04:48:56 PM PDT 24
Finished Jul 11 04:50:22 PM PDT 24
Peak memory 199940 kb
Host smart-29721994-9849-4eaf-829a-403cac0bb9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614356304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3614356304
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3254438669
Short name T145
Test name
Test status
Simulation time 870472316387 ps
CPU time 1128.65 seconds
Started Jul 11 04:50:24 PM PDT 24
Finished Jul 11 05:09:15 PM PDT 24
Peak memory 229412 kb
Host smart-09248d1d-7f79-4f25-a097-8f5fbb98997f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254438669 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3254438669
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1855753458
Short name T1280
Test name
Test status
Simulation time 86942698 ps
CPU time 1.4 seconds
Started Jul 11 04:27:24 PM PDT 24
Finished Jul 11 04:27:27 PM PDT 24
Peak memory 198936 kb
Host smart-4301d1a2-5923-48cf-a6d1-e6eb92cdf07b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855753458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1855753458
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2411070267
Short name T144
Test name
Test status
Simulation time 23945023586 ps
CPU time 71.88 seconds
Started Jul 11 04:50:34 PM PDT 24
Finished Jul 11 04:51:50 PM PDT 24
Peak memory 199924 kb
Host smart-04882da1-dd82-4170-b513-ea95f1ad8d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411070267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2411070267
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.4058142940
Short name T179
Test name
Test status
Simulation time 408090704306 ps
CPU time 1028.67 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 05:06:01 PM PDT 24
Peak memory 199828 kb
Host smart-f2a12e07-ad77-4281-b8fc-e21b9b49a077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058142940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4058142940
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3635222873
Short name T319
Test name
Test status
Simulation time 122686387294 ps
CPU time 87.89 seconds
Started Jul 11 04:50:12 PM PDT 24
Finished Jul 11 04:51:44 PM PDT 24
Peak memory 199892 kb
Host smart-ef808816-da45-4322-b8b1-82d656d59f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635222873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3635222873
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3151282069
Short name T9
Test name
Test status
Simulation time 129704004792 ps
CPU time 444.64 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:55:57 PM PDT 24
Peak memory 216420 kb
Host smart-fecd363a-70d3-4ae6-94b8-9d0dff49cfa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151282069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3151282069
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2108601241
Short name T139
Test name
Test status
Simulation time 45111963145 ps
CPU time 9.75 seconds
Started Jul 11 04:50:44 PM PDT 24
Finished Jul 11 04:50:57 PM PDT 24
Peak memory 199764 kb
Host smart-d64420ae-837c-419b-aef2-9a0d700e50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108601241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2108601241
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.820355415
Short name T169
Test name
Test status
Simulation time 27871801675 ps
CPU time 40.41 seconds
Started Jul 11 04:51:04 PM PDT 24
Finished Jul 11 04:51:48 PM PDT 24
Peak memory 199640 kb
Host smart-f2498057-2e66-4eab-a04c-193d33633c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820355415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.820355415
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3839086789
Short name T37
Test name
Test status
Simulation time 82607472489 ps
CPU time 31.27 seconds
Started Jul 11 04:50:32 PM PDT 24
Finished Jul 11 04:51:08 PM PDT 24
Peak memory 199772 kb
Host smart-b8bf9c4b-33a2-43f8-9ab6-affe3619b27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839086789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3839086789
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3039017967
Short name T154
Test name
Test status
Simulation time 79928549897 ps
CPU time 29.89 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:51:15 PM PDT 24
Peak memory 199712 kb
Host smart-fc4a33d8-4a9c-456f-b463-8405ac54f477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039017967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3039017967
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3702509862
Short name T231
Test name
Test status
Simulation time 17607596898 ps
CPU time 24.6 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 199776 kb
Host smart-2dd801cb-88f7-4fb2-a44d-f6a9be3931a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702509862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3702509862
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.385379560
Short name T329
Test name
Test status
Simulation time 102756418413 ps
CPU time 252.94 seconds
Started Jul 11 04:50:59 PM PDT 24
Finished Jul 11 04:55:14 PM PDT 24
Peak memory 199752 kb
Host smart-807d2dc7-48bc-40cd-9fd6-5ec571d4f93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385379560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.385379560
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.4028461705
Short name T314
Test name
Test status
Simulation time 55627863324 ps
CPU time 663.86 seconds
Started Jul 11 04:48:37 PM PDT 24
Finished Jul 11 04:59:49 PM PDT 24
Peak memory 229828 kb
Host smart-d74c546f-78e7-4f52-a32a-1c95b0d6709e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028461705 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.4028461705
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1647754963
Short name T128
Test name
Test status
Simulation time 25249043349 ps
CPU time 44.73 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:51:37 PM PDT 24
Peak memory 200064 kb
Host smart-01610c3f-8bb3-4844-9812-779f0d938127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647754963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1647754963
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4118411755
Short name T177
Test name
Test status
Simulation time 165444289508 ps
CPU time 525.95 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:59:39 PM PDT 24
Peak memory 199888 kb
Host smart-b8f9f9c1-0f58-40a4-ac29-391abfa2dff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118411755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4118411755
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1244735028
Short name T183
Test name
Test status
Simulation time 376767772860 ps
CPU time 42.01 seconds
Started Jul 11 04:50:50 PM PDT 24
Finished Jul 11 04:51:34 PM PDT 24
Peak memory 199792 kb
Host smart-a19c91e1-3382-4a0c-9eda-066ceca42a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244735028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1244735028
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2842287812
Short name T11
Test name
Test status
Simulation time 21058043246 ps
CPU time 51.93 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 199776 kb
Host smart-9d710a3e-8398-4817-86c9-f4e44a49694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842287812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2842287812
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2762873295
Short name T115
Test name
Test status
Simulation time 178339599 ps
CPU time 1.4 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:48 PM PDT 24
Peak memory 198192 kb
Host smart-adfc1f00-c8af-4c34-81e8-cec35171c8fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762873295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2762873295
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/13.uart_stress_all.2598942081
Short name T208
Test name
Test status
Simulation time 251576582093 ps
CPU time 1277.75 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 05:09:53 PM PDT 24
Peak memory 199720 kb
Host smart-ca9e76ed-a8be-4e5c-b2ca-58fda20f0f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598942081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2598942081
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all.4099597091
Short name T162
Test name
Test status
Simulation time 269436311517 ps
CPU time 1673.43 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 05:16:23 PM PDT 24
Peak memory 199808 kb
Host smart-b4008f2c-2486-4f5e-a514-16e6da4a4b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099597091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.4099597091
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.556057534
Short name T189
Test name
Test status
Simulation time 21384227419 ps
CPU time 32.4 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 199900 kb
Host smart-311ff864-8f02-4667-8dc7-947cb3fe517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556057534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.556057534
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1462292567
Short name T950
Test name
Test status
Simulation time 256669781212 ps
CPU time 28.95 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 199724 kb
Host smart-abe41f7c-b217-4857-a6b8-5098162df163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462292567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1462292567
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1487723402
Short name T222
Test name
Test status
Simulation time 149345871817 ps
CPU time 197.97 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:54:12 PM PDT 24
Peak memory 199780 kb
Host smart-50438aca-07ab-47de-9564-ddd5fa77c728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487723402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1487723402
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2420221193
Short name T472
Test name
Test status
Simulation time 11375958771 ps
CPU time 11.31 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 199836 kb
Host smart-cc7bac78-6ed8-4427-aa46-31c2c9755e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420221193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2420221193
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.631611599
Short name T188
Test name
Test status
Simulation time 30518349732 ps
CPU time 49 seconds
Started Jul 11 04:48:51 PM PDT 24
Finished Jul 11 04:49:47 PM PDT 24
Peak memory 199916 kb
Host smart-ca42295c-65df-486f-aecf-4cfe9b0a33a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631611599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.631611599
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2551300794
Short name T909
Test name
Test status
Simulation time 171035631248 ps
CPU time 22.07 seconds
Started Jul 11 04:51:14 PM PDT 24
Finished Jul 11 04:51:38 PM PDT 24
Peak memory 199488 kb
Host smart-1c8408ad-054c-4063-bb68-0db83dba6278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551300794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2551300794
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3021932496
Short name T242
Test name
Test status
Simulation time 351709082986 ps
CPU time 167.4 seconds
Started Jul 11 04:50:05 PM PDT 24
Finished Jul 11 04:52:54 PM PDT 24
Peak memory 200156 kb
Host smart-58071276-a99b-43b9-b580-b9bac0e0c8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021932496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3021932496
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.348071900
Short name T67
Test name
Test status
Simulation time 365805629178 ps
CPU time 1007.07 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 05:06:57 PM PDT 24
Peak memory 224776 kb
Host smart-a095758f-03d3-4c05-9cab-70f04c523840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348071900 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.348071900
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.808060455
Short name T220
Test name
Test status
Simulation time 134056872233 ps
CPU time 99.9 seconds
Started Jul 11 04:47:47 PM PDT 24
Finished Jul 11 04:49:34 PM PDT 24
Peak memory 200164 kb
Host smart-60751bfd-9f9c-49f9-9f76-c0eb1871a476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808060455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.808060455
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1753626217
Short name T34
Test name
Test status
Simulation time 40409418479 ps
CPU time 20.1 seconds
Started Jul 11 04:50:31 PM PDT 24
Finished Jul 11 04:50:55 PM PDT 24
Peak memory 199916 kb
Host smart-78533f09-bcfc-4e80-bd67-3305fa696951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753626217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1753626217
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2760580786
Short name T237
Test name
Test status
Simulation time 13231676848 ps
CPU time 22.09 seconds
Started Jul 11 04:50:28 PM PDT 24
Finished Jul 11 04:50:53 PM PDT 24
Peak memory 199788 kb
Host smart-d334881d-f85a-4efd-94b7-3128b9468627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760580786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2760580786
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3555820678
Short name T249
Test name
Test status
Simulation time 22335991690 ps
CPU time 37.93 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:51:23 PM PDT 24
Peak memory 199612 kb
Host smart-2dfa5519-a2f0-4e23-8644-3aa46c0ccc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555820678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3555820678
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.810320250
Short name T247
Test name
Test status
Simulation time 207610930415 ps
CPU time 80.53 seconds
Started Jul 11 04:50:39 PM PDT 24
Finished Jul 11 04:52:04 PM PDT 24
Peak memory 199808 kb
Host smart-e2539a5f-27f3-4ac6-97bd-bd75cdac721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810320250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.810320250
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.166445415
Short name T262
Test name
Test status
Simulation time 162453087014 ps
CPU time 50.05 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:49:22 PM PDT 24
Peak memory 199856 kb
Host smart-b830b6c8-034f-4122-a700-5465defa14b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166445415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.166445415
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3832032193
Short name T236
Test name
Test status
Simulation time 64625519533 ps
CPU time 24.93 seconds
Started Jul 11 04:50:41 PM PDT 24
Finished Jul 11 04:51:10 PM PDT 24
Peak memory 199888 kb
Host smart-558e96f0-2b7f-4d4b-af68-e32108300df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832032193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3832032193
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3401548985
Short name T216
Test name
Test status
Simulation time 13364197746 ps
CPU time 10.43 seconds
Started Jul 11 04:50:40 PM PDT 24
Finished Jul 11 04:50:54 PM PDT 24
Peak memory 199880 kb
Host smart-0da6b870-7494-4a9f-84c8-7f8cf32fb9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401548985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3401548985
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3335124634
Short name T174
Test name
Test status
Simulation time 45217129203 ps
CPU time 25.09 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:51:18 PM PDT 24
Peak memory 199944 kb
Host smart-9fa489f9-5c94-4875-8e84-c7e6c94c4c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335124634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3335124634
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2211193937
Short name T140
Test name
Test status
Simulation time 60067541583 ps
CPU time 25.33 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 199776 kb
Host smart-78a59c00-0053-4cf2-a672-a07482f29268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211193937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2211193937
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.4208271485
Short name T210
Test name
Test status
Simulation time 99930475088 ps
CPU time 22.05 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:51:16 PM PDT 24
Peak memory 199804 kb
Host smart-75c7affe-c0d3-4628-a219-2b69c900faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208271485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4208271485
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3673376999
Short name T246
Test name
Test status
Simulation time 124445497968 ps
CPU time 124.35 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:50:41 PM PDT 24
Peak memory 199828 kb
Host smart-40869d9d-1989-4cd6-aa1f-245575af0047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673376999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3673376999
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3780685571
Short name T196
Test name
Test status
Simulation time 40747062289 ps
CPU time 43.14 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:42 PM PDT 24
Peak memory 199860 kb
Host smart-1c06a1b2-6da2-45bb-9dac-f1f970b998ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780685571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3780685571
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2753470516
Short name T239
Test name
Test status
Simulation time 82655385524 ps
CPU time 278.57 seconds
Started Jul 11 04:50:52 PM PDT 24
Finished Jul 11 04:55:34 PM PDT 24
Peak memory 199776 kb
Host smart-0d7d9b89-b5df-462e-903c-41c9fcb46d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753470516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2753470516
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1557413378
Short name T214
Test name
Test status
Simulation time 117049487135 ps
CPU time 107.39 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:52:44 PM PDT 24
Peak memory 199916 kb
Host smart-4424a486-8e73-4d3c-8a36-d2b9d45153d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557413378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1557413378
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3631724755
Short name T243
Test name
Test status
Simulation time 99979078175 ps
CPU time 346.78 seconds
Started Jul 11 04:49:50 PM PDT 24
Finished Jul 11 04:55:40 PM PDT 24
Peak memory 199876 kb
Host smart-fd03b19d-f6c5-43d5-8445-25944888dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631724755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3631724755
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1915503935
Short name T7
Test name
Test status
Simulation time 183008209415 ps
CPU time 406.26 seconds
Started Jul 11 04:50:07 PM PDT 24
Finished Jul 11 04:56:55 PM PDT 24
Peak memory 199700 kb
Host smart-77ff473d-baaa-49e6-b119-af63cd8b5d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915503935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1915503935
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.930157117
Short name T234
Test name
Test status
Simulation time 40045141124 ps
CPU time 15.77 seconds
Started Jul 11 04:50:20 PM PDT 24
Finished Jul 11 04:50:39 PM PDT 24
Peak memory 199860 kb
Host smart-d0a1a965-34cb-442c-b7cb-2bed398817f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930157117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.930157117
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1309825270
Short name T229
Test name
Test status
Simulation time 155200468156 ps
CPU time 35.6 seconds
Started Jul 11 04:50:18 PM PDT 24
Finished Jul 11 04:50:57 PM PDT 24
Peak memory 199816 kb
Host smart-08633fe8-9876-4c13-87cb-f1f50461e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309825270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1309825270
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1940439639
Short name T1269
Test name
Test status
Simulation time 252859432 ps
CPU time 0.78 seconds
Started Jul 11 04:26:29 PM PDT 24
Finished Jul 11 04:26:32 PM PDT 24
Peak memory 196888 kb
Host smart-3addc159-a1ba-4bd6-a613-32f1847f7c51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940439639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1940439639
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.447032731
Short name T1240
Test name
Test status
Simulation time 344637637 ps
CPU time 2.2 seconds
Started Jul 11 04:20:30 PM PDT 24
Finished Jul 11 04:20:33 PM PDT 24
Peak memory 197356 kb
Host smart-47e75076-3cbd-45c8-896c-8dcacca463be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447032731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.447032731
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1099896349
Short name T1199
Test name
Test status
Simulation time 23931155 ps
CPU time 0.6 seconds
Started Jul 11 04:20:23 PM PDT 24
Finished Jul 11 04:20:24 PM PDT 24
Peak memory 196412 kb
Host smart-773c5cbb-06c8-40c4-8765-c78ea2fa087a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099896349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1099896349
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2252905029
Short name T1197
Test name
Test status
Simulation time 32486534 ps
CPU time 0.88 seconds
Started Jul 11 04:26:11 PM PDT 24
Finished Jul 11 04:26:16 PM PDT 24
Peak memory 199552 kb
Host smart-2975ce34-72e9-4d8d-abff-01451e23ecae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252905029 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2252905029
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2708507066
Short name T1286
Test name
Test status
Simulation time 32226604 ps
CPU time 0.62 seconds
Started Jul 11 04:20:22 PM PDT 24
Finished Jul 11 04:20:23 PM PDT 24
Peak memory 195124 kb
Host smart-8766562d-b00a-4843-ab10-d556ac27d015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708507066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2708507066
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.745568448
Short name T1314
Test name
Test status
Simulation time 22031892 ps
CPU time 0.62 seconds
Started Jul 11 04:20:24 PM PDT 24
Finished Jul 11 04:20:27 PM PDT 24
Peak memory 194112 kb
Host smart-e41c5ef8-5bac-471b-a9ed-bf1753283d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745568448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.745568448
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1324779377
Short name T1311
Test name
Test status
Simulation time 80658214 ps
CPU time 0.65 seconds
Started Jul 11 04:26:29 PM PDT 24
Finished Jul 11 04:26:31 PM PDT 24
Peak memory 196240 kb
Host smart-2d9fb98a-c0d1-4a42-aa5d-a83604ee73e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324779377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1324779377
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2830265136
Short name T1290
Test name
Test status
Simulation time 91642695 ps
CPU time 1.4 seconds
Started Jul 11 04:26:31 PM PDT 24
Finished Jul 11 04:26:34 PM PDT 24
Peak memory 199728 kb
Host smart-74b17c71-d2a6-40ac-a5c5-63b48670811f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830265136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2830265136
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3808839429
Short name T90
Test name
Test status
Simulation time 69519854 ps
CPU time 1.22 seconds
Started Jul 11 04:20:30 PM PDT 24
Finished Jul 11 04:20:32 PM PDT 24
Peak memory 198776 kb
Host smart-60a5d33e-a97d-4b5d-a228-49b4a86ad348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808839429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3808839429
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.341129013
Short name T1315
Test name
Test status
Simulation time 45644157 ps
CPU time 0.7 seconds
Started Jul 11 04:26:56 PM PDT 24
Finished Jul 11 04:26:58 PM PDT 24
Peak memory 194712 kb
Host smart-3e086455-646f-419d-a063-7fbb4f98a8bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341129013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.341129013
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1547987660
Short name T1207
Test name
Test status
Simulation time 591667027 ps
CPU time 2.27 seconds
Started Jul 11 04:21:04 PM PDT 24
Finished Jul 11 04:21:07 PM PDT 24
Peak memory 198640 kb
Host smart-eba01e44-affc-4c4c-9365-ccdf5819e25a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547987660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1547987660
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1450980000
Short name T1213
Test name
Test status
Simulation time 53694522 ps
CPU time 0.62 seconds
Started Jul 11 04:25:47 PM PDT 24
Finished Jul 11 04:25:49 PM PDT 24
Peak memory 195128 kb
Host smart-2da5dbdf-3c11-4a16-964b-7cf8b8b04c7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450980000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1450980000
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2965454682
Short name T1194
Test name
Test status
Simulation time 67191570 ps
CPU time 1.1 seconds
Started Jul 11 04:20:22 PM PDT 24
Finished Jul 11 04:20:24 PM PDT 24
Peak memory 200784 kb
Host smart-986fd559-f6fd-469c-bb32-f49893f3d50e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965454682 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2965454682
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2078805507
Short name T1209
Test name
Test status
Simulation time 54672783 ps
CPU time 0.62 seconds
Started Jul 11 04:26:10 PM PDT 24
Finished Jul 11 04:26:14 PM PDT 24
Peak memory 194896 kb
Host smart-e5ab3489-a2ed-435b-97ee-6a27b3f34265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078805507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2078805507
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4243652079
Short name T1230
Test name
Test status
Simulation time 28471221 ps
CPU time 0.6 seconds
Started Jul 11 04:24:09 PM PDT 24
Finished Jul 11 04:24:10 PM PDT 24
Peak memory 194960 kb
Host smart-f85f2cb1-27b5-4e2e-a254-9fe3ac30debf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243652079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4243652079
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.282730549
Short name T1259
Test name
Test status
Simulation time 35254628 ps
CPU time 0.78 seconds
Started Jul 11 04:21:12 PM PDT 24
Finished Jul 11 04:21:14 PM PDT 24
Peak memory 198108 kb
Host smart-c7bdceda-f0a1-4c78-8a02-7bdcb2f6c5b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282730549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.282730549
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2777949607
Short name T1251
Test name
Test status
Simulation time 112669296 ps
CPU time 1.35 seconds
Started Jul 11 04:27:24 PM PDT 24
Finished Jul 11 04:27:27 PM PDT 24
Peak memory 200276 kb
Host smart-895f6dde-b71c-42ed-8650-c0a87e09bbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777949607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2777949607
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.294968886
Short name T1219
Test name
Test status
Simulation time 103805942 ps
CPU time 0.76 seconds
Started Jul 11 04:24:08 PM PDT 24
Finished Jul 11 04:24:09 PM PDT 24
Peak memory 199348 kb
Host smart-245316f3-ce5a-4288-8004-09e60774e65d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294968886 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.294968886
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3726390274
Short name T1300
Test name
Test status
Simulation time 57333454 ps
CPU time 0.66 seconds
Started Jul 11 04:26:23 PM PDT 24
Finished Jul 11 04:26:26 PM PDT 24
Peak memory 195112 kb
Host smart-aff5047c-aba9-4bd4-8b73-2e29ce090978
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726390274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3726390274
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3483548948
Short name T1202
Test name
Test status
Simulation time 97417486 ps
CPU time 0.62 seconds
Started Jul 11 04:25:53 PM PDT 24
Finished Jul 11 04:25:55 PM PDT 24
Peak memory 194120 kb
Host smart-572bb41f-e4ae-446f-a9fb-d9a12ebd94ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483548948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3483548948
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3966748871
Short name T1310
Test name
Test status
Simulation time 46293263 ps
CPU time 0.71 seconds
Started Jul 11 04:24:12 PM PDT 24
Finished Jul 11 04:24:14 PM PDT 24
Peak memory 197508 kb
Host smart-97629f87-6c2a-49c7-bd3c-b8f5976dc7f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966748871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3966748871
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1280319384
Short name T1287
Test name
Test status
Simulation time 131656978 ps
CPU time 1.97 seconds
Started Jul 11 04:26:48 PM PDT 24
Finished Jul 11 04:26:54 PM PDT 24
Peak memory 198224 kb
Host smart-1cfe0ad8-8785-44a3-9bbc-b1a94cff24d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280319384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1280319384
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1154014334
Short name T89
Test name
Test status
Simulation time 595467151 ps
CPU time 1.33 seconds
Started Jul 11 04:26:48 PM PDT 24
Finished Jul 11 04:26:53 PM PDT 24
Peak memory 197036 kb
Host smart-5903c948-906d-48b9-bdbf-7249040774b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154014334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1154014334
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.128831999
Short name T1265
Test name
Test status
Simulation time 21944230 ps
CPU time 1.04 seconds
Started Jul 11 04:24:32 PM PDT 24
Finished Jul 11 04:24:34 PM PDT 24
Peak memory 200360 kb
Host smart-7a675975-fa3d-4140-8746-62268579fe0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128831999 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.128831999
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1672220361
Short name T52
Test name
Test status
Simulation time 16977496 ps
CPU time 0.69 seconds
Started Jul 11 04:24:39 PM PDT 24
Finished Jul 11 04:24:41 PM PDT 24
Peak memory 196092 kb
Host smart-24be7586-fbed-40bb-8b57-b627e3832b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672220361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1672220361
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2445233128
Short name T1215
Test name
Test status
Simulation time 18531006 ps
CPU time 0.55 seconds
Started Jul 11 04:26:48 PM PDT 24
Finished Jul 11 04:26:52 PM PDT 24
Peak memory 194976 kb
Host smart-7f6bccb2-a917-41e6-8166-32551def05c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445233128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2445233128
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.968175939
Short name T77
Test name
Test status
Simulation time 33923839 ps
CPU time 0.81 seconds
Started Jul 11 04:26:13 PM PDT 24
Finished Jul 11 04:26:16 PM PDT 24
Peak memory 197536 kb
Host smart-30190842-bb8b-444c-97e8-63116bd9fdac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968175939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.968175939
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.452090540
Short name T1245
Test name
Test status
Simulation time 168303655 ps
CPU time 1.3 seconds
Started Jul 11 04:24:05 PM PDT 24
Finished Jul 11 04:24:08 PM PDT 24
Peak memory 200996 kb
Host smart-c625f060-4d7a-4cdf-8800-39114761c3f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452090540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.452090540
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.993143807
Short name T1313
Test name
Test status
Simulation time 253985184 ps
CPU time 0.92 seconds
Started Jul 11 04:26:48 PM PDT 24
Finished Jul 11 04:26:52 PM PDT 24
Peak memory 199496 kb
Host smart-a7a45679-637f-48ca-beae-97f3ca84ce59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993143807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.993143807
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3621041068
Short name T1195
Test name
Test status
Simulation time 123085032 ps
CPU time 0.83 seconds
Started Jul 11 04:26:47 PM PDT 24
Finished Jul 11 04:26:51 PM PDT 24
Peak memory 200332 kb
Host smart-e5e818cf-f097-46bf-bd82-ded9980b03fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621041068 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3621041068
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.199327240
Short name T1276
Test name
Test status
Simulation time 50555496 ps
CPU time 0.62 seconds
Started Jul 11 04:26:32 PM PDT 24
Finished Jul 11 04:26:35 PM PDT 24
Peak memory 194756 kb
Host smart-dbd39530-6982-4652-9935-295abf2cfb0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199327240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.199327240
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2869953827
Short name T1223
Test name
Test status
Simulation time 44055669 ps
CPU time 0.6 seconds
Started Jul 11 04:24:24 PM PDT 24
Finished Jul 11 04:24:26 PM PDT 24
Peak memory 194916 kb
Host smart-767cd46d-9bae-4163-badb-9fa4562a4a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869953827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2869953827
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.31534715
Short name T1297
Test name
Test status
Simulation time 57111743 ps
CPU time 0.79 seconds
Started Jul 11 04:26:32 PM PDT 24
Finished Jul 11 04:26:35 PM PDT 24
Peak memory 196404 kb
Host smart-368f6603-6b77-4de4-8f79-e65382d2e052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31534715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_
outstanding.31534715
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2822430892
Short name T1294
Test name
Test status
Simulation time 535702403 ps
CPU time 2.19 seconds
Started Jul 11 04:26:33 PM PDT 24
Finished Jul 11 04:26:38 PM PDT 24
Peak memory 200128 kb
Host smart-831acc89-c7bf-4b59-a2c1-d2065219c4a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822430892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2822430892
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.722369836
Short name T87
Test name
Test status
Simulation time 107564291 ps
CPU time 1 seconds
Started Jul 11 04:24:30 PM PDT 24
Finished Jul 11 04:24:32 PM PDT 24
Peak memory 199624 kb
Host smart-9d3ddf0f-81ea-43d3-850f-f2122d99a458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722369836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.722369836
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2442832971
Short name T1192
Test name
Test status
Simulation time 270091246 ps
CPU time 0.65 seconds
Started Jul 11 04:26:24 PM PDT 24
Finished Jul 11 04:26:26 PM PDT 24
Peak memory 198192 kb
Host smart-7bb9fa58-9491-46a8-b1f9-8ef76c06bf4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442832971 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2442832971
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.555618374
Short name T73
Test name
Test status
Simulation time 105774591 ps
CPU time 0.59 seconds
Started Jul 11 04:26:47 PM PDT 24
Finished Jul 11 04:26:51 PM PDT 24
Peak memory 196100 kb
Host smart-4980c63f-19df-4ff4-b540-c091152839b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555618374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.555618374
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1386350570
Short name T1249
Test name
Test status
Simulation time 12206582 ps
CPU time 0.6 seconds
Started Jul 11 04:26:30 PM PDT 24
Finished Jul 11 04:26:32 PM PDT 24
Peak memory 193784 kb
Host smart-0075b61e-0d95-489d-8c31-65d785d78904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386350570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1386350570
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1749947355
Short name T70
Test name
Test status
Simulation time 90065396 ps
CPU time 0.78 seconds
Started Jul 11 04:26:30 PM PDT 24
Finished Jul 11 04:26:32 PM PDT 24
Peak memory 196368 kb
Host smart-9ec3967e-4e0f-4a73-abbc-b2826bc4f0bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749947355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1749947355
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2468969848
Short name T1205
Test name
Test status
Simulation time 107559310 ps
CPU time 1.63 seconds
Started Jul 11 04:24:30 PM PDT 24
Finished Jul 11 04:24:32 PM PDT 24
Peak memory 200524 kb
Host smart-993ee666-ef02-42fc-b815-ecee72d8b1fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468969848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2468969848
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1866063039
Short name T1217
Test name
Test status
Simulation time 178100931 ps
CPU time 0.72 seconds
Started Jul 11 04:25:47 PM PDT 24
Finished Jul 11 04:25:49 PM PDT 24
Peak memory 198092 kb
Host smart-a4552bfc-ff97-4a5f-a3f6-735000997008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866063039 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1866063039
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.304137425
Short name T1301
Test name
Test status
Simulation time 15404200 ps
CPU time 0.59 seconds
Started Jul 11 04:27:10 PM PDT 24
Finished Jul 11 04:27:13 PM PDT 24
Peak memory 196188 kb
Host smart-707a123c-e2ed-4d44-a764-c841f48cb540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304137425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.304137425
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3094640972
Short name T1281
Test name
Test status
Simulation time 26003422 ps
CPU time 0.56 seconds
Started Jul 11 04:26:32 PM PDT 24
Finished Jul 11 04:26:34 PM PDT 24
Peak memory 194568 kb
Host smart-8a8321ab-d6d5-44b8-bdaf-232f509614bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094640972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3094640972
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2054899123
Short name T1278
Test name
Test status
Simulation time 25090047 ps
CPU time 0.72 seconds
Started Jul 11 04:25:47 PM PDT 24
Finished Jul 11 04:25:49 PM PDT 24
Peak memory 197248 kb
Host smart-8153f40c-373f-49df-85bd-f7bf5fbd86b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054899123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2054899123
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.764682458
Short name T1228
Test name
Test status
Simulation time 471482746 ps
CPU time 2.5 seconds
Started Jul 11 04:26:03 PM PDT 24
Finished Jul 11 04:26:09 PM PDT 24
Peak memory 199548 kb
Host smart-7a46669f-ffe5-4447-be59-3ca704e81f54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764682458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.764682458
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1784882850
Short name T86
Test name
Test status
Simulation time 52525455 ps
CPU time 1.05 seconds
Started Jul 11 04:26:31 PM PDT 24
Finished Jul 11 04:26:34 PM PDT 24
Peak memory 197804 kb
Host smart-2b62b388-9f6c-4574-a19e-11962d0c6230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784882850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1784882850
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.653451444
Short name T1272
Test name
Test status
Simulation time 19666641 ps
CPU time 0.84 seconds
Started Jul 11 04:26:07 PM PDT 24
Finished Jul 11 04:26:11 PM PDT 24
Peak memory 199304 kb
Host smart-46de0396-0994-44ec-8f32-de562775cead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653451444 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.653451444
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2849676543
Short name T1252
Test name
Test status
Simulation time 28420655 ps
CPU time 0.62 seconds
Started Jul 11 04:26:33 PM PDT 24
Finished Jul 11 04:26:36 PM PDT 24
Peak memory 194916 kb
Host smart-07859955-e3ae-482a-8297-a25651ee32d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849676543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2849676543
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.436771581
Short name T1316
Test name
Test status
Simulation time 38049789 ps
CPU time 0.64 seconds
Started Jul 11 04:26:27 PM PDT 24
Finished Jul 11 04:26:29 PM PDT 24
Peak memory 193396 kb
Host smart-6a9b5017-dad4-4654-8d39-3541a4037132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436771581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.436771581
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1055355377
Short name T1258
Test name
Test status
Simulation time 74884336 ps
CPU time 0.72 seconds
Started Jul 11 04:25:01 PM PDT 24
Finished Jul 11 04:25:03 PM PDT 24
Peak memory 197040 kb
Host smart-f45e1c24-7c8b-4443-86b4-4fd5eb7c217b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055355377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1055355377
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.128955458
Short name T1262
Test name
Test status
Simulation time 46485080 ps
CPU time 2.07 seconds
Started Jul 11 04:26:31 PM PDT 24
Finished Jul 11 04:26:35 PM PDT 24
Peak memory 198836 kb
Host smart-43b0c4f6-7005-46d3-8e5f-54512380c5be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128955458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.128955458
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2601451172
Short name T116
Test name
Test status
Simulation time 147703270 ps
CPU time 1.29 seconds
Started Jul 11 04:26:06 PM PDT 24
Finished Jul 11 04:26:12 PM PDT 24
Peak memory 198604 kb
Host smart-c9f33c12-9684-441c-b514-a6f755857d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601451172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2601451172
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4082032540
Short name T1214
Test name
Test status
Simulation time 31831701 ps
CPU time 0.74 seconds
Started Jul 11 04:26:57 PM PDT 24
Finished Jul 11 04:26:59 PM PDT 24
Peak memory 198788 kb
Host smart-0e75fa53-5689-426d-b31c-87bce9d36452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082032540 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4082032540
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1884792396
Short name T1231
Test name
Test status
Simulation time 66616358 ps
CPU time 0.57 seconds
Started Jul 11 04:26:33 PM PDT 24
Finished Jul 11 04:26:36 PM PDT 24
Peak memory 193772 kb
Host smart-e1c0b80e-1a5f-47b8-8765-68b6d78c84f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884792396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1884792396
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.343407453
Short name T1267
Test name
Test status
Simulation time 18983516 ps
CPU time 0.66 seconds
Started Jul 11 04:24:55 PM PDT 24
Finished Jul 11 04:24:58 PM PDT 24
Peak memory 197016 kb
Host smart-82fc3a18-934c-4031-a4f0-62a71cc133f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343407453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.343407453
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3879162120
Short name T1235
Test name
Test status
Simulation time 29204396 ps
CPU time 1.41 seconds
Started Jul 11 04:26:27 PM PDT 24
Finished Jul 11 04:26:30 PM PDT 24
Peak memory 199304 kb
Host smart-ef601d25-7a84-45f9-9cb3-5fbc69acafab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879162120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3879162120
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2263069119
Short name T91
Test name
Test status
Simulation time 914965167 ps
CPU time 1.26 seconds
Started Jul 11 04:26:24 PM PDT 24
Finished Jul 11 04:26:27 PM PDT 24
Peak memory 199896 kb
Host smart-db04b34c-db5a-48ea-982e-888510b4e3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263069119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2263069119
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4233182712
Short name T1224
Test name
Test status
Simulation time 18898910 ps
CPU time 0.69 seconds
Started Jul 11 04:26:34 PM PDT 24
Finished Jul 11 04:26:38 PM PDT 24
Peak memory 195928 kb
Host smart-17691924-9793-4414-8a12-859060221b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233182712 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4233182712
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3411257370
Short name T1309
Test name
Test status
Simulation time 10427631 ps
CPU time 0.57 seconds
Started Jul 11 04:26:57 PM PDT 24
Finished Jul 11 04:27:00 PM PDT 24
Peak memory 195604 kb
Host smart-60aa5e4f-37d2-4b6e-ac5d-d86b33c1078c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411257370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3411257370
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.134798619
Short name T1307
Test name
Test status
Simulation time 73352797 ps
CPU time 0.61 seconds
Started Jul 11 04:24:56 PM PDT 24
Finished Jul 11 04:24:58 PM PDT 24
Peak memory 194964 kb
Host smart-acb051a4-7511-4391-9572-429e7823531f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134798619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.134798619
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.948764487
Short name T71
Test name
Test status
Simulation time 26298294 ps
CPU time 0.72 seconds
Started Jul 11 04:26:58 PM PDT 24
Finished Jul 11 04:27:00 PM PDT 24
Peak memory 196736 kb
Host smart-3bd7f808-6600-4d33-828d-1f5c7efa887f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948764487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.948764487
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3493474305
Short name T1261
Test name
Test status
Simulation time 105135688 ps
CPU time 1.92 seconds
Started Jul 11 04:26:57 PM PDT 24
Finished Jul 11 04:27:01 PM PDT 24
Peak memory 200236 kb
Host smart-7918789b-1588-4a0c-96a5-a1acf84c50e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493474305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3493474305
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3436713257
Short name T80
Test name
Test status
Simulation time 74722166 ps
CPU time 1.25 seconds
Started Jul 11 04:24:53 PM PDT 24
Finished Jul 11 04:24:56 PM PDT 24
Peak memory 199932 kb
Host smart-1de4019e-813f-4683-8071-0a437cfc45d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436713257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3436713257
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1470914715
Short name T1241
Test name
Test status
Simulation time 20627873 ps
CPU time 0.65 seconds
Started Jul 11 04:26:59 PM PDT 24
Finished Jul 11 04:27:01 PM PDT 24
Peak memory 197612 kb
Host smart-fc9bcc2e-27d7-4319-b528-f8a7223c5bdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470914715 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1470914715
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2190092152
Short name T58
Test name
Test status
Simulation time 15589733 ps
CPU time 0.58 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:48 PM PDT 24
Peak memory 195064 kb
Host smart-534d44f3-924e-4bb5-b4da-effed5f93f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190092152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2190092152
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3781338430
Short name T1242
Test name
Test status
Simulation time 13499167 ps
CPU time 0.6 seconds
Started Jul 11 04:26:47 PM PDT 24
Finished Jul 11 04:26:51 PM PDT 24
Peak memory 192412 kb
Host smart-70f9f975-ceac-446f-8a4e-a6e75e28db5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781338430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3781338430
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2508819080
Short name T1243
Test name
Test status
Simulation time 47834444 ps
CPU time 0.79 seconds
Started Jul 11 04:25:17 PM PDT 24
Finished Jul 11 04:25:19 PM PDT 24
Peak memory 197712 kb
Host smart-3a78b8af-1e72-4955-956b-a582018b6b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508819080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2508819080
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.544547388
Short name T1273
Test name
Test status
Simulation time 188470510 ps
CPU time 1.16 seconds
Started Jul 11 04:24:56 PM PDT 24
Finished Jul 11 04:24:58 PM PDT 24
Peak memory 200536 kb
Host smart-2d0b9f95-21f0-4340-af3d-eca25b0e4647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544547388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.544547388
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.750104250
Short name T84
Test name
Test status
Simulation time 291381907 ps
CPU time 0.98 seconds
Started Jul 11 04:26:58 PM PDT 24
Finished Jul 11 04:27:01 PM PDT 24
Peak memory 199244 kb
Host smart-ea3a8b5b-7fad-435d-a1ef-787a0f2f6718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750104250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.750104250
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1099217149
Short name T1312
Test name
Test status
Simulation time 24601833 ps
CPU time 0.74 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:48 PM PDT 24
Peak memory 197772 kb
Host smart-3023bd00-7c13-4950-ad50-113a530b30d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099217149 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1099217149
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1072571455
Short name T1201
Test name
Test status
Simulation time 20762064 ps
CPU time 0.58 seconds
Started Jul 11 04:25:17 PM PDT 24
Finished Jul 11 04:25:19 PM PDT 24
Peak memory 195980 kb
Host smart-4db79280-70e5-4adb-8e8c-d2ba51c29575
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072571455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1072571455
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1082633526
Short name T1257
Test name
Test status
Simulation time 15146235 ps
CPU time 0.62 seconds
Started Jul 11 04:25:05 PM PDT 24
Finished Jul 11 04:25:08 PM PDT 24
Peak memory 195408 kb
Host smart-170493de-e9ce-488d-a843-eb64d7df0d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082633526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1082633526
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1798847303
Short name T1253
Test name
Test status
Simulation time 35565068 ps
CPU time 0.75 seconds
Started Jul 11 04:26:47 PM PDT 24
Finished Jul 11 04:26:51 PM PDT 24
Peak memory 194032 kb
Host smart-149a770f-3ba5-4f50-9f6a-1b8417d151a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798847303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1798847303
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1033382849
Short name T1248
Test name
Test status
Simulation time 378671415 ps
CPU time 1.95 seconds
Started Jul 11 04:25:18 PM PDT 24
Finished Jul 11 04:25:21 PM PDT 24
Peak memory 200596 kb
Host smart-9f863bf5-c1f0-4c68-bcbe-3846c49b14c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033382849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1033382849
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.451493314
Short name T1305
Test name
Test status
Simulation time 97538111 ps
CPU time 1.3 seconds
Started Jul 11 04:26:47 PM PDT 24
Finished Jul 11 04:26:52 PM PDT 24
Peak memory 197484 kb
Host smart-015a098c-eaba-466a-abc6-b352699d72df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451493314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.451493314
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.128366226
Short name T1221
Test name
Test status
Simulation time 32133755 ps
CPU time 0.77 seconds
Started Jul 11 04:26:38 PM PDT 24
Finished Jul 11 04:26:41 PM PDT 24
Peak memory 196496 kb
Host smart-2e0bdb11-f567-4eef-96e7-e636d5e3ff8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128366226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.128366226
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3479298463
Short name T51
Test name
Test status
Simulation time 135282318 ps
CPU time 1.58 seconds
Started Jul 11 04:27:06 PM PDT 24
Finished Jul 11 04:27:15 PM PDT 24
Peak memory 197980 kb
Host smart-79bb7d3e-5582-4fb5-a25b-6ba5b2322e35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479298463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3479298463
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3521825058
Short name T57
Test name
Test status
Simulation time 15565929 ps
CPU time 0.67 seconds
Started Jul 11 04:26:10 PM PDT 24
Finished Jul 11 04:26:14 PM PDT 24
Peak memory 194804 kb
Host smart-306c73b3-e8b1-40fb-a39f-1b1b49de4e5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521825058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3521825058
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4212347001
Short name T1284
Test name
Test status
Simulation time 19037062 ps
CPU time 0.92 seconds
Started Jul 11 04:24:23 PM PDT 24
Finished Jul 11 04:24:25 PM PDT 24
Peak memory 200388 kb
Host smart-0f2cda33-f9d9-4824-9bea-d64e3c9861ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212347001 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.4212347001
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4222083824
Short name T1239
Test name
Test status
Simulation time 31710807 ps
CPU time 0.63 seconds
Started Jul 11 04:26:23 PM PDT 24
Finished Jul 11 04:26:25 PM PDT 24
Peak memory 195312 kb
Host smart-605f4698-0c15-4fc1-b425-ac92975f3946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222083824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4222083824
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3916274908
Short name T1198
Test name
Test status
Simulation time 14190417 ps
CPU time 0.58 seconds
Started Jul 11 04:21:48 PM PDT 24
Finished Jul 11 04:21:50 PM PDT 24
Peak memory 195364 kb
Host smart-b4abb0b4-d9c1-4724-b9e5-c805c17f2acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916274908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3916274908
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2407735548
Short name T1270
Test name
Test status
Simulation time 106525630 ps
CPU time 0.73 seconds
Started Jul 11 04:22:24 PM PDT 24
Finished Jul 11 04:22:25 PM PDT 24
Peak memory 196888 kb
Host smart-9f56e8cc-57d2-4377-b448-0c84404fcf3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407735548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2407735548
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2788033558
Short name T1212
Test name
Test status
Simulation time 226843897 ps
CPU time 2 seconds
Started Jul 11 04:26:31 PM PDT 24
Finished Jul 11 04:26:35 PM PDT 24
Peak memory 198772 kb
Host smart-cb922d3c-cf1b-433d-a26e-2fd946b30629
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788033558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2788033558
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.736220240
Short name T81
Test name
Test status
Simulation time 57828308 ps
CPU time 1.04 seconds
Started Jul 11 04:22:02 PM PDT 24
Finished Jul 11 04:22:03 PM PDT 24
Peak memory 199732 kb
Host smart-ef448082-a890-4134-95b3-c49306d1294b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736220240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.736220240
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1408810721
Short name T1260
Test name
Test status
Simulation time 17751000 ps
CPU time 0.59 seconds
Started Jul 11 04:26:47 PM PDT 24
Finished Jul 11 04:26:51 PM PDT 24
Peak memory 192940 kb
Host smart-f8fb9903-f415-49ef-813b-f0adb1a08589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408810721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1408810721
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2385592376
Short name T1193
Test name
Test status
Simulation time 30212361 ps
CPU time 0.61 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:48 PM PDT 24
Peak memory 193808 kb
Host smart-38f34efa-45e7-45b8-9113-b082c6d681e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385592376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2385592376
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.450596462
Short name T1236
Test name
Test status
Simulation time 65175468 ps
CPU time 0.57 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:48 PM PDT 24
Peak memory 193868 kb
Host smart-4db7dda7-bad0-43b7-9064-be7e3bce4de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450596462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.450596462
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3110711818
Short name T1293
Test name
Test status
Simulation time 16606127 ps
CPU time 0.59 seconds
Started Jul 11 04:25:06 PM PDT 24
Finished Jul 11 04:25:08 PM PDT 24
Peak memory 195404 kb
Host smart-447e9d6b-6b16-4d89-86aa-3e0b023af432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110711818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3110711818
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4246228334
Short name T1246
Test name
Test status
Simulation time 41423120 ps
CPU time 0.68 seconds
Started Jul 11 04:26:40 PM PDT 24
Finished Jul 11 04:26:44 PM PDT 24
Peak memory 194128 kb
Host smart-ac55ac56-314a-498f-8fb0-6e677864fe58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246228334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4246228334
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.371104641
Short name T1302
Test name
Test status
Simulation time 50762465 ps
CPU time 0.56 seconds
Started Jul 11 04:25:29 PM PDT 24
Finished Jul 11 04:25:32 PM PDT 24
Peak memory 194852 kb
Host smart-46fc8f22-3493-47b6-9ea4-8eca7205fca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371104641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.371104641
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3581937284
Short name T1196
Test name
Test status
Simulation time 79377749 ps
CPU time 0.6 seconds
Started Jul 11 04:25:09 PM PDT 24
Finished Jul 11 04:25:12 PM PDT 24
Peak memory 194952 kb
Host smart-f71f711d-45cb-4675-8379-c6c7dc4e3963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581937284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3581937284
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3059061171
Short name T1264
Test name
Test status
Simulation time 31587216 ps
CPU time 0.57 seconds
Started Jul 11 04:25:06 PM PDT 24
Finished Jul 11 04:25:08 PM PDT 24
Peak memory 194980 kb
Host smart-70be23fa-f967-48fc-af79-361edee532a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059061171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3059061171
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1560419593
Short name T1289
Test name
Test status
Simulation time 22044199 ps
CPU time 0.58 seconds
Started Jul 11 04:25:29 PM PDT 24
Finished Jul 11 04:25:32 PM PDT 24
Peak memory 194964 kb
Host smart-ace37697-60f3-4cd7-9fdf-7daa2aab6791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560419593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1560419593
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1265734035
Short name T1226
Test name
Test status
Simulation time 179484419 ps
CPU time 0.59 seconds
Started Jul 11 04:25:10 PM PDT 24
Finished Jul 11 04:25:12 PM PDT 24
Peak memory 194956 kb
Host smart-6c571d74-8bc4-40d9-b500-a73fa3b08d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265734035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1265734035
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3069517543
Short name T1220
Test name
Test status
Simulation time 55481589 ps
CPU time 0.66 seconds
Started Jul 11 04:22:49 PM PDT 24
Finished Jul 11 04:22:50 PM PDT 24
Peak memory 195272 kb
Host smart-02415435-9dcc-45c7-8e72-4a7a4201296d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069517543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3069517543
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2775030591
Short name T55
Test name
Test status
Simulation time 58665817 ps
CPU time 2.34 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:49 PM PDT 24
Peak memory 195744 kb
Host smart-d8f5898e-133f-43dc-9898-36591c8052d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775030591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2775030591
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3609736471
Short name T53
Test name
Test status
Simulation time 53156478 ps
CPU time 0.68 seconds
Started Jul 11 04:26:36 PM PDT 24
Finished Jul 11 04:26:41 PM PDT 24
Peak memory 195128 kb
Host smart-2f5d5ac6-b27e-49c2-962d-3068aad31325
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609736471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3609736471
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2769353282
Short name T1238
Test name
Test status
Simulation time 19469050 ps
CPU time 0.7 seconds
Started Jul 11 04:26:03 PM PDT 24
Finished Jul 11 04:26:07 PM PDT 24
Peak memory 198860 kb
Host smart-fffbb741-6d2b-460f-834f-d30c4e485289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769353282 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2769353282
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3277816511
Short name T69
Test name
Test status
Simulation time 55687954 ps
CPU time 0.55 seconds
Started Jul 11 04:26:15 PM PDT 24
Finished Jul 11 04:26:17 PM PDT 24
Peak memory 195984 kb
Host smart-63517fc4-8888-4450-abef-33c96b1c8f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277816511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3277816511
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.4271028592
Short name T1234
Test name
Test status
Simulation time 13113555 ps
CPU time 0.55 seconds
Started Jul 11 04:26:32 PM PDT 24
Finished Jul 11 04:26:34 PM PDT 24
Peak memory 194556 kb
Host smart-37d6daa4-4b9a-4fbb-ba2b-8f39bd960b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271028592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4271028592
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.641460054
Short name T1237
Test name
Test status
Simulation time 36986751 ps
CPU time 0.71 seconds
Started Jul 11 04:26:03 PM PDT 24
Finished Jul 11 04:26:06 PM PDT 24
Peak memory 194176 kb
Host smart-67238c34-4147-486f-a2df-18993020c98d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641460054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.641460054
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1727380259
Short name T1211
Test name
Test status
Simulation time 27130332 ps
CPU time 1.61 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:48 PM PDT 24
Peak memory 198920 kb
Host smart-2a4bdc7d-0254-4d75-85e0-186ed7243ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727380259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1727380259
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.191918658
Short name T82
Test name
Test status
Simulation time 56177074 ps
CPU time 1 seconds
Started Jul 11 04:22:16 PM PDT 24
Finished Jul 11 04:22:17 PM PDT 24
Peak memory 200124 kb
Host smart-7d021660-060a-4f4e-ad5e-68490fedddf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191918658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.191918658
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2159919630
Short name T1203
Test name
Test status
Simulation time 12935616 ps
CPU time 0.56 seconds
Started Jul 11 04:26:38 PM PDT 24
Finished Jul 11 04:26:41 PM PDT 24
Peak memory 194628 kb
Host smart-2ece2b5a-5cfe-44fc-a8f0-e71ee3b7b2ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159919630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2159919630
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2362727127
Short name T1210
Test name
Test status
Simulation time 13075219 ps
CPU time 0.6 seconds
Started Jul 11 04:26:58 PM PDT 24
Finished Jul 11 04:27:00 PM PDT 24
Peak memory 194880 kb
Host smart-30df73be-4e7d-4380-a4d8-4ed0ec15f7ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362727127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2362727127
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.598515040
Short name T1308
Test name
Test status
Simulation time 13604972 ps
CPU time 0.57 seconds
Started Jul 11 04:25:29 PM PDT 24
Finished Jul 11 04:25:32 PM PDT 24
Peak memory 194868 kb
Host smart-dc64a3ea-c6a3-464b-872b-bab841c4589f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598515040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.598515040
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1380685643
Short name T1263
Test name
Test status
Simulation time 13727585 ps
CPU time 0.6 seconds
Started Jul 11 04:26:53 PM PDT 24
Finished Jul 11 04:26:55 PM PDT 24
Peak memory 193784 kb
Host smart-b388618b-e325-4dd0-8ec5-5c01a21581f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380685643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1380685643
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1131751082
Short name T1232
Test name
Test status
Simulation time 14368612 ps
CPU time 0.59 seconds
Started Jul 11 04:25:29 PM PDT 24
Finished Jul 11 04:25:32 PM PDT 24
Peak memory 194952 kb
Host smart-12c5a689-d752-43c1-9735-1c067c5af4da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131751082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1131751082
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3996613460
Short name T1191
Test name
Test status
Simulation time 31381799 ps
CPU time 0.58 seconds
Started Jul 11 04:26:38 PM PDT 24
Finished Jul 11 04:26:42 PM PDT 24
Peak memory 194636 kb
Host smart-80a77884-43cd-4c38-920c-f618af12bfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996613460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3996613460
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.4130797837
Short name T1296
Test name
Test status
Simulation time 15618618 ps
CPU time 0.58 seconds
Started Jul 11 04:26:50 PM PDT 24
Finished Jul 11 04:26:54 PM PDT 24
Peak memory 194932 kb
Host smart-ea131eea-31f3-4832-ad78-93a59c986871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130797837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4130797837
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2232496200
Short name T1188
Test name
Test status
Simulation time 141411608 ps
CPU time 0.54 seconds
Started Jul 11 04:26:38 PM PDT 24
Finished Jul 11 04:26:41 PM PDT 24
Peak memory 194564 kb
Host smart-3aaec893-8ace-44f1-98d0-1eaf738c6efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232496200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2232496200
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.797736107
Short name T1206
Test name
Test status
Simulation time 33858308 ps
CPU time 0.56 seconds
Started Jul 11 04:25:29 PM PDT 24
Finished Jul 11 04:25:32 PM PDT 24
Peak memory 194952 kb
Host smart-bde1a024-a275-4796-abd3-828b0616366c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797736107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.797736107
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3174627685
Short name T1303
Test name
Test status
Simulation time 14915084 ps
CPU time 0.65 seconds
Started Jul 11 04:26:37 PM PDT 24
Finished Jul 11 04:26:41 PM PDT 24
Peak memory 194112 kb
Host smart-e8ef024c-90df-4ead-9db7-75dd8701118c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174627685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3174627685
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.648177429
Short name T54
Test name
Test status
Simulation time 35771417 ps
CPU time 0.82 seconds
Started Jul 11 04:24:00 PM PDT 24
Finished Jul 11 04:24:02 PM PDT 24
Peak memory 196044 kb
Host smart-769602ee-2abe-4be2-a357-acf431f07cf6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648177429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.648177429
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1915038787
Short name T1274
Test name
Test status
Simulation time 958671395 ps
CPU time 2.69 seconds
Started Jul 11 04:26:23 PM PDT 24
Finished Jul 11 04:26:27 PM PDT 24
Peak memory 198184 kb
Host smart-30205e72-3e2d-4a5d-93e5-38bff71c7a7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915038787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1915038787
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3590490213
Short name T68
Test name
Test status
Simulation time 93002775 ps
CPU time 0.58 seconds
Started Jul 11 04:26:30 PM PDT 24
Finished Jul 11 04:26:33 PM PDT 24
Peak memory 195592 kb
Host smart-3b456678-5384-42f0-8fac-5cc150ed16f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590490213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3590490213
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3805390302
Short name T1200
Test name
Test status
Simulation time 21038649 ps
CPU time 0.68 seconds
Started Jul 11 04:26:31 PM PDT 24
Finished Jul 11 04:26:33 PM PDT 24
Peak memory 198048 kb
Host smart-811cd24d-8be1-475d-91d3-216f83a516e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805390302 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3805390302
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.921766155
Short name T1299
Test name
Test status
Simulation time 40528031 ps
CPU time 0.64 seconds
Started Jul 11 04:26:58 PM PDT 24
Finished Jul 11 04:27:00 PM PDT 24
Peak memory 195136 kb
Host smart-ce0bc4be-86dd-4cfc-b165-38efd6587ec6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921766155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.921766155
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1220931103
Short name T1292
Test name
Test status
Simulation time 16761456 ps
CPU time 0.61 seconds
Started Jul 11 04:23:51 PM PDT 24
Finished Jul 11 04:23:52 PM PDT 24
Peak memory 195284 kb
Host smart-b80bb5a8-a2f6-41b9-bd7a-49c6383ceda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220931103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1220931103
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1684346704
Short name T1288
Test name
Test status
Simulation time 229244012 ps
CPU time 0.67 seconds
Started Jul 11 04:25:05 PM PDT 24
Finished Jul 11 04:25:08 PM PDT 24
Peak memory 196516 kb
Host smart-ecadebf1-7763-4675-ace6-a10807b6d53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684346704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1684346704
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3619951004
Short name T1190
Test name
Test status
Simulation time 310623398 ps
CPU time 1.54 seconds
Started Jul 11 04:23:22 PM PDT 24
Finished Jul 11 04:23:24 PM PDT 24
Peak memory 200604 kb
Host smart-444bf92b-293c-4a48-a788-ca49e4739e37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619951004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3619951004
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.755951092
Short name T1189
Test name
Test status
Simulation time 10815778 ps
CPU time 0.57 seconds
Started Jul 11 04:25:29 PM PDT 24
Finished Jul 11 04:25:32 PM PDT 24
Peak memory 194964 kb
Host smart-4f8153a5-cfd7-4ab4-9660-fe8a1d250f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755951092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.755951092
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.815684540
Short name T1271
Test name
Test status
Simulation time 11233301 ps
CPU time 0.55 seconds
Started Jul 11 04:26:35 PM PDT 24
Finished Jul 11 04:26:38 PM PDT 24
Peak memory 193564 kb
Host smart-930e5e2d-8e4e-4b87-bfe8-e0dad8722b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815684540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.815684540
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3232948240
Short name T1225
Test name
Test status
Simulation time 12725035 ps
CPU time 0.66 seconds
Started Jul 11 04:26:34 PM PDT 24
Finished Jul 11 04:26:38 PM PDT 24
Peak memory 193240 kb
Host smart-7ea5590d-04c2-4e73-ae15-b7542c0549eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232948240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3232948240
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3953994360
Short name T1250
Test name
Test status
Simulation time 40873239 ps
CPU time 0.61 seconds
Started Jul 11 04:25:21 PM PDT 24
Finished Jul 11 04:25:22 PM PDT 24
Peak memory 195420 kb
Host smart-01fcd47f-15e9-4975-b406-2aec447b621c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953994360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3953994360
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1690665614
Short name T1285
Test name
Test status
Simulation time 17743278 ps
CPU time 0.56 seconds
Started Jul 11 04:26:35 PM PDT 24
Finished Jul 11 04:26:38 PM PDT 24
Peak memory 194592 kb
Host smart-c0222f96-3395-4ca8-a414-03ad9d093bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690665614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1690665614
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2623777543
Short name T1222
Test name
Test status
Simulation time 15180981 ps
CPU time 0.62 seconds
Started Jul 11 04:26:34 PM PDT 24
Finished Jul 11 04:26:38 PM PDT 24
Peak memory 192652 kb
Host smart-a83ec5d1-a6f4-4bbb-b320-eea542c004b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623777543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2623777543
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1612719176
Short name T1275
Test name
Test status
Simulation time 14002461 ps
CPU time 0.55 seconds
Started Jul 11 04:26:34 PM PDT 24
Finished Jul 11 04:26:38 PM PDT 24
Peak memory 193400 kb
Host smart-bf1fbc90-4e48-4440-ad9c-13a95afd51a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612719176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1612719176
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.687756723
Short name T1291
Test name
Test status
Simulation time 47390531 ps
CPU time 0.61 seconds
Started Jul 11 04:25:20 PM PDT 24
Finished Jul 11 04:25:22 PM PDT 24
Peak memory 195364 kb
Host smart-7e478f54-567a-4af6-b43a-7cc535bef10e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687756723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.687756723
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3897376451
Short name T1268
Test name
Test status
Simulation time 13160319 ps
CPU time 0.61 seconds
Started Jul 11 04:26:34 PM PDT 24
Finished Jul 11 04:26:38 PM PDT 24
Peak memory 192568 kb
Host smart-a6119eba-2458-4cfe-af7f-f65c4bd0d033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897376451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3897376451
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3380194901
Short name T1229
Test name
Test status
Simulation time 14226245 ps
CPU time 0.59 seconds
Started Jul 11 04:25:22 PM PDT 24
Finished Jul 11 04:25:24 PM PDT 24
Peak memory 194916 kb
Host smart-b097c7d8-c8a4-476f-a550-1cfb354a537b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380194901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3380194901
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2285571000
Short name T1218
Test name
Test status
Simulation time 19410956 ps
CPU time 0.78 seconds
Started Jul 11 04:24:46 PM PDT 24
Finished Jul 11 04:24:47 PM PDT 24
Peak memory 198520 kb
Host smart-5fb2e84a-d733-441b-b744-6be98e3d69fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285571000 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2285571000
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3987232842
Short name T56
Test name
Test status
Simulation time 34329802 ps
CPU time 0.66 seconds
Started Jul 11 04:26:08 PM PDT 24
Finished Jul 11 04:26:13 PM PDT 24
Peak memory 194744 kb
Host smart-27d90e36-1438-4feb-a75f-75a8a42009e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987232842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3987232842
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4170144946
Short name T1282
Test name
Test status
Simulation time 12429199 ps
CPU time 0.65 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:47 PM PDT 24
Peak memory 192988 kb
Host smart-256a0c5c-32be-424f-b6b1-342a2d0ea05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170144946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4170144946
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2756387220
Short name T76
Test name
Test status
Simulation time 363283735 ps
CPU time 0.8 seconds
Started Jul 11 04:26:08 PM PDT 24
Finished Jul 11 04:26:13 PM PDT 24
Peak memory 196416 kb
Host smart-807f4306-8b74-40d3-b3ee-7327c0293e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756387220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2756387220
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.574701695
Short name T1216
Test name
Test status
Simulation time 1034954346 ps
CPU time 1.88 seconds
Started Jul 11 04:24:20 PM PDT 24
Finished Jul 11 04:24:23 PM PDT 24
Peak memory 200604 kb
Host smart-3a30b4cf-da6a-42ec-8e63-293c9b61f7d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574701695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.574701695
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2293596385
Short name T114
Test name
Test status
Simulation time 175604528 ps
CPU time 0.91 seconds
Started Jul 11 04:26:11 PM PDT 24
Finished Jul 11 04:26:14 PM PDT 24
Peak memory 199376 kb
Host smart-e1bda3a0-6182-449f-a81f-228f114c1884
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293596385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2293596385
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.508322890
Short name T1233
Test name
Test status
Simulation time 30635878 ps
CPU time 0.92 seconds
Started Jul 11 04:26:53 PM PDT 24
Finished Jul 11 04:26:56 PM PDT 24
Peak memory 199292 kb
Host smart-40f273ef-4e3c-411e-a95d-b204b821fe05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508322890 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.508322890
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2194999120
Short name T1317
Test name
Test status
Simulation time 56545908 ps
CPU time 0.68 seconds
Started Jul 11 04:23:55 PM PDT 24
Finished Jul 11 04:23:56 PM PDT 24
Peak memory 194456 kb
Host smart-7781022b-fe23-49ec-9ed4-2ecc9896d28a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194999120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2194999120
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2984706770
Short name T1244
Test name
Test status
Simulation time 18558481 ps
CPU time 0.63 seconds
Started Jul 11 04:25:55 PM PDT 24
Finished Jul 11 04:25:58 PM PDT 24
Peak memory 194108 kb
Host smart-e4d338c2-ba16-4517-aeee-a46d166cde8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984706770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2984706770
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.199238337
Short name T72
Test name
Test status
Simulation time 16352988 ps
CPU time 0.69 seconds
Started Jul 11 04:26:57 PM PDT 24
Finished Jul 11 04:26:59 PM PDT 24
Peak memory 196712 kb
Host smart-97bafad6-d1c9-4bf3-8dea-0372a7a1a440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199238337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.199238337
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3054085811
Short name T1304
Test name
Test status
Simulation time 146250042 ps
CPU time 2.17 seconds
Started Jul 11 04:26:43 PM PDT 24
Finished Jul 11 04:26:49 PM PDT 24
Peak memory 199216 kb
Host smart-2b9175bd-2b54-4039-8071-4c261659b06e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054085811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3054085811
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3684142821
Short name T1266
Test name
Test status
Simulation time 41853066 ps
CPU time 0.9 seconds
Started Jul 11 04:26:55 PM PDT 24
Finished Jul 11 04:26:57 PM PDT 24
Peak memory 199512 kb
Host smart-8ce475c7-22fb-4f39-b9a0-3a9606e61445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684142821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3684142821
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2683684698
Short name T1204
Test name
Test status
Simulation time 53070351 ps
CPU time 0.84 seconds
Started Jul 11 04:25:46 PM PDT 24
Finished Jul 11 04:25:47 PM PDT 24
Peak memory 199936 kb
Host smart-b18c8ce2-68fb-469a-8b5f-3acbd00a09ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683684698 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2683684698
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1993424181
Short name T1295
Test name
Test status
Simulation time 41934761 ps
CPU time 0.63 seconds
Started Jul 11 04:23:55 PM PDT 24
Finished Jul 11 04:23:56 PM PDT 24
Peak memory 194072 kb
Host smart-a230e4b1-60a7-4eae-baf5-0f1595734256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993424181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1993424181
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.199621394
Short name T1255
Test name
Test status
Simulation time 62137485 ps
CPU time 0.56 seconds
Started Jul 11 04:26:09 PM PDT 24
Finished Jul 11 04:26:13 PM PDT 24
Peak memory 194888 kb
Host smart-f31d308b-25f1-49a3-a1c4-c75fbb8fcd18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199621394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.199621394
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1665218429
Short name T74
Test name
Test status
Simulation time 24276456 ps
CPU time 0.69 seconds
Started Jul 11 04:25:45 PM PDT 24
Finished Jul 11 04:25:47 PM PDT 24
Peak memory 194984 kb
Host smart-0611b805-dc3d-4a2d-af88-739f2a816315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665218429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1665218429
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.177021426
Short name T1279
Test name
Test status
Simulation time 865507311 ps
CPU time 2.49 seconds
Started Jul 11 04:23:55 PM PDT 24
Finished Jul 11 04:23:58 PM PDT 24
Peak memory 199004 kb
Host smart-8f5214a9-6cb8-4829-960a-d0ff128aebcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177021426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.177021426
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1724382082
Short name T88
Test name
Test status
Simulation time 196373316 ps
CPU time 1.37 seconds
Started Jul 11 04:25:59 PM PDT 24
Finished Jul 11 04:26:02 PM PDT 24
Peak memory 199788 kb
Host smart-dd99ea26-2372-45a7-abfe-f2b82df15115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724382082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1724382082
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4083322749
Short name T1306
Test name
Test status
Simulation time 22933630 ps
CPU time 0.84 seconds
Started Jul 11 04:26:48 PM PDT 24
Finished Jul 11 04:26:52 PM PDT 24
Peak memory 197756 kb
Host smart-4bc21012-5503-4019-975c-79a1c76f0382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083322749 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4083322749
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3508360656
Short name T1318
Test name
Test status
Simulation time 16477702 ps
CPU time 0.63 seconds
Started Jul 11 04:25:30 PM PDT 24
Finished Jul 11 04:25:33 PM PDT 24
Peak memory 195968 kb
Host smart-e4b50c60-4d35-418a-bfe0-556719abb705
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508360656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3508360656
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1802122331
Short name T1254
Test name
Test status
Simulation time 21717410 ps
CPU time 0.59 seconds
Started Jul 11 04:26:57 PM PDT 24
Finished Jul 11 04:26:59 PM PDT 24
Peak memory 194656 kb
Host smart-42c448fd-1e70-4a9d-baed-37526922c1e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802122331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1802122331
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4047426155
Short name T75
Test name
Test status
Simulation time 29688571 ps
CPU time 0.75 seconds
Started Jul 11 04:25:56 PM PDT 24
Finished Jul 11 04:25:58 PM PDT 24
Peak memory 197768 kb
Host smart-ceac4483-6205-418a-813f-ff32c8c5230b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047426155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4047426155
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3292947666
Short name T1227
Test name
Test status
Simulation time 843986510 ps
CPU time 2.2 seconds
Started Jul 11 04:25:45 PM PDT 24
Finished Jul 11 04:25:49 PM PDT 24
Peak memory 199420 kb
Host smart-ddecbe94-61af-4e77-88db-4b83a8d7d6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292947666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3292947666
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4201766553
Short name T1277
Test name
Test status
Simulation time 52771268 ps
CPU time 0.96 seconds
Started Jul 11 04:26:48 PM PDT 24
Finished Jul 11 04:26:53 PM PDT 24
Peak memory 197048 kb
Host smart-f9907bbd-7ff0-430a-b010-6bcca953f80f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201766553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4201766553
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1406911301
Short name T1247
Test name
Test status
Simulation time 32601145 ps
CPU time 0.77 seconds
Started Jul 11 04:26:15 PM PDT 24
Finished Jul 11 04:26:17 PM PDT 24
Peak memory 200404 kb
Host smart-2d27068c-02a8-4752-b5cc-e94ada6ea1dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406911301 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1406911301
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2404642780
Short name T1298
Test name
Test status
Simulation time 40719641 ps
CPU time 0.69 seconds
Started Jul 11 04:25:51 PM PDT 24
Finished Jul 11 04:25:52 PM PDT 24
Peak memory 195168 kb
Host smart-9747f8b5-5eae-4adc-961e-7319cba304ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404642780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2404642780
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2524164156
Short name T1256
Test name
Test status
Simulation time 32802938 ps
CPU time 0.63 seconds
Started Jul 11 04:26:48 PM PDT 24
Finished Jul 11 04:26:52 PM PDT 24
Peak memory 192752 kb
Host smart-1ff11cc1-5643-4b54-83c5-1fb212146c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524164156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2524164156
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2097903221
Short name T1283
Test name
Test status
Simulation time 41100646 ps
CPU time 0.65 seconds
Started Jul 11 04:24:07 PM PDT 24
Finished Jul 11 04:24:09 PM PDT 24
Peak memory 195972 kb
Host smart-e5720da1-bd76-4164-9286-fb651a38bb0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097903221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2097903221
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2364952807
Short name T1208
Test name
Test status
Simulation time 162263801 ps
CPU time 1.54 seconds
Started Jul 11 04:26:48 PM PDT 24
Finished Jul 11 04:26:53 PM PDT 24
Peak memory 198140 kb
Host smart-e8ffac73-0f3b-44ea-98fa-7292a862df71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364952807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2364952807
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3248622252
Short name T85
Test name
Test status
Simulation time 331224850 ps
CPU time 1 seconds
Started Jul 11 04:25:30 PM PDT 24
Finished Jul 11 04:25:34 PM PDT 24
Peak memory 199528 kb
Host smart-8d7ac062-c933-40bd-87f7-174cefa63076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248622252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3248622252
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2729839829
Short name T430
Test name
Test status
Simulation time 37753209 ps
CPU time 0.56 seconds
Started Jul 11 04:47:47 PM PDT 24
Finished Jul 11 04:47:56 PM PDT 24
Peak memory 194412 kb
Host smart-e91ca87d-d7e0-4009-996d-a8da5256ef78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729839829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2729839829
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1302339488
Short name T257
Test name
Test status
Simulation time 147401104505 ps
CPU time 36.54 seconds
Started Jul 11 04:47:53 PM PDT 24
Finished Jul 11 04:48:37 PM PDT 24
Peak memory 199924 kb
Host smart-ff7a58de-4239-48e9-a54a-8cd0ec2993cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302339488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1302339488
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1864778438
Short name T908
Test name
Test status
Simulation time 12970639066 ps
CPU time 20.07 seconds
Started Jul 11 04:47:48 PM PDT 24
Finished Jul 11 04:48:15 PM PDT 24
Peak memory 199920 kb
Host smart-a0078907-c1de-4aaa-a9dc-a74334a88537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864778438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1864778438
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.1967119720
Short name T306
Test name
Test status
Simulation time 26622020355 ps
CPU time 8.21 seconds
Started Jul 11 04:47:51 PM PDT 24
Finished Jul 11 04:48:06 PM PDT 24
Peak memory 199676 kb
Host smart-bf713a9c-86a2-4910-8000-4fc11e733924
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967119720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1967119720
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3422101611
Short name T832
Test name
Test status
Simulation time 60972402659 ps
CPU time 387.16 seconds
Started Jul 11 04:47:48 PM PDT 24
Finished Jul 11 04:54:22 PM PDT 24
Peak memory 199772 kb
Host smart-f49e1d7b-6a59-45bb-a16a-e35695727275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422101611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3422101611
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1223276066
Short name T336
Test name
Test status
Simulation time 10843191998 ps
CPU time 2.7 seconds
Started Jul 11 04:47:50 PM PDT 24
Finished Jul 11 04:48:00 PM PDT 24
Peak memory 199204 kb
Host smart-aae17923-3b4f-4cc7-9646-144618eef99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223276066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1223276066
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.4056778693
Short name T555
Test name
Test status
Simulation time 76863776358 ps
CPU time 128.44 seconds
Started Jul 11 04:47:47 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 198712 kb
Host smart-537159b3-b901-464a-bf5d-e655d426c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056778693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4056778693
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3898202650
Short name T358
Test name
Test status
Simulation time 7997494014 ps
CPU time 223.54 seconds
Started Jul 11 04:47:49 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 199820 kb
Host smart-9d48e160-f1ef-423b-8995-9d2220df59da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898202650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3898202650
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3163083234
Short name T556
Test name
Test status
Simulation time 5527526948 ps
CPU time 50.8 seconds
Started Jul 11 04:47:52 PM PDT 24
Finished Jul 11 04:48:50 PM PDT 24
Peak memory 199376 kb
Host smart-3d883398-1dfa-4457-81bc-94c0d2fca6b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163083234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3163083234
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1763215049
Short name T1058
Test name
Test status
Simulation time 18539156155 ps
CPU time 31.38 seconds
Started Jul 11 04:47:49 PM PDT 24
Finished Jul 11 04:48:27 PM PDT 24
Peak memory 199568 kb
Host smart-864e82c5-fcfb-47b9-8279-6c5098827125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763215049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1763215049
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.197663979
Short name T320
Test name
Test status
Simulation time 39204588332 ps
CPU time 30.79 seconds
Started Jul 11 04:47:46 PM PDT 24
Finished Jul 11 04:48:24 PM PDT 24
Peak memory 195868 kb
Host smart-29c0d103-6464-4068-972d-a20f12706535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197663979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.197663979
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2598312567
Short name T21
Test name
Test status
Simulation time 35858887 ps
CPU time 0.82 seconds
Started Jul 11 04:47:48 PM PDT 24
Finished Jul 11 04:47:56 PM PDT 24
Peak memory 218356 kb
Host smart-7773ca02-9724-4d24-9f38-329a09150fe8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598312567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2598312567
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.4290275118
Short name T1048
Test name
Test status
Simulation time 292758141 ps
CPU time 1.2 seconds
Started Jul 11 04:47:46 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 198644 kb
Host smart-eb23811c-492a-408d-89c6-a77e536b5c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290275118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4290275118
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.350098450
Short name T977
Test name
Test status
Simulation time 144762744131 ps
CPU time 273.47 seconds
Started Jul 11 04:47:48 PM PDT 24
Finished Jul 11 04:52:29 PM PDT 24
Peak memory 199820 kb
Host smart-c042d891-6d1e-4d82-9753-032595bc20cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350098450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.350098450
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3859245705
Short name T1044
Test name
Test status
Simulation time 136392285650 ps
CPU time 327 seconds
Started Jul 11 04:47:48 PM PDT 24
Finished Jul 11 04:53:22 PM PDT 24
Peak memory 216372 kb
Host smart-15bc5ea0-a85b-41e7-b2a5-a667c5abd7e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859245705 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3859245705
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2216516564
Short name T1030
Test name
Test status
Simulation time 1511805044 ps
CPU time 2.58 seconds
Started Jul 11 04:47:50 PM PDT 24
Finished Jul 11 04:48:00 PM PDT 24
Peak memory 198884 kb
Host smart-552eb492-ba62-4bf4-b83c-7864472b465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216516564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2216516564
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.446402418
Short name T973
Test name
Test status
Simulation time 4556770885 ps
CPU time 7.86 seconds
Started Jul 11 04:47:48 PM PDT 24
Finished Jul 11 04:48:03 PM PDT 24
Peak memory 199440 kb
Host smart-fca8f76b-d75e-4052-8e6a-a3d58daead04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446402418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.446402418
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2600376896
Short name T435
Test name
Test status
Simulation time 47509247 ps
CPU time 0.56 seconds
Started Jul 11 04:48:03 PM PDT 24
Finished Jul 11 04:48:08 PM PDT 24
Peak memory 195152 kb
Host smart-5f6ba086-75fd-4396-9e76-7e2dfe2dac05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600376896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2600376896
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1277809825
Short name T913
Test name
Test status
Simulation time 91757128558 ps
CPU time 118.86 seconds
Started Jul 11 04:47:50 PM PDT 24
Finished Jul 11 04:49:56 PM PDT 24
Peak memory 199836 kb
Host smart-28dae778-bb3d-4e8e-8877-f9ff1877db53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277809825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1277809825
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1226011412
Short name T61
Test name
Test status
Simulation time 77742765437 ps
CPU time 32.91 seconds
Started Jul 11 04:47:49 PM PDT 24
Finished Jul 11 04:48:29 PM PDT 24
Peak memory 199832 kb
Host smart-3f23838f-9e71-4cb6-9cf4-b83f52e2b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226011412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1226011412
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3415496378
Short name T824
Test name
Test status
Simulation time 26680001648 ps
CPU time 44.41 seconds
Started Jul 11 04:47:52 PM PDT 24
Finished Jul 11 04:48:43 PM PDT 24
Peak memory 199724 kb
Host smart-2fff5172-7d3a-40ef-bdbe-de83db81a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415496378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3415496378
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.517724980
Short name T930
Test name
Test status
Simulation time 33594718594 ps
CPU time 50.83 seconds
Started Jul 11 04:47:47 PM PDT 24
Finished Jul 11 04:48:45 PM PDT 24
Peak memory 199236 kb
Host smart-81738b79-7424-4bb5-b612-9b8482a7350f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517724980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.517724980
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.834670515
Short name T823
Test name
Test status
Simulation time 91014355135 ps
CPU time 202.15 seconds
Started Jul 11 04:47:53 PM PDT 24
Finished Jul 11 04:51:22 PM PDT 24
Peak memory 199896 kb
Host smart-423f2809-324e-4c78-a644-b999489b1e53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834670515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.834670515
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.361602020
Short name T572
Test name
Test status
Simulation time 5240543913 ps
CPU time 9.25 seconds
Started Jul 11 04:47:58 PM PDT 24
Finished Jul 11 04:48:13 PM PDT 24
Peak memory 197932 kb
Host smart-97c12884-c0f6-4047-857a-a2c61a65254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361602020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.361602020
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.4148095973
Short name T292
Test name
Test status
Simulation time 89119370671 ps
CPU time 46.61 seconds
Started Jul 11 04:47:54 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 199596 kb
Host smart-261c84a1-2c25-4ee5-89de-c849edcc7301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148095973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4148095973
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3942778901
Short name T523
Test name
Test status
Simulation time 2947157498 ps
CPU time 83.12 seconds
Started Jul 11 04:47:59 PM PDT 24
Finished Jul 11 04:49:29 PM PDT 24
Peak memory 199716 kb
Host smart-30c4cf3a-0fad-41d3-aeef-91d98363e976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942778901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3942778901
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.292360386
Short name T489
Test name
Test status
Simulation time 3831566675 ps
CPU time 28.12 seconds
Started Jul 11 04:47:47 PM PDT 24
Finished Jul 11 04:48:23 PM PDT 24
Peak memory 198692 kb
Host smart-a596a5bb-84c7-446e-b73d-7009f59f3fd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292360386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.292360386
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.201228705
Short name T445
Test name
Test status
Simulation time 41554418562 ps
CPU time 6.29 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:48:16 PM PDT 24
Peak memory 199432 kb
Host smart-4c725be0-b9e5-4e3a-b347-3cdcf8255c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201228705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.201228705
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.733470100
Short name T1116
Test name
Test status
Simulation time 29524910244 ps
CPU time 45.84 seconds
Started Jul 11 04:47:58 PM PDT 24
Finished Jul 11 04:48:50 PM PDT 24
Peak memory 195892 kb
Host smart-6cebda4e-b41b-4236-97d5-35ea7bbf92c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733470100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.733470100
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2976441723
Short name T92
Test name
Test status
Simulation time 448061097 ps
CPU time 0.87 seconds
Started Jul 11 04:47:49 PM PDT 24
Finished Jul 11 04:47:57 PM PDT 24
Peak memory 218232 kb
Host smart-b0ebb309-6428-4063-8b56-09f33a5c149a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976441723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2976441723
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1316900773
Short name T1020
Test name
Test status
Simulation time 119751609 ps
CPU time 0.77 seconds
Started Jul 11 04:47:46 PM PDT 24
Finished Jul 11 04:47:55 PM PDT 24
Peak memory 196820 kb
Host smart-3be2b6a0-44fe-48e0-a673-c57531416e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316900773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1316900773
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3465944635
Short name T819
Test name
Test status
Simulation time 180758343051 ps
CPU time 379.68 seconds
Started Jul 11 04:47:53 PM PDT 24
Finished Jul 11 04:54:19 PM PDT 24
Peak memory 199776 kb
Host smart-afb3d4ad-8f95-46fa-aadc-6e48534a67f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465944635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3465944635
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.11992648
Short name T627
Test name
Test status
Simulation time 51853456244 ps
CPU time 312.24 seconds
Started Jul 11 04:47:52 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 215912 kb
Host smart-5fff28d1-2ba3-4a30-bc4a-d5af1612fbe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11992648 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.11992648
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2739134313
Short name T628
Test name
Test status
Simulation time 2874974320 ps
CPU time 2.12 seconds
Started Jul 11 04:47:49 PM PDT 24
Finished Jul 11 04:47:58 PM PDT 24
Peak memory 198424 kb
Host smart-ec127870-e5ee-4425-91a2-a6f24824497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739134313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2739134313
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3649559413
Short name T892
Test name
Test status
Simulation time 17189875344 ps
CPU time 35.04 seconds
Started Jul 11 04:47:53 PM PDT 24
Finished Jul 11 04:48:34 PM PDT 24
Peak memory 199848 kb
Host smart-760d1d06-48a8-4cf7-8bc9-2b81797507fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649559413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3649559413
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3932370668
Short name T651
Test name
Test status
Simulation time 43948712 ps
CPU time 0.54 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:48:30 PM PDT 24
Peak memory 195516 kb
Host smart-f27e3703-d4df-4a94-a070-2eaa9cd1d0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932370668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3932370668
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.495495668
Short name T996
Test name
Test status
Simulation time 79970752115 ps
CPU time 116.77 seconds
Started Jul 11 04:48:15 PM PDT 24
Finished Jul 11 04:50:16 PM PDT 24
Peak memory 199860 kb
Host smart-f9560a06-386e-4e5a-a5c1-6e39cec7dcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495495668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.495495668
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3300437302
Short name T941
Test name
Test status
Simulation time 91472720074 ps
CPU time 12.57 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:48:34 PM PDT 24
Peak memory 199864 kb
Host smart-1ee9b629-3d62-4b47-95bb-0985cd6f3430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300437302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3300437302
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3791427585
Short name T734
Test name
Test status
Simulation time 41501239541 ps
CPU time 55.68 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:49:26 PM PDT 24
Peak memory 199788 kb
Host smart-dcb6264f-b4e4-4b7b-8de1-2a0ef815fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791427585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3791427585
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2221111336
Short name T1096
Test name
Test status
Simulation time 25653373316 ps
CPU time 5.81 seconds
Started Jul 11 04:48:14 PM PDT 24
Finished Jul 11 04:48:24 PM PDT 24
Peak memory 199580 kb
Host smart-f01ffce6-3ca5-4409-9dd8-ee52fea6659b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221111336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2221111336
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3820374089
Short name T425
Test name
Test status
Simulation time 62317697917 ps
CPU time 325.85 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:53:58 PM PDT 24
Peak memory 199736 kb
Host smart-d409a0f1-e1b4-4334-b28d-37b0d687d4da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820374089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3820374089
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.4160401983
Short name T339
Test name
Test status
Simulation time 3918820841 ps
CPU time 7.27 seconds
Started Jul 11 04:48:20 PM PDT 24
Finished Jul 11 04:48:33 PM PDT 24
Peak memory 199892 kb
Host smart-92abb9ee-273d-44b6-b7d5-7a309848e80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160401983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4160401983
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1821492167
Short name T936
Test name
Test status
Simulation time 66703856518 ps
CPU time 35.6 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:49:00 PM PDT 24
Peak memory 199076 kb
Host smart-49b20490-dbd0-4217-a70c-85200291f55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821492167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1821492167
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.726612703
Short name T360
Test name
Test status
Simulation time 11646657047 ps
CPU time 158.51 seconds
Started Jul 11 04:48:14 PM PDT 24
Finished Jul 11 04:50:56 PM PDT 24
Peak memory 199752 kb
Host smart-f2ab0d2c-b83d-419f-a7f3-6a545ca491c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726612703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.726612703
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1752315944
Short name T1086
Test name
Test status
Simulation time 3452374047 ps
CPU time 18.24 seconds
Started Jul 11 04:48:20 PM PDT 24
Finished Jul 11 04:48:44 PM PDT 24
Peak memory 198080 kb
Host smart-3f0cf108-b087-4283-a3a6-30786c4d8f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752315944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1752315944
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1382736281
Short name T378
Test name
Test status
Simulation time 13858580139 ps
CPU time 13.59 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 199816 kb
Host smart-c3290557-0310-477a-bf88-abc42a363183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382736281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1382736281
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3625974342
Short name T1095
Test name
Test status
Simulation time 4569793014 ps
CPU time 3.83 seconds
Started Jul 11 04:48:14 PM PDT 24
Finished Jul 11 04:48:21 PM PDT 24
Peak memory 195960 kb
Host smart-1837ee3b-239e-4e4f-92d2-14a025092f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625974342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3625974342
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1632300097
Short name T730
Test name
Test status
Simulation time 842366467 ps
CPU time 3.17 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:48:28 PM PDT 24
Peak memory 199464 kb
Host smart-8e75d100-c1ce-4178-b097-24f51162da67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632300097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1632300097
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2331365386
Short name T428
Test name
Test status
Simulation time 43084208977 ps
CPU time 682.7 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:59:45 PM PDT 24
Peak memory 216544 kb
Host smart-23402390-d490-49aa-9b23-e6fd87405880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331365386 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2331365386
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.688652357
Short name T475
Test name
Test status
Simulation time 864473243 ps
CPU time 1.87 seconds
Started Jul 11 04:48:21 PM PDT 24
Finished Jul 11 04:48:29 PM PDT 24
Peak memory 198292 kb
Host smart-70b3bbe0-0bc6-4b41-b41f-cd4415db09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688652357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.688652357
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1871358815
Short name T35
Test name
Test status
Simulation time 115984018729 ps
CPU time 15.67 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:48:50 PM PDT 24
Peak memory 199864 kb
Host smart-8621caa3-29e9-4a00-a5cd-c26b76df6fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871358815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1871358815
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1150051401
Short name T993
Test name
Test status
Simulation time 87750393431 ps
CPU time 87.41 seconds
Started Jul 11 04:50:28 PM PDT 24
Finished Jul 11 04:51:57 PM PDT 24
Peak memory 199800 kb
Host smart-cbac5087-dd51-47b0-a061-0dc93f04da6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150051401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1150051401
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.4199737528
Short name T226
Test name
Test status
Simulation time 77295617345 ps
CPU time 39.6 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:51:12 PM PDT 24
Peak memory 199820 kb
Host smart-afe5f405-55a6-45c1-a1dd-c35567354857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199737528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4199737528
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.203312698
Short name T182
Test name
Test status
Simulation time 119083303605 ps
CPU time 167.44 seconds
Started Jul 11 04:50:36 PM PDT 24
Finished Jul 11 04:53:28 PM PDT 24
Peak memory 199588 kb
Host smart-8d90bc78-ea73-41c0-acb4-26ff239ea38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203312698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.203312698
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.4207016639
Short name T686
Test name
Test status
Simulation time 16102735849 ps
CPU time 23.73 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:50:55 PM PDT 24
Peak memory 199876 kb
Host smart-220ab5cd-8ab5-4abf-a23f-36c1ab07e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207016639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4207016639
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2320195720
Short name T120
Test name
Test status
Simulation time 80600826516 ps
CPU time 32.84 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:51:05 PM PDT 24
Peak memory 199908 kb
Host smart-8cf03c5b-691e-4b01-a04b-d8070ba6e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320195720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2320195720
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1622244342
Short name T108
Test name
Test status
Simulation time 36580717141 ps
CPU time 17.43 seconds
Started Jul 11 04:50:36 PM PDT 24
Finished Jul 11 04:50:58 PM PDT 24
Peak memory 199640 kb
Host smart-292079a5-7e00-4177-a66b-2653afaf5e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622244342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1622244342
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3444865109
Short name T644
Test name
Test status
Simulation time 17258854630 ps
CPU time 28.72 seconds
Started Jul 11 04:50:30 PM PDT 24
Finished Jul 11 04:51:01 PM PDT 24
Peak memory 199780 kb
Host smart-b2e941bf-33ef-4d30-883b-529215fb6ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444865109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3444865109
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2582424031
Short name T252
Test name
Test status
Simulation time 477800601765 ps
CPU time 39.72 seconds
Started Jul 11 04:50:31 PM PDT 24
Finished Jul 11 04:51:14 PM PDT 24
Peak memory 199884 kb
Host smart-c9de9f97-c599-46b5-8e54-535bdf0c5d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582424031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2582424031
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4220780106
Short name T241
Test name
Test status
Simulation time 69823752657 ps
CPU time 30.74 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:51:17 PM PDT 24
Peak memory 199908 kb
Host smart-f53d07a5-c8b1-4297-a732-5086e02b1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220780106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4220780106
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.794896976
Short name T1040
Test name
Test status
Simulation time 81080135181 ps
CPU time 15.26 seconds
Started Jul 11 04:48:18 PM PDT 24
Finished Jul 11 04:48:38 PM PDT 24
Peak memory 199416 kb
Host smart-b8119285-7dad-4aac-b147-423bfa4062bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794896976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.794896976
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.18158650
Short name T1017
Test name
Test status
Simulation time 8803782107 ps
CPU time 17.71 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 04:48:56 PM PDT 24
Peak memory 199864 kb
Host smart-51d08970-5bf9-4869-afec-ebd035e62bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18158650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.18158650
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.714181401
Short name T1016
Test name
Test status
Simulation time 41358730841 ps
CPU time 18.8 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 199920 kb
Host smart-17feccd8-2d47-455e-863d-8c6d17c9acdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714181401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.714181401
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1264925972
Short name T877
Test name
Test status
Simulation time 54549288864 ps
CPU time 83.79 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 199820 kb
Host smart-be7755d0-21ea-46c0-88ba-8fcb05ad9724
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264925972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1264925972
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2790658644
Short name T357
Test name
Test status
Simulation time 42737182086 ps
CPU time 177.99 seconds
Started Jul 11 04:48:16 PM PDT 24
Finished Jul 11 04:51:19 PM PDT 24
Peak memory 199892 kb
Host smart-b39ea5ca-3e83-4bff-b864-3237860bbc2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790658644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2790658644
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2529522076
Short name T853
Test name
Test status
Simulation time 4525175769 ps
CPU time 9.37 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:48:34 PM PDT 24
Peak memory 198456 kb
Host smart-0f607836-9a87-4992-896b-fee06692a7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529522076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2529522076
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2842060701
Short name T395
Test name
Test status
Simulation time 34716678683 ps
CPU time 57.7 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:57 PM PDT 24
Peak memory 199860 kb
Host smart-3a3b0834-98a0-4a5e-897f-17cbbcd1b05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842060701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2842060701
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2244476427
Short name T492
Test name
Test status
Simulation time 16676904955 ps
CPU time 510.33 seconds
Started Jul 11 04:48:11 PM PDT 24
Finished Jul 11 04:56:46 PM PDT 24
Peak memory 199756 kb
Host smart-a49e1916-73b0-4531-96e8-6cefbd04e706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244476427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2244476427
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3805894588
Short name T1152
Test name
Test status
Simulation time 1824420586 ps
CPU time 2.98 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:48:27 PM PDT 24
Peak memory 198704 kb
Host smart-de440529-662d-4d4a-9aaf-5f2bc6b09750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805894588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3805894588
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2373321112
Short name T821
Test name
Test status
Simulation time 73883548053 ps
CPU time 119.37 seconds
Started Jul 11 04:48:13 PM PDT 24
Finished Jul 11 04:50:16 PM PDT 24
Peak memory 199788 kb
Host smart-a9c358e5-e914-4514-ab72-33bc94f71e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373321112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2373321112
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1388525752
Short name T431
Test name
Test status
Simulation time 35048897112 ps
CPU time 12.6 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 04:48:28 PM PDT 24
Peak memory 195720 kb
Host smart-6dd81b58-4270-402b-a6a8-e507ea50d715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388525752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1388525752
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2401079045
Short name T675
Test name
Test status
Simulation time 11092787964 ps
CPU time 39.98 seconds
Started Jul 11 04:48:12 PM PDT 24
Finished Jul 11 04:48:57 PM PDT 24
Peak memory 199784 kb
Host smart-6075a857-779f-4045-a83c-b98e27b2b1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401079045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2401079045
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3708639299
Short name T1089
Test name
Test status
Simulation time 315462758681 ps
CPU time 365.76 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 199768 kb
Host smart-34cb0306-89c6-48df-88b4-e119666cc82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708639299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3708639299
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.486030065
Short name T1129
Test name
Test status
Simulation time 248635852774 ps
CPU time 1088.05 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 05:06:32 PM PDT 24
Peak memory 216512 kb
Host smart-efd15e11-cafe-4892-8eb7-c9ec67587771
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486030065 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.486030065
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3355085102
Short name T614
Test name
Test status
Simulation time 1558602321 ps
CPU time 1.52 seconds
Started Jul 11 04:48:18 PM PDT 24
Finished Jul 11 04:48:24 PM PDT 24
Peak memory 198260 kb
Host smart-c34736e8-d225-431a-a556-4264ab64060f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355085102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3355085102
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3111400726
Short name T285
Test name
Test status
Simulation time 73390833089 ps
CPU time 96.93 seconds
Started Jul 11 04:48:18 PM PDT 24
Finished Jul 11 04:49:59 PM PDT 24
Peak memory 199828 kb
Host smart-ea975f4b-1028-4019-bc2c-2b2292dd70b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111400726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3111400726
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2667540395
Short name T971
Test name
Test status
Simulation time 40441372999 ps
CPU time 47.74 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:51:19 PM PDT 24
Peak memory 199912 kb
Host smart-54dcb898-ecd2-43a8-b393-0eb5e6444658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667540395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2667540395
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1441642125
Short name T193
Test name
Test status
Simulation time 79902336793 ps
CPU time 242.62 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:54:34 PM PDT 24
Peak memory 199876 kb
Host smart-d4f5bcee-cb41-4c04-a862-753e31258a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441642125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1441642125
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.354855522
Short name T487
Test name
Test status
Simulation time 56355944976 ps
CPU time 85.89 seconds
Started Jul 11 04:50:27 PM PDT 24
Finished Jul 11 04:51:54 PM PDT 24
Peak memory 199808 kb
Host smart-56e4bce5-aa58-4b65-a657-13df58560a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354855522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.354855522
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.613673064
Short name T134
Test name
Test status
Simulation time 45943801704 ps
CPU time 45.97 seconds
Started Jul 11 04:50:31 PM PDT 24
Finished Jul 11 04:51:21 PM PDT 24
Peak memory 199756 kb
Host smart-12c1b5e7-0021-40c4-a38d-acb7cce16eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613673064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.613673064
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3059033140
Short name T129
Test name
Test status
Simulation time 171575399482 ps
CPU time 73.16 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:51:59 PM PDT 24
Peak memory 199864 kb
Host smart-c557c948-3f08-4fad-818c-caf7c11948e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059033140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3059033140
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.721318627
Short name T653
Test name
Test status
Simulation time 41226678973 ps
CPU time 18.96 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:50:50 PM PDT 24
Peak memory 199656 kb
Host smart-ef26e0ba-5149-497d-a37e-026b3cfb3e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721318627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.721318627
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2655696981
Short name T1090
Test name
Test status
Simulation time 36940419863 ps
CPU time 127.42 seconds
Started Jul 11 04:50:34 PM PDT 24
Finished Jul 11 04:52:46 PM PDT 24
Peak memory 199840 kb
Host smart-83ea5653-8d4a-4f3d-a346-566c88a722bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655696981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2655696981
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1497472106
Short name T1037
Test name
Test status
Simulation time 43523831237 ps
CPU time 81.55 seconds
Started Jul 11 04:50:34 PM PDT 24
Finished Jul 11 04:52:00 PM PDT 24
Peak memory 199868 kb
Host smart-6b361776-582e-4444-bbea-84c87a32de82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497472106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1497472106
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2539641002
Short name T702
Test name
Test status
Simulation time 13588727 ps
CPU time 0.58 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:48:25 PM PDT 24
Peak memory 195232 kb
Host smart-d8fcf21d-22a0-4f7a-8289-fd63b04c3290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539641002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2539641002
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.339895821
Short name T732
Test name
Test status
Simulation time 229698703621 ps
CPU time 204.03 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 199828 kb
Host smart-7c476005-fb1c-46f3-ad5e-48d53a7ae0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339895821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.339895821
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3408560066
Short name T885
Test name
Test status
Simulation time 7427683576 ps
CPU time 11.47 seconds
Started Jul 11 04:48:16 PM PDT 24
Finished Jul 11 04:48:32 PM PDT 24
Peak memory 199816 kb
Host smart-061332ea-8f3b-4e15-bb87-1228daf31920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408560066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3408560066
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2640371953
Short name T830
Test name
Test status
Simulation time 159476196284 ps
CPU time 223.25 seconds
Started Jul 11 04:48:08 PM PDT 24
Finished Jul 11 04:51:55 PM PDT 24
Peak memory 199872 kb
Host smart-066e86e2-6e25-431c-a819-ae2ce81967d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640371953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2640371953
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2647307646
Short name T580
Test name
Test status
Simulation time 17101577033 ps
CPU time 17.06 seconds
Started Jul 11 04:48:16 PM PDT 24
Finished Jul 11 04:48:38 PM PDT 24
Peak memory 199724 kb
Host smart-8eca5c53-438f-4323-a200-e2b0c4c4664c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647307646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2647307646
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3957918916
Short name T1142
Test name
Test status
Simulation time 167522925179 ps
CPU time 620.34 seconds
Started Jul 11 04:48:20 PM PDT 24
Finished Jul 11 04:58:46 PM PDT 24
Peak memory 200180 kb
Host smart-6f941ebe-0de2-4fde-aeb0-05313425e3aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3957918916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3957918916
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1916077424
Short name T866
Test name
Test status
Simulation time 7737908429 ps
CPU time 5.4 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:48:40 PM PDT 24
Peak memory 198004 kb
Host smart-afc4a07f-e700-4b49-9a9e-ae3eeb61b821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916077424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1916077424
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3944385780
Short name T1145
Test name
Test status
Simulation time 56438607659 ps
CPU time 73.11 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:49:35 PM PDT 24
Peak memory 199728 kb
Host smart-923166e8-93ef-49a6-8fd4-a260918ba9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944385780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3944385780
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1659594773
Short name T1002
Test name
Test status
Simulation time 28123749014 ps
CPU time 78.33 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:49:40 PM PDT 24
Peak memory 199836 kb
Host smart-53f23099-e066-43f2-9915-02cbe34b655c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659594773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1659594773
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1226301219
Short name T911
Test name
Test status
Simulation time 4975279491 ps
CPU time 49.09 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:49:13 PM PDT 24
Peak memory 198320 kb
Host smart-c91388ad-2353-41fc-8600-673abe54aa63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226301219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1226301219
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.267680639
Short name T769
Test name
Test status
Simulation time 182751145625 ps
CPU time 77.16 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:49:52 PM PDT 24
Peak memory 199916 kb
Host smart-f36b85b3-cd0c-4d4c-859c-fdba6639a0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267680639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.267680639
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.4037849955
Short name T454
Test name
Test status
Simulation time 2918301982 ps
CPU time 4.49 seconds
Started Jul 11 04:48:16 PM PDT 24
Finished Jul 11 04:48:24 PM PDT 24
Peak memory 195788 kb
Host smart-ffe6b34a-2fb8-40b3-89e5-63d3940fc163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037849955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.4037849955
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.8735228
Short name T602
Test name
Test status
Simulation time 534486124 ps
CPU time 1.93 seconds
Started Jul 11 04:48:15 PM PDT 24
Finished Jul 11 04:48:20 PM PDT 24
Peak memory 199116 kb
Host smart-edc378c7-2e2e-4bf5-86c1-8b35edf124f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8735228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.8735228
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1436103827
Short name T149
Test name
Test status
Simulation time 324389446463 ps
CPU time 129.99 seconds
Started Jul 11 04:48:18 PM PDT 24
Finished Jul 11 04:50:33 PM PDT 24
Peak memory 199472 kb
Host smart-ddff0c6b-98e2-43bc-ad7e-fcdeed7b4f5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436103827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1436103827
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2433399109
Short name T843
Test name
Test status
Simulation time 8477010438 ps
CPU time 10.13 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:48:51 PM PDT 24
Peak memory 199816 kb
Host smart-d1f78132-549e-481a-99a6-ea1428e1dd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433399109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2433399109
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1923819913
Short name T1014
Test name
Test status
Simulation time 24422154195 ps
CPU time 20.24 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:48:41 PM PDT 24
Peak memory 197872 kb
Host smart-53142f14-1f5d-4843-9640-cf2fcdc45235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923819913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1923819913
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.438767636
Short name T197
Test name
Test status
Simulation time 97237105188 ps
CPU time 185.2 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:53:37 PM PDT 24
Peak memory 199744 kb
Host smart-76ccf2a6-3ed3-4ba5-abf6-4a7a37038baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438767636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.438767636
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2599246829
Short name T131
Test name
Test status
Simulation time 16890288931 ps
CPU time 26.82 seconds
Started Jul 11 04:50:32 PM PDT 24
Finished Jul 11 04:51:03 PM PDT 24
Peak memory 199832 kb
Host smart-9a105dd9-5e01-44c8-aaa7-e80b9e25b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599246829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2599246829
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3149517016
Short name T259
Test name
Test status
Simulation time 168518220208 ps
CPU time 245.32 seconds
Started Jul 11 04:50:33 PM PDT 24
Finished Jul 11 04:54:44 PM PDT 24
Peak memory 199768 kb
Host smart-ac7e9c83-dce6-489e-b2d2-39ba514ad839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149517016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3149517016
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2113264875
Short name T791
Test name
Test status
Simulation time 182714732724 ps
CPU time 135.01 seconds
Started Jul 11 04:50:32 PM PDT 24
Finished Jul 11 04:52:52 PM PDT 24
Peak memory 200132 kb
Host smart-bda20213-7384-4e88-9d9c-72039d676fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113264875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2113264875
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1861563476
Short name T1033
Test name
Test status
Simulation time 3213222565 ps
CPU time 4.05 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:50:36 PM PDT 24
Peak memory 199856 kb
Host smart-342625bf-a069-4bab-bb3b-3e883284b7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861563476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1861563476
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3684070553
Short name T117
Test name
Test status
Simulation time 94052370810 ps
CPU time 149.26 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:53:15 PM PDT 24
Peak memory 199836 kb
Host smart-68da3d80-761e-4e49-9034-22cff288212a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684070553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3684070553
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2710014915
Short name T496
Test name
Test status
Simulation time 141682989315 ps
CPU time 110.13 seconds
Started Jul 11 04:50:30 PM PDT 24
Finished Jul 11 04:52:23 PM PDT 24
Peak memory 199684 kb
Host smart-2b6bdaec-0d25-4de3-8952-99fda2f7c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710014915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2710014915
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3779235708
Short name T1147
Test name
Test status
Simulation time 113648623477 ps
CPU time 48.51 seconds
Started Jul 11 04:50:28 PM PDT 24
Finished Jul 11 04:51:19 PM PDT 24
Peak memory 199868 kb
Host smart-05fc24bf-2bf7-476a-8d42-d833efea0447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779235708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3779235708
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1406805527
Short name T631
Test name
Test status
Simulation time 12929793 ps
CPU time 0.56 seconds
Started Jul 11 04:48:16 PM PDT 24
Finished Jul 11 04:48:21 PM PDT 24
Peak memory 195232 kb
Host smart-c2ebec64-d518-4ad8-9f89-d19f997a5e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406805527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1406805527
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1226853081
Short name T868
Test name
Test status
Simulation time 55821635935 ps
CPU time 22.4 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:48:56 PM PDT 24
Peak memory 199820 kb
Host smart-38c8dbcf-8826-4139-ba22-fb3b86d5c961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226853081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1226853081
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2571116594
Short name T856
Test name
Test status
Simulation time 86929164396 ps
CPU time 105.18 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:50:10 PM PDT 24
Peak memory 199880 kb
Host smart-452e4840-a78f-45fa-9297-df7607b41cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571116594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2571116594
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2913821921
Short name T696
Test name
Test status
Simulation time 198018601862 ps
CPU time 288.79 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:53:19 PM PDT 24
Peak memory 199916 kb
Host smart-467a8def-6df4-4c6a-b254-8d5444002b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913821921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2913821921
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3404504721
Short name T338
Test name
Test status
Simulation time 9341537879 ps
CPU time 13.56 seconds
Started Jul 11 04:48:16 PM PDT 24
Finished Jul 11 04:48:34 PM PDT 24
Peak memory 196772 kb
Host smart-c891d2b7-f19e-4c06-8dfd-25c643c4f208
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404504721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3404504721
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3713949830
Short name T937
Test name
Test status
Simulation time 135475913259 ps
CPU time 859.07 seconds
Started Jul 11 04:48:36 PM PDT 24
Finished Jul 11 05:03:03 PM PDT 24
Peak memory 199692 kb
Host smart-c2b46346-5b7a-426d-934a-949c62a6769f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713949830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3713949830
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.526425295
Short name T1180
Test name
Test status
Simulation time 8828986529 ps
CPU time 11.98 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:48:46 PM PDT 24
Peak memory 199664 kb
Host smart-cfad582b-9df6-4e61-8aa7-94e53bc0db86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526425295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.526425295
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3320131593
Short name T716
Test name
Test status
Simulation time 52751899175 ps
CPU time 119.62 seconds
Started Jul 11 04:48:15 PM PDT 24
Finished Jul 11 04:50:18 PM PDT 24
Peak memory 199968 kb
Host smart-76ad0f0b-c057-41a9-943d-eac571d801ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320131593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3320131593
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1911289104
Short name T264
Test name
Test status
Simulation time 25182923429 ps
CPU time 219.99 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:52:12 PM PDT 24
Peak memory 199732 kb
Host smart-f258a527-427f-4f57-a5d7-a0662b87ac45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911289104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1911289104
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1535578175
Short name T956
Test name
Test status
Simulation time 3189531224 ps
CPU time 6.37 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:48:28 PM PDT 24
Peak memory 198936 kb
Host smart-29773a8b-ffb5-4376-809b-5e79aeb8b6ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535578175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1535578175
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.4196975999
Short name T1012
Test name
Test status
Simulation time 360719415541 ps
CPU time 141.59 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:50:58 PM PDT 24
Peak memory 199796 kb
Host smart-4f2ba3e6-8898-4af4-b7c2-615107db42b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196975999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4196975999
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2519006990
Short name T879
Test name
Test status
Simulation time 2414639069 ps
CPU time 2.2 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:48:37 PM PDT 24
Peak memory 195884 kb
Host smart-0cbb26a6-0664-4413-a2c1-35604d46d8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519006990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2519006990
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1446477039
Short name T793
Test name
Test status
Simulation time 5817012157 ps
CPU time 21.32 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:49:15 PM PDT 24
Peak memory 199876 kb
Host smart-b0d5ebcb-b7e0-4ffe-9ab0-ec754da88a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446477039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1446477039
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1149002423
Short name T910
Test name
Test status
Simulation time 567432222491 ps
CPU time 580.61 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:58:21 PM PDT 24
Peak memory 225884 kb
Host smart-059cefdf-0bef-458c-b497-a5137c5ebb23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149002423 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1149002423
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2520978248
Short name T603
Test name
Test status
Simulation time 7464451284 ps
CPU time 16 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:48:40 PM PDT 24
Peak memory 199652 kb
Host smart-5220c5fd-3ac5-4ee9-8388-5036299661ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520978248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2520978248
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1184322215
Short name T861
Test name
Test status
Simulation time 104980479237 ps
CPU time 62.38 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:49:25 PM PDT 24
Peak memory 199824 kb
Host smart-556a69f1-c14b-4280-8718-e0bbeaf4d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184322215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1184322215
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2743493335
Short name T704
Test name
Test status
Simulation time 151844569987 ps
CPU time 67.46 seconds
Started Jul 11 04:50:30 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 199836 kb
Host smart-0407b2b6-e4a8-4fc2-b2f7-54c4dd9f6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743493335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2743493335
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1773446239
Short name T864
Test name
Test status
Simulation time 100029319705 ps
CPU time 14.26 seconds
Started Jul 11 04:50:34 PM PDT 24
Finished Jul 11 04:50:53 PM PDT 24
Peak memory 199720 kb
Host smart-2f891646-a3a2-4de5-9972-42f71b8f7180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773446239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1773446239
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.220700262
Short name T895
Test name
Test status
Simulation time 44252419856 ps
CPU time 61.72 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:51:33 PM PDT 24
Peak memory 199804 kb
Host smart-bacc01d9-905d-47b3-9924-c7b476de5a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220700262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.220700262
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.4110932902
Short name T554
Test name
Test status
Simulation time 43662727132 ps
CPU time 61.74 seconds
Started Jul 11 04:50:29 PM PDT 24
Finished Jul 11 04:51:33 PM PDT 24
Peak memory 199828 kb
Host smart-777df480-d3f7-4386-ad95-06e563a53195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110932902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4110932902
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.287494725
Short name T763
Test name
Test status
Simulation time 24890004366 ps
CPU time 18.55 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:51:05 PM PDT 24
Peak memory 199800 kb
Host smart-4845315f-5d81-49a3-b669-3b90e273dae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287494725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.287494725
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.649938643
Short name T1000
Test name
Test status
Simulation time 137005059143 ps
CPU time 210.55 seconds
Started Jul 11 04:50:44 PM PDT 24
Finished Jul 11 04:54:18 PM PDT 24
Peak memory 199840 kb
Host smart-705a15a7-1862-4315-abe9-1f058f1eca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649938643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.649938643
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3398781878
Short name T405
Test name
Test status
Simulation time 18033636202 ps
CPU time 15.59 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:51:01 PM PDT 24
Peak memory 199732 kb
Host smart-07e2f0ec-cc0e-4129-8da4-608b7dc4223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398781878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3398781878
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1713436715
Short name T251
Test name
Test status
Simulation time 77633929515 ps
CPU time 16.41 seconds
Started Jul 11 04:50:44 PM PDT 24
Finished Jul 11 04:51:03 PM PDT 24
Peak memory 199860 kb
Host smart-7feabd42-48e7-437d-b210-42d38ad08a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713436715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1713436715
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2739732635
Short name T327
Test name
Test status
Simulation time 14747055304 ps
CPU time 25.96 seconds
Started Jul 11 04:50:44 PM PDT 24
Finished Jul 11 04:51:13 PM PDT 24
Peak memory 199924 kb
Host smart-4d6b4162-111e-4116-8021-b3a248c409f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739732635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2739732635
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3580614663
Short name T1107
Test name
Test status
Simulation time 137721543 ps
CPU time 0.54 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 04:48:38 PM PDT 24
Peak memory 195168 kb
Host smart-ea0c8ad5-5118-492f-9b38-e8ad20ea7e36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580614663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3580614663
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1262804958
Short name T736
Test name
Test status
Simulation time 107612791721 ps
CPU time 263.31 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:52:52 PM PDT 24
Peak memory 199772 kb
Host smart-8659591d-49c4-4281-920a-584c99f98799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262804958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1262804958
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.226102080
Short name T974
Test name
Test status
Simulation time 115768093918 ps
CPU time 40.14 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:49:16 PM PDT 24
Peak memory 199428 kb
Host smart-bea90894-2356-4a92-883e-9bee0507baf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226102080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.226102080
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3996120524
Short name T195
Test name
Test status
Simulation time 137744452527 ps
CPU time 71.73 seconds
Started Jul 11 04:48:21 PM PDT 24
Finished Jul 11 04:49:39 PM PDT 24
Peak memory 199696 kb
Host smart-6c237920-ff7a-45ab-8ec1-e068e1c993bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996120524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3996120524
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2088754965
Short name T649
Test name
Test status
Simulation time 55208373151 ps
CPU time 95.61 seconds
Started Jul 11 04:48:21 PM PDT 24
Finished Jul 11 04:50:03 PM PDT 24
Peak memory 199904 kb
Host smart-f6a7d939-d248-49fd-86d6-8df1d03e5a32
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088754965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2088754965
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1601684133
Short name T513
Test name
Test status
Simulation time 40062066731 ps
CPU time 183.49 seconds
Started Jul 11 04:48:21 PM PDT 24
Finished Jul 11 04:51:30 PM PDT 24
Peak memory 199884 kb
Host smart-b98ada46-1df5-4c91-969a-19fb55677e5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1601684133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1601684133
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3748433695
Short name T797
Test name
Test status
Simulation time 7384911893 ps
CPU time 11.57 seconds
Started Jul 11 04:48:30 PM PDT 24
Finished Jul 11 04:48:51 PM PDT 24
Peak memory 198276 kb
Host smart-e2fa7edd-9bb2-4496-9a1c-bc82c45cbb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748433695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3748433695
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1624301704
Short name T1184
Test name
Test status
Simulation time 48357896643 ps
CPU time 80.76 seconds
Started Jul 11 04:48:34 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 200068 kb
Host smart-d2d6f4af-01d4-4cd7-b86b-eb08e84a635d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624301704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1624301704
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2192079053
Short name T1019
Test name
Test status
Simulation time 14047117254 ps
CPU time 150.18 seconds
Started Jul 11 04:48:15 PM PDT 24
Finished Jul 11 04:50:49 PM PDT 24
Peak memory 199888 kb
Host smart-62754014-8732-42e0-99c1-360eabe5e2b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192079053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2192079053
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3283373694
Short name T897
Test name
Test status
Simulation time 4456014513 ps
CPU time 39.33 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:49:09 PM PDT 24
Peak memory 199064 kb
Host smart-7a3c215b-9914-483e-b1c3-a9aec26dd5ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3283373694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3283373694
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3852430062
Short name T289
Test name
Test status
Simulation time 93855874713 ps
CPU time 160.52 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:51:13 PM PDT 24
Peak memory 199848 kb
Host smart-67ce8cd5-a498-4b1b-8bb7-c5dbda8240c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852430062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3852430062
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3692468451
Short name T787
Test name
Test status
Simulation time 4889897129 ps
CPU time 7.84 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:45 PM PDT 24
Peak memory 195884 kb
Host smart-e059c6b9-2210-4a3f-9d05-eb426f574dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692468451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3692468451
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1997191329
Short name T585
Test name
Test status
Simulation time 671197713 ps
CPU time 2.1 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:48:24 PM PDT 24
Peak memory 198268 kb
Host smart-5b9596d4-d69f-4375-bc08-53df7b53be20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997191329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1997191329
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1839948830
Short name T170
Test name
Test status
Simulation time 930103011696 ps
CPU time 1370.42 seconds
Started Jul 11 04:48:34 PM PDT 24
Finished Jul 11 05:11:33 PM PDT 24
Peak memory 229552 kb
Host smart-7a5a778e-ea51-451e-8491-b71a270a95f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839948830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1839948830
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2887948181
Short name T391
Test name
Test status
Simulation time 345099403 ps
CPU time 1.36 seconds
Started Jul 11 04:48:33 PM PDT 24
Finished Jul 11 04:48:43 PM PDT 24
Peak memory 197892 kb
Host smart-2058ae65-4e90-4778-98f9-30315cde2b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887948181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2887948181
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2764593353
Short name T497
Test name
Test status
Simulation time 68500971262 ps
CPU time 48.79 seconds
Started Jul 11 04:48:34 PM PDT 24
Finished Jul 11 04:49:32 PM PDT 24
Peak memory 199828 kb
Host smart-bf60e4a5-8127-480c-afb5-f1c9b125ae8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764593353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2764593353
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.496437293
Short name T1106
Test name
Test status
Simulation time 50617493796 ps
CPU time 69.44 seconds
Started Jul 11 04:50:43 PM PDT 24
Finished Jul 11 04:51:56 PM PDT 24
Peak memory 199852 kb
Host smart-2df17a0c-d774-4ef3-9991-acbe4c563311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496437293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.496437293
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2462993524
Short name T521
Test name
Test status
Simulation time 44565256764 ps
CPU time 66.07 seconds
Started Jul 11 04:50:44 PM PDT 24
Finished Jul 11 04:51:54 PM PDT 24
Peak memory 200172 kb
Host smart-243ab71e-cc81-41b8-aeb5-0f51608e1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462993524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2462993524
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3625453854
Short name T865
Test name
Test status
Simulation time 54995601846 ps
CPU time 86.38 seconds
Started Jul 11 04:50:43 PM PDT 24
Finished Jul 11 04:52:13 PM PDT 24
Peak memory 199752 kb
Host smart-942b7258-79d2-41ec-a1d0-d2002e9cd6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625453854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3625453854
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.348579407
Short name T1050
Test name
Test status
Simulation time 183504898105 ps
CPU time 86.6 seconds
Started Jul 11 04:50:41 PM PDT 24
Finished Jul 11 04:52:11 PM PDT 24
Peak memory 199920 kb
Host smart-29492b6a-bffd-4e1e-94e7-7ac3b5cfee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348579407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.348579407
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2558891944
Short name T309
Test name
Test status
Simulation time 166905821754 ps
CPU time 72.79 seconds
Started Jul 11 04:50:41 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 199888 kb
Host smart-001f597f-c93f-4395-90c9-e54d8c8d57e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558891944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2558891944
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1552366924
Short name T710
Test name
Test status
Simulation time 44950134561 ps
CPU time 35.85 seconds
Started Jul 11 04:50:41 PM PDT 24
Finished Jul 11 04:51:21 PM PDT 24
Peak memory 199764 kb
Host smart-858423f9-a240-4f7d-846b-c53d7cb94b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552366924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1552366924
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1884754651
Short name T227
Test name
Test status
Simulation time 17351398970 ps
CPU time 27.93 seconds
Started Jul 11 04:50:45 PM PDT 24
Finished Jul 11 04:51:15 PM PDT 24
Peak memory 200168 kb
Host smart-8ed68fe1-38d1-48a4-aafe-7c361ab7fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884754651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1884754651
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2922725516
Short name T161
Test name
Test status
Simulation time 96992435807 ps
CPU time 156.77 seconds
Started Jul 11 04:50:43 PM PDT 24
Finished Jul 11 04:53:23 PM PDT 24
Peak memory 199860 kb
Host smart-a7b4f3bd-7b28-48f8-a6d5-4f66e2333928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922725516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2922725516
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.632310687
Short name T393
Test name
Test status
Simulation time 45387762 ps
CPU time 0.56 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:48:32 PM PDT 24
Peak memory 195224 kb
Host smart-b17f4035-9ee8-4c22-826d-ca50a519ac96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632310687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.632310687
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.404752163
Short name T689
Test name
Test status
Simulation time 83085846807 ps
CPU time 30.4 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 199832 kb
Host smart-1e906546-73a3-4b93-8f97-06b3cb877739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404752163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.404752163
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2498627950
Short name T370
Test name
Test status
Simulation time 34884716188 ps
CPU time 32.16 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:49:07 PM PDT 24
Peak memory 199808 kb
Host smart-6352f103-2cc8-4ce1-a1b1-a6f1c0ea3980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498627950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2498627950
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1872776686
Short name T413
Test name
Test status
Simulation time 38385383094 ps
CPU time 30.88 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:49:08 PM PDT 24
Peak memory 199640 kb
Host smart-cd0acb40-763a-4bd1-add5-4656b858dae2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872776686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1872776686
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1912005500
Short name T377
Test name
Test status
Simulation time 120781239576 ps
CPU time 721.17 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 05:00:33 PM PDT 24
Peak memory 199836 kb
Host smart-b8836db9-f68a-451c-9342-3fa65b53dbc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912005500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1912005500
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2429562603
Short name T722
Test name
Test status
Simulation time 10351586842 ps
CPU time 6.07 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:48:39 PM PDT 24
Peak memory 198524 kb
Host smart-512a8040-06d5-4f28-81c9-80a26cc52728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429562603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2429562603
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1599400516
Short name T118
Test name
Test status
Simulation time 135701877480 ps
CPU time 62.44 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:49:46 PM PDT 24
Peak memory 215460 kb
Host smart-eba936cb-db34-4c08-aa6a-28cad067f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599400516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1599400516
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2967818993
Short name T1169
Test name
Test status
Simulation time 19143818969 ps
CPU time 62.29 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 04:49:41 PM PDT 24
Peak memory 199900 kb
Host smart-fd77d2a0-6939-4173-9894-2df9f2c775a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967818993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2967818993
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3403026530
Short name T371
Test name
Test status
Simulation time 2187905829 ps
CPU time 8.87 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:48:37 PM PDT 24
Peak memory 198028 kb
Host smart-c02ea331-53a1-48f7-9618-d3ef71f7a324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403026530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3403026530
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1858499923
Short name T3
Test name
Test status
Simulation time 89609242974 ps
CPU time 31.67 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:49:07 PM PDT 24
Peak memory 199772 kb
Host smart-51ab0131-e1ab-4244-8af4-20e15f52078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858499923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1858499923
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.351553122
Short name T918
Test name
Test status
Simulation time 5126795814 ps
CPU time 2.72 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:48:37 PM PDT 24
Peak memory 196040 kb
Host smart-c832bc50-7eb8-4911-8597-82a39619d3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351553122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.351553122
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2486160090
Short name T703
Test name
Test status
Simulation time 470654898 ps
CPU time 2.47 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:48:34 PM PDT 24
Peak memory 198788 kb
Host smart-4ba0e64b-72fe-430b-921a-b9f86fa4da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486160090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2486160090
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1257236104
Short name T863
Test name
Test status
Simulation time 71530148252 ps
CPU time 103.97 seconds
Started Jul 11 04:48:29 PM PDT 24
Finished Jul 11 04:50:23 PM PDT 24
Peak memory 199888 kb
Host smart-f5c58d41-bc53-463c-81b6-a6fa876c1fb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257236104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1257236104
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1448277379
Short name T10
Test name
Test status
Simulation time 71607158615 ps
CPU time 402.24 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:55:13 PM PDT 24
Peak memory 216340 kb
Host smart-0e36412a-3e9b-4072-b3c0-fe8651880a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448277379 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1448277379
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.425885496
Short name T1036
Test name
Test status
Simulation time 711822393 ps
CPU time 2.65 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:40 PM PDT 24
Peak memory 198688 kb
Host smart-426d4b2a-b4ae-4cf0-a0da-26a87ac410cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425885496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.425885496
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1992286869
Short name T606
Test name
Test status
Simulation time 79899939587 ps
CPU time 184.83 seconds
Started Jul 11 04:48:29 PM PDT 24
Finished Jul 11 04:51:44 PM PDT 24
Peak memory 199868 kb
Host smart-c4c091b2-0d34-4704-8a4b-a71ab0696ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992286869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1992286869
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3058767390
Short name T635
Test name
Test status
Simulation time 42907711598 ps
CPU time 103.67 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:52:30 PM PDT 24
Peak memory 199828 kb
Host smart-1139aeab-f6f1-4d7b-bcda-b15aaceb84e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058767390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3058767390
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3380618334
Short name T590
Test name
Test status
Simulation time 15259217663 ps
CPU time 21.69 seconds
Started Jul 11 04:50:45 PM PDT 24
Finished Jul 11 04:51:10 PM PDT 24
Peak memory 199836 kb
Host smart-203eec9b-90af-4b5a-92cf-70c2270343e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380618334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3380618334
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3442239297
Short name T186
Test name
Test status
Simulation time 26935017604 ps
CPU time 47.74 seconds
Started Jul 11 04:50:40 PM PDT 24
Finished Jul 11 04:51:32 PM PDT 24
Peak memory 199840 kb
Host smart-0fee2ecd-67ec-4bdf-8b79-f9ec657ca6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442239297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3442239297
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3237300134
Short name T335
Test name
Test status
Simulation time 83255975545 ps
CPU time 72.63 seconds
Started Jul 11 04:50:41 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 199816 kb
Host smart-7bd03c8a-a56a-41f4-abb4-d951bdadf4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237300134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3237300134
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.226963248
Short name T1148
Test name
Test status
Simulation time 35820129428 ps
CPU time 69.21 seconds
Started Jul 11 04:50:41 PM PDT 24
Finished Jul 11 04:51:54 PM PDT 24
Peak memory 199848 kb
Host smart-6e07321d-991e-49f8-bb33-3b48f8b42684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226963248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.226963248
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.155522124
Short name T498
Test name
Test status
Simulation time 193016536185 ps
CPU time 48.43 seconds
Started Jul 11 04:50:40 PM PDT 24
Finished Jul 11 04:51:33 PM PDT 24
Peak memory 199728 kb
Host smart-5776329b-2424-4acd-98f5-dcad50cc7b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155522124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.155522124
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.778366813
Short name T191
Test name
Test status
Simulation time 14320081167 ps
CPU time 23.33 seconds
Started Jul 11 04:50:44 PM PDT 24
Finished Jul 11 04:51:11 PM PDT 24
Peak memory 199952 kb
Host smart-64dc6922-4972-48e6-8c37-900707d95682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778366813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.778366813
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.284791009
Short name T904
Test name
Test status
Simulation time 36145717474 ps
CPU time 13.8 seconds
Started Jul 11 04:50:39 PM PDT 24
Finished Jul 11 04:50:57 PM PDT 24
Peak memory 199632 kb
Host smart-20457323-851d-46e6-8441-83f48dcacd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284791009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.284791009
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.225597592
Short name T527
Test name
Test status
Simulation time 120974722860 ps
CPU time 100.9 seconds
Started Jul 11 04:50:43 PM PDT 24
Finished Jul 11 04:52:27 PM PDT 24
Peak memory 199824 kb
Host smart-6f3d0cab-ad45-4484-a72a-3b8978ddcf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225597592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.225597592
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2594285602
Short name T1028
Test name
Test status
Simulation time 12166823 ps
CPU time 0.6 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:37 PM PDT 24
Peak memory 195436 kb
Host smart-5301de9f-8f68-45e3-92f7-ba907f5d4378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594285602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2594285602
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3039664244
Short name T608
Test name
Test status
Simulation time 112897593643 ps
CPU time 37.94 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:49:21 PM PDT 24
Peak memory 199716 kb
Host smart-231f4593-3aec-4737-b6c7-024fed356fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039664244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3039664244
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1722723248
Short name T248
Test name
Test status
Simulation time 10774114260 ps
CPU time 5.02 seconds
Started Jul 11 04:48:29 PM PDT 24
Finished Jul 11 04:48:43 PM PDT 24
Peak memory 198856 kb
Host smart-e769993c-9c6a-46f5-8683-262e3cdce6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722723248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1722723248
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2739504596
Short name T349
Test name
Test status
Simulation time 37737757938 ps
CPU time 7.16 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:48:48 PM PDT 24
Peak memory 199232 kb
Host smart-18e71f8c-912d-4715-bfbf-20c4309b08ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739504596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2739504596
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.4151788496
Short name T62
Test name
Test status
Simulation time 272490833784 ps
CPU time 113.46 seconds
Started Jul 11 04:48:32 PM PDT 24
Finished Jul 11 04:50:35 PM PDT 24
Peak memory 199764 kb
Host smart-e4079f25-f1b1-48cc-9415-70da83d459cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151788496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.4151788496
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2693634485
Short name T767
Test name
Test status
Simulation time 4166565009 ps
CPU time 4.59 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 04:48:42 PM PDT 24
Peak memory 199300 kb
Host smart-edd85aa3-4100-4724-98ae-4dd8839fb9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693634485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2693634485
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3754626241
Short name T410
Test name
Test status
Simulation time 32516489391 ps
CPU time 11.86 seconds
Started Jul 11 04:48:48 PM PDT 24
Finished Jul 11 04:49:07 PM PDT 24
Peak memory 194980 kb
Host smart-472a1270-70a2-4fc3-944e-4208dc770888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754626241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3754626241
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1332268963
Short name T1119
Test name
Test status
Simulation time 13565791596 ps
CPU time 819.47 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 05:02:17 PM PDT 24
Peak memory 199864 kb
Host smart-a570b12f-8947-4e38-8b06-b29cf7eb8458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332268963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1332268963
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1039559746
Short name T779
Test name
Test status
Simulation time 4625498806 ps
CPU time 6.5 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 198192 kb
Host smart-0d62eca0-98ee-4f0e-b032-f31e9226e2bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039559746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1039559746
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2892444789
Short name T568
Test name
Test status
Simulation time 86197122041 ps
CPU time 91.99 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:50:10 PM PDT 24
Peak memory 200200 kb
Host smart-10812b28-d560-4e7e-acdd-67b47f37c29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892444789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2892444789
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2461959003
Short name T715
Test name
Test status
Simulation time 3165480717 ps
CPU time 1.92 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:38 PM PDT 24
Peak memory 196408 kb
Host smart-a8de6190-6f1f-48cd-b70c-9cf8743867f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461959003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2461959003
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2398224279
Short name T30
Test name
Test status
Simulation time 671544266 ps
CPU time 1.45 seconds
Started Jul 11 04:48:30 PM PDT 24
Finished Jul 11 04:48:41 PM PDT 24
Peak memory 198316 kb
Host smart-ebb30d58-80d1-4b25-96ed-ed6593bbfcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398224279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2398224279
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.128057950
Short name T138
Test name
Test status
Simulation time 325003060149 ps
CPU time 182.22 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:51:38 PM PDT 24
Peak memory 199732 kb
Host smart-c0dc040f-4594-4c9c-9d88-30f89f5c9667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128057950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.128057950
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1234974631
Short name T807
Test name
Test status
Simulation time 2247425032 ps
CPU time 2.93 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:48:32 PM PDT 24
Peak memory 198752 kb
Host smart-534d381c-aea3-4827-814f-f3bb809e93ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234974631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1234974631
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2070963129
Short name T1091
Test name
Test status
Simulation time 42005760134 ps
CPU time 62.93 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:49:39 PM PDT 24
Peak memory 199848 kb
Host smart-41b1d484-35fe-42d1-bb28-fdbf1b71fad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070963129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2070963129
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2066460657
Short name T717
Test name
Test status
Simulation time 31161435524 ps
CPU time 42.72 seconds
Started Jul 11 04:50:43 PM PDT 24
Finished Jul 11 04:51:29 PM PDT 24
Peak memory 199832 kb
Host smart-a30611b9-65e9-42b4-9d57-e4967db23df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066460657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2066460657
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1843587597
Short name T1009
Test name
Test status
Simulation time 25261184801 ps
CPU time 13.8 seconds
Started Jul 11 04:50:45 PM PDT 24
Finished Jul 11 04:51:02 PM PDT 24
Peak memory 199852 kb
Host smart-fbf82b5f-3b2a-48e0-9c00-e918e8f1a0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843587597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1843587597
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2089828259
Short name T526
Test name
Test status
Simulation time 13251504643 ps
CPU time 20.16 seconds
Started Jul 11 04:50:45 PM PDT 24
Finished Jul 11 04:51:08 PM PDT 24
Peak memory 199856 kb
Host smart-6631902f-e96b-4f3f-a088-bff5de94a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089828259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2089828259
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.828692338
Short name T130
Test name
Test status
Simulation time 66382317199 ps
CPU time 8.7 seconds
Started Jul 11 04:50:49 PM PDT 24
Finished Jul 11 04:50:58 PM PDT 24
Peak memory 199580 kb
Host smart-cd130b04-ca4b-4e90-8a5b-36d00779be81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828692338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.828692338
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1189576659
Short name T375
Test name
Test status
Simulation time 70275061153 ps
CPU time 91.09 seconds
Started Jul 11 04:50:44 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 199720 kb
Host smart-8cb92b43-e991-46a1-ac5c-723546eaa635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189576659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1189576659
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3684816785
Short name T605
Test name
Test status
Simulation time 43687056874 ps
CPU time 77.41 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:52:03 PM PDT 24
Peak memory 199800 kb
Host smart-191060aa-d9fe-4084-9f1d-a4db385400f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684816785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3684816785
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2980982407
Short name T951
Test name
Test status
Simulation time 221086270815 ps
CPU time 62.51 seconds
Started Jul 11 04:50:42 PM PDT 24
Finished Jul 11 04:51:48 PM PDT 24
Peak memory 199860 kb
Host smart-e235b51b-5dff-4123-b3ba-0a85d2d927be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980982407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2980982407
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.675305766
Short name T206
Test name
Test status
Simulation time 43899247670 ps
CPU time 71.33 seconds
Started Jul 11 04:50:50 PM PDT 24
Finished Jul 11 04:52:02 PM PDT 24
Peak memory 199900 kb
Host smart-f72e366e-6db4-4810-9be6-0b46becaaa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675305766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.675305766
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1756631677
Short name T350
Test name
Test status
Simulation time 71181634 ps
CPU time 0.54 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:48:33 PM PDT 24
Peak memory 194124 kb
Host smart-ddad3960-936d-4ab0-ac6e-a0eb6fd70467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756631677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1756631677
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.527593784
Short name T1068
Test name
Test status
Simulation time 23636620359 ps
CPU time 7.68 seconds
Started Jul 11 04:48:20 PM PDT 24
Finished Jul 11 04:48:34 PM PDT 24
Peak memory 199796 kb
Host smart-a0d42e84-59ee-4995-87d9-acc562e2a9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527593784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.527593784
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1185796186
Short name T165
Test name
Test status
Simulation time 11993148566 ps
CPU time 12.69 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:48:44 PM PDT 24
Peak memory 199616 kb
Host smart-4e37ccf8-f5f0-4b10-9b80-e890c7c2a414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185796186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1185796186
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.4151453480
Short name T584
Test name
Test status
Simulation time 174911949439 ps
CPU time 101.78 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:50:25 PM PDT 24
Peak memory 199832 kb
Host smart-6b2b6003-ded8-422c-831c-e6a9d208e265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151453480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.4151453480
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3701772391
Short name T1085
Test name
Test status
Simulation time 25925704705 ps
CPU time 13.63 seconds
Started Jul 11 04:48:34 PM PDT 24
Finished Jul 11 04:48:56 PM PDT 24
Peak memory 199352 kb
Host smart-043c5471-45c2-4818-a8cc-ade4fb4a95f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701772391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3701772391
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3531163148
Short name T365
Test name
Test status
Simulation time 101131630962 ps
CPU time 467.26 seconds
Started Jul 11 04:48:36 PM PDT 24
Finished Jul 11 04:56:31 PM PDT 24
Peak memory 199820 kb
Host smart-8b271458-97da-49c6-91f6-256b77c3c18a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531163148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3531163148
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2269599947
Short name T684
Test name
Test status
Simulation time 2048955298 ps
CPU time 2.49 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:48:43 PM PDT 24
Peak memory 198376 kb
Host smart-971525c1-3f05-41a6-97f5-1ffcb4eabe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269599947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2269599947
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2833453534
Short name T870
Test name
Test status
Simulation time 156600111969 ps
CPU time 70.31 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 200240 kb
Host smart-185791e5-54f4-485e-ad19-beb2d56f8660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833453534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2833453534
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3750521548
Short name T749
Test name
Test status
Simulation time 24326371859 ps
CPU time 328.21 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:54:09 PM PDT 24
Peak memory 199780 kb
Host smart-a7204724-2ca2-4ab2-bfa7-9225b22213df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750521548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3750521548
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.616953383
Short name T403
Test name
Test status
Simulation time 3042447842 ps
CPU time 19.02 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 198988 kb
Host smart-68f8ed8b-84a0-42a9-a652-f78bb60f2dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616953383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.616953383
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1289770326
Short name T1077
Test name
Test status
Simulation time 42738269378 ps
CPU time 60.22 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:49:36 PM PDT 24
Peak memory 195712 kb
Host smart-e572b0d1-f5f7-41ef-9eea-959255f696f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289770326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1289770326
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1199420491
Short name T99
Test name
Test status
Simulation time 522500248 ps
CPU time 1.69 seconds
Started Jul 11 04:48:29 PM PDT 24
Finished Jul 11 04:48:41 PM PDT 24
Peak memory 198672 kb
Host smart-d930b130-ae02-4541-b41d-78c0b0c86487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199420491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1199420491
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.480876471
Short name T414
Test name
Test status
Simulation time 460505229787 ps
CPU time 50.42 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:49:22 PM PDT 24
Peak memory 208228 kb
Host smart-cd4a362a-5774-4346-a57e-cd9c8eff5662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480876471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.480876471
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1056365538
Short name T110
Test name
Test status
Simulation time 135168093008 ps
CPU time 315.69 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:53:52 PM PDT 24
Peak memory 216292 kb
Host smart-cf05dacf-96b0-4c69-b39f-16d3242c3628
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056365538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1056365538
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3891319649
Short name T758
Test name
Test status
Simulation time 6069030040 ps
CPU time 18.21 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 199628 kb
Host smart-29c75b02-c328-446f-830c-2c67a14c2f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891319649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3891319649
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2695246961
Short name T724
Test name
Test status
Simulation time 28153480700 ps
CPU time 51.85 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 04:49:30 PM PDT 24
Peak memory 199872 kb
Host smart-6e15e06a-3f17-48a8-91d7-ab69b0be33f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695246961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2695246961
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.4026669489
Short name T184
Test name
Test status
Simulation time 125750395928 ps
CPU time 245.5 seconds
Started Jul 11 04:50:49 PM PDT 24
Finished Jul 11 04:54:56 PM PDT 24
Peak memory 199780 kb
Host smart-0367cc82-5bb1-45e9-810a-1be81c3eaa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026669489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4026669489
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2377439278
Short name T233
Test name
Test status
Simulation time 172266307880 ps
CPU time 217.28 seconds
Started Jul 11 04:50:49 PM PDT 24
Finished Jul 11 04:54:27 PM PDT 24
Peak memory 199896 kb
Host smart-3de7fd2f-fd3e-450f-9209-dd8fe6b489e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377439278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2377439278
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.92342069
Short name T1137
Test name
Test status
Simulation time 6023083622 ps
CPU time 9.68 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:51:03 PM PDT 24
Peak memory 197252 kb
Host smart-1fba5f2e-f549-4cf2-8ddb-6c09a2f08dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92342069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.92342069
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2194235927
Short name T63
Test name
Test status
Simulation time 21061136127 ps
CPU time 28.71 seconds
Started Jul 11 04:50:52 PM PDT 24
Finished Jul 11 04:51:25 PM PDT 24
Peak memory 199712 kb
Host smart-66a248d2-71c2-446a-948d-bdfd6e629fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194235927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2194235927
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3359222694
Short name T263
Test name
Test status
Simulation time 16558351269 ps
CPU time 12.97 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:51:05 PM PDT 24
Peak memory 199832 kb
Host smart-71eb44a9-0661-4c3a-9178-965628cdff8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359222694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3359222694
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.4239913439
Short name T1078
Test name
Test status
Simulation time 208184331220 ps
CPU time 225.81 seconds
Started Jul 11 04:50:52 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 199776 kb
Host smart-3e1a19ba-62a0-408a-a2c4-478fc0dd8114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239913439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4239913439
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2625971912
Short name T780
Test name
Test status
Simulation time 13386231443 ps
CPU time 19.87 seconds
Started Jul 11 04:50:52 PM PDT 24
Finished Jul 11 04:51:14 PM PDT 24
Peak memory 199832 kb
Host smart-317f6c08-9b90-4738-a52c-9f7b71c99aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625971912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2625971912
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.860467409
Short name T808
Test name
Test status
Simulation time 15131820802 ps
CPU time 24.08 seconds
Started Jul 11 04:50:49 PM PDT 24
Finished Jul 11 04:51:14 PM PDT 24
Peak memory 199820 kb
Host smart-4a8c1aaa-f071-4822-ad51-05bd4b3686f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860467409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.860467409
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.4116204894
Short name T1174
Test name
Test status
Simulation time 62834351844 ps
CPU time 12.11 seconds
Started Jul 11 04:50:50 PM PDT 24
Finished Jul 11 04:51:04 PM PDT 24
Peak memory 199832 kb
Host smart-6e0922f0-d1b7-4a0a-9317-65c74773f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116204894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.4116204894
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1709576045
Short name T756
Test name
Test status
Simulation time 14260415 ps
CPU time 0.57 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:48:53 PM PDT 24
Peak memory 195500 kb
Host smart-a15330ac-6a7c-4f9f-9607-06d79c4a3d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709576045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1709576045
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2264850162
Short name T692
Test name
Test status
Simulation time 109683247318 ps
CPU time 41.02 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:49:10 PM PDT 24
Peak memory 199700 kb
Host smart-51bcc70b-7352-4c20-a9cc-3d54c72ea7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264850162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2264850162
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.947046023
Short name T265
Test name
Test status
Simulation time 173918874153 ps
CPU time 61.31 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:49:32 PM PDT 24
Peak memory 199832 kb
Host smart-722985b2-c2d9-4329-b3fd-b38b6e19e633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947046023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.947046023
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3249492043
Short name T406
Test name
Test status
Simulation time 128936221705 ps
CPU time 20.35 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:49:01 PM PDT 24
Peak memory 199844 kb
Host smart-2409a8c2-10e9-4580-9b24-08eaea5fbf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249492043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3249492043
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.4292416124
Short name T400
Test name
Test status
Simulation time 30773511692 ps
CPU time 4.89 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:48:36 PM PDT 24
Peak memory 199788 kb
Host smart-1f839145-ea02-4706-afa9-3a710bf19322
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292416124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4292416124
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3245641619
Short name T860
Test name
Test status
Simulation time 74163237145 ps
CPU time 649.97 seconds
Started Jul 11 04:48:32 PM PDT 24
Finished Jul 11 04:59:32 PM PDT 24
Peak memory 199848 kb
Host smart-7c0e5734-fdca-41a8-8b67-4351d3add9a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245641619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3245641619
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1373997621
Short name T318
Test name
Test status
Simulation time 4455664079 ps
CPU time 2.92 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:40 PM PDT 24
Peak memory 199352 kb
Host smart-cbf823d9-0d73-475e-aa43-96f4b2d9c29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373997621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1373997621
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2582953414
Short name T460
Test name
Test status
Simulation time 32081651700 ps
CPU time 14.04 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:48:45 PM PDT 24
Peak memory 197292 kb
Host smart-22511480-0d17-41a5-b805-d7c1cf248887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582953414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2582953414
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3272064414
Short name T695
Test name
Test status
Simulation time 26787598076 ps
CPU time 160.41 seconds
Started Jul 11 04:48:37 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 199900 kb
Host smart-038cd77d-a869-4ef6-ace1-c7daa28a29f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272064414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3272064414
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1018359133
Short name T914
Test name
Test status
Simulation time 6738603356 ps
CPU time 28.72 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:49:16 PM PDT 24
Peak memory 197744 kb
Host smart-b8be5cea-8082-4acd-a3a8-a223013f362c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018359133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1018359133
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3775808325
Short name T979
Test name
Test status
Simulation time 116249030510 ps
CPU time 47.29 seconds
Started Jul 11 04:48:30 PM PDT 24
Finished Jul 11 04:49:27 PM PDT 24
Peak memory 199900 kb
Host smart-6bc23228-e491-4d53-9717-04c15d3d1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775808325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3775808325
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3806259748
Short name T709
Test name
Test status
Simulation time 1859406896 ps
CPU time 3.28 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:48:57 PM PDT 24
Peak memory 195532 kb
Host smart-29284a89-66a0-46a5-a307-398cb450845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806259748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3806259748
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.443885944
Short name T804
Test name
Test status
Simulation time 5555013161 ps
CPU time 12.05 seconds
Started Jul 11 04:48:38 PM PDT 24
Finished Jul 11 04:48:58 PM PDT 24
Peak memory 198900 kb
Host smart-813a8909-22c8-4420-a57f-b4b5d6c110c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443885944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.443885944
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2012323770
Short name T194
Test name
Test status
Simulation time 120385110613 ps
CPU time 153.43 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:51:28 PM PDT 24
Peak memory 199720 kb
Host smart-5b0b3565-3dbc-4ba2-b740-c333cb81e12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012323770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2012323770
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1098836942
Short name T313
Test name
Test status
Simulation time 77087339867 ps
CPU time 513.22 seconds
Started Jul 11 04:48:32 PM PDT 24
Finished Jul 11 04:57:14 PM PDT 24
Peak memory 215932 kb
Host smart-36ef07a1-a5af-4705-8a5e-04afdef14c6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098836942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1098836942
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3377332420
Short name T764
Test name
Test status
Simulation time 3104331121 ps
CPU time 2.94 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:48:27 PM PDT 24
Peak memory 199092 kb
Host smart-0878f826-bdd2-43a2-b28b-ccb8c3ef98b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377332420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3377332420
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.230503316
Short name T706
Test name
Test status
Simulation time 36198218922 ps
CPU time 15.99 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:48:57 PM PDT 24
Peak memory 199920 kb
Host smart-0b570246-1754-472a-932d-bab9908243a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230503316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.230503316
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1322886835
Short name T332
Test name
Test status
Simulation time 40113611549 ps
CPU time 76.24 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:52:15 PM PDT 24
Peak memory 199840 kb
Host smart-6cde131d-75d3-42f0-962f-5592adc6bc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322886835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1322886835
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1993525967
Short name T801
Test name
Test status
Simulation time 65620715359 ps
CPU time 194.26 seconds
Started Jul 11 04:50:50 PM PDT 24
Finished Jul 11 04:54:06 PM PDT 24
Peak memory 199660 kb
Host smart-ff051926-53dc-4e85-85c8-222526d50e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993525967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1993525967
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1630117722
Short name T682
Test name
Test status
Simulation time 72559518903 ps
CPU time 122.23 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:52:59 PM PDT 24
Peak memory 199680 kb
Host smart-6d694fce-9b71-4719-882d-00f65aa96c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630117722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1630117722
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2866964299
Short name T387
Test name
Test status
Simulation time 39134592212 ps
CPU time 62.12 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:52:01 PM PDT 24
Peak memory 199764 kb
Host smart-978e9c06-cd09-40c2-b135-606887f22331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866964299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2866964299
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1506571146
Short name T738
Test name
Test status
Simulation time 108262365561 ps
CPU time 222.75 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:54:36 PM PDT 24
Peak memory 199752 kb
Host smart-7fc09b57-b562-486b-9d69-7061955f4cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506571146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1506571146
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3653177897
Short name T629
Test name
Test status
Simulation time 112050241153 ps
CPU time 85.8 seconds
Started Jul 11 04:50:59 PM PDT 24
Finished Jul 11 04:52:27 PM PDT 24
Peak memory 199776 kb
Host smart-714ec812-6d11-452b-b9bf-5d5a25c55cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653177897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3653177897
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2735680487
Short name T1186
Test name
Test status
Simulation time 14407186314 ps
CPU time 24.22 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:23 PM PDT 24
Peak memory 199920 kb
Host smart-754be111-b583-4b79-9551-225a6aff1df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735680487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2735680487
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1399387859
Short name T836
Test name
Test status
Simulation time 42668545 ps
CPU time 0.55 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:48:32 PM PDT 24
Peak memory 195088 kb
Host smart-b75c273a-65d2-4be4-93c4-4261109f09c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399387859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1399387859
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1536373632
Short name T354
Test name
Test status
Simulation time 36840974453 ps
CPU time 22.59 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 199780 kb
Host smart-c8ca13ac-6e8e-4f34-88f2-7ea13170e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536373632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1536373632
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1913015407
Short name T943
Test name
Test status
Simulation time 101368458238 ps
CPU time 14.08 seconds
Started Jul 11 04:48:38 PM PDT 24
Finished Jul 11 04:49:00 PM PDT 24
Peak memory 199916 kb
Host smart-6db74adc-3613-4cdf-a497-ccf0aab23552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913015407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1913015407
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3310020316
Short name T232
Test name
Test status
Simulation time 43093725450 ps
CPU time 10.85 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 04:48:49 PM PDT 24
Peak memory 199768 kb
Host smart-60a1c77e-1aa1-49d5-a0ec-5736ace97f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310020316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3310020316
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3762810855
Short name T109
Test name
Test status
Simulation time 29852775477 ps
CPU time 50.74 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:49:31 PM PDT 24
Peak memory 199792 kb
Host smart-9811467f-e783-4a3f-8d80-9ffa3a34bde4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762810855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3762810855
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1118103360
Short name T1168
Test name
Test status
Simulation time 117343049657 ps
CPU time 1150.05 seconds
Started Jul 11 04:48:36 PM PDT 24
Finished Jul 11 05:07:55 PM PDT 24
Peak memory 199820 kb
Host smart-5fc9e0d7-8e82-4d71-9ac7-729c333efffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118103360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1118103360
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.880538440
Short name T1092
Test name
Test status
Simulation time 5601046349 ps
CPU time 15.47 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:48:48 PM PDT 24
Peak memory 199584 kb
Host smart-65d3ab2a-378b-4d24-af35-6d7b6fcf3da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880538440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.880538440
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2314581645
Short name T1164
Test name
Test status
Simulation time 83010106621 ps
CPU time 65.7 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 04:49:44 PM PDT 24
Peak memory 200028 kb
Host smart-8409cdb9-ca2b-4e11-9bed-285ab560eb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314581645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2314581645
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.755130624
Short name T788
Test name
Test status
Simulation time 16537341670 ps
CPU time 418.14 seconds
Started Jul 11 04:48:28 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 199900 kb
Host smart-97adf3ce-e6ef-4b7b-aea2-c706dd99a41d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755130624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.755130624
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3152767185
Short name T921
Test name
Test status
Simulation time 3030348356 ps
CPU time 11.85 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:48 PM PDT 24
Peak memory 198412 kb
Host smart-05771120-5f6f-415d-8919-1dca28570ebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3152767185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3152767185
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.4187310425
Short name T862
Test name
Test status
Simulation time 55134174007 ps
CPU time 46.09 seconds
Started Jul 11 04:48:33 PM PDT 24
Finished Jul 11 04:49:29 PM PDT 24
Peak memory 199752 kb
Host smart-634a2510-6ecd-4a7b-bbab-091062fb149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187310425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4187310425
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.698587474
Short name T1135
Test name
Test status
Simulation time 38586669963 ps
CPU time 58.51 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:49:50 PM PDT 24
Peak memory 196296 kb
Host smart-101d2344-f85d-4351-a3cf-a797942a311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698587474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.698587474
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.752284093
Short name T1108
Test name
Test status
Simulation time 88867748 ps
CPU time 0.84 seconds
Started Jul 11 04:48:32 PM PDT 24
Finished Jul 11 04:48:43 PM PDT 24
Peak memory 197076 kb
Host smart-b97e73be-dd06-4957-913b-9cd76b0512f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752284093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.752284093
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.427983675
Short name T607
Test name
Test status
Simulation time 260208999067 ps
CPU time 164.29 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:51:36 PM PDT 24
Peak memory 208244 kb
Host smart-e641348b-2e8b-4d80-8679-fd7288938f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427983675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.427983675
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4028605447
Short name T12
Test name
Test status
Simulation time 26932811996 ps
CPU time 485.64 seconds
Started Jul 11 04:48:32 PM PDT 24
Finished Jul 11 04:56:47 PM PDT 24
Peak memory 215496 kb
Host smart-3db5101c-4003-496f-9805-198549aeb8e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028605447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4028605447
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3740245366
Short name T991
Test name
Test status
Simulation time 891807634 ps
CPU time 4.06 seconds
Started Jul 11 04:48:38 PM PDT 24
Finished Jul 11 04:48:50 PM PDT 24
Peak memory 198328 kb
Host smart-a0767f4f-234b-4bba-834e-905e7d77bb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740245366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3740245366
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3552626847
Short name T494
Test name
Test status
Simulation time 57480552971 ps
CPU time 24.65 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:49:05 PM PDT 24
Peak memory 199568 kb
Host smart-91022a56-a4f1-47ce-8a1c-3f294fcaff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552626847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3552626847
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3966791605
Short name T1031
Test name
Test status
Simulation time 55064340109 ps
CPU time 82.84 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:52:19 PM PDT 24
Peak memory 199916 kb
Host smart-9ff7f912-0632-46c4-91a8-f66c49efa305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966791605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3966791605
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1811434915
Short name T1167
Test name
Test status
Simulation time 51814756284 ps
CPU time 73.68 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:52:13 PM PDT 24
Peak memory 199860 kb
Host smart-917f5f76-daa0-4c9d-8614-5dffcfb6a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811434915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1811434915
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1743085263
Short name T1097
Test name
Test status
Simulation time 16471608324 ps
CPU time 26.12 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:25 PM PDT 24
Peak memory 199840 kb
Host smart-73d89dcd-5d96-4f1b-91dc-538e64f8fecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743085263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1743085263
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.973603955
Short name T40
Test name
Test status
Simulation time 7508852957 ps
CPU time 11.71 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:51:05 PM PDT 24
Peak memory 198064 kb
Host smart-19d52951-1982-4df5-b3de-817782284cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973603955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.973603955
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.805267763
Short name T999
Test name
Test status
Simulation time 89760026948 ps
CPU time 143.42 seconds
Started Jul 11 04:50:59 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 199760 kb
Host smart-e6b5473d-bb3b-4ddb-9809-2cdcac41261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805267763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.805267763
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3035929824
Short name T1081
Test name
Test status
Simulation time 58531289454 ps
CPU time 25.53 seconds
Started Jul 11 04:50:52 PM PDT 24
Finished Jul 11 04:51:20 PM PDT 24
Peak memory 199904 kb
Host smart-ee58e076-19d6-4a61-bc83-14bb75680d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035929824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3035929824
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3351079305
Short name T432
Test name
Test status
Simulation time 11974610 ps
CPU time 0.61 seconds
Started Jul 11 04:47:55 PM PDT 24
Finished Jul 11 04:48:02 PM PDT 24
Peak memory 194492 kb
Host smart-f7f14405-7a36-4510-8d40-af12fc5591e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351079305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3351079305
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2752530311
Short name T151
Test name
Test status
Simulation time 108554686225 ps
CPU time 119.02 seconds
Started Jul 11 04:47:59 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 199800 kb
Host smart-dc71a988-eb99-4d35-85fa-254341382699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752530311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2752530311
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.827378967
Short name T924
Test name
Test status
Simulation time 51413102449 ps
CPU time 59.63 seconds
Started Jul 11 04:48:02 PM PDT 24
Finished Jul 11 04:49:07 PM PDT 24
Peak memory 199720 kb
Host smart-a52adce5-0ef6-4afb-95bc-76a56a09fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827378967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.827378967
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.909955763
Short name T744
Test name
Test status
Simulation time 54541752098 ps
CPU time 87.37 seconds
Started Jul 11 04:47:55 PM PDT 24
Finished Jul 11 04:49:28 PM PDT 24
Peak memory 199780 kb
Host smart-84e7326d-6074-4654-8504-3583bd521b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909955763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.909955763
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.428607766
Short name T777
Test name
Test status
Simulation time 646298688 ps
CPU time 0.77 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:03 PM PDT 24
Peak memory 195344 kb
Host smart-aa8767b7-b09a-4ca9-8f37-8c60e8aba1c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428607766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.428607766
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2166107873
Short name T297
Test name
Test status
Simulation time 112456222727 ps
CPU time 834.54 seconds
Started Jul 11 04:48:08 PM PDT 24
Finished Jul 11 05:02:06 PM PDT 24
Peak memory 199748 kb
Host smart-fbb21ed4-cda5-4c34-acb5-5f8435518310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166107873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2166107873
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2294265270
Short name T828
Test name
Test status
Simulation time 1695852376 ps
CPU time 2.07 seconds
Started Jul 11 04:47:52 PM PDT 24
Finished Jul 11 04:48:01 PM PDT 24
Peak memory 198428 kb
Host smart-0b462ffb-1218-41fd-9a5a-75869c927fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294265270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2294265270
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2030623163
Short name T646
Test name
Test status
Simulation time 246698152522 ps
CPU time 25.9 seconds
Started Jul 11 04:47:50 PM PDT 24
Finished Jul 11 04:48:27 PM PDT 24
Peak memory 200032 kb
Host smart-7decd499-da62-4d10-abcf-a7fea3858e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030623163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2030623163
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.4022837614
Short name T517
Test name
Test status
Simulation time 28932905130 ps
CPU time 357.13 seconds
Started Jul 11 04:48:02 PM PDT 24
Finished Jul 11 04:54:05 PM PDT 24
Peak memory 199672 kb
Host smart-46bda68d-9e56-498f-bb5d-04cd9d2ae3cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022837614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4022837614
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3945178477
Short name T928
Test name
Test status
Simulation time 5006016444 ps
CPU time 9.35 seconds
Started Jul 11 04:47:58 PM PDT 24
Finished Jul 11 04:48:13 PM PDT 24
Peak memory 198644 kb
Host smart-7fb1a715-4781-48bd-b032-3764e77d6bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945178477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3945178477
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2458123692
Short name T729
Test name
Test status
Simulation time 43528402017 ps
CPU time 13.52 seconds
Started Jul 11 04:48:04 PM PDT 24
Finished Jul 11 04:48:22 PM PDT 24
Peak memory 199788 kb
Host smart-9b8448a4-d69d-4e65-9029-1d63fc172caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458123692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2458123692
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.365874908
Short name T444
Test name
Test status
Simulation time 4416014297 ps
CPU time 4.11 seconds
Started Jul 11 04:47:51 PM PDT 24
Finished Jul 11 04:48:02 PM PDT 24
Peak memory 196072 kb
Host smart-7b529ff7-f78e-4c89-826f-a87660af11e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365874908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.365874908
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.1312406914
Short name T1151
Test name
Test status
Simulation time 722145819 ps
CPU time 1.31 seconds
Started Jul 11 04:47:51 PM PDT 24
Finished Jul 11 04:47:59 PM PDT 24
Peak memory 199460 kb
Host smart-536a094d-b9e1-474e-b282-f0730e59900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312406914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1312406914
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3572547463
Short name T300
Test name
Test status
Simulation time 22934319632 ps
CPU time 16.98 seconds
Started Jul 11 04:47:53 PM PDT 24
Finished Jul 11 04:48:17 PM PDT 24
Peak memory 198348 kb
Host smart-209a2b4f-16ce-4c51-a7b1-3934b0ba882a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572547463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3572547463
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3468618950
Short name T845
Test name
Test status
Simulation time 28795171324 ps
CPU time 330.43 seconds
Started Jul 11 04:47:54 PM PDT 24
Finished Jul 11 04:53:31 PM PDT 24
Peak memory 216432 kb
Host smart-d21e3e80-3f50-474f-b12f-81a36d50e8bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468618950 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3468618950
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3986933945
Short name T1098
Test name
Test status
Simulation time 2016298416 ps
CPU time 1.5 seconds
Started Jul 11 04:47:54 PM PDT 24
Finished Jul 11 04:48:02 PM PDT 24
Peak memory 196748 kb
Host smart-8018bf57-c964-4548-ba53-27574c3317fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986933945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3986933945
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3278980515
Short name T712
Test name
Test status
Simulation time 30639085309 ps
CPU time 44.24 seconds
Started Jul 11 04:47:59 PM PDT 24
Finished Jul 11 04:48:49 PM PDT 24
Peak memory 199696 kb
Host smart-846d90a7-4bb6-4f80-99c2-b359bf4da793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278980515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3278980515
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3307691244
Short name T905
Test name
Test status
Simulation time 12381980 ps
CPU time 0.58 seconds
Started Jul 11 04:48:36 PM PDT 24
Finished Jul 11 04:48:45 PM PDT 24
Peak memory 194600 kb
Host smart-c4b6a234-7208-4714-bb09-9266a9b27aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307691244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3307691244
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2777293955
Short name T638
Test name
Test status
Simulation time 41338311874 ps
CPU time 15.62 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:49:04 PM PDT 24
Peak memory 199752 kb
Host smart-2bbfff88-c9fd-4ad7-868e-4744451e9277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777293955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2777293955
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.435476715
Short name T1093
Test name
Test status
Simulation time 75791875980 ps
CPU time 70.98 seconds
Started Jul 11 04:48:34 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 199748 kb
Host smart-c72533d1-8363-4f9e-8b50-5412d636ef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435476715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.435476715
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.2669791659
Short name T989
Test name
Test status
Simulation time 2407967895 ps
CPU time 1.15 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:37 PM PDT 24
Peak memory 195544 kb
Host smart-08e26522-f078-4146-9d9a-1b4506a2fa3e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669791659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2669791659
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1754269221
Short name T1013
Test name
Test status
Simulation time 109720352421 ps
CPU time 508.89 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:57:23 PM PDT 24
Peak memory 199772 kb
Host smart-ae14d41f-c3f1-471c-99ac-3e4986531adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754269221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1754269221
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2754071384
Short name T754
Test name
Test status
Simulation time 3441900003 ps
CPU time 6.63 seconds
Started Jul 11 04:48:39 PM PDT 24
Finished Jul 11 04:48:54 PM PDT 24
Peak memory 197920 kb
Host smart-2ba76ccd-bb46-45f2-8f81-6b4bc509c436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754071384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2754071384
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2852662771
Short name T934
Test name
Test status
Simulation time 84828944146 ps
CPU time 18.48 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:49:12 PM PDT 24
Peak memory 198748 kb
Host smart-be7aa5a0-afb3-4045-95d7-aca63685ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852662771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2852662771
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3866665486
Short name T293
Test name
Test status
Simulation time 8068682014 ps
CPU time 112.23 seconds
Started Jul 11 04:48:38 PM PDT 24
Finished Jul 11 04:50:38 PM PDT 24
Peak memory 199860 kb
Host smart-0d377b96-e04c-4837-9248-34bf3634ab2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866665486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3866665486
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1478716727
Short name T802
Test name
Test status
Simulation time 6225145967 ps
CPU time 14.5 seconds
Started Jul 11 04:48:32 PM PDT 24
Finished Jul 11 04:48:56 PM PDT 24
Peak memory 198172 kb
Host smart-cf2c4e8d-1e0b-464d-bbc3-c46e6721040e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478716727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1478716727
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.463181168
Short name T915
Test name
Test status
Simulation time 130811179708 ps
CPU time 29.89 seconds
Started Jul 11 04:48:34 PM PDT 24
Finished Jul 11 04:49:13 PM PDT 24
Peak memory 199812 kb
Host smart-33521722-7026-42ec-a4ef-cc23b0c81a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463181168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.463181168
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2078174796
Short name T321
Test name
Test status
Simulation time 40442656652 ps
CPU time 31.67 seconds
Started Jul 11 04:48:39 PM PDT 24
Finished Jul 11 04:49:19 PM PDT 24
Peak memory 196172 kb
Host smart-54997220-27f2-43b6-b72f-248566d6ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078174796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2078174796
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3200741685
Short name T1063
Test name
Test status
Simulation time 5778530688 ps
CPU time 6.79 seconds
Started Jul 11 04:48:39 PM PDT 24
Finished Jul 11 04:48:54 PM PDT 24
Peak memory 199692 kb
Host smart-239ce52a-ccea-4824-8252-ba8b3eac6a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200741685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3200741685
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1244588975
Short name T520
Test name
Test status
Simulation time 63006613387 ps
CPU time 396.92 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:55:32 PM PDT 24
Peak memory 208428 kb
Host smart-25642eee-30dd-45d6-a17c-222539648673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244588975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1244588975
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2884588020
Short name T44
Test name
Test status
Simulation time 130922456138 ps
CPU time 789.28 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 05:01:58 PM PDT 24
Peak memory 216620 kb
Host smart-d2fb90b8-5573-455a-88c6-02773a0222ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884588020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2884588020
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.37044871
Short name T1146
Test name
Test status
Simulation time 2764398116 ps
CPU time 2.38 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:48:50 PM PDT 24
Peak memory 198800 kb
Host smart-877b480a-f9cc-49ea-bd01-2d972f78874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37044871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.37044871
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3094047539
Short name T848
Test name
Test status
Simulation time 321806271170 ps
CPU time 26.02 seconds
Started Jul 11 04:48:29 PM PDT 24
Finished Jul 11 04:49:05 PM PDT 24
Peak memory 199844 kb
Host smart-af4ac1b7-58ef-4c70-9cf1-76a5585c5787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094047539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3094047539
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3497141171
Short name T833
Test name
Test status
Simulation time 115156653460 ps
CPU time 74.07 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:52:13 PM PDT 24
Peak memory 199840 kb
Host smart-3b15e207-1496-4067-9680-0ddf302fb20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497141171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3497141171
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1007026030
Short name T920
Test name
Test status
Simulation time 125067447733 ps
CPU time 177.21 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:53:54 PM PDT 24
Peak memory 199772 kb
Host smart-a756e2f4-6fe1-46fa-b0b9-6fdb53df879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007026030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1007026030
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2697400449
Short name T654
Test name
Test status
Simulation time 50077801183 ps
CPU time 52.75 seconds
Started Jul 11 04:50:52 PM PDT 24
Finished Jul 11 04:51:47 PM PDT 24
Peak memory 199860 kb
Host smart-ea8723d9-7950-44ca-89f8-403900bba2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697400449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2697400449
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.377641598
Short name T482
Test name
Test status
Simulation time 127126827229 ps
CPU time 49.42 seconds
Started Jul 11 04:50:56 PM PDT 24
Finished Jul 11 04:51:50 PM PDT 24
Peak memory 199924 kb
Host smart-689df552-3651-4f8d-845c-f3b41be3f8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377641598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.377641598
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3884934806
Short name T181
Test name
Test status
Simulation time 52459252194 ps
CPU time 18.19 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:51:16 PM PDT 24
Peak memory 199864 kb
Host smart-fe0f04f7-637f-43d7-88e1-2adb70a4f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884934806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3884934806
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3852488953
Short name T217
Test name
Test status
Simulation time 160206019216 ps
CPU time 241.26 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:55:00 PM PDT 24
Peak memory 199796 kb
Host smart-1dced69d-bd7a-465a-8dfb-199ee16776c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852488953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3852488953
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4009130061
Short name T443
Test name
Test status
Simulation time 11748894 ps
CPU time 0.58 seconds
Started Jul 11 04:48:39 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 195148 kb
Host smart-1c39e4bb-98b2-45d3-9429-3b0991225d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009130061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4009130061
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3814895780
Short name T1162
Test name
Test status
Simulation time 80151404744 ps
CPU time 136.09 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:51:00 PM PDT 24
Peak memory 199924 kb
Host smart-d22ad873-f328-4e1b-9b37-602fa3dadaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814895780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3814895780
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.4139487089
Short name T490
Test name
Test status
Simulation time 66253050615 ps
CPU time 52.9 seconds
Started Jul 11 04:48:39 PM PDT 24
Finished Jul 11 04:49:40 PM PDT 24
Peak memory 199880 kb
Host smart-7096c017-4c0c-48dc-a7db-10c3d71bfe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139487089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.4139487089
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3863368699
Short name T888
Test name
Test status
Simulation time 121860182842 ps
CPU time 161 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:51:35 PM PDT 24
Peak memory 199864 kb
Host smart-30cba24e-18de-471f-85c1-803c5b8d8984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863368699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3863368699
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1738209243
Short name T665
Test name
Test status
Simulation time 18971192602 ps
CPU time 13.04 seconds
Started Jul 11 04:48:36 PM PDT 24
Finished Jul 11 04:48:58 PM PDT 24
Peak memory 199772 kb
Host smart-f02d731c-4e39-40ed-ac1a-f30d15c82a7b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738209243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1738209243
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.618597859
Short name T810
Test name
Test status
Simulation time 93524426724 ps
CPU time 222.87 seconds
Started Jul 11 04:48:42 PM PDT 24
Finished Jul 11 04:52:33 PM PDT 24
Peak memory 199752 kb
Host smart-a4bc0936-14be-48c8-b70b-6657afcc978a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618597859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.618597859
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3255444607
Short name T401
Test name
Test status
Simulation time 4613102999 ps
CPU time 5.13 seconds
Started Jul 11 04:48:37 PM PDT 24
Finished Jul 11 04:48:50 PM PDT 24
Peak memory 197820 kb
Host smart-32d0d920-6f4b-4516-8580-b673a1538a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255444607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3255444607
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1634544733
Short name T1
Test name
Test status
Simulation time 108658689504 ps
CPU time 41.01 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:49:29 PM PDT 24
Peak memory 208252 kb
Host smart-7b59b05a-c1af-4472-b7bc-741756acfa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634544733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1634544733
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3056987355
Short name T822
Test name
Test status
Simulation time 15000252132 ps
CPU time 448.75 seconds
Started Jul 11 04:48:48 PM PDT 24
Finished Jul 11 04:56:24 PM PDT 24
Peak memory 199744 kb
Host smart-645494aa-87f2-46e7-86b9-bfc2e2ce3d01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056987355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3056987355
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.572545496
Short name T975
Test name
Test status
Simulation time 5001970053 ps
CPU time 20.68 seconds
Started Jul 11 04:48:37 PM PDT 24
Finished Jul 11 04:49:05 PM PDT 24
Peak memory 198084 kb
Host smart-0182f1a9-5bc1-4bd4-89df-faa4c3147cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572545496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.572545496
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.554995221
Short name T295
Test name
Test status
Simulation time 80633043292 ps
CPU time 202.61 seconds
Started Jul 11 04:48:37 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 199888 kb
Host smart-11b592ba-c158-4e67-8809-1cdc9dea2351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554995221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.554995221
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2094629390
Short name T666
Test name
Test status
Simulation time 2463276249 ps
CPU time 4.52 seconds
Started Jul 11 04:48:33 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 196260 kb
Host smart-81893262-5b79-45ac-ba43-a2c21f322a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094629390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2094629390
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.340680335
Short name T782
Test name
Test status
Simulation time 462135765 ps
CPU time 1.28 seconds
Started Jul 11 04:48:42 PM PDT 24
Finished Jul 11 04:48:51 PM PDT 24
Peak memory 198404 kb
Host smart-b76d81dd-d7b5-4f2a-82f3-91e2eb70f28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340680335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.340680335
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.157998374
Short name T1005
Test name
Test status
Simulation time 193608423316 ps
CPU time 111.89 seconds
Started Jul 11 04:48:42 PM PDT 24
Finished Jul 11 04:50:42 PM PDT 24
Peak memory 199884 kb
Host smart-8e8a8a20-db2e-48a5-b1ee-f0df11c9d593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157998374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.157998374
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1942849510
Short name T630
Test name
Test status
Simulation time 57902536911 ps
CPU time 941.34 seconds
Started Jul 11 04:48:36 PM PDT 24
Finished Jul 11 05:04:25 PM PDT 24
Peak memory 224816 kb
Host smart-1cbf8465-2645-46b3-8aec-28896301b7c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942849510 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1942849510
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1252116745
Short name T851
Test name
Test status
Simulation time 1483964290 ps
CPU time 2.04 seconds
Started Jul 11 04:48:35 PM PDT 24
Finished Jul 11 04:48:45 PM PDT 24
Peak memory 198656 kb
Host smart-148c5a27-68c9-454b-b77a-3a7bf9f34b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252116745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1252116745
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1363788390
Short name T981
Test name
Test status
Simulation time 211327983281 ps
CPU time 127.93 seconds
Started Jul 11 04:48:37 PM PDT 24
Finished Jul 11 04:50:53 PM PDT 24
Peak memory 200108 kb
Host smart-f9a06bab-27ea-404e-b152-b234bfeb2da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363788390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1363788390
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1754518143
Short name T1182
Test name
Test status
Simulation time 26205819458 ps
CPU time 6.25 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:05 PM PDT 24
Peak memory 199788 kb
Host smart-59094939-a1c5-4510-8447-e5eea2faa4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754518143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1754518143
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3772958792
Short name T452
Test name
Test status
Simulation time 61165250154 ps
CPU time 95.63 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:52:34 PM PDT 24
Peak memory 199704 kb
Host smart-2b4f1137-9618-4c88-8d11-2248168a5ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772958792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3772958792
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3531261952
Short name T1029
Test name
Test status
Simulation time 256671793828 ps
CPU time 38.08 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:51:35 PM PDT 24
Peak memory 199560 kb
Host smart-0f4a3f4e-edcd-478c-b4ea-86d12490334c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531261952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3531261952
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2112422905
Short name T1045
Test name
Test status
Simulation time 115060532234 ps
CPU time 192.34 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:54:10 PM PDT 24
Peak memory 199776 kb
Host smart-a6a1eec7-88ac-4aff-a6dc-8899be14b6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112422905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2112422905
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2304554710
Short name T478
Test name
Test status
Simulation time 131800707160 ps
CPU time 64 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:52:01 PM PDT 24
Peak memory 199900 kb
Host smart-f52e20a5-f97f-4db0-8c54-228a45713c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304554710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2304554710
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3968254248
Short name T152
Test name
Test status
Simulation time 212255116387 ps
CPU time 42.28 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 199784 kb
Host smart-f7c6e3db-ae53-480e-b018-5b4a3210d93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968254248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3968254248
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1665098217
Short name T244
Test name
Test status
Simulation time 51080479559 ps
CPU time 7.98 seconds
Started Jul 11 04:50:51 PM PDT 24
Finished Jul 11 04:51:02 PM PDT 24
Peak memory 199440 kb
Host smart-348bf386-488c-4451-813f-f55078ea0df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665098217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1665098217
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.783208458
Short name T505
Test name
Test status
Simulation time 58040449719 ps
CPU time 84 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 199768 kb
Host smart-62c351e5-164d-45b7-824d-6dbb0e48f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783208458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.783208458
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2249855722
Short name T1111
Test name
Test status
Simulation time 95684038634 ps
CPU time 147.11 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:53:24 PM PDT 24
Peak memory 199852 kb
Host smart-dad241b4-4fdf-48e1-9e18-a90fc0851111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249855722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2249855722
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2611123112
Short name T486
Test name
Test status
Simulation time 190321065196 ps
CPU time 35.5 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:51:33 PM PDT 24
Peak memory 199772 kb
Host smart-dd06300f-d5a5-4530-855e-636372f3aeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611123112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2611123112
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2505297710
Short name T676
Test name
Test status
Simulation time 28185802 ps
CPU time 0.56 seconds
Started Jul 11 04:48:39 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 195496 kb
Host smart-6c07782c-f4ef-473f-9682-6b50553e7ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505297710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2505297710
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2045036868
Short name T107
Test name
Test status
Simulation time 25623620606 ps
CPU time 45.42 seconds
Started Jul 11 04:48:42 PM PDT 24
Finished Jul 11 04:49:36 PM PDT 24
Peak memory 199828 kb
Host smart-100f98fd-0c73-4a49-b621-9866cc07e079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045036868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2045036868
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1701670118
Short name T588
Test name
Test status
Simulation time 32953639664 ps
CPU time 54.09 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:49:57 PM PDT 24
Peak memory 199808 kb
Host smart-1c34d7ff-b4a4-4e6a-a180-88d94b3c59d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701670118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1701670118
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.4258124447
Short name T746
Test name
Test status
Simulation time 15108092586 ps
CPU time 32.6 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:49:38 PM PDT 24
Peak memory 199780 kb
Host smart-0e340ef0-277c-4a30-8ff6-a465bacd09f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258124447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4258124447
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2270567435
Short name T990
Test name
Test status
Simulation time 279633961687 ps
CPU time 675.47 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 05:00:09 PM PDT 24
Peak memory 199696 kb
Host smart-c1ead9f9-5c6f-41f5-ad71-607e49300cc1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270567435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2270567435
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2604527285
Short name T898
Test name
Test status
Simulation time 117046610424 ps
CPU time 356.92 seconds
Started Jul 11 04:48:54 PM PDT 24
Finished Jul 11 04:54:58 PM PDT 24
Peak memory 199812 kb
Host smart-4df4ac15-944b-4a95-9913-51511b2ae106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604527285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2604527285
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.799384253
Short name T739
Test name
Test status
Simulation time 7653706726 ps
CPU time 5.9 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:48:54 PM PDT 24
Peak memory 199768 kb
Host smart-cb2ba608-b36c-4beb-810a-e37e3f29a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799384253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.799384253
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1828944380
Short name T1126
Test name
Test status
Simulation time 84837654233 ps
CPU time 62 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:49:55 PM PDT 24
Peak memory 199620 kb
Host smart-711e6894-df55-4de3-b35d-0cfdac20b3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828944380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1828944380
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2908549428
Short name T463
Test name
Test status
Simulation time 2334573659 ps
CPU time 129.29 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:51:01 PM PDT 24
Peak memory 199772 kb
Host smart-7d89a0e8-b668-4b7b-859a-fa0e0a5eb1e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908549428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2908549428
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2261972883
Short name T917
Test name
Test status
Simulation time 5072803420 ps
CPU time 41.88 seconds
Started Jul 11 04:48:53 PM PDT 24
Finished Jul 11 04:49:41 PM PDT 24
Peak memory 199136 kb
Host smart-856006b3-17d2-442c-b747-d21c26bd77c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261972883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2261972883
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3514012034
Short name T421
Test name
Test status
Simulation time 43599670162 ps
CPU time 15.49 seconds
Started Jul 11 04:48:38 PM PDT 24
Finished Jul 11 04:49:02 PM PDT 24
Peak memory 199868 kb
Host smart-ae9b580b-a80e-4f37-9e8e-99e7f377fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514012034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3514012034
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3611518626
Short name T524
Test name
Test status
Simulation time 1412301378 ps
CPU time 2.92 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:48:56 PM PDT 24
Peak memory 195536 kb
Host smart-9448d48a-f107-4b17-977e-aef296ea023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611518626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3611518626
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2814544018
Short name T570
Test name
Test status
Simulation time 5774160027 ps
CPU time 6.66 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:49:00 PM PDT 24
Peak memory 199740 kb
Host smart-8b9d8aca-a3f2-47c0-aadf-7e881986e2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814544018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2814544018
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4087860285
Short name T946
Test name
Test status
Simulation time 181297127267 ps
CPU time 203.3 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:52:28 PM PDT 24
Peak memory 199828 kb
Host smart-5492c85d-ef46-4c8a-a54a-c9b6cb93e43d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087860285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4087860285
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.210390108
Short name T916
Test name
Test status
Simulation time 324427977722 ps
CPU time 296.15 seconds
Started Jul 11 04:48:43 PM PDT 24
Finished Jul 11 04:53:47 PM PDT 24
Peak memory 216528 kb
Host smart-abab2255-da1e-41b7-98f8-2e4248abb4a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210390108 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.210390108
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1060117545
Short name T436
Test name
Test status
Simulation time 1297220472 ps
CPU time 1.98 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:49:07 PM PDT 24
Peak memory 199488 kb
Host smart-519ae123-e86b-44de-bea3-b840fbc62e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060117545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1060117545
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3122817646
Short name T380
Test name
Test status
Simulation time 52442910333 ps
CPU time 81.14 seconds
Started Jul 11 04:48:43 PM PDT 24
Finished Jul 11 04:50:12 PM PDT 24
Peak memory 199784 kb
Host smart-dacb1ffa-b578-43ee-9150-73e130a6f213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122817646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3122817646
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3452692220
Short name T212
Test name
Test status
Simulation time 114993054304 ps
CPU time 153.71 seconds
Started Jul 11 04:50:56 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 199924 kb
Host smart-4611473f-febd-4bc3-861c-ea7b825fd70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452692220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3452692220
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.706413601
Short name T985
Test name
Test status
Simulation time 116224586694 ps
CPU time 25.68 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 199924 kb
Host smart-18c8fe52-7249-4eee-a7a8-299b8ea17236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706413601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.706413601
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3946425086
Short name T223
Test name
Test status
Simulation time 112228873375 ps
CPU time 106.74 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:52:44 PM PDT 24
Peak memory 199844 kb
Host smart-fd1f496d-75eb-44a0-8544-2c7b1c91ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946425086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3946425086
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1467253643
Short name T325
Test name
Test status
Simulation time 9360732579 ps
CPU time 16.09 seconds
Started Jul 11 04:51:01 PM PDT 24
Finished Jul 11 04:51:20 PM PDT 24
Peak memory 199724 kb
Host smart-fb3be856-0d74-491b-9838-27ea6c2c3d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467253643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1467253643
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.541461938
Short name T899
Test name
Test status
Simulation time 216188440939 ps
CPU time 176.65 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:53:56 PM PDT 24
Peak memory 199920 kb
Host smart-d910a39d-da72-44e1-aaeb-7fe9e7ab2276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541461938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.541461938
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1975663693
Short name T1052
Test name
Test status
Simulation time 37712162882 ps
CPU time 63.77 seconds
Started Jul 11 04:50:59 PM PDT 24
Finished Jul 11 04:52:05 PM PDT 24
Peak memory 199772 kb
Host smart-27cb07a2-1356-447f-9cd3-1dd131592a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975663693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1975663693
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2264674014
Short name T230
Test name
Test status
Simulation time 96181388070 ps
CPU time 51.15 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:51:49 PM PDT 24
Peak memory 199808 kb
Host smart-4c297d97-4e1d-42c4-8c4c-30e808fb3414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264674014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2264674014
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3648463933
Short name T721
Test name
Test status
Simulation time 94307534861 ps
CPU time 19.55 seconds
Started Jul 11 04:50:55 PM PDT 24
Finished Jul 11 04:51:19 PM PDT 24
Peak memory 198284 kb
Host smart-ef54030b-3548-40d2-923c-565c71ee0954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648463933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3648463933
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.562730141
Short name T849
Test name
Test status
Simulation time 43731919 ps
CPU time 0.56 seconds
Started Jul 11 04:48:38 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 195232 kb
Host smart-e0c6d2d7-03b6-41f7-bb6a-a445b9d6a0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562730141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.562730141
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1499086595
Short name T907
Test name
Test status
Simulation time 117026373589 ps
CPU time 50.29 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:49:44 PM PDT 24
Peak memory 199836 kb
Host smart-29b12f8b-883f-43f2-b05a-7d2bb4a25a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499086595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1499086595
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.723553846
Short name T305
Test name
Test status
Simulation time 25956954638 ps
CPU time 13.55 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:49:02 PM PDT 24
Peak memory 200012 kb
Host smart-7212610c-1080-40a7-852e-fa53cbd6ccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723553846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.723553846
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3799583864
Short name T502
Test name
Test status
Simulation time 20414091781 ps
CPU time 49.2 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:49:43 PM PDT 24
Peak memory 199860 kb
Host smart-147c57c2-e873-41cd-9d7e-e4bef24894d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799583864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3799583864
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3889343678
Short name T955
Test name
Test status
Simulation time 11532418304 ps
CPU time 9.85 seconds
Started Jul 11 04:48:38 PM PDT 24
Finished Jul 11 04:48:55 PM PDT 24
Peak memory 196408 kb
Host smart-69d557f9-ab5a-4274-a505-498144b03260
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889343678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3889343678
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.290425136
Short name T984
Test name
Test status
Simulation time 74221592838 ps
CPU time 337.75 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:54:30 PM PDT 24
Peak memory 199824 kb
Host smart-7a74ff2a-a002-489b-8ed7-4d39a578b661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290425136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.290425136
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.272344999
Short name T382
Test name
Test status
Simulation time 11024380465 ps
CPU time 19.84 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:49:12 PM PDT 24
Peak memory 199168 kb
Host smart-2d538af5-3b00-41e0-9f2e-4f3c02eadf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272344999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.272344999
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3230629883
Short name T448
Test name
Test status
Simulation time 91991859284 ps
CPU time 108.05 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:50:45 PM PDT 24
Peak memory 208228 kb
Host smart-4588b93c-873c-4d73-922b-167c21a0b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230629883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3230629883
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.4244921637
Short name T640
Test name
Test status
Simulation time 2446889358 ps
CPU time 28.29 seconds
Started Jul 11 04:48:41 PM PDT 24
Finished Jul 11 04:49:18 PM PDT 24
Peak memory 199832 kb
Host smart-2e6f22f0-c394-4379-874f-0b0dfeb323c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244921637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4244921637
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3400514511
Short name T970
Test name
Test status
Simulation time 3560636367 ps
CPU time 5.69 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:48:54 PM PDT 24
Peak memory 198384 kb
Host smart-faed59cc-3923-4660-b941-2a8817887fb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400514511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3400514511
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2440741445
Short name T698
Test name
Test status
Simulation time 40360021086 ps
CPU time 62.02 seconds
Started Jul 11 04:48:50 PM PDT 24
Finished Jul 11 04:49:59 PM PDT 24
Peak memory 195880 kb
Host smart-4e85a2da-490c-4b0c-91c3-c6daf66714f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440741445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2440741445
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4235235119
Short name T803
Test name
Test status
Simulation time 319407538 ps
CPU time 1.43 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:48:54 PM PDT 24
Peak memory 199744 kb
Host smart-d6a637f4-aea0-4de8-ae40-d575ec034baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235235119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4235235119
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2431324588
Short name T948
Test name
Test status
Simulation time 559283713968 ps
CPU time 703.11 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 05:00:37 PM PDT 24
Peak memory 216316 kb
Host smart-ce93b121-ce37-4c69-ac1d-3abea07fc4aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431324588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2431324588
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.4176651946
Short name T576
Test name
Test status
Simulation time 707549375 ps
CPU time 1.5 seconds
Started Jul 11 04:48:50 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 198156 kb
Host smart-051ebaf6-44f5-4b49-86ad-e63b43df8854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176651946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4176651946
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3372079686
Short name T835
Test name
Test status
Simulation time 201754152882 ps
CPU time 114.72 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:50:47 PM PDT 24
Peak memory 199756 kb
Host smart-617f4d4a-f610-44aa-99f5-aed72ef116ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372079686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3372079686
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2271381388
Short name T743
Test name
Test status
Simulation time 13637553989 ps
CPU time 20.46 seconds
Started Jul 11 04:50:56 PM PDT 24
Finished Jul 11 04:51:21 PM PDT 24
Peak memory 199884 kb
Host smart-4c5c9b77-8a2e-44fc-b9d1-0f51f1d435bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271381388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2271381388
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.594372423
Short name T894
Test name
Test status
Simulation time 82423651251 ps
CPU time 35.71 seconds
Started Jul 11 04:50:59 PM PDT 24
Finished Jul 11 04:51:37 PM PDT 24
Peak memory 199812 kb
Host smart-9eed8416-dff9-489e-aea9-43f2931b373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594372423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.594372423
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.177032943
Short name T952
Test name
Test status
Simulation time 51553676445 ps
CPU time 18.27 seconds
Started Jul 11 04:50:55 PM PDT 24
Finished Jul 11 04:51:17 PM PDT 24
Peak memory 199948 kb
Host smart-da063620-e6d0-4a0d-a4cc-96c3d48911a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177032943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.177032943
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3212771317
Short name T250
Test name
Test status
Simulation time 228241091034 ps
CPU time 32.76 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:32 PM PDT 24
Peak memory 199840 kb
Host smart-c4020ab1-f8f9-4e4b-ad3e-8c1059be28ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212771317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3212771317
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1850495563
Short name T983
Test name
Test status
Simulation time 29650345481 ps
CPU time 50.7 seconds
Started Jul 11 04:50:54 PM PDT 24
Finished Jul 11 04:51:50 PM PDT 24
Peak memory 199844 kb
Host smart-1253ccc0-1959-49e4-90e2-b6616a47c486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850495563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1850495563
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1230047139
Short name T563
Test name
Test status
Simulation time 46236122249 ps
CPU time 38.23 seconds
Started Jul 11 04:50:53 PM PDT 24
Finished Jul 11 04:51:36 PM PDT 24
Peak memory 199696 kb
Host smart-fa2fab51-53ff-4748-b659-1f98ea0d48fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230047139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1230047139
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3021697112
Short name T566
Test name
Test status
Simulation time 87793053880 ps
CPU time 123.58 seconds
Started Jul 11 04:51:11 PM PDT 24
Finished Jul 11 04:53:17 PM PDT 24
Peak memory 199860 kb
Host smart-08572c1a-d01e-442c-9573-a8f43380518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021697112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3021697112
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1565462875
Short name T733
Test name
Test status
Simulation time 44050829648 ps
CPU time 30.62 seconds
Started Jul 11 04:51:00 PM PDT 24
Finished Jul 11 04:51:34 PM PDT 24
Peak memory 199852 kb
Host smart-9ed5a9f1-e777-446f-9a08-12b1d6b63c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565462875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1565462875
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2037115514
Short name T296
Test name
Test status
Simulation time 89279351977 ps
CPU time 77.65 seconds
Started Jul 11 04:50:59 PM PDT 24
Finished Jul 11 04:52:20 PM PDT 24
Peak memory 200112 kb
Host smart-663f535a-e734-4d86-ad6a-4f706a81abe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037115514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2037115514
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1555955235
Short name T1039
Test name
Test status
Simulation time 27139127407 ps
CPU time 11.63 seconds
Started Jul 11 04:51:05 PM PDT 24
Finished Jul 11 04:51:19 PM PDT 24
Peak memory 198196 kb
Host smart-da763e24-7d4c-4634-9ebd-9305146f1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555955235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1555955235
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3183337618
Short name T396
Test name
Test status
Simulation time 84673697 ps
CPU time 0.55 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:48:55 PM PDT 24
Peak memory 195228 kb
Host smart-6cf83c0e-9472-4bd1-9574-ee64a5d96295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183337618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3183337618
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.343429918
Short name T574
Test name
Test status
Simulation time 167384393049 ps
CPU time 24.96 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:49:27 PM PDT 24
Peak memory 199568 kb
Host smart-2f19f4ce-2c8f-4503-935c-88e4f3ea71b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343429918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.343429918
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1437962560
Short name T1041
Test name
Test status
Simulation time 128787533567 ps
CPU time 52.01 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:49:44 PM PDT 24
Peak memory 199860 kb
Host smart-0d011265-7958-43da-afa6-a96bbc706f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437962560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1437962560
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1991018580
Short name T1034
Test name
Test status
Simulation time 29333184518 ps
CPU time 18.1 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:49:10 PM PDT 24
Peak memory 199640 kb
Host smart-4a89945c-af2c-4282-8981-fc7cc0f22703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991018580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1991018580
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4195595111
Short name T345
Test name
Test status
Simulation time 15453343587 ps
CPU time 1.81 seconds
Started Jul 11 04:48:42 PM PDT 24
Finished Jul 11 04:48:51 PM PDT 24
Peak memory 197852 kb
Host smart-58261741-007d-4f93-8e42-146e649a71b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195595111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4195595111
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_loopback.3189616475
Short name T958
Test name
Test status
Simulation time 6622468613 ps
CPU time 22.32 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:49:17 PM PDT 24
Peak memory 198580 kb
Host smart-f8252abe-7928-47d3-a062-14caa75b4937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189616475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3189616475
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2537994107
Short name T528
Test name
Test status
Simulation time 44575375718 ps
CPU time 4.05 seconds
Started Jul 11 04:48:42 PM PDT 24
Finished Jul 11 04:48:54 PM PDT 24
Peak memory 194476 kb
Host smart-bee04410-843e-4f24-abdc-0c834d499f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537994107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2537994107
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.228167496
Short name T455
Test name
Test status
Simulation time 26852987755 ps
CPU time 555.63 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:58:10 PM PDT 24
Peak memory 199820 kb
Host smart-83d56aa7-671d-4ba3-aaa1-ea8d0d350921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228167496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.228167496
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2487428165
Short name T671
Test name
Test status
Simulation time 1899421750 ps
CPU time 8.98 seconds
Started Jul 11 04:48:53 PM PDT 24
Finished Jul 11 04:49:10 PM PDT 24
Peak memory 197988 kb
Host smart-0962845d-c0d0-47c5-af14-e715a8646413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487428165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2487428165
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2937837500
Short name T1105
Test name
Test status
Simulation time 190355384078 ps
CPU time 81.6 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:50:17 PM PDT 24
Peak memory 199836 kb
Host smart-dc40ba49-be54-47c2-9efc-bde7b8869432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937837500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2937837500
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.354917251
Short name T461
Test name
Test status
Simulation time 1768662992 ps
CPU time 3.59 seconds
Started Jul 11 04:48:48 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 195516 kb
Host smart-3044c830-797e-4b86-8ae2-74cdce04e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354917251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.354917251
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3600747183
Short name T1100
Test name
Test status
Simulation time 5334406143 ps
CPU time 24.17 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:49:18 PM PDT 24
Peak memory 199564 kb
Host smart-08d3e6f5-3d87-4f58-92d8-86e70c1f60a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600747183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3600747183
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1921665677
Short name T652
Test name
Test status
Simulation time 90123970666 ps
CPU time 124.96 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:50:59 PM PDT 24
Peak memory 199800 kb
Host smart-920c8471-45ba-4e12-ab17-44431506fcbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921665677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1921665677
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.189293631
Short name T829
Test name
Test status
Simulation time 36401544360 ps
CPU time 362.13 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:54:59 PM PDT 24
Peak memory 216516 kb
Host smart-a530120b-37af-4aa2-a19c-8e4d70b77bc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189293631 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.189293631
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1298029436
Short name T1170
Test name
Test status
Simulation time 7040827422 ps
CPU time 16.18 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:49:12 PM PDT 24
Peak memory 199568 kb
Host smart-c2655252-eb8b-4295-8d16-868ca322e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298029436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1298029436
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1480143751
Short name T982
Test name
Test status
Simulation time 111653381188 ps
CPU time 47.2 seconds
Started Jul 11 04:48:51 PM PDT 24
Finished Jul 11 04:49:46 PM PDT 24
Peak memory 199920 kb
Host smart-7d3e8431-6c45-403f-857d-7cc0ae2624cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480143751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1480143751
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3158085052
Short name T187
Test name
Test status
Simulation time 60634484396 ps
CPU time 25.1 seconds
Started Jul 11 04:50:58 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 199736 kb
Host smart-c4da5f78-1a20-4049-a5a8-41453a199f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158085052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3158085052
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.4055285065
Short name T291
Test name
Test status
Simulation time 144913811143 ps
CPU time 58.6 seconds
Started Jul 11 04:51:05 PM PDT 24
Finished Jul 11 04:52:06 PM PDT 24
Peak memory 199848 kb
Host smart-d72c0152-26c2-4f97-b485-e61ebde494b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055285065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4055285065
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.841844849
Short name T1155
Test name
Test status
Simulation time 16854648939 ps
CPU time 34.24 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 199780 kb
Host smart-bcde8ccd-bd45-4299-81c0-845bde8f401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841844849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.841844849
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2645060891
Short name T677
Test name
Test status
Simulation time 70567807911 ps
CPU time 118.4 seconds
Started Jul 11 04:51:01 PM PDT 24
Finished Jul 11 04:53:03 PM PDT 24
Peak memory 200076 kb
Host smart-df7a6830-e5b1-439c-8065-063197667b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645060891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2645060891
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.340036787
Short name T543
Test name
Test status
Simulation time 34924512833 ps
CPU time 28.41 seconds
Started Jul 11 04:51:00 PM PDT 24
Finished Jul 11 04:51:31 PM PDT 24
Peak memory 199796 kb
Host smart-37b90fae-ed25-49fc-b614-b49834977450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340036787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.340036787
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2560933712
Short name T1187
Test name
Test status
Simulation time 135516520848 ps
CPU time 110.77 seconds
Started Jul 11 04:50:59 PM PDT 24
Finished Jul 11 04:52:53 PM PDT 24
Peak memory 199852 kb
Host smart-b3360710-d66a-44b8-addc-7c967ade6ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560933712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2560933712
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3042145965
Short name T1136
Test name
Test status
Simulation time 45099715462 ps
CPU time 14.29 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 04:51:21 PM PDT 24
Peak memory 199832 kb
Host smart-3c3a844c-e747-4a69-aaf7-dfadad328ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042145965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3042145965
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.171292856
Short name T601
Test name
Test status
Simulation time 26891929032 ps
CPU time 20.79 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 04:51:27 PM PDT 24
Peak memory 199772 kb
Host smart-55d70414-306e-4d11-bdb0-b944e4c46de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171292856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.171292856
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1583351822
Short name T947
Test name
Test status
Simulation time 131841775127 ps
CPU time 177.26 seconds
Started Jul 11 04:51:01 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 199768 kb
Host smart-835e1def-1ef6-47b5-993d-e12b2adb12cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583351822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1583351822
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2298120124
Short name T636
Test name
Test status
Simulation time 22692555 ps
CPU time 0.57 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:48:54 PM PDT 24
Peak memory 195152 kb
Host smart-444b0061-43ff-42db-b057-fa3e7e33c13e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298120124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2298120124
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3675575648
Short name T569
Test name
Test status
Simulation time 37894247432 ps
CPU time 31.61 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:49:28 PM PDT 24
Peak memory 199848 kb
Host smart-b73d6a73-9342-4de3-96a0-1a21a745d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675575648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3675575648
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3905681711
Short name T648
Test name
Test status
Simulation time 19761120299 ps
CPU time 15.33 seconds
Started Jul 11 04:48:42 PM PDT 24
Finished Jul 11 04:49:05 PM PDT 24
Peak memory 199776 kb
Host smart-947e8a40-d232-47f7-b82f-ff493fbf0507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905681711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3905681711
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.3677344227
Short name T968
Test name
Test status
Simulation time 12894905562 ps
CPU time 23.39 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:49:16 PM PDT 24
Peak memory 199696 kb
Host smart-6885ac80-5265-4346-a0aa-8ef2f77b5035
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677344227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3677344227
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3676995263
Short name T416
Test name
Test status
Simulation time 189285461084 ps
CPU time 216.45 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:52:33 PM PDT 24
Peak memory 199840 kb
Host smart-c878d561-07ef-449a-bc50-4e573ebc9eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676995263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3676995263
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.34206454
Short name T685
Test name
Test status
Simulation time 268909647 ps
CPU time 0.72 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:48:57 PM PDT 24
Peak memory 195812 kb
Host smart-0b195d19-50e4-421f-9511-e52d78e23c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34206454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.34206454
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2828241096
Short name T960
Test name
Test status
Simulation time 40466385869 ps
CPU time 68.76 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:50:03 PM PDT 24
Peak memory 199656 kb
Host smart-48652c61-e565-4132-94d8-aa3626830a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828241096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2828241096
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.272559657
Short name T790
Test name
Test status
Simulation time 11075111022 ps
CPU time 656.5 seconds
Started Jul 11 04:48:48 PM PDT 24
Finished Jul 11 04:59:52 PM PDT 24
Peak memory 199824 kb
Host smart-7a7122d3-d4b8-4ad8-9ed6-365680a8efcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=272559657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.272559657
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1131502174
Short name T1004
Test name
Test status
Simulation time 3263111970 ps
CPU time 27.14 seconds
Started Jul 11 04:48:45 PM PDT 24
Finished Jul 11 04:49:19 PM PDT 24
Peak memory 198224 kb
Host smart-c7fe3692-9d71-4935-8283-acd69f9ba521
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131502174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1131502174
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3189294213
Short name T557
Test name
Test status
Simulation time 28868442253 ps
CPU time 40.94 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:49:38 PM PDT 24
Peak memory 199916 kb
Host smart-8f875a22-3488-41f1-93ac-4bf84f3b16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189294213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3189294213
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1332460133
Short name T969
Test name
Test status
Simulation time 31312327450 ps
CPU time 6.81 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:49:01 PM PDT 24
Peak memory 196028 kb
Host smart-23b65c85-b5da-4d66-9970-bd3a28d47520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332460133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1332460133
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2788960016
Short name T669
Test name
Test status
Simulation time 646544830 ps
CPU time 1.72 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:48:55 PM PDT 24
Peak memory 198176 kb
Host smart-b1dcea59-d26e-4e13-ba9b-bb3738fb7410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788960016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2788960016
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2506515580
Short name T550
Test name
Test status
Simulation time 268588708874 ps
CPU time 1145.87 seconds
Started Jul 11 04:48:51 PM PDT 24
Finished Jul 11 05:08:04 PM PDT 24
Peak memory 199804 kb
Host smart-c1807a89-0459-448d-af60-954636b54130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506515580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2506515580
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.979226362
Short name T312
Test name
Test status
Simulation time 27797821432 ps
CPU time 353.38 seconds
Started Jul 11 04:48:51 PM PDT 24
Finished Jul 11 04:54:51 PM PDT 24
Peak memory 216524 kb
Host smart-64c94370-b6fb-44ac-a4ad-1b5e97beea68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979226362 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.979226362
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2511969528
Short name T901
Test name
Test status
Simulation time 1514751430 ps
CPU time 1.69 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:48:56 PM PDT 24
Peak memory 198420 kb
Host smart-b8b5d4d7-8034-4428-8f96-c7a3974db262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511969528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2511969528
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1141750991
Short name T1109
Test name
Test status
Simulation time 101814667626 ps
CPU time 45.81 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:49:40 PM PDT 24
Peak memory 199924 kb
Host smart-6918dff2-f4de-43ef-b211-6853a6700b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141750991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1141750991
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2558229133
Short name T1069
Test name
Test status
Simulation time 20345509136 ps
CPU time 17.8 seconds
Started Jul 11 04:51:01 PM PDT 24
Finished Jul 11 04:51:22 PM PDT 24
Peak memory 199848 kb
Host smart-4bd9b793-556a-4757-8110-632efa1f358f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558229133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2558229133
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2176068223
Short name T59
Test name
Test status
Simulation time 33187557005 ps
CPU time 25.22 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 04:51:32 PM PDT 24
Peak memory 199860 kb
Host smart-154ccb75-5067-4427-8250-ff430eab372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176068223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2176068223
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.484260199
Short name T157
Test name
Test status
Simulation time 94193457789 ps
CPU time 74.74 seconds
Started Jul 11 04:51:04 PM PDT 24
Finished Jul 11 04:52:22 PM PDT 24
Peak memory 199844 kb
Host smart-325e2802-aee7-436d-b69c-357d0cf183cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484260199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.484260199
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.179947081
Short name T1060
Test name
Test status
Simulation time 95359119890 ps
CPU time 64.97 seconds
Started Jul 11 04:51:06 PM PDT 24
Finished Jul 11 04:52:13 PM PDT 24
Peak memory 199884 kb
Host smart-b9791eb4-0a7b-4bdc-8da2-5fc86934d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179947081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.179947081
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.217944810
Short name T659
Test name
Test status
Simulation time 77667523371 ps
CPU time 71.18 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 04:52:18 PM PDT 24
Peak memory 199832 kb
Host smart-2254ceea-41dd-482d-a2f7-dd875d8e9372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217944810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.217944810
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1233829478
Short name T476
Test name
Test status
Simulation time 23510586889 ps
CPU time 39.12 seconds
Started Jul 11 04:51:01 PM PDT 24
Finished Jul 11 04:51:43 PM PDT 24
Peak memory 199748 kb
Host smart-db9bfd78-8d25-4be9-a892-d3dae945754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233829478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1233829478
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3450977290
Short name T298
Test name
Test status
Simulation time 113275552850 ps
CPU time 45.21 seconds
Started Jul 11 04:50:58 PM PDT 24
Finished Jul 11 04:51:47 PM PDT 24
Peak memory 199372 kb
Host smart-2fd18a87-e5dd-4395-8f51-5189d84216c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450977290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3450977290
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2675622840
Short name T880
Test name
Test status
Simulation time 64519413911 ps
CPU time 88.04 seconds
Started Jul 11 04:51:01 PM PDT 24
Finished Jul 11 04:52:31 PM PDT 24
Peak memory 199740 kb
Host smart-2e847bdf-ae26-4d92-9bf2-6b8c1165fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675622840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2675622840
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1487230070
Short name T200
Test name
Test status
Simulation time 74162358946 ps
CPU time 28.38 seconds
Started Jul 11 04:51:00 PM PDT 24
Finished Jul 11 04:51:31 PM PDT 24
Peak memory 199828 kb
Host smart-412bce5d-a6f3-4845-a26d-0701c9e47128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487230070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1487230070
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2033822276
Short name T328
Test name
Test status
Simulation time 20455424898 ps
CPU time 37.52 seconds
Started Jul 11 04:51:05 PM PDT 24
Finished Jul 11 04:51:45 PM PDT 24
Peak memory 199884 kb
Host smart-c386d31d-e4e7-490b-ac5f-e7d2f212d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033822276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2033822276
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1652429783
Short name T480
Test name
Test status
Simulation time 15295491 ps
CPU time 0.55 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:48:53 PM PDT 24
Peak memory 195196 kb
Host smart-3d943bd7-5af2-46c4-9e30-bdc3163a19d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652429783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1652429783
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2613861618
Short name T926
Test name
Test status
Simulation time 42435700082 ps
CPU time 23.39 seconds
Started Jul 11 04:48:56 PM PDT 24
Finished Jul 11 04:49:26 PM PDT 24
Peak memory 199856 kb
Host smart-0c63d272-f3dc-4473-90e3-c578b2d8281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613861618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2613861618
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2685252098
Short name T1173
Test name
Test status
Simulation time 95037727646 ps
CPU time 77.73 seconds
Started Jul 11 04:48:53 PM PDT 24
Finished Jul 11 04:50:17 PM PDT 24
Peak memory 199588 kb
Host smart-bc4b5e87-7254-4bd6-985a-b8a4fda798f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685252098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2685252098
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3734813551
Short name T192
Test name
Test status
Simulation time 84281991083 ps
CPU time 96.95 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:50:29 PM PDT 24
Peak memory 199832 kb
Host smart-a3d0d730-441e-4a4f-a73b-ef34218d46ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734813551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3734813551
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.4101979457
Short name T324
Test name
Test status
Simulation time 27379978853 ps
CPU time 15.29 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:49:12 PM PDT 24
Peak memory 199792 kb
Host smart-d3365f3b-8548-4bfb-a136-8b921a9174c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101979457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.4101979457
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3695892713
Short name T407
Test name
Test status
Simulation time 198709530701 ps
CPU time 159.16 seconds
Started Jul 11 04:48:50 PM PDT 24
Finished Jul 11 04:51:37 PM PDT 24
Peak memory 199820 kb
Host smart-bd14915c-33ad-48af-9661-17b74349a39e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695892713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3695892713
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1803106662
Short name T978
Test name
Test status
Simulation time 9016712465 ps
CPU time 6.75 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:49:03 PM PDT 24
Peak memory 198680 kb
Host smart-10f85683-93db-43cc-a2fa-230196a20c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803106662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1803106662
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3110501856
Short name T751
Test name
Test status
Simulation time 287815269704 ps
CPU time 189.56 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:52:15 PM PDT 24
Peak memory 207940 kb
Host smart-897938e1-e10d-4e8c-be12-53dca5aa97de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110501856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3110501856
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2939565242
Short name T1003
Test name
Test status
Simulation time 34702995771 ps
CPU time 581.7 seconds
Started Jul 11 04:48:54 PM PDT 24
Finished Jul 11 04:58:42 PM PDT 24
Peak memory 199864 kb
Host smart-36d9b451-fcf5-4896-9869-0cf49236e7ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939565242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2939565242
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3935593494
Short name T546
Test name
Test status
Simulation time 6228172773 ps
CPU time 27.96 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:49:24 PM PDT 24
Peak memory 199240 kb
Host smart-0278d22e-8326-436f-9f8f-866d2964a7d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935593494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3935593494
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2443199156
Short name T516
Test name
Test status
Simulation time 125786009449 ps
CPU time 43.99 seconds
Started Jul 11 04:48:48 PM PDT 24
Finished Jul 11 04:49:39 PM PDT 24
Peak memory 199752 kb
Host smart-7aedd13c-fcbc-4598-93af-10474e594f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443199156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2443199156
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4214069440
Short name T384
Test name
Test status
Simulation time 3074401062 ps
CPU time 5 seconds
Started Jul 11 04:48:48 PM PDT 24
Finished Jul 11 04:49:00 PM PDT 24
Peak memory 195676 kb
Host smart-273302bb-4450-4254-a532-82e623cbbd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214069440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4214069440
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.912214446
Short name T1160
Test name
Test status
Simulation time 268410117 ps
CPU time 1.8 seconds
Started Jul 11 04:48:40 PM PDT 24
Finished Jul 11 04:48:50 PM PDT 24
Peak memory 198900 kb
Host smart-67733255-e02a-4be3-bc33-c653a711b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912214446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.912214446
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3883439094
Short name T720
Test name
Test status
Simulation time 385847133674 ps
CPU time 135.93 seconds
Started Jul 11 04:48:46 PM PDT 24
Finished Jul 11 04:51:09 PM PDT 24
Peak memory 199680 kb
Host smart-53bcd818-a794-4e0f-8efb-a1bffb9b9ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883439094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3883439094
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3533167712
Short name T1022
Test name
Test status
Simulation time 288564352209 ps
CPU time 526.49 seconds
Started Jul 11 04:48:54 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 224728 kb
Host smart-3f1b539a-ea09-4de5-a845-cce69fe0cb0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533167712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3533167712
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1288460168
Short name T479
Test name
Test status
Simulation time 7179969495 ps
CPU time 10.69 seconds
Started Jul 11 04:48:53 PM PDT 24
Finished Jul 11 04:49:11 PM PDT 24
Peak memory 199364 kb
Host smart-ea2c6703-3663-4af6-bbad-7572c025bb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288460168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1288460168
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1490216291
Short name T837
Test name
Test status
Simulation time 95597077459 ps
CPU time 36.58 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:49:41 PM PDT 24
Peak memory 199840 kb
Host smart-dece152d-0a9c-4787-9da9-e53fa6f6dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490216291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1490216291
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2208542747
Short name T381
Test name
Test status
Simulation time 122209050279 ps
CPU time 171.9 seconds
Started Jul 11 04:51:02 PM PDT 24
Finished Jul 11 04:53:57 PM PDT 24
Peak memory 199840 kb
Host smart-6e49d35a-58b3-4786-b44c-0b7534312608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208542747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2208542747
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.4117939749
Short name T204
Test name
Test status
Simulation time 74709998661 ps
CPU time 67.08 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 04:52:13 PM PDT 24
Peak memory 199804 kb
Host smart-c353da2c-4c69-475d-89cc-6c748db80515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117939749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4117939749
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3956618238
Short name T750
Test name
Test status
Simulation time 22725583056 ps
CPU time 30.38 seconds
Started Jul 11 04:51:00 PM PDT 24
Finished Jul 11 04:51:33 PM PDT 24
Peak memory 199832 kb
Host smart-da67e489-4735-494b-8d18-cfc42a79cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956618238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3956618238
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3436845049
Short name T760
Test name
Test status
Simulation time 10003179174 ps
CPU time 15 seconds
Started Jul 11 04:52:00 PM PDT 24
Finished Jul 11 04:52:16 PM PDT 24
Peak memory 199812 kb
Host smart-bcbffe32-4924-4677-8870-606ff085d57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436845049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3436845049
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.18003008
Short name T992
Test name
Test status
Simulation time 14527106918 ps
CPU time 35.39 seconds
Started Jul 11 04:51:04 PM PDT 24
Finished Jul 11 04:51:43 PM PDT 24
Peak memory 199848 kb
Host smart-1baf6a31-2a4d-41d9-af81-92939ce782c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18003008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.18003008
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1445323626
Short name T510
Test name
Test status
Simulation time 14300788825 ps
CPU time 14.48 seconds
Started Jul 11 04:51:01 PM PDT 24
Finished Jul 11 04:51:19 PM PDT 24
Peak memory 199456 kb
Host smart-e03d4700-321c-49f0-b215-49f9dccf15d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445323626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1445323626
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.455957117
Short name T203
Test name
Test status
Simulation time 36655920669 ps
CPU time 17.1 seconds
Started Jul 11 04:51:07 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 199816 kb
Host smart-dd3c901e-be59-435f-81ef-ce73eb46b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455957117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.455957117
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2877562004
Short name T39
Test name
Test status
Simulation time 101962264105 ps
CPU time 149.4 seconds
Started Jul 11 04:51:07 PM PDT 24
Finished Jul 11 04:53:38 PM PDT 24
Peak memory 199668 kb
Host smart-b89c42e1-f5d8-49f4-afd4-084b5b3222cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877562004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2877562004
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1673990244
Short name T1138
Test name
Test status
Simulation time 50057651 ps
CPU time 0.58 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:49:08 PM PDT 24
Peak memory 195496 kb
Host smart-af93ebb8-1375-48ed-adeb-6d65f9382479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673990244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1673990244
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.872941268
Short name T1057
Test name
Test status
Simulation time 80961518565 ps
CPU time 25.03 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:49:17 PM PDT 24
Peak memory 199916 kb
Host smart-f7792167-591c-4ea6-8b8f-66eb52840d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872941268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.872941268
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.663979985
Short name T304
Test name
Test status
Simulation time 76984316884 ps
CPU time 113.78 seconds
Started Jul 11 04:48:48 PM PDT 24
Finished Jul 11 04:50:49 PM PDT 24
Peak memory 199836 kb
Host smart-80ed4be8-cc57-4959-a1d3-2f113c399d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663979985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.663979985
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1130041956
Short name T334
Test name
Test status
Simulation time 80442290704 ps
CPU time 30.43 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:49:26 PM PDT 24
Peak memory 199868 kb
Host smart-f42857d8-c309-40d7-8fb0-54b7d08bf8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130041956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1130041956
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1797822788
Short name T322
Test name
Test status
Simulation time 18537443851 ps
CPU time 16.52 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:49:18 PM PDT 24
Peak memory 199724 kb
Host smart-2747a844-3b13-4c24-8dbd-f877c44ce667
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797822788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1797822788
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1725604698
Short name T1121
Test name
Test status
Simulation time 81911680026 ps
CPU time 754.92 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 05:01:39 PM PDT 24
Peak memory 199740 kb
Host smart-97f85e22-eed5-4d05-93df-3edc11589fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725604698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1725604698
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3093865557
Short name T1035
Test name
Test status
Simulation time 2228286912 ps
CPU time 2.64 seconds
Started Jul 11 04:49:02 PM PDT 24
Finished Jul 11 04:49:12 PM PDT 24
Peak memory 196092 kb
Host smart-c6b46f19-1543-4a13-b719-500c858c16c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093865557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3093865557
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1998719111
Short name T786
Test name
Test status
Simulation time 75163953603 ps
CPU time 111.05 seconds
Started Jul 11 04:48:44 PM PDT 24
Finished Jul 11 04:50:43 PM PDT 24
Peak memory 199680 kb
Host smart-30f54104-c395-4e05-afb8-3536dc150898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998719111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1998719111
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1549300023
Short name T634
Test name
Test status
Simulation time 34996367700 ps
CPU time 335.82 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:54:32 PM PDT 24
Peak memory 199896 kb
Host smart-af19f49d-5d1e-41e2-b9d5-7a88f98f9c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549300023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1549300023
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1175517180
Short name T537
Test name
Test status
Simulation time 5029392978 ps
CPU time 11.34 seconds
Started Jul 11 04:48:53 PM PDT 24
Finished Jul 11 04:49:11 PM PDT 24
Peak memory 198024 kb
Host smart-f1ce8824-456f-4055-9ee5-3f811e6007a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175517180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1175517180
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1763245820
Short name T589
Test name
Test status
Simulation time 20144707980 ps
CPU time 34.21 seconds
Started Jul 11 04:48:43 PM PDT 24
Finished Jul 11 04:49:25 PM PDT 24
Peak memory 199608 kb
Host smart-de631d7d-b23c-4828-9ca8-67cad940ed84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763245820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1763245820
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2648232227
Short name T741
Test name
Test status
Simulation time 2122557856 ps
CPU time 1.57 seconds
Started Jul 11 04:48:48 PM PDT 24
Finished Jul 11 04:48:57 PM PDT 24
Peak memory 195280 kb
Host smart-ce815051-d376-4ca6-bf4d-806877988673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648232227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2648232227
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1443450592
Short name T267
Test name
Test status
Simulation time 5362007414 ps
CPU time 19.09 seconds
Started Jul 11 04:48:47 PM PDT 24
Finished Jul 11 04:49:13 PM PDT 24
Peak memory 199268 kb
Host smart-c0ea2966-0b2e-4dad-b4d1-5675c1841616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443450592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1443450592
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3427155617
Short name T1124
Test name
Test status
Simulation time 179565433959 ps
CPU time 136.89 seconds
Started Jul 11 04:48:56 PM PDT 24
Finished Jul 11 04:51:20 PM PDT 24
Peak memory 200200 kb
Host smart-63ae7919-dc20-4de0-a9ce-c4b8375f6fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427155617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3427155617
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3553355248
Short name T1087
Test name
Test status
Simulation time 33536677535 ps
CPU time 190.01 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:52:12 PM PDT 24
Peak memory 216388 kb
Host smart-6f163376-b91b-4475-a3e6-6d75be3b76f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553355248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3553355248
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1962488308
Short name T1079
Test name
Test status
Simulation time 1244357560 ps
CPU time 2.49 seconds
Started Jul 11 04:48:52 PM PDT 24
Finished Jul 11 04:49:01 PM PDT 24
Peak memory 198932 kb
Host smart-f796abd1-bfca-4a9f-b13b-2773a1ba540f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962488308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1962488308
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2868869790
Short name T439
Test name
Test status
Simulation time 17851482045 ps
CPU time 29.3 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:49:25 PM PDT 24
Peak memory 199932 kb
Host smart-aa629ee2-bf8a-4f60-9001-9c4104f36304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868869790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2868869790
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.4190273275
Short name T219
Test name
Test status
Simulation time 230980110094 ps
CPU time 88.71 seconds
Started Jul 11 04:51:08 PM PDT 24
Finished Jul 11 04:52:38 PM PDT 24
Peak memory 199832 kb
Host smart-3fb6152f-aedd-4186-9690-58781edd33dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190273275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.4190273275
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.593402328
Short name T221
Test name
Test status
Simulation time 46131721521 ps
CPU time 17.04 seconds
Started Jul 11 04:51:07 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 199552 kb
Host smart-4c1852e2-c299-4310-8253-e0835ba1913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593402328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.593402328
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2940422457
Short name T708
Test name
Test status
Simulation time 165683698596 ps
CPU time 50.09 seconds
Started Jul 11 04:51:06 PM PDT 24
Finished Jul 11 04:51:58 PM PDT 24
Peak memory 199544 kb
Host smart-c1c1b9d7-e3b1-4ed6-96eb-b3e7e01cec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940422457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2940422457
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2430522578
Short name T1113
Test name
Test status
Simulation time 35519301140 ps
CPU time 12.99 seconds
Started Jul 11 04:51:13 PM PDT 24
Finished Jul 11 04:51:28 PM PDT 24
Peak memory 199876 kb
Host smart-6586fc98-52c7-4eb2-ab4d-a0d03b5f934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430522578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2430522578
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2084630220
Short name T927
Test name
Test status
Simulation time 129274316725 ps
CPU time 30.29 seconds
Started Jul 11 04:51:11 PM PDT 24
Finished Jul 11 04:51:42 PM PDT 24
Peak memory 199916 kb
Host smart-a6835b25-5cdc-4270-be1c-c83ec0f2063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084630220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2084630220
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2012162317
Short name T1043
Test name
Test status
Simulation time 13485311994 ps
CPU time 22.86 seconds
Started Jul 11 04:51:10 PM PDT 24
Finished Jul 11 04:51:34 PM PDT 24
Peak memory 199884 kb
Host smart-540a7f87-3574-4027-80c9-f0c689bbbb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012162317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2012162317
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1179070925
Short name T95
Test name
Test status
Simulation time 130172099444 ps
CPU time 122.35 seconds
Started Jul 11 04:51:05 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 199840 kb
Host smart-b8142025-60a0-430f-a271-36f9eb212622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179070925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1179070925
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2096979111
Short name T1054
Test name
Test status
Simulation time 50196870648 ps
CPU time 25.67 seconds
Started Jul 11 04:51:06 PM PDT 24
Finished Jul 11 04:51:34 PM PDT 24
Peak memory 199864 kb
Host smart-18533659-8656-45eb-9daf-34025bc1fe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096979111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2096979111
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2236536811
Short name T1021
Test name
Test status
Simulation time 170253909621 ps
CPU time 61.13 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 199544 kb
Host smart-2a704b06-3a5d-4e23-a858-6835d3f48a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236536811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2236536811
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.811803521
Short name T1001
Test name
Test status
Simulation time 197929493405 ps
CPU time 146.94 seconds
Started Jul 11 04:51:11 PM PDT 24
Finished Jul 11 04:53:40 PM PDT 24
Peak memory 199864 kb
Host smart-7cfd15b8-d606-47d9-a493-9170f1664837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811803521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.811803521
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3008378103
Short name T656
Test name
Test status
Simulation time 11383989 ps
CPU time 0.54 seconds
Started Jul 11 04:48:54 PM PDT 24
Finished Jul 11 04:49:01 PM PDT 24
Peak memory 194048 kb
Host smart-706f3d50-72a1-4e72-b239-b8edffb9810d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008378103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3008378103
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.489790100
Short name T564
Test name
Test status
Simulation time 165454876321 ps
CPU time 70.77 seconds
Started Jul 11 04:48:51 PM PDT 24
Finished Jul 11 04:50:09 PM PDT 24
Peak memory 199920 kb
Host smart-e795bf17-3b5f-465d-a025-3d087e5a1aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489790100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.489790100
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3098115928
Short name T277
Test name
Test status
Simulation time 130061015995 ps
CPU time 101.94 seconds
Started Jul 11 04:48:56 PM PDT 24
Finished Jul 11 04:50:45 PM PDT 24
Peak memory 199860 kb
Host smart-e826f042-7db6-4af1-a865-318cba34a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098115928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3098115928
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.557480889
Short name T931
Test name
Test status
Simulation time 139042928163 ps
CPU time 195.79 seconds
Started Jul 11 04:48:54 PM PDT 24
Finished Jul 11 04:52:17 PM PDT 24
Peak memory 199720 kb
Host smart-c980045b-70b9-46e2-a660-233aa0e0ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557480889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.557480889
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2403975555
Short name T294
Test name
Test status
Simulation time 34870564329 ps
CPU time 62.83 seconds
Started Jul 11 04:48:50 PM PDT 24
Finished Jul 11 04:49:59 PM PDT 24
Peak memory 200124 kb
Host smart-b6a51906-d3c1-4b75-9f91-dbfda5ef83cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403975555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2403975555
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3751803632
Short name T592
Test name
Test status
Simulation time 87335826061 ps
CPU time 421.73 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:56:03 PM PDT 24
Peak memory 199804 kb
Host smart-13313d8a-d10c-425e-9165-56c0d03dabcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751803632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3751803632
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1218090308
Short name T945
Test name
Test status
Simulation time 6483891080 ps
CPU time 4.13 seconds
Started Jul 11 04:49:03 PM PDT 24
Finished Jul 11 04:49:14 PM PDT 24
Peak memory 199760 kb
Host smart-d24bc7a9-b4e4-427d-bf5f-d2b1d7ad01eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218090308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1218090308
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1936098934
Short name T621
Test name
Test status
Simulation time 39873857602 ps
CPU time 59.42 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:50:02 PM PDT 24
Peak memory 199828 kb
Host smart-48eaa993-56ce-4f78-8739-7aa2131f0735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936098934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1936098934
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.4024307641
Short name T468
Test name
Test status
Simulation time 17514288147 ps
CPU time 49.79 seconds
Started Jul 11 04:48:52 PM PDT 24
Finished Jul 11 04:49:49 PM PDT 24
Peak memory 199896 kb
Host smart-762ec96c-3eac-4fa1-bd0d-8c07d6e1243d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024307641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4024307641
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.934563898
Short name T79
Test name
Test status
Simulation time 5459733370 ps
CPU time 40.46 seconds
Started Jul 11 04:48:54 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 199040 kb
Host smart-7514d29d-74cd-42e9-adc1-9ef426df7ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934563898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.934563898
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2685287075
Short name T962
Test name
Test status
Simulation time 39204772985 ps
CPU time 35.7 seconds
Started Jul 11 04:48:50 PM PDT 24
Finished Jul 11 04:49:33 PM PDT 24
Peak memory 199748 kb
Host smart-ddec51dd-0ac1-46d1-ad90-29857ef930c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685287075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2685287075
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.4062434291
Short name T284
Test name
Test status
Simulation time 3243199076 ps
CPU time 5.78 seconds
Started Jul 11 04:48:50 PM PDT 24
Finished Jul 11 04:49:04 PM PDT 24
Peak memory 196256 kb
Host smart-f18c8e34-0c0e-4926-9733-80f1f24ef414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062434291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4062434291
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3189969580
Short name T1139
Test name
Test status
Simulation time 681859698 ps
CPU time 1.8 seconds
Started Jul 11 04:48:49 PM PDT 24
Finished Jul 11 04:48:57 PM PDT 24
Peak memory 199424 kb
Host smart-8e2cdb83-57ea-4c0b-8409-508613f43d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189969580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3189969580
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.951341557
Short name T827
Test name
Test status
Simulation time 532620011896 ps
CPU time 115.95 seconds
Started Jul 11 04:48:53 PM PDT 24
Finished Jul 11 04:50:57 PM PDT 24
Peak memory 216332 kb
Host smart-7af5da56-cdfd-4ba0-be8e-1d6934db067e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951341557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.951341557
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.494983923
Short name T536
Test name
Test status
Simulation time 17486126142 ps
CPU time 553.79 seconds
Started Jul 11 04:48:59 PM PDT 24
Finished Jul 11 04:58:20 PM PDT 24
Peak memory 216572 kb
Host smart-4e874366-a623-4be3-9395-14d150c9a4ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494983923 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.494983923
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2743987650
Short name T269
Test name
Test status
Simulation time 1365287255 ps
CPU time 2.52 seconds
Started Jul 11 04:48:57 PM PDT 24
Finished Jul 11 04:49:06 PM PDT 24
Peak memory 199500 kb
Host smart-13eee59b-de92-40f4-a6b1-9560cb51a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743987650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2743987650
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3840654482
Short name T867
Test name
Test status
Simulation time 59874684683 ps
CPU time 44.55 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:49:47 PM PDT 24
Peak memory 199844 kb
Host smart-4e86b456-3251-475c-97c5-07d7a61deed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840654482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3840654482
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.492250160
Short name T333
Test name
Test status
Simulation time 272981172337 ps
CPU time 32.26 seconds
Started Jul 11 04:51:10 PM PDT 24
Finished Jul 11 04:51:44 PM PDT 24
Peak memory 199884 kb
Host smart-c4015692-99b0-420b-9e3c-93df48a2bf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492250160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.492250160
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.777051173
Short name T167
Test name
Test status
Simulation time 77648089726 ps
CPU time 39.17 seconds
Started Jul 11 04:51:06 PM PDT 24
Finished Jul 11 04:51:48 PM PDT 24
Peak memory 199896 kb
Host smart-38901e15-4b24-4caa-8e73-39993c94ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777051173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.777051173
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.740699987
Short name T540
Test name
Test status
Simulation time 55682042509 ps
CPU time 46.19 seconds
Started Jul 11 04:51:14 PM PDT 24
Finished Jul 11 04:52:03 PM PDT 24
Peak memory 199652 kb
Host smart-6ecdee0c-6e48-44ce-8852-94d17843c86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740699987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.740699987
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.68332993
Short name T1131
Test name
Test status
Simulation time 155030327569 ps
CPU time 98.59 seconds
Started Jul 11 04:51:14 PM PDT 24
Finished Jul 11 04:52:55 PM PDT 24
Peak memory 199820 kb
Host smart-422c8fd6-cbff-46cd-80de-d45ab59372d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68332993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.68332993
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4006685595
Short name T100
Test name
Test status
Simulation time 66529561974 ps
CPU time 25.92 seconds
Started Jul 11 04:51:08 PM PDT 24
Finished Jul 11 04:51:35 PM PDT 24
Peak memory 199248 kb
Host smart-485ef93b-b7a5-4616-a137-25ed841747bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006685595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4006685595
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3701937412
Short name T783
Test name
Test status
Simulation time 32427149480 ps
CPU time 33.08 seconds
Started Jul 11 04:51:08 PM PDT 24
Finished Jul 11 04:51:42 PM PDT 24
Peak memory 199944 kb
Host smart-5399821e-da5b-46bb-bea6-1c86f21681d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701937412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3701937412
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3548024474
Short name T525
Test name
Test status
Simulation time 17712429515 ps
CPU time 10.45 seconds
Started Jul 11 04:51:14 PM PDT 24
Finished Jul 11 04:51:27 PM PDT 24
Peak memory 199876 kb
Host smart-35b7d6e6-09a7-47d3-a971-c81046829187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548024474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3548024474
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1884432438
Short name T215
Test name
Test status
Simulation time 206692877091 ps
CPU time 163.47 seconds
Started Jul 11 04:51:14 PM PDT 24
Finished Jul 11 04:54:00 PM PDT 24
Peak memory 199668 kb
Host smart-b05484a3-5bfa-40a7-9b91-7d4cd35a6554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884432438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1884432438
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.846840396
Short name T668
Test name
Test status
Simulation time 24756003455 ps
CPU time 19.34 seconds
Started Jul 11 04:51:14 PM PDT 24
Finished Jul 11 04:51:35 PM PDT 24
Peak memory 200108 kb
Host smart-424e0b90-f809-47b0-be6c-d3abbfb3c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846840396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.846840396
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1875840173
Short name T875
Test name
Test status
Simulation time 24251651 ps
CPU time 0.58 seconds
Started Jul 11 04:48:57 PM PDT 24
Finished Jul 11 04:49:05 PM PDT 24
Peak memory 195156 kb
Host smart-cb3b6605-425e-4364-a468-63c257b693aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875840173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1875840173
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3692625191
Short name T670
Test name
Test status
Simulation time 66825354430 ps
CPU time 96.85 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:50:41 PM PDT 24
Peak memory 199564 kb
Host smart-b46f890b-7d25-4282-ad22-1a95e00041da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692625191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3692625191
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.178505263
Short name T308
Test name
Test status
Simulation time 109980824288 ps
CPU time 169.55 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:51:54 PM PDT 24
Peak memory 199780 kb
Host smart-85b6e46f-d3f2-4f91-afb5-07361800714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178505263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.178505263
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1427693598
Short name T771
Test name
Test status
Simulation time 51590408249 ps
CPU time 46.53 seconds
Started Jul 11 04:49:01 PM PDT 24
Finished Jul 11 04:49:55 PM PDT 24
Peak memory 199760 kb
Host smart-a0e39ba2-d6fc-4974-bd48-8e5b8664ff69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427693598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1427693598
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1647781131
Short name T372
Test name
Test status
Simulation time 29689820330 ps
CPU time 102.43 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:50:45 PM PDT 24
Peak memory 199900 kb
Host smart-8bec3d04-0367-47eb-b2fa-55d604ae96c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647781131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1647781131
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1110883636
Short name T615
Test name
Test status
Simulation time 8019345663 ps
CPU time 4.15 seconds
Started Jul 11 04:48:56 PM PDT 24
Finished Jul 11 04:49:07 PM PDT 24
Peak memory 198868 kb
Host smart-f4f72024-44b8-44f6-908c-bba302670b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110883636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1110883636
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.13384086
Short name T713
Test name
Test status
Simulation time 17557865784 ps
CPU time 17.51 seconds
Started Jul 11 04:48:59 PM PDT 24
Finished Jul 11 04:49:24 PM PDT 24
Peak memory 198376 kb
Host smart-f9fb4296-b0e9-418f-8c23-739bc13ed9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13384086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.13384086
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.991075892
Short name T271
Test name
Test status
Simulation time 15569492199 ps
CPU time 221.34 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:52:46 PM PDT 24
Peak memory 199736 kb
Host smart-cb932da6-3fd8-48fd-be1e-47352f35c4a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991075892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.991075892
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3939586326
Short name T846
Test name
Test status
Simulation time 4527586494 ps
CPU time 8.16 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:49:13 PM PDT 24
Peak memory 198748 kb
Host smart-a6f4aeff-339a-4f6c-a42d-144e90eb5a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939586326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3939586326
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.677959047
Short name T176
Test name
Test status
Simulation time 55875662826 ps
CPU time 57.99 seconds
Started Jul 11 04:48:56 PM PDT 24
Finished Jul 11 04:50:01 PM PDT 24
Peak memory 199612 kb
Host smart-4e2665ec-f534-4671-9f45-5919d341e649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677959047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.677959047
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4263477864
Short name T707
Test name
Test status
Simulation time 3501658601 ps
CPU time 5.95 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:49:11 PM PDT 24
Peak memory 196364 kb
Host smart-2d858727-6991-4fdc-9153-dc34154680a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263477864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4263477864
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3417047061
Short name T596
Test name
Test status
Simulation time 5489416259 ps
CPU time 15.67 seconds
Started Jul 11 04:48:55 PM PDT 24
Finished Jul 11 04:49:19 PM PDT 24
Peak memory 199712 kb
Host smart-273b9d5f-fd77-4971-b183-67ab573922bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417047061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3417047061
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3741185788
Short name T757
Test name
Test status
Simulation time 243293267287 ps
CPU time 1493.85 seconds
Started Jul 11 04:49:04 PM PDT 24
Finished Jul 11 05:14:05 PM PDT 24
Peak memory 199852 kb
Host smart-178ae623-c0e1-4b19-a471-5b04ae38ae41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741185788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3741185788
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1507706281
Short name T929
Test name
Test status
Simulation time 156395336586 ps
CPU time 334.9 seconds
Started Jul 11 04:49:02 PM PDT 24
Finished Jul 11 04:54:44 PM PDT 24
Peak memory 216024 kb
Host smart-10972eb3-1d24-46c4-9b95-c01bee0b49da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507706281 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1507706281
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2251569333
Short name T1011
Test name
Test status
Simulation time 6859839371 ps
CPU time 37.34 seconds
Started Jul 11 04:48:58 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 199904 kb
Host smart-fb347656-758f-4d00-9617-65c3cde67da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251569333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2251569333
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3895527517
Short name T8
Test name
Test status
Simulation time 132981290188 ps
CPU time 75.65 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:50:23 PM PDT 24
Peak memory 199912 kb
Host smart-2ca156b3-1b02-48e5-a260-dca09e8e46cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895527517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3895527517
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.768818119
Short name T274
Test name
Test status
Simulation time 128653244953 ps
CPU time 44.24 seconds
Started Jul 11 04:51:21 PM PDT 24
Finished Jul 11 04:52:09 PM PDT 24
Peak memory 199256 kb
Host smart-2cdab9ac-fd60-4901-be29-39d777189820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768818119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.768818119
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1366577562
Short name T1047
Test name
Test status
Simulation time 46651564057 ps
CPU time 73.61 seconds
Started Jul 11 04:51:12 PM PDT 24
Finished Jul 11 04:52:28 PM PDT 24
Peak memory 199920 kb
Host smart-06e7c39e-a072-4830-93cb-15cf9761f170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366577562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1366577562
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1195377333
Short name T633
Test name
Test status
Simulation time 129077623790 ps
CPU time 10.82 seconds
Started Jul 11 04:51:11 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 199716 kb
Host smart-85e31b61-5e5f-4534-92b8-fa49ab52ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195377333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1195377333
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1378749780
Short name T595
Test name
Test status
Simulation time 91311988269 ps
CPU time 145.66 seconds
Started Jul 11 04:51:16 PM PDT 24
Finished Jul 11 04:53:43 PM PDT 24
Peak memory 199776 kb
Host smart-ae6fd8d2-c72b-41b2-9727-4735b25f780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378749780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1378749780
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2589394030
Short name T137
Test name
Test status
Simulation time 19778965591 ps
CPU time 30.47 seconds
Started Jul 11 04:51:11 PM PDT 24
Finished Jul 11 04:51:44 PM PDT 24
Peak memory 199848 kb
Host smart-16893da6-97b9-46db-85af-671939210bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589394030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2589394030
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3074032602
Short name T417
Test name
Test status
Simulation time 29241936941 ps
CPU time 11.57 seconds
Started Jul 11 04:51:14 PM PDT 24
Finished Jul 11 04:51:28 PM PDT 24
Peak memory 199864 kb
Host smart-46e1fb1b-9f67-4f66-bcba-28698b24023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074032602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3074032602
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2381155315
Short name T933
Test name
Test status
Simulation time 11032068708 ps
CPU time 9.91 seconds
Started Jul 11 04:51:21 PM PDT 24
Finished Jul 11 04:51:35 PM PDT 24
Peak memory 199204 kb
Host smart-7dd57763-777b-4c93-ac6c-8ee2c1da2ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381155315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2381155315
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3672844581
Short name T1099
Test name
Test status
Simulation time 20431844710 ps
CPU time 22.23 seconds
Started Jul 11 04:51:12 PM PDT 24
Finished Jul 11 04:51:36 PM PDT 24
Peak memory 199920 kb
Host smart-ef284004-921e-4b13-8144-d05a3e4f4665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672844581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3672844581
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3181203756
Short name T205
Test name
Test status
Simulation time 29960866404 ps
CPU time 67.72 seconds
Started Jul 11 04:51:13 PM PDT 24
Finished Jul 11 04:52:23 PM PDT 24
Peak memory 199896 kb
Host smart-d021e5b4-3748-43cc-bd12-b2af9cf82142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181203756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3181203756
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1323373258
Short name T642
Test name
Test status
Simulation time 36381715 ps
CPU time 0.56 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:03 PM PDT 24
Peak memory 194208 kb
Host smart-588df8ba-b62a-4fec-bd69-83cf4bca6408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323373258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1323373258
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1845983636
Short name T260
Test name
Test status
Simulation time 130047255906 ps
CPU time 289.21 seconds
Started Jul 11 04:48:09 PM PDT 24
Finished Jul 11 04:53:02 PM PDT 24
Peak memory 199848 kb
Host smart-493e9266-48eb-40cb-a608-47bcfa2d2e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845983636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1845983636
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3364509264
Short name T881
Test name
Test status
Simulation time 12202379451 ps
CPU time 21.33 seconds
Started Jul 11 04:48:07 PM PDT 24
Finished Jul 11 04:48:32 PM PDT 24
Peak memory 199740 kb
Host smart-f2ee75a3-9d59-41eb-b536-54eccfb4a340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364509264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3364509264
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2206808640
Short name T213
Test name
Test status
Simulation time 21697744658 ps
CPU time 15.9 seconds
Started Jul 11 04:48:00 PM PDT 24
Finished Jul 11 04:48:22 PM PDT 24
Peak memory 199772 kb
Host smart-f9339ea3-b162-4824-ab9e-28132d8f809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206808640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2206808640
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2303050664
Short name T871
Test name
Test status
Simulation time 38258939319 ps
CPU time 61.31 seconds
Started Jul 11 04:47:58 PM PDT 24
Finished Jul 11 04:49:05 PM PDT 24
Peak memory 199880 kb
Host smart-3924528f-a052-4b91-a645-f81de9322481
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303050664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2303050664
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.365711722
Short name T278
Test name
Test status
Simulation time 149177940574 ps
CPU time 286.88 seconds
Started Jul 11 04:48:09 PM PDT 24
Finished Jul 11 04:53:01 PM PDT 24
Peak memory 199792 kb
Host smart-dee1dc2c-8056-45ff-afd8-76f26f7a732d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365711722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.365711722
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3517310828
Short name T752
Test name
Test status
Simulation time 795665394 ps
CPU time 1.18 seconds
Started Jul 11 04:48:03 PM PDT 24
Finished Jul 11 04:48:09 PM PDT 24
Peak memory 198300 kb
Host smart-aad50bc5-3de1-46b8-b8ef-3b6e592701a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517310828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3517310828
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2090694990
Short name T501
Test name
Test status
Simulation time 33068630959 ps
CPU time 49.95 seconds
Started Jul 11 04:48:09 PM PDT 24
Finished Jul 11 04:49:04 PM PDT 24
Peak memory 199924 kb
Host smart-87a1bc14-a1bd-4892-b217-4cfaba398209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090694990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2090694990
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.415923046
Short name T942
Test name
Test status
Simulation time 21041485690 ps
CPU time 245.55 seconds
Started Jul 11 04:47:57 PM PDT 24
Finished Jul 11 04:52:08 PM PDT 24
Peak memory 199848 kb
Host smart-5bad3edf-3f6a-4424-b79c-26741987a1b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415923046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.415923046
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3168334297
Short name T718
Test name
Test status
Simulation time 2239680458 ps
CPU time 8.39 seconds
Started Jul 11 04:48:12 PM PDT 24
Finished Jul 11 04:48:25 PM PDT 24
Peak memory 198732 kb
Host smart-b855d4f6-d5c8-49de-ace1-5f30f6175019
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168334297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3168334297
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.331843087
Short name T1130
Test name
Test status
Simulation time 29752690584 ps
CPU time 55.11 seconds
Started Jul 11 04:47:57 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 199832 kb
Host smart-c11132d3-234c-4849-8759-7b4926cc56bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331843087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.331843087
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.4279276193
Short name T98
Test name
Test status
Simulation time 3823486846 ps
CPU time 2.08 seconds
Started Jul 11 04:48:08 PM PDT 24
Finished Jul 11 04:48:14 PM PDT 24
Peak memory 196300 kb
Host smart-ce90fd41-344e-4b4b-a0b9-c2f37fb3f271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279276193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.4279276193
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3430471568
Short name T22
Test name
Test status
Simulation time 35403285 ps
CPU time 0.83 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:02 PM PDT 24
Peak memory 218372 kb
Host smart-8c74eef2-1d51-4b00-8ad9-76e5dcd3eaec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430471568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3430471568
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2799144180
Short name T967
Test name
Test status
Simulation time 295120908 ps
CPU time 1.17 seconds
Started Jul 11 04:47:54 PM PDT 24
Finished Jul 11 04:48:02 PM PDT 24
Peak memory 198292 kb
Host smart-17f29b82-fe4e-4e23-bd45-97b6af41736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799144180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2799144180
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1792715691
Short name T611
Test name
Test status
Simulation time 6604295759 ps
CPU time 25.44 seconds
Started Jul 11 04:48:16 PM PDT 24
Finished Jul 11 04:48:45 PM PDT 24
Peak memory 199824 kb
Host smart-225a08ab-5365-494f-97f2-ac08bb25971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792715691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1792715691
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.853809944
Short name T1101
Test name
Test status
Simulation time 28522909264 ps
CPU time 45.63 seconds
Started Jul 11 04:48:08 PM PDT 24
Finished Jul 11 04:48:57 PM PDT 24
Peak memory 199900 kb
Host smart-b314200e-ba41-4cf9-8dd9-4ab4b867a711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853809944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.853809944
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.252100555
Short name T19
Test name
Test status
Simulation time 45752090 ps
CPU time 0.59 seconds
Started Jul 11 04:49:01 PM PDT 24
Finished Jul 11 04:49:09 PM PDT 24
Peak memory 195148 kb
Host smart-8c28bb22-04cb-4fe9-b71c-fa3428409558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252100555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.252100555
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2752724009
Short name T348
Test name
Test status
Simulation time 106956933763 ps
CPU time 80.07 seconds
Started Jul 11 04:49:01 PM PDT 24
Finished Jul 11 04:50:28 PM PDT 24
Peak memory 199828 kb
Host smart-fd905042-87c9-496a-b0eb-ffb0506abb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752724009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2752724009
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.4167561346
Short name T266
Test name
Test status
Simulation time 44385847658 ps
CPU time 26.89 seconds
Started Jul 11 04:48:59 PM PDT 24
Finished Jul 11 04:49:33 PM PDT 24
Peak memory 199800 kb
Host smart-29019689-e6d8-496f-84a9-74bcc6d593de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167561346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.4167561346
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.66864979
Short name T361
Test name
Test status
Simulation time 11206066376 ps
CPU time 2.32 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:49:09 PM PDT 24
Peak memory 199816 kb
Host smart-cbff9771-1961-4e45-ba33-a0fdacf5ab77
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66864979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.66864979
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2071362374
Short name T1088
Test name
Test status
Simulation time 43443879675 ps
CPU time 43.12 seconds
Started Jul 11 04:49:02 PM PDT 24
Finished Jul 11 04:49:52 PM PDT 24
Peak memory 199760 kb
Host smart-999baddf-c52d-4171-bdf5-d87147771778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071362374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2071362374
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.604348334
Short name T485
Test name
Test status
Simulation time 2960198578 ps
CPU time 6.98 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:49:14 PM PDT 24
Peak memory 198364 kb
Host smart-d1622b82-f218-44f0-bc3a-0faf2282c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604348334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.604348334
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2418498296
Short name T1065
Test name
Test status
Simulation time 29808496483 ps
CPU time 25.64 seconds
Started Jul 11 04:48:59 PM PDT 24
Finished Jul 11 04:49:31 PM PDT 24
Peak memory 198240 kb
Host smart-88746942-3887-4c96-84fe-ff5f8bfd9e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418498296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2418498296
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.179632839
Short name T1179
Test name
Test status
Simulation time 4493731508 ps
CPU time 73.07 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:50:20 PM PDT 24
Peak memory 199800 kb
Host smart-b1553ac3-090f-46ee-93ec-47c2d1e0605b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179632839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.179632839
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1800393862
Short name T727
Test name
Test status
Simulation time 5483699149 ps
CPU time 44.16 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:49:51 PM PDT 24
Peak memory 199844 kb
Host smart-61dc744a-1348-4d52-836c-ddca3786de99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800393862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1800393862
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3416939696
Short name T168
Test name
Test status
Simulation time 122978438481 ps
CPU time 64.71 seconds
Started Jul 11 04:49:01 PM PDT 24
Finished Jul 11 04:50:13 PM PDT 24
Peak memory 199660 kb
Host smart-28258d61-4498-48fd-a1c0-fa5c0e1be166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416939696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3416939696
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2382094811
Short name T352
Test name
Test status
Simulation time 2500111457 ps
CPU time 0.93 seconds
Started Jul 11 04:49:05 PM PDT 24
Finished Jul 11 04:49:13 PM PDT 24
Peak memory 195844 kb
Host smart-292a4153-dd6d-45c0-af09-713789f61d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382094811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2382094811
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3422376808
Short name T800
Test name
Test status
Simulation time 552559630 ps
CPU time 2.03 seconds
Started Jul 11 04:49:04 PM PDT 24
Finished Jul 11 04:49:13 PM PDT 24
Peak memory 198392 kb
Host smart-f09b8233-e7fe-4dfa-8e89-36bffb8b25f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422376808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3422376808
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.4078277903
Short name T473
Test name
Test status
Simulation time 341646441437 ps
CPU time 139.68 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:51:27 PM PDT 24
Peak memory 199860 kb
Host smart-0894f117-f784-4749-b1c1-d8a7b95606f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078277903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4078277903
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1699542659
Short name T43
Test name
Test status
Simulation time 99424943390 ps
CPU time 507.35 seconds
Started Jul 11 04:49:01 PM PDT 24
Finished Jul 11 04:57:36 PM PDT 24
Peak memory 225776 kb
Host smart-0e9693d2-3120-4519-9563-9784fb8a8cd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699542659 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1699542659
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2166266935
Short name T488
Test name
Test status
Simulation time 786394855 ps
CPU time 1.93 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:49:09 PM PDT 24
Peak memory 199024 kb
Host smart-8b09d2e3-fafa-4dda-bcd9-fe3b5792ac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166266935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2166266935
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.4292102710
Short name T1006
Test name
Test status
Simulation time 79449291466 ps
CPU time 35.92 seconds
Started Jul 11 04:48:56 PM PDT 24
Finished Jul 11 04:49:39 PM PDT 24
Peak memory 199868 kb
Host smart-c59494aa-eeca-40cc-9670-eb1b9a9aaab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292102710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4292102710
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1737908444
Short name T1073
Test name
Test status
Simulation time 42091794 ps
CPU time 0.6 seconds
Started Jul 11 04:49:08 PM PDT 24
Finished Jul 11 04:49:14 PM PDT 24
Peak memory 195516 kb
Host smart-5e190fa0-e454-426d-91bf-ebd1ed90eb97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737908444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1737908444
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.765276283
Short name T379
Test name
Test status
Simulation time 17479010194 ps
CPU time 41.66 seconds
Started Jul 11 04:49:06 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 199908 kb
Host smart-43e7cca5-ad25-43a0-89c9-80dcccc4b952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765276283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.765276283
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3403783685
Short name T33
Test name
Test status
Simulation time 104407585427 ps
CPU time 44.7 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:49:52 PM PDT 24
Peak memory 199856 kb
Host smart-2c379424-52e5-4d04-bb24-bf897a95bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403783685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3403783685
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3606376232
Short name T623
Test name
Test status
Simulation time 62308209941 ps
CPU time 29.59 seconds
Started Jul 11 04:49:02 PM PDT 24
Finished Jul 11 04:49:39 PM PDT 24
Peak memory 199820 kb
Host smart-523e79ee-410b-429f-a11b-841f1ff03148
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606376232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3606376232
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2126569137
Short name T906
Test name
Test status
Simulation time 84095385186 ps
CPU time 625.8 seconds
Started Jul 11 04:49:05 PM PDT 24
Finished Jul 11 04:59:37 PM PDT 24
Peak memory 199764 kb
Host smart-c77842c4-7ba1-44b4-9391-d39612666b48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126569137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2126569137
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1584098830
Short name T366
Test name
Test status
Simulation time 245193415 ps
CPU time 0.84 seconds
Started Jul 11 04:49:06 PM PDT 24
Finished Jul 11 04:49:13 PM PDT 24
Peak memory 197852 kb
Host smart-c1568905-359b-4263-9869-f4f987f900e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584098830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1584098830
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3275392143
Short name T957
Test name
Test status
Simulation time 22539521617 ps
CPU time 46.46 seconds
Started Jul 11 04:49:05 PM PDT 24
Finished Jul 11 04:49:58 PM PDT 24
Peak memory 199996 kb
Host smart-28adceb0-77c0-4b18-a053-c37199456045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275392143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3275392143
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3504915647
Short name T618
Test name
Test status
Simulation time 16445533291 ps
CPU time 946.88 seconds
Started Jul 11 04:49:16 PM PDT 24
Finished Jul 11 05:05:09 PM PDT 24
Peak memory 199756 kb
Host smart-be57c2b2-267e-41e0-9e49-7c6f93a554f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504915647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3504915647
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1744225815
Short name T579
Test name
Test status
Simulation time 5890253777 ps
CPU time 49.44 seconds
Started Jul 11 04:48:59 PM PDT 24
Finished Jul 11 04:49:56 PM PDT 24
Peak memory 197956 kb
Host smart-5024fbf6-70d4-4100-8dd9-3021849b4fa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1744225815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1744225815
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1375955885
Short name T5
Test name
Test status
Simulation time 56299651106 ps
CPU time 84.65 seconds
Started Jul 11 04:49:04 PM PDT 24
Finished Jul 11 04:50:36 PM PDT 24
Peak memory 199852 kb
Host smart-f34b35ce-7db3-4b59-a583-cf401a8425eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375955885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1375955885
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.197975098
Short name T886
Test name
Test status
Simulation time 5112026496 ps
CPU time 1.83 seconds
Started Jul 11 04:49:06 PM PDT 24
Finished Jul 11 04:49:14 PM PDT 24
Peak memory 196328 kb
Host smart-04cbe18e-6414-499c-b626-6058a82dd67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197975098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.197975098
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1256379459
Short name T1172
Test name
Test status
Simulation time 6242212787 ps
CPU time 45.18 seconds
Started Jul 11 04:49:00 PM PDT 24
Finished Jul 11 04:49:52 PM PDT 24
Peak memory 199836 kb
Host smart-7402f7b3-667c-4ae9-b140-656edb385c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256379459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1256379459
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3869466500
Short name T650
Test name
Test status
Simulation time 164677723041 ps
CPU time 594.58 seconds
Started Jul 11 04:49:06 PM PDT 24
Finished Jul 11 04:59:07 PM PDT 24
Peak memory 199896 kb
Host smart-dd09a558-45f0-49a3-b1ae-7a16d3e3c473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869466500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3869466500
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1077219056
Short name T315
Test name
Test status
Simulation time 58632859685 ps
CPU time 326.55 seconds
Started Jul 11 04:49:10 PM PDT 24
Finished Jul 11 04:54:42 PM PDT 24
Peak memory 215712 kb
Host smart-b9ab0698-08be-48e6-b1a9-30e4bd6eb7db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077219056 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1077219056
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1036626132
Short name T577
Test name
Test status
Simulation time 973361710 ps
CPU time 1.2 seconds
Started Jul 11 04:49:08 PM PDT 24
Finished Jul 11 04:49:15 PM PDT 24
Peak memory 198008 kb
Host smart-40a21c18-aeac-40ee-885c-b8cac188ca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036626132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1036626132
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.4051021364
Short name T889
Test name
Test status
Simulation time 97318727846 ps
CPU time 146.64 seconds
Started Jul 11 04:48:59 PM PDT 24
Finished Jul 11 04:51:33 PM PDT 24
Peak memory 199820 kb
Host smart-f4bb6801-1ed6-4293-9823-f896c595366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051021364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4051021364
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4174488429
Short name T831
Test name
Test status
Simulation time 127439011 ps
CPU time 0.56 seconds
Started Jul 11 04:49:12 PM PDT 24
Finished Jul 11 04:49:17 PM PDT 24
Peak memory 195236 kb
Host smart-d09a1ad5-da55-48cd-9c11-d4ef8ea93c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174488429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4174488429
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3263064132
Short name T1038
Test name
Test status
Simulation time 87635555097 ps
CPU time 23.25 seconds
Started Jul 11 04:49:14 PM PDT 24
Finished Jul 11 04:49:44 PM PDT 24
Peak memory 199836 kb
Host smart-9283539c-f802-4c5c-977e-2fc842bc425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263064132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3263064132
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.219676418
Short name T1159
Test name
Test status
Simulation time 144140814970 ps
CPU time 357.67 seconds
Started Jul 11 04:49:16 PM PDT 24
Finished Jul 11 04:55:19 PM PDT 24
Peak memory 199776 kb
Host smart-d151868c-2b20-4964-83d1-b391c8bd6800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219676418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.219676418
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.503691699
Short name T518
Test name
Test status
Simulation time 110087027819 ps
CPU time 41.96 seconds
Started Jul 11 04:49:10 PM PDT 24
Finished Jul 11 04:49:58 PM PDT 24
Peak memory 199772 kb
Host smart-4ce862bf-efc6-4033-9ba4-240a2c4a5dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503691699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.503691699
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1858930329
Short name T1140
Test name
Test status
Simulation time 60657329081 ps
CPU time 13.02 seconds
Started Jul 11 04:49:12 PM PDT 24
Finished Jul 11 04:49:31 PM PDT 24
Peak memory 199764 kb
Host smart-caa9b435-e4e7-4697-a5d7-1a56c2cce8f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858930329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1858930329
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.4221145655
Short name T575
Test name
Test status
Simulation time 81651939697 ps
CPU time 660.42 seconds
Started Jul 11 04:49:11 PM PDT 24
Finished Jul 11 05:00:17 PM PDT 24
Peak memory 199848 kb
Host smart-98c10f1d-5d19-4ba1-b925-54b669d60423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221145655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.4221145655
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1488228253
Short name T679
Test name
Test status
Simulation time 2504471322 ps
CPU time 1.67 seconds
Started Jul 11 04:49:12 PM PDT 24
Finished Jul 11 04:49:20 PM PDT 24
Peak memory 197024 kb
Host smart-ac6ff50c-4ba0-4d89-8a1c-a4d301fe53ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488228253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1488228253
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1438387142
Short name T356
Test name
Test status
Simulation time 78114853575 ps
CPU time 41.67 seconds
Started Jul 11 04:49:05 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 208124 kb
Host smart-fc9beca2-4ba9-43a8-8634-7857ea7402d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438387142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1438387142
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2650761222
Short name T586
Test name
Test status
Simulation time 12590393583 ps
CPU time 295.04 seconds
Started Jul 11 04:49:14 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 199904 kb
Host smart-bc3243e1-16df-4801-92f1-84e2950a52c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650761222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2650761222
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3120227284
Short name T477
Test name
Test status
Simulation time 6707046664 ps
CPU time 30.23 seconds
Started Jul 11 04:49:06 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 198108 kb
Host smart-de396b0c-4cad-49d0-9fe8-b478686ab182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120227284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3120227284
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.319996840
Short name T1042
Test name
Test status
Simulation time 3168763318 ps
CPU time 0.9 seconds
Started Jul 11 04:49:08 PM PDT 24
Finished Jul 11 04:49:14 PM PDT 24
Peak memory 195820 kb
Host smart-a442bd14-fdaf-4ef8-b02b-e503f1d54706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319996840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.319996840
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3453419813
Short name T469
Test name
Test status
Simulation time 269418073 ps
CPU time 1.89 seconds
Started Jul 11 04:49:17 PM PDT 24
Finished Jul 11 04:49:24 PM PDT 24
Peak memory 198716 kb
Host smart-504a130d-ab86-45ff-9e53-d8b6d059af94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453419813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3453419813
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3714297871
Short name T740
Test name
Test status
Simulation time 71835562403 ps
CPU time 37.52 seconds
Started Jul 11 04:49:10 PM PDT 24
Finished Jul 11 04:49:53 PM PDT 24
Peak memory 216056 kb
Host smart-21d7c919-9f86-4c5a-8290-96fc732b6a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714297871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3714297871
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.207218485
Short name T111
Test name
Test status
Simulation time 110719382352 ps
CPU time 1348.01 seconds
Started Jul 11 04:49:11 PM PDT 24
Finished Jul 11 05:11:45 PM PDT 24
Peak memory 224540 kb
Host smart-788a4ad4-07d0-48cc-a086-20872928cbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207218485 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.207218485
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2707295878
Short name T534
Test name
Test status
Simulation time 585850001 ps
CPU time 1.57 seconds
Started Jul 11 04:49:10 PM PDT 24
Finished Jul 11 04:49:17 PM PDT 24
Peak memory 198392 kb
Host smart-113d1e53-011d-4800-ad7b-f4e1def4ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707295878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2707295878
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.964854558
Short name T954
Test name
Test status
Simulation time 100359385377 ps
CPU time 52.7 seconds
Started Jul 11 04:49:16 PM PDT 24
Finished Jul 11 04:50:15 PM PDT 24
Peak memory 199804 kb
Host smart-da710db0-0ea0-4c29-be80-314bfc32e3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964854558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.964854558
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1902670297
Short name T412
Test name
Test status
Simulation time 28844548 ps
CPU time 0.54 seconds
Started Jul 11 04:49:14 PM PDT 24
Finished Jul 11 04:49:21 PM PDT 24
Peak memory 194120 kb
Host smart-24cd6768-4739-489c-a8db-55fc42fd1752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902670297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1902670297
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.4114382414
Short name T826
Test name
Test status
Simulation time 16942001427 ps
CPU time 27.22 seconds
Started Jul 11 04:49:11 PM PDT 24
Finished Jul 11 04:49:44 PM PDT 24
Peak memory 199904 kb
Host smart-78eba628-2cea-486e-92c7-327432ccbdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114382414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4114382414
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.689438323
Short name T66
Test name
Test status
Simulation time 200549502066 ps
CPU time 76.79 seconds
Started Jul 11 04:49:11 PM PDT 24
Finished Jul 11 04:50:33 PM PDT 24
Peak memory 199800 kb
Host smart-c4e969a2-3972-42d3-8c15-39852cc3a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689438323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.689438323
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1393989942
Short name T245
Test name
Test status
Simulation time 62665054122 ps
CPU time 24.23 seconds
Started Jul 11 04:49:14 PM PDT 24
Finished Jul 11 04:49:44 PM PDT 24
Peak memory 199864 kb
Host smart-3d8876dd-4f15-4133-a45f-7032bce09cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393989942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1393989942
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3520147567
Short name T748
Test name
Test status
Simulation time 43950523337 ps
CPU time 47.84 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:50:08 PM PDT 24
Peak memory 199912 kb
Host smart-103b57da-5c2b-445f-953a-3c2617475453
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520147567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3520147567
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.967554041
Short name T6
Test name
Test status
Simulation time 303710416973 ps
CPU time 197.19 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:52:42 PM PDT 24
Peak memory 199808 kb
Host smart-21db1032-a3c3-418b-86bd-1317ab4c4caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967554041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.967554041
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.854982813
Short name T531
Test name
Test status
Simulation time 1081313823 ps
CPU time 2.87 seconds
Started Jul 11 04:49:12 PM PDT 24
Finished Jul 11 04:49:20 PM PDT 24
Peak memory 198504 kb
Host smart-387501a6-5272-4ead-a65b-602d3915f135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854982813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.854982813
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.980011445
Short name T1066
Test name
Test status
Simulation time 210976199733 ps
CPU time 36.09 seconds
Started Jul 11 04:49:10 PM PDT 24
Finished Jul 11 04:49:51 PM PDT 24
Peak memory 207956 kb
Host smart-c2fa9965-ef63-401d-9a56-be458934ce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980011445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.980011445
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.830559350
Short name T544
Test name
Test status
Simulation time 18399527161 ps
CPU time 537.54 seconds
Started Jul 11 04:49:09 PM PDT 24
Finished Jul 11 04:58:12 PM PDT 24
Peak memory 199712 kb
Host smart-2874a297-e620-4c5d-817f-267a72fdfbe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830559350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.830559350
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3973489888
Short name T342
Test name
Test status
Simulation time 3372843604 ps
CPU time 21.44 seconds
Started Jul 11 04:49:11 PM PDT 24
Finished Jul 11 04:49:38 PM PDT 24
Peak memory 197800 kb
Host smart-6dc71ab0-f49b-461c-baa9-eeeca9f835f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3973489888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3973489888
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3351035933
Short name T594
Test name
Test status
Simulation time 272734482596 ps
CPU time 33.06 seconds
Started Jul 11 04:49:11 PM PDT 24
Finished Jul 11 04:49:50 PM PDT 24
Peak memory 199920 kb
Host smart-d2eabcb3-5a64-4b0b-becd-73903f98c7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351035933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3351035933
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1305516720
Short name T426
Test name
Test status
Simulation time 3112716219 ps
CPU time 2.05 seconds
Started Jul 11 04:49:09 PM PDT 24
Finished Jul 11 04:49:17 PM PDT 24
Peak memory 195832 kb
Host smart-7ac37b9b-0c80-4bad-88d3-e9db3224bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305516720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1305516720
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.811478994
Short name T347
Test name
Test status
Simulation time 311733335 ps
CPU time 0.96 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:49:24 PM PDT 24
Peak memory 198944 kb
Host smart-22954998-87c7-4d17-abc4-e09fc1b6d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811478994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.811478994
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3684611436
Short name T834
Test name
Test status
Simulation time 77692369536 ps
CPU time 219.56 seconds
Started Jul 11 04:49:17 PM PDT 24
Finished Jul 11 04:53:02 PM PDT 24
Peak memory 199892 kb
Host smart-e985a16a-9ea8-44b6-921e-a42219406f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684611436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3684611436
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3433057786
Short name T988
Test name
Test status
Simulation time 8625009722 ps
CPU time 4.57 seconds
Started Jul 11 04:49:11 PM PDT 24
Finished Jul 11 04:49:21 PM PDT 24
Peak memory 199776 kb
Host smart-0a9efec1-e108-495e-98a4-d248573b7aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433057786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3433057786
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.4230203036
Short name T60
Test name
Test status
Simulation time 53029418660 ps
CPU time 81.89 seconds
Started Jul 11 04:49:10 PM PDT 24
Finished Jul 11 04:50:37 PM PDT 24
Peak memory 199876 kb
Host smart-e1460020-cc0e-42c6-854a-5bf08c08aaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230203036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.4230203036
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.595449533
Short name T812
Test name
Test status
Simulation time 16605947 ps
CPU time 0.56 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:49:22 PM PDT 24
Peak memory 195396 kb
Host smart-2354f2b7-3e04-4b7f-b7fe-cf161aea416d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595449533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.595449533
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.30750324
Short name T438
Test name
Test status
Simulation time 45832388013 ps
CPU time 17.39 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 199924 kb
Host smart-da230554-a125-4089-9b77-73d8744550f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30750324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.30750324
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1511874965
Short name T1158
Test name
Test status
Simulation time 132331879851 ps
CPU time 90.7 seconds
Started Jul 11 04:49:10 PM PDT 24
Finished Jul 11 04:50:45 PM PDT 24
Peak memory 199792 kb
Host smart-1c7e3b5f-67aa-4f65-830a-eb48cc46079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511874965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1511874965
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2073097389
Short name T453
Test name
Test status
Simulation time 36205979409 ps
CPU time 49.76 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:50:10 PM PDT 24
Peak memory 199772 kb
Host smart-80832605-ed53-4e15-83af-9c15c88b84b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073097389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2073097389
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2852834383
Short name T346
Test name
Test status
Simulation time 12285863615 ps
CPU time 7.5 seconds
Started Jul 11 04:49:20 PM PDT 24
Finished Jul 11 04:49:32 PM PDT 24
Peak memory 196488 kb
Host smart-9e305c34-777f-4772-a980-b6eeedc1e4ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852834383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2852834383
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2554370740
Short name T647
Test name
Test status
Simulation time 106339552907 ps
CPU time 173.62 seconds
Started Jul 11 04:49:18 PM PDT 24
Finished Jul 11 04:52:17 PM PDT 24
Peak memory 199912 kb
Host smart-d9778454-89b8-412d-bade-4a39150e12dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554370740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2554370740
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3808000584
Short name T609
Test name
Test status
Simulation time 5067386781 ps
CPU time 7.6 seconds
Started Jul 11 04:49:13 PM PDT 24
Finished Jul 11 04:49:27 PM PDT 24
Peak memory 196452 kb
Host smart-35e4ea2f-11b6-443e-ac40-5564b6bb2c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808000584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3808000584
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2229832097
Short name T940
Test name
Test status
Simulation time 308478822512 ps
CPU time 48.67 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:50:09 PM PDT 24
Peak memory 208236 kb
Host smart-696a3e39-e379-41e7-9d73-ce0dca79fd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229832097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2229832097
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3661618528
Short name T1051
Test name
Test status
Simulation time 18314489209 ps
CPU time 376.95 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:55:37 PM PDT 24
Peak memory 199892 kb
Host smart-8ce68ba7-c93c-477c-b2a6-45a11ac2dfb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661618528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3661618528
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2305807305
Short name T547
Test name
Test status
Simulation time 5499865950 ps
CPU time 49.2 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:50:10 PM PDT 24
Peak memory 198252 kb
Host smart-bdf5326a-d3f5-460f-840d-17a65448171a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305807305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2305807305
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2247286285
Short name T583
Test name
Test status
Simulation time 140810561175 ps
CPU time 205.53 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:52:46 PM PDT 24
Peak memory 199904 kb
Host smart-30b87944-0f84-485d-9e3d-abd26a36873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247286285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2247286285
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.4229363939
Short name T522
Test name
Test status
Simulation time 47007366590 ps
CPU time 67.72 seconds
Started Jul 11 04:49:17 PM PDT 24
Finished Jul 11 04:50:30 PM PDT 24
Peak memory 195568 kb
Host smart-6fe8e018-f686-488a-8ba3-ac6664a9c5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229363939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4229363939
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.47336942
Short name T903
Test name
Test status
Simulation time 548268937 ps
CPU time 2.07 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:49:23 PM PDT 24
Peak memory 198652 kb
Host smart-5a620f10-0f5f-48e8-905b-a10aa5560e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47336942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.47336942
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2074309049
Short name T112
Test name
Test status
Simulation time 17388000390 ps
CPU time 99.83 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:51:00 PM PDT 24
Peak memory 199860 kb
Host smart-3bf7ef7f-2b2f-404d-8835-9477b69302d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074309049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2074309049
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2475589383
Short name T857
Test name
Test status
Simulation time 611181826353 ps
CPU time 442.86 seconds
Started Jul 11 04:49:16 PM PDT 24
Finished Jul 11 04:56:45 PM PDT 24
Peak memory 216540 kb
Host smart-dda89727-bc11-44bf-bed8-aeb95d4c274c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475589383 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2475589383
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.43925697
Short name T1080
Test name
Test status
Simulation time 423473724 ps
CPU time 1.26 seconds
Started Jul 11 04:49:20 PM PDT 24
Finished Jul 11 04:49:26 PM PDT 24
Peak memory 198188 kb
Host smart-f20a50e2-05ff-4fac-af39-16db0bd17afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43925697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.43925697
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1903352826
Short name T499
Test name
Test status
Simulation time 42238917321 ps
CPU time 9.01 seconds
Started Jul 11 04:49:12 PM PDT 24
Finished Jul 11 04:49:26 PM PDT 24
Peak memory 199864 kb
Host smart-edc214b2-1ad5-44a6-bbce-71164890900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903352826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1903352826
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3532763711
Short name T995
Test name
Test status
Simulation time 15929646 ps
CPU time 0.56 seconds
Started Jul 11 04:49:24 PM PDT 24
Finished Jul 11 04:49:29 PM PDT 24
Peak memory 195240 kb
Host smart-63e7a083-f554-4f88-8c09-46705bbe9f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532763711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3532763711
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.145451545
Short name T359
Test name
Test status
Simulation time 18773180516 ps
CPU time 28.13 seconds
Started Jul 11 04:49:15 PM PDT 24
Finished Jul 11 04:49:48 PM PDT 24
Peak memory 199900 kb
Host smart-cf4d14af-eab1-469d-a816-e72617917246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145451545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.145451545
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3956931487
Short name T355
Test name
Test status
Simulation time 124018498401 ps
CPU time 19.94 seconds
Started Jul 11 04:49:17 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 199924 kb
Host smart-1e065f5d-7a93-47d5-9a23-771bb425ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956931487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3956931487
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1606435858
Short name T211
Test name
Test status
Simulation time 147543245405 ps
CPU time 95.66 seconds
Started Jul 11 04:49:14 PM PDT 24
Finished Jul 11 04:50:55 PM PDT 24
Peak memory 199772 kb
Host smart-47a56606-022e-4145-ab9a-bd3564842d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606435858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1606435858
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3250190552
Short name T1144
Test name
Test status
Simulation time 19013833329 ps
CPU time 34.55 seconds
Started Jul 11 04:49:24 PM PDT 24
Finished Jul 11 04:50:03 PM PDT 24
Peak memory 199904 kb
Host smart-81983688-b64d-4b67-8232-8fcbb20b6c49
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250190552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3250190552
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.4183749155
Short name T838
Test name
Test status
Simulation time 74991696764 ps
CPU time 67.96 seconds
Started Jul 11 04:49:20 PM PDT 24
Finished Jul 11 04:50:33 PM PDT 24
Peak memory 199748 kb
Host smart-643d8aa8-8610-45a5-a26b-27ae9fad03c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183749155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4183749155
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1336676853
Short name T687
Test name
Test status
Simulation time 390416067 ps
CPU time 1.24 seconds
Started Jul 11 04:49:13 PM PDT 24
Finished Jul 11 04:49:20 PM PDT 24
Peak memory 195756 kb
Host smart-525cd90f-9562-4ad6-a636-37f5ed7d2a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336676853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1336676853
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1001505005
Short name T900
Test name
Test status
Simulation time 148600798122 ps
CPU time 92.01 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:50:57 PM PDT 24
Peak memory 199564 kb
Host smart-a406bcb9-4a33-42d5-9203-f9a21dc6f883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001505005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1001505005
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1573271313
Short name T418
Test name
Test status
Simulation time 2026972195 ps
CPU time 99.49 seconds
Started Jul 11 04:49:20 PM PDT 24
Finished Jul 11 04:51:04 PM PDT 24
Peak memory 199812 kb
Host smart-3e5f6c43-0b6d-4378-954b-3fbf6e5cde08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573271313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1573271313
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1799796490
Short name T340
Test name
Test status
Simulation time 6747481349 ps
CPU time 59 seconds
Started Jul 11 04:49:14 PM PDT 24
Finished Jul 11 04:50:19 PM PDT 24
Peak memory 198504 kb
Host smart-4ce6a396-4fae-4736-b09e-cff9ce6248f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799796490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1799796490
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.354963005
Short name T4
Test name
Test status
Simulation time 47391100147 ps
CPU time 14.12 seconds
Started Jul 11 04:49:16 PM PDT 24
Finished Jul 11 04:49:36 PM PDT 24
Peak memory 199520 kb
Host smart-94cc0ae2-36b0-4c57-b3cf-276a99feb937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354963005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.354963005
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3402514033
Short name T390
Test name
Test status
Simulation time 619768336 ps
CPU time 1.5 seconds
Started Jul 11 04:49:14 PM PDT 24
Finished Jul 11 04:49:22 PM PDT 24
Peak memory 195536 kb
Host smart-1f7ccc4f-e8af-4144-8c38-61d18625e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402514033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3402514033
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1189068567
Short name T841
Test name
Test status
Simulation time 5889317401 ps
CPU time 7.58 seconds
Started Jul 11 04:49:18 PM PDT 24
Finished Jul 11 04:49:30 PM PDT 24
Peak memory 199576 kb
Host smart-ac207514-768d-4708-b70d-cc3c2ea9606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189068567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1189068567
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3832860900
Short name T799
Test name
Test status
Simulation time 26632808162 ps
CPU time 43.95 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:50:08 PM PDT 24
Peak memory 199720 kb
Host smart-46d4c51a-864c-46d6-8b06-a63c35564565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832860900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3832860900
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2403166192
Short name T316
Test name
Test status
Simulation time 38922227492 ps
CPU time 508.68 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 216280 kb
Host smart-eaab9ea9-0730-417b-9813-6f57b7d7c3ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403166192 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2403166192
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.517356642
Short name T1059
Test name
Test status
Simulation time 8769618147 ps
CPU time 8.5 seconds
Started Jul 11 04:49:14 PM PDT 24
Finished Jul 11 04:49:28 PM PDT 24
Peak memory 199816 kb
Host smart-209bd412-891c-4de0-bc4e-d740ce834cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517356642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.517356642
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1804981511
Short name T719
Test name
Test status
Simulation time 64701438273 ps
CPU time 53.62 seconds
Started Jul 11 04:49:24 PM PDT 24
Finished Jul 11 04:50:22 PM PDT 24
Peak memory 199840 kb
Host smart-33db395f-59ca-435d-9f46-7af01af883ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804981511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1804981511
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.360173800
Short name T512
Test name
Test status
Simulation time 40903479 ps
CPU time 0.56 seconds
Started Jul 11 04:49:21 PM PDT 24
Finished Jul 11 04:49:26 PM PDT 24
Peak memory 195208 kb
Host smart-ec3f8cd1-4b48-4cbc-b5f1-b6367b3ab6bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360173800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.360173800
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2668107524
Short name T657
Test name
Test status
Simulation time 245669552526 ps
CPU time 80.02 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:50:44 PM PDT 24
Peak memory 199852 kb
Host smart-378a6b36-9c08-4512-9bd3-841e081955e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668107524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2668107524
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.63812308
Short name T143
Test name
Test status
Simulation time 35739323476 ps
CPU time 34.36 seconds
Started Jul 11 04:49:20 PM PDT 24
Finished Jul 11 04:49:59 PM PDT 24
Peak memory 199836 kb
Host smart-2e7f950a-0aaa-4801-a947-8404d7fb41db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63812308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.63812308
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.567560712
Short name T185
Test name
Test status
Simulation time 97889448886 ps
CPU time 21.09 seconds
Started Jul 11 04:49:23 PM PDT 24
Finished Jul 11 04:49:49 PM PDT 24
Peak memory 199608 kb
Host smart-f629a2a0-5d9f-40a1-99df-be5cc42bc0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567560712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.567560712
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1519887200
Short name T420
Test name
Test status
Simulation time 8386950031 ps
CPU time 2.55 seconds
Started Jul 11 04:49:21 PM PDT 24
Finished Jul 11 04:49:28 PM PDT 24
Peak memory 199760 kb
Host smart-c99084d5-ef03-4524-8c15-c5fa477acf75
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519887200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1519887200
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1888820812
Short name T353
Test name
Test status
Simulation time 87863526979 ps
CPU time 246.35 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:53:45 PM PDT 24
Peak memory 199888 kb
Host smart-5357696e-492d-477d-975a-4760644ace47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888820812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1888820812
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2388731980
Short name T616
Test name
Test status
Simulation time 7448545633 ps
CPU time 4.61 seconds
Started Jul 11 04:49:18 PM PDT 24
Finished Jul 11 04:49:28 PM PDT 24
Peak memory 198524 kb
Host smart-f2ea6d0b-38b4-4186-9256-85bfa8a02265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388731980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2388731980
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1155478374
Short name T1149
Test name
Test status
Simulation time 89745753837 ps
CPU time 131.69 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:51:51 PM PDT 24
Peak memory 198744 kb
Host smart-c70785dd-ef71-47f7-a3c1-9b5f8dd3b0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155478374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1155478374
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2443375339
Short name T655
Test name
Test status
Simulation time 5277064226 ps
CPU time 315.15 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:54:40 PM PDT 24
Peak memory 199860 kb
Host smart-f91da796-e406-4c9c-a473-03a31bfcfffa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443375339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2443375339
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3069985229
Short name T539
Test name
Test status
Simulation time 4022823914 ps
CPU time 7.93 seconds
Started Jul 11 04:49:20 PM PDT 24
Finished Jul 11 04:49:33 PM PDT 24
Peak memory 198780 kb
Host smart-4417839e-3ab2-4611-a76a-0832b0e295b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069985229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3069985229
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2691156058
Short name T1094
Test name
Test status
Simulation time 122876821060 ps
CPU time 68.69 seconds
Started Jul 11 04:49:35 PM PDT 24
Finished Jul 11 04:50:47 PM PDT 24
Peak memory 199876 kb
Host smart-5ca03a9b-4f19-4de9-bee5-bb81c9af9982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691156058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2691156058
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.523662799
Short name T876
Test name
Test status
Simulation time 5161541877 ps
CPU time 7.6 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:49:47 PM PDT 24
Peak memory 196332 kb
Host smart-b61bf7fd-63aa-4ce8-9a4d-b2b2765f8d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523662799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.523662799
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1266872782
Short name T662
Test name
Test status
Simulation time 268784792 ps
CPU time 1.37 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 198372 kb
Host smart-acb6488d-e9d9-47ac-879f-caa72ee09802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266872782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1266872782
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1827608108
Short name T663
Test name
Test status
Simulation time 239903706774 ps
CPU time 952.85 seconds
Started Jul 11 04:49:25 PM PDT 24
Finished Jul 11 05:05:23 PM PDT 24
Peak memory 199828 kb
Host smart-25e74bcd-cc41-4423-a1e6-81ed69583123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827608108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1827608108
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1440429702
Short name T672
Test name
Test status
Simulation time 10816810665 ps
CPU time 130.19 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:51:34 PM PDT 24
Peak memory 215756 kb
Host smart-c82c4cf4-e1a6-48cc-967d-afe8c381a4c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440429702 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1440429702
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.688748586
Short name T562
Test name
Test status
Simulation time 3979803906 ps
CPU time 1.41 seconds
Started Jul 11 04:49:25 PM PDT 24
Finished Jul 11 04:49:31 PM PDT 24
Peak memory 199840 kb
Host smart-783e0f22-b543-4b59-bf19-fe80b7289d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688748586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.688748586
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1142230742
Short name T471
Test name
Test status
Simulation time 421826984073 ps
CPU time 82.63 seconds
Started Jul 11 04:49:20 PM PDT 24
Finished Jul 11 04:50:48 PM PDT 24
Peak memory 199800 kb
Host smart-c3eda074-3ad6-48e4-bd85-c9531488cdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142230742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1142230742
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.4080161486
Short name T923
Test name
Test status
Simulation time 16029649 ps
CPU time 0.61 seconds
Started Jul 11 04:49:23 PM PDT 24
Finished Jul 11 04:49:28 PM PDT 24
Peak memory 195236 kb
Host smart-dde6597e-69ef-44c2-a5aa-efb5361f03db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080161486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.4080161486
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2450821637
Short name T701
Test name
Test status
Simulation time 35344457661 ps
CPU time 49.2 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:50:29 PM PDT 24
Peak memory 199928 kb
Host smart-91e6fac6-2f3a-4f80-9249-d9a803fd44a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450821637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2450821637
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.973436911
Short name T474
Test name
Test status
Simulation time 20625481999 ps
CPU time 17.2 seconds
Started Jul 11 04:49:24 PM PDT 24
Finished Jul 11 04:49:45 PM PDT 24
Peak memory 199552 kb
Host smart-7dd984cc-06ab-404a-8e9f-fb2f8551c75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973436911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.973436911
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3485831752
Short name T814
Test name
Test status
Simulation time 197907324956 ps
CPU time 241.48 seconds
Started Jul 11 04:49:28 PM PDT 24
Finished Jul 11 04:53:34 PM PDT 24
Peak memory 199804 kb
Host smart-4ff65865-3189-4019-b748-277dd5f294f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485831752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3485831752
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.621089758
Short name T13
Test name
Test status
Simulation time 288278805931 ps
CPU time 443.51 seconds
Started Jul 11 04:49:28 PM PDT 24
Finished Jul 11 04:56:56 PM PDT 24
Peak memory 199848 kb
Host smart-5cda2fc7-aad3-4acd-a39b-0261d180160e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621089758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.621089758
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3027490391
Short name T404
Test name
Test status
Simulation time 47626885833 ps
CPU time 129.39 seconds
Started Jul 11 04:49:27 PM PDT 24
Finished Jul 11 04:51:41 PM PDT 24
Peak memory 199756 kb
Host smart-bf2982b2-5799-462e-a40e-88c8c2aec76a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3027490391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3027490391
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.206316085
Short name T507
Test name
Test status
Simulation time 12470729153 ps
CPU time 12.97 seconds
Started Jul 11 04:49:26 PM PDT 24
Finished Jul 11 04:49:43 PM PDT 24
Peak memory 199836 kb
Host smart-db33c784-d3e3-4ae7-a5de-bbb20c6d560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206316085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.206316085
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1331051482
Short name T273
Test name
Test status
Simulation time 14290002493 ps
CPU time 25.32 seconds
Started Jul 11 04:49:25 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 199900 kb
Host smart-872e15a2-9aed-4f39-98c4-e79a97d125cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331051482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1331051482
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1762736240
Short name T664
Test name
Test status
Simulation time 24906547649 ps
CPU time 205.47 seconds
Started Jul 11 04:49:23 PM PDT 24
Finished Jul 11 04:52:53 PM PDT 24
Peak memory 199820 kb
Host smart-0cb4de99-32e7-4b0b-a229-aae006eb5dfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762736240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1762736240
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.4091930679
Short name T434
Test name
Test status
Simulation time 1511146337 ps
CPU time 1.79 seconds
Started Jul 11 04:49:25 PM PDT 24
Finished Jul 11 04:49:31 PM PDT 24
Peak memory 197980 kb
Host smart-3fbb9253-ff0c-45c7-a541-bc99645d6eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091930679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.4091930679
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.392678435
Short name T809
Test name
Test status
Simulation time 118674275048 ps
CPU time 99.65 seconds
Started Jul 11 04:49:24 PM PDT 24
Finished Jul 11 04:51:08 PM PDT 24
Peak memory 199856 kb
Host smart-28dd157e-f792-4cb2-965c-b67076f8947d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392678435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.392678435
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2505784272
Short name T735
Test name
Test status
Simulation time 36317812793 ps
CPU time 8.6 seconds
Started Jul 11 04:49:28 PM PDT 24
Finished Jul 11 04:49:41 PM PDT 24
Peak memory 195636 kb
Host smart-08c1970f-e55a-4133-911e-7d4103d38aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505784272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2505784272
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1244102990
Short name T949
Test name
Test status
Simulation time 6047792229 ps
CPU time 11.61 seconds
Started Jul 11 04:49:19 PM PDT 24
Finished Jul 11 04:49:36 PM PDT 24
Peak memory 199792 kb
Host smart-efe38e2d-7c8f-4064-b210-3a5e395ba0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244102990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1244102990
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2082445962
Short name T902
Test name
Test status
Simulation time 102474366476 ps
CPU time 225.49 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:53:25 PM PDT 24
Peak memory 199636 kb
Host smart-787bc7b5-0fb1-419a-96e3-e0c243c6e019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082445962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2082445962
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3930099637
Short name T661
Test name
Test status
Simulation time 19713358220 ps
CPU time 97.48 seconds
Started Jul 11 04:49:22 PM PDT 24
Finished Jul 11 04:51:04 PM PDT 24
Peak memory 216000 kb
Host smart-a2c0f0b8-de96-4840-9b12-3a5f803224d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930099637 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3930099637
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.736909517
Short name T373
Test name
Test status
Simulation time 784607096 ps
CPU time 2.33 seconds
Started Jul 11 04:49:26 PM PDT 24
Finished Jul 11 04:49:33 PM PDT 24
Peak memory 198208 kb
Host smart-c1186c2e-eade-46f4-94ad-1236278b4fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736909517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.736909517
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1232865310
Short name T1023
Test name
Test status
Simulation time 34791145652 ps
CPU time 26.02 seconds
Started Jul 11 04:49:22 PM PDT 24
Finished Jul 11 04:49:53 PM PDT 24
Peak memory 199768 kb
Host smart-6baacd57-4e8c-455f-af27-fd1c762e001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232865310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1232865310
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.654677787
Short name T465
Test name
Test status
Simulation time 36770128 ps
CPU time 0.56 seconds
Started Jul 11 04:49:30 PM PDT 24
Finished Jul 11 04:49:35 PM PDT 24
Peak memory 194128 kb
Host smart-089b0153-934f-4411-9a96-3673dab73194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654677787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.654677787
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3081441366
Short name T156
Test name
Test status
Simulation time 143747768599 ps
CPU time 64.56 seconds
Started Jul 11 04:49:26 PM PDT 24
Finished Jul 11 04:50:35 PM PDT 24
Peak memory 199860 kb
Host smart-e0485f50-dbf3-4e5b-86eb-8929723e1d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081441366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3081441366
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.74016831
Short name T632
Test name
Test status
Simulation time 235783680443 ps
CPU time 84.8 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:51:04 PM PDT 24
Peak memory 199836 kb
Host smart-0851af46-f12b-4387-9ee4-3224efc41a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74016831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.74016831
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1676086911
Short name T199
Test name
Test status
Simulation time 317873474167 ps
CPU time 27.86 seconds
Started Jul 11 04:49:22 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 199792 kb
Host smart-38ec150f-a468-4600-b64e-e5b7117a9c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676086911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1676086911
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3565572190
Short name T311
Test name
Test status
Simulation time 29461081673 ps
CPU time 13.85 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:49:53 PM PDT 24
Peak memory 199812 kb
Host smart-878e6483-eedd-4d8f-8d0f-59778e5224af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565572190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3565572190
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1469244687
Short name T369
Test name
Test status
Simulation time 126736672588 ps
CPU time 676.49 seconds
Started Jul 11 04:49:31 PM PDT 24
Finished Jul 11 05:00:51 PM PDT 24
Peak memory 199772 kb
Host smart-f9d41247-aeec-4875-aa35-50ef0190f30c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469244687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1469244687
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1380212978
Short name T1104
Test name
Test status
Simulation time 6404616003 ps
CPU time 1.44 seconds
Started Jul 11 04:49:24 PM PDT 24
Finished Jul 11 04:49:30 PM PDT 24
Peak memory 196480 kb
Host smart-176e70aa-723d-4096-9dd7-0e2d027879c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380212978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1380212978
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.734664262
Short name T994
Test name
Test status
Simulation time 24063404401 ps
CPU time 43.4 seconds
Started Jul 11 04:49:26 PM PDT 24
Finished Jul 11 04:50:14 PM PDT 24
Peak memory 198208 kb
Host smart-ee996420-e372-487d-93fc-3fc9a75e8a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734664262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.734664262
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3711185455
Short name T1171
Test name
Test status
Simulation time 19674490907 ps
CPU time 223.19 seconds
Started Jul 11 04:49:25 PM PDT 24
Finished Jul 11 04:53:12 PM PDT 24
Peak memory 199888 kb
Host smart-4c683b4b-7ee0-4ab3-b10f-d0a27132e402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3711185455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3711185455
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.196920171
Short name T368
Test name
Test status
Simulation time 3824119624 ps
CPU time 5.15 seconds
Started Jul 11 04:49:24 PM PDT 24
Finished Jul 11 04:49:34 PM PDT 24
Peak memory 198960 kb
Host smart-37309e80-56a6-4d62-b509-d823f95345f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196920171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.196920171
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2426507327
Short name T127
Test name
Test status
Simulation time 59542727196 ps
CPU time 87.1 seconds
Started Jul 11 04:49:26 PM PDT 24
Finished Jul 11 04:50:57 PM PDT 24
Peak memory 199848 kb
Host smart-8163dea8-9bac-48d4-95a0-a728cb9990fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426507327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2426507327
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2338611803
Short name T1161
Test name
Test status
Simulation time 3191729815 ps
CPU time 2.58 seconds
Started Jul 11 04:49:35 PM PDT 24
Finished Jul 11 04:49:41 PM PDT 24
Peak memory 196412 kb
Host smart-ddca6127-d2d5-4832-855f-d20de9c4c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338611803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2338611803
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.144802970
Short name T41
Test name
Test status
Simulation time 873839391 ps
CPU time 2.11 seconds
Started Jul 11 04:49:25 PM PDT 24
Finished Jul 11 04:49:32 PM PDT 24
Peak memory 199532 kb
Host smart-7eb4a5f3-6174-48e9-b4f7-902c8059b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144802970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.144802970
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2490372221
Short name T806
Test name
Test status
Simulation time 144385581602 ps
CPU time 701.58 seconds
Started Jul 11 04:49:29 PM PDT 24
Finished Jul 11 05:01:15 PM PDT 24
Peak memory 199688 kb
Host smart-34b79bcd-a2bb-4c78-b951-9bdefa50287c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490372221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2490372221
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3830237697
Short name T1122
Test name
Test status
Simulation time 30371063051 ps
CPU time 254.21 seconds
Started Jul 11 04:49:30 PM PDT 24
Finished Jul 11 04:53:48 PM PDT 24
Peak memory 215376 kb
Host smart-e736fc95-0299-40ce-8ee1-53714f5e807e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830237697 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3830237697
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.449517644
Short name T792
Test name
Test status
Simulation time 1078779897 ps
CPU time 3.03 seconds
Started Jul 11 04:49:26 PM PDT 24
Finished Jul 11 04:49:34 PM PDT 24
Peak memory 198544 kb
Host smart-1ff21ea5-660b-46c7-85f2-e754684a7f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449517644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.449517644
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2705538887
Short name T529
Test name
Test status
Simulation time 47072258295 ps
CPU time 23.11 seconds
Started Jul 11 04:49:25 PM PDT 24
Finished Jul 11 04:49:52 PM PDT 24
Peak memory 199888 kb
Host smart-17dec9d4-96c2-4a95-935b-9d4628d00b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705538887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2705538887
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3440416994
Short name T433
Test name
Test status
Simulation time 42368919 ps
CPU time 0.58 seconds
Started Jul 11 04:49:33 PM PDT 24
Finished Jul 11 04:49:37 PM PDT 24
Peak memory 194664 kb
Host smart-3940e8f9-6dda-4f2c-8f06-b495b4b2cb9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440416994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3440416994
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1538470224
Short name T770
Test name
Test status
Simulation time 76150530200 ps
CPU time 40.9 seconds
Started Jul 11 04:49:33 PM PDT 24
Finished Jul 11 04:50:18 PM PDT 24
Peak memory 199836 kb
Host smart-45d13c70-0834-46e3-8679-957bfd951be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538470224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1538470224
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3528434166
Short name T394
Test name
Test status
Simulation time 61749452610 ps
CPU time 26 seconds
Started Jul 11 04:49:31 PM PDT 24
Finished Jul 11 04:50:01 PM PDT 24
Peak memory 199268 kb
Host smart-70632caa-00ca-4b5d-a146-e903490d9cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528434166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3528434166
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.396175475
Short name T228
Test name
Test status
Simulation time 16041984495 ps
CPU time 13.81 seconds
Started Jul 11 04:49:30 PM PDT 24
Finished Jul 11 04:49:48 PM PDT 24
Peak memory 199772 kb
Host smart-334486a8-c079-4617-bcbf-d90510c9217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396175475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.396175475
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2917627394
Short name T772
Test name
Test status
Simulation time 10559889141 ps
CPU time 9.9 seconds
Started Jul 11 04:49:32 PM PDT 24
Finished Jul 11 04:49:45 PM PDT 24
Peak memory 199784 kb
Host smart-19a18559-2376-4634-9a00-b88a7f55c365
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917627394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2917627394
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1815781641
Short name T890
Test name
Test status
Simulation time 198744115303 ps
CPU time 91.93 seconds
Started Jul 11 04:49:31 PM PDT 24
Finished Jul 11 04:51:07 PM PDT 24
Peak memory 199844 kb
Host smart-a54d21dc-f560-44d6-b2e9-d585034779e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815781641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1815781641
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1148111512
Short name T548
Test name
Test status
Simulation time 2983301020 ps
CPU time 2.78 seconds
Started Jul 11 04:49:32 PM PDT 24
Finished Jul 11 04:49:38 PM PDT 24
Peak memory 196076 kb
Host smart-e6e9ed6d-7d7e-4d91-8dd5-36bbab7d8a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148111512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1148111512
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1115341405
Short name T97
Test name
Test status
Simulation time 126788282857 ps
CPU time 85.94 seconds
Started Jul 11 04:49:30 PM PDT 24
Finished Jul 11 04:51:00 PM PDT 24
Peak memory 200200 kb
Host smart-85ad20c0-b5f5-4b46-b0a6-26e7c9f1e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115341405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1115341405
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1075973607
Short name T398
Test name
Test status
Simulation time 12579442097 ps
CPU time 184.63 seconds
Started Jul 11 04:49:30 PM PDT 24
Finished Jul 11 04:52:39 PM PDT 24
Peak memory 199904 kb
Host smart-0fc50885-95df-4910-84cc-63803ce37d76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075973607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1075973607
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1062499971
Short name T762
Test name
Test status
Simulation time 6823878511 ps
CPU time 66 seconds
Started Jul 11 04:49:31 PM PDT 24
Finished Jul 11 04:50:41 PM PDT 24
Peak memory 198184 kb
Host smart-09dd0e0f-2676-463f-b95a-c1b6fc3b6343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062499971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1062499971
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1203418485
Short name T854
Test name
Test status
Simulation time 31060044372 ps
CPU time 46.94 seconds
Started Jul 11 04:49:32 PM PDT 24
Finished Jul 11 04:50:23 PM PDT 24
Peak memory 199744 kb
Host smart-70844d50-119a-4a16-804f-28adc9316d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203418485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1203418485
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3847405755
Short name T388
Test name
Test status
Simulation time 2163847607 ps
CPU time 1.28 seconds
Started Jul 11 04:49:31 PM PDT 24
Finished Jul 11 04:49:36 PM PDT 24
Peak memory 195848 kb
Host smart-20591d02-020a-4686-b143-3d6c7f4e83f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847405755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3847405755
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.597989619
Short name T1046
Test name
Test status
Simulation time 311137899 ps
CPU time 1.05 seconds
Started Jul 11 04:49:31 PM PDT 24
Finished Jul 11 04:49:35 PM PDT 24
Peak memory 198528 kb
Host smart-f31ceee7-fb00-48b7-b065-f4a5b0fe8455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597989619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.597989619
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1958003168
Short name T190
Test name
Test status
Simulation time 444070320551 ps
CPU time 865.69 seconds
Started Jul 11 04:49:30 PM PDT 24
Finished Jul 11 05:03:59 PM PDT 24
Peak memory 209432 kb
Host smart-b1b2b661-8c5e-4ab7-b52b-e15b132f77a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958003168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1958003168
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2672292314
Short name T674
Test name
Test status
Simulation time 114374565569 ps
CPU time 379.66 seconds
Started Jul 11 04:49:31 PM PDT 24
Finished Jul 11 04:55:54 PM PDT 24
Peak memory 216424 kb
Host smart-fa4c06a1-8089-47fe-a0ef-e6837fa57e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672292314 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2672292314
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2507741826
Short name T389
Test name
Test status
Simulation time 7212419374 ps
CPU time 24.59 seconds
Started Jul 11 04:49:33 PM PDT 24
Finished Jul 11 04:50:01 PM PDT 24
Peak memory 199276 kb
Host smart-90059357-9b98-499a-8cd5-074edcbe4a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507741826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2507741826
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2915109644
Short name T755
Test name
Test status
Simulation time 126343462057 ps
CPU time 99.79 seconds
Started Jul 11 04:49:28 PM PDT 24
Finished Jul 11 04:51:12 PM PDT 24
Peak memory 199924 kb
Host smart-1e86ade4-f169-418e-9bd7-7cec3ebf2934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915109644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2915109644
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2781424530
Short name T1112
Test name
Test status
Simulation time 49940541 ps
CPU time 0.57 seconds
Started Jul 11 04:48:09 PM PDT 24
Finished Jul 11 04:48:14 PM PDT 24
Peak memory 195128 kb
Host smart-032037b3-d052-4b3f-aa49-a49134dea175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781424530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2781424530
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1226527464
Short name T794
Test name
Test status
Simulation time 99325034429 ps
CPU time 27.57 seconds
Started Jul 11 04:48:02 PM PDT 24
Finished Jul 11 04:48:35 PM PDT 24
Peak memory 199784 kb
Host smart-024899c0-2b08-4942-a04f-5b284129aa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226527464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1226527464
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4061625163
Short name T1185
Test name
Test status
Simulation time 98798266463 ps
CPU time 150.61 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:51:02 PM PDT 24
Peak memory 199820 kb
Host smart-b67a6bad-5898-47c7-b11e-6811c13800bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061625163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4061625163
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3600790789
Short name T896
Test name
Test status
Simulation time 105815550078 ps
CPU time 276.17 seconds
Started Jul 11 04:47:58 PM PDT 24
Finished Jul 11 04:52:40 PM PDT 24
Peak memory 199876 kb
Host smart-0572e46e-e537-48af-980c-ba430d65800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600790789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3600790789
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.841964642
Short name T878
Test name
Test status
Simulation time 1924091008 ps
CPU time 3.65 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:06 PM PDT 24
Peak memory 195436 kb
Host smart-559d0e13-7a54-499c-a0c1-b770d631890f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841964642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.841964642
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1634605068
Short name T953
Test name
Test status
Simulation time 87187235530 ps
CPU time 486.43 seconds
Started Jul 11 04:48:02 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 199704 kb
Host smart-6d40fdf0-02ad-4e84-99c4-8974806d3ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634605068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1634605068
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1298088629
Short name T551
Test name
Test status
Simulation time 7748200753 ps
CPU time 15.83 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:19 PM PDT 24
Peak memory 198976 kb
Host smart-238396d9-8cee-45ed-9607-70bde63db426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298088629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1298088629
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3921542671
Short name T281
Test name
Test status
Simulation time 10592544094 ps
CPU time 20.14 seconds
Started Jul 11 04:48:04 PM PDT 24
Finished Jul 11 04:48:28 PM PDT 24
Peak memory 200076 kb
Host smart-d2d05d42-1c79-4b3b-b2e7-c5dddfe5501b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921542671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3921542671
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.4103755122
Short name T408
Test name
Test status
Simulation time 10465123674 ps
CPU time 467.43 seconds
Started Jul 11 04:47:57 PM PDT 24
Finished Jul 11 04:55:50 PM PDT 24
Peak memory 199732 kb
Host smart-4b7cf88f-7cb5-4419-bbc6-d7b55548d060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103755122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4103755122
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1401181402
Short name T15
Test name
Test status
Simulation time 7368233751 ps
CPU time 64.98 seconds
Started Jul 11 04:47:57 PM PDT 24
Finished Jul 11 04:49:08 PM PDT 24
Peak memory 199052 kb
Host smart-715b4a70-714f-490f-af76-500b54ed0a84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401181402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1401181402
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2961800887
Short name T1178
Test name
Test status
Simulation time 124520799364 ps
CPU time 145.72 seconds
Started Jul 11 04:47:58 PM PDT 24
Finished Jul 11 04:50:30 PM PDT 24
Peak memory 199892 kb
Host smart-c4ade160-252f-4953-bdc4-e6a217c11de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961800887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2961800887
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1889091038
Short name T1075
Test name
Test status
Simulation time 35155961244 ps
CPU time 8.01 seconds
Started Jul 11 04:48:02 PM PDT 24
Finished Jul 11 04:48:15 PM PDT 24
Peak memory 195616 kb
Host smart-d39047f2-baa0-4da1-8a43-01e860ec22da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889091038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1889091038
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3703054489
Short name T93
Test name
Test status
Simulation time 43972192 ps
CPU time 0.77 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:04 PM PDT 24
Peak memory 218108 kb
Host smart-c46e2a70-ba33-497f-b31b-54beb168ceb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703054489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3703054489
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4208404229
Short name T383
Test name
Test status
Simulation time 287141845 ps
CPU time 1.63 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:48:12 PM PDT 24
Peak memory 198048 kb
Host smart-16e0b120-4bf5-42ab-8401-7e40e5aea2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208404229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4208404229
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.871739377
Short name T869
Test name
Test status
Simulation time 60171809750 ps
CPU time 145.27 seconds
Started Jul 11 04:47:57 PM PDT 24
Finished Jul 11 04:50:28 PM PDT 24
Peak memory 199856 kb
Host smart-55ef0994-7902-44be-9a72-4338d710a59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871739377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.871739377
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3856011001
Short name T503
Test name
Test status
Simulation time 140240367143 ps
CPU time 869.67 seconds
Started Jul 11 04:48:12 PM PDT 24
Finished Jul 11 05:02:46 PM PDT 24
Peak memory 224700 kb
Host smart-dc500a5a-744a-41f0-8dfd-a71b8c408e37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856011001 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3856011001
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3359263172
Short name T397
Test name
Test status
Simulation time 3023060248 ps
CPU time 3.21 seconds
Started Jul 11 04:48:12 PM PDT 24
Finished Jul 11 04:48:19 PM PDT 24
Peak memory 199432 kb
Host smart-ba32a5a3-8e9e-4bc3-88c1-4393c5953215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359263172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3359263172
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3255607761
Short name T972
Test name
Test status
Simulation time 88434914646 ps
CPU time 38.55 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:41 PM PDT 24
Peak memory 199924 kb
Host smart-37a67d1a-d28f-4285-89ec-8a7dfad0a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255607761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3255607761
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2697064420
Short name T508
Test name
Test status
Simulation time 34131896 ps
CPU time 0.54 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:49:40 PM PDT 24
Peak memory 194124 kb
Host smart-aa511a2f-453c-42b8-af65-5a38116fee30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697064420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2697064420
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3789319326
Short name T775
Test name
Test status
Simulation time 127566057362 ps
CPU time 307.24 seconds
Started Jul 11 04:49:41 PM PDT 24
Finished Jul 11 04:54:51 PM PDT 24
Peak memory 199856 kb
Host smart-aeef17ea-82b3-49b0-8647-ce0f4dbdb17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789319326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3789319326
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1149527288
Short name T331
Test name
Test status
Simulation time 72285492673 ps
CPU time 12.57 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:49:51 PM PDT 24
Peak memory 200164 kb
Host smart-8c271427-c0ce-4914-a0a5-1c042bc6495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149527288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1149527288
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3928224511
Short name T240
Test name
Test status
Simulation time 133199631693 ps
CPU time 194.66 seconds
Started Jul 11 04:49:35 PM PDT 24
Finished Jul 11 04:52:52 PM PDT 24
Peak memory 199808 kb
Host smart-372af5aa-e222-4d87-9473-d71a87283f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928224511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3928224511
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1818968339
Short name T883
Test name
Test status
Simulation time 197655882177 ps
CPU time 104.5 seconds
Started Jul 11 04:49:38 PM PDT 24
Finished Jul 11 04:51:27 PM PDT 24
Peak memory 199872 kb
Host smart-f2834950-a770-42f9-9ce7-75e0f40e1ce2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818968339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1818968339
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1117287674
Short name T261
Test name
Test status
Simulation time 101059271113 ps
CPU time 249.55 seconds
Started Jul 11 04:49:40 PM PDT 24
Finished Jul 11 04:53:53 PM PDT 24
Peak memory 199820 kb
Host smart-822678c3-8733-4dac-bd18-d0930693c6a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117287674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1117287674
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3651213910
Short name T987
Test name
Test status
Simulation time 12758885734 ps
CPU time 20.89 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:50:02 PM PDT 24
Peak memory 199836 kb
Host smart-848c80ee-10ad-4fdb-967a-f5e5a9c54a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651213910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3651213910
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.771542931
Short name T441
Test name
Test status
Simulation time 3877739926 ps
CPU time 6.2 seconds
Started Jul 11 04:49:38 PM PDT 24
Finished Jul 11 04:49:48 PM PDT 24
Peak memory 195468 kb
Host smart-62d89f50-5f08-4c7d-957d-5d984bba7367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771542931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.771542931
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.901467118
Short name T549
Test name
Test status
Simulation time 5907719051 ps
CPU time 81.64 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:51:03 PM PDT 24
Peak memory 199908 kb
Host smart-a089b936-8035-40ec-a3e9-30faf073532c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901467118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.901467118
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2338414309
Short name T887
Test name
Test status
Simulation time 1396357550 ps
CPU time 1.67 seconds
Started Jul 11 04:49:35 PM PDT 24
Finished Jul 11 04:49:39 PM PDT 24
Peak memory 198380 kb
Host smart-2d921e46-d697-4fee-a6ab-81074f8a665e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338414309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2338414309
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1675067753
Short name T302
Test name
Test status
Simulation time 43826549721 ps
CPU time 37.34 seconds
Started Jul 11 04:49:34 PM PDT 24
Finished Jul 11 04:50:14 PM PDT 24
Peak memory 199520 kb
Host smart-88294b0b-aa16-4ec2-9518-0b04c7e06868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675067753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1675067753
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1251892114
Short name T500
Test name
Test status
Simulation time 32874826547 ps
CPU time 25.13 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 195804 kb
Host smart-eedf6d42-9b67-4aae-9e0c-e63cfd4dd7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251892114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1251892114
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2045621469
Short name T450
Test name
Test status
Simulation time 690681098 ps
CPU time 1.43 seconds
Started Jul 11 04:49:31 PM PDT 24
Finished Jul 11 04:49:36 PM PDT 24
Peak memory 198696 kb
Host smart-f2d1bfcb-d8db-42e8-8aa0-994b11c7652d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045621469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2045621469
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2480459337
Short name T1117
Test name
Test status
Simulation time 230249325137 ps
CPU time 649.52 seconds
Started Jul 11 04:49:35 PM PDT 24
Finished Jul 11 05:00:27 PM PDT 24
Peak memory 216260 kb
Host smart-70b4b891-5824-4ef8-af57-d30730c8d375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480459337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2480459337
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1035373106
Short name T103
Test name
Test status
Simulation time 42503852643 ps
CPU time 175.78 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:52:36 PM PDT 24
Peak memory 199972 kb
Host smart-59bf98a8-f8c2-495b-b2db-e26d9a41d716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035373106 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1035373106
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1269564918
Short name T553
Test name
Test status
Simulation time 970077826 ps
CPU time 4.67 seconds
Started Jul 11 04:49:39 PM PDT 24
Finished Jul 11 04:49:47 PM PDT 24
Peak memory 198724 kb
Host smart-fb847d74-3219-4591-8b72-0570c0ed5b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269564918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1269564918
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.831863632
Short name T280
Test name
Test status
Simulation time 37725213904 ps
CPU time 29.49 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:50:11 PM PDT 24
Peak memory 199804 kb
Host smart-bb8e426b-8d42-48e8-bf88-b269cc300c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831863632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.831863632
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1413929325
Short name T1133
Test name
Test status
Simulation time 53521261 ps
CPU time 0.59 seconds
Started Jul 11 04:49:38 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 195196 kb
Host smart-9be4f68b-975e-4714-af69-8d4e694ab554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413929325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1413929325
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2480177097
Short name T283
Test name
Test status
Simulation time 142970840171 ps
CPU time 272.27 seconds
Started Jul 11 04:49:39 PM PDT 24
Finished Jul 11 04:54:15 PM PDT 24
Peak memory 199892 kb
Host smart-60b3680f-93be-41b7-8c3f-740e891a3f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480177097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2480177097
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1417803482
Short name T509
Test name
Test status
Simulation time 78070711949 ps
CPU time 34.74 seconds
Started Jul 11 04:49:39 PM PDT 24
Finished Jul 11 04:50:17 PM PDT 24
Peak memory 199836 kb
Host smart-55390a8a-4322-453c-b71c-6684cb45aa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417803482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1417803482
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.993883548
Short name T944
Test name
Test status
Simulation time 43534500592 ps
CPU time 71.93 seconds
Started Jul 11 04:49:39 PM PDT 24
Finished Jul 11 04:50:54 PM PDT 24
Peak memory 199836 kb
Host smart-3315caa0-47f5-4b41-bbc0-7a80d52a36cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993883548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.993883548
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3356417482
Short name T1084
Test name
Test status
Simulation time 224715347480 ps
CPU time 176.86 seconds
Started Jul 11 04:49:38 PM PDT 24
Finished Jul 11 04:52:39 PM PDT 24
Peak memory 197440 kb
Host smart-1efaa867-c459-467c-a4af-1284a3547f3f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356417482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3356417482
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2294990628
Short name T495
Test name
Test status
Simulation time 152450491274 ps
CPU time 1194.78 seconds
Started Jul 11 04:49:38 PM PDT 24
Finished Jul 11 05:09:36 PM PDT 24
Peak memory 199848 kb
Host smart-a0cf9249-07ef-4e3e-a6a2-dacac44c5fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294990628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2294990628
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3523942612
Short name T16
Test name
Test status
Simulation time 8759845167 ps
CPU time 5.67 seconds
Started Jul 11 04:49:39 PM PDT 24
Finished Jul 11 04:49:48 PM PDT 24
Peak memory 198856 kb
Host smart-acfef6ac-06f0-4be9-8d84-fc2706469e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523942612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3523942612
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3885142232
Short name T317
Test name
Test status
Simulation time 14760516228 ps
CPU time 11.09 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:49:50 PM PDT 24
Peak memory 197232 kb
Host smart-ad29ceda-7c8d-4348-b89c-fca6a537e0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885142232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3885142232
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2313615682
Short name T424
Test name
Test status
Simulation time 11736116750 ps
CPU time 175.65 seconds
Started Jul 11 04:49:35 PM PDT 24
Finished Jul 11 04:52:34 PM PDT 24
Peak memory 199840 kb
Host smart-910e5507-7b41-4473-ae36-d5e4feb96c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313615682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2313615682
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3657918010
Short name T818
Test name
Test status
Simulation time 7643875817 ps
CPU time 15.28 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 198748 kb
Host smart-ef4eebec-9852-442b-9f99-4a7882d28c2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657918010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3657918010
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2856316176
Short name T600
Test name
Test status
Simulation time 206271560120 ps
CPU time 57.48 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:50:38 PM PDT 24
Peak memory 199696 kb
Host smart-78d20deb-b739-4936-b36e-24a392723936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856316176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2856316176
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1314408782
Short name T753
Test name
Test status
Simulation time 1827055209 ps
CPU time 1.24 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:49:41 PM PDT 24
Peak memory 195260 kb
Host smart-809eae4a-29d2-4182-8ae1-95ea9ec29755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314408782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1314408782
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.427731227
Short name T437
Test name
Test status
Simulation time 506235980 ps
CPU time 1.21 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 198076 kb
Host smart-63436eb8-b643-48cd-9fe4-81dc7c62adc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427731227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.427731227
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3227106955
Short name T427
Test name
Test status
Simulation time 159145830796 ps
CPU time 1467.21 seconds
Started Jul 11 04:49:35 PM PDT 24
Finished Jul 11 05:14:06 PM PDT 24
Peak memory 199916 kb
Host smart-4379d260-d4b8-46e0-8ddb-14d9ec790b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227106955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3227106955
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2050206401
Short name T142
Test name
Test status
Simulation time 125074272874 ps
CPU time 363.45 seconds
Started Jul 11 04:49:39 PM PDT 24
Finished Jul 11 04:55:46 PM PDT 24
Peak memory 216444 kb
Host smart-f76b9a5d-7a88-4e40-be70-8d03a019e34a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050206401 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2050206401
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3217760109
Short name T625
Test name
Test status
Simulation time 7822808280 ps
CPU time 9.16 seconds
Started Jul 11 04:49:35 PM PDT 24
Finished Jul 11 04:49:47 PM PDT 24
Peak memory 199676 kb
Host smart-30c9445b-8917-466d-901f-9f945d09f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217760109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3217760109
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.952851891
Short name T330
Test name
Test status
Simulation time 15713716611 ps
CPU time 6.78 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:49:47 PM PDT 24
Peak memory 199532 kb
Host smart-ac7b21bb-62c2-4059-92a9-8b2359c96e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952851891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.952851891
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3148626225
Short name T593
Test name
Test status
Simulation time 12789740 ps
CPU time 0.54 seconds
Started Jul 11 05:12:21 PM PDT 24
Finished Jul 11 05:12:22 PM PDT 24
Peak memory 194212 kb
Host smart-d2b6d0ce-35c7-47ce-9c13-e553746c5883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148626225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3148626225
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.4131285114
Short name T626
Test name
Test status
Simulation time 96035449316 ps
CPU time 150.19 seconds
Started Jul 11 04:49:40 PM PDT 24
Finished Jul 11 04:52:14 PM PDT 24
Peak memory 200160 kb
Host smart-21baad2f-dc5f-4e4a-9bda-d7f3d1eec55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131285114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4131285114
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2573319263
Short name T1156
Test name
Test status
Simulation time 22443784979 ps
CPU time 36.59 seconds
Started Jul 11 04:49:41 PM PDT 24
Finished Jul 11 04:50:20 PM PDT 24
Peak memory 199804 kb
Host smart-591034eb-2186-495b-8511-8c2cd34973b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573319263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2573319263
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2548634976
Short name T1157
Test name
Test status
Simulation time 63857356826 ps
CPU time 54.02 seconds
Started Jul 11 04:49:43 PM PDT 24
Finished Jul 11 04:50:39 PM PDT 24
Peak memory 199864 kb
Host smart-1838d264-295e-494b-9fb1-30e576b01766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548634976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2548634976
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3760756968
Short name T1083
Test name
Test status
Simulation time 9349239267 ps
CPU time 3.4 seconds
Started Jul 11 04:49:42 PM PDT 24
Finished Jul 11 04:49:48 PM PDT 24
Peak memory 196296 kb
Host smart-c6c8c12c-aee1-4b9a-b86e-c61edc8b8c44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760756968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3760756968
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2729959759
Short name T742
Test name
Test status
Simulation time 64207943461 ps
CPU time 204.52 seconds
Started Jul 11 04:55:56 PM PDT 24
Finished Jul 11 04:59:25 PM PDT 24
Peak memory 199848 kb
Host smart-51a67510-9995-4502-8636-643e99709844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729959759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2729959759
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3865648471
Short name T680
Test name
Test status
Simulation time 228343675 ps
CPU time 1.07 seconds
Started Jul 11 05:12:13 PM PDT 24
Finished Jul 11 05:12:14 PM PDT 24
Peak memory 197456 kb
Host smart-e171b353-8a9d-4140-b4d1-34bb9ad0a53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865648471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3865648471
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1135365840
Short name T1027
Test name
Test status
Simulation time 171135235166 ps
CPU time 122.38 seconds
Started Jul 11 04:49:42 PM PDT 24
Finished Jul 11 04:51:47 PM PDT 24
Peak memory 200028 kb
Host smart-994b62ed-55d9-4aa9-9ff0-0044662a6ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135365840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1135365840
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3995317517
Short name T559
Test name
Test status
Simulation time 14370810455 ps
CPU time 767.11 seconds
Started Jul 11 04:56:51 PM PDT 24
Finished Jul 11 05:09:46 PM PDT 24
Peak memory 199864 kb
Host smart-3117c392-3518-462a-975c-036364f49cf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995317517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3995317517
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3438735931
Short name T759
Test name
Test status
Simulation time 4511419583 ps
CPU time 18.18 seconds
Started Jul 11 04:49:43 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 199076 kb
Host smart-4d86f967-a471-40dd-905e-e601895d0f2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438735931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3438735931
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2765091850
Short name T126
Test name
Test status
Simulation time 51106976883 ps
CPU time 82.32 seconds
Started Jul 11 05:31:15 PM PDT 24
Finished Jul 11 05:32:40 PM PDT 24
Peak memory 199712 kb
Host smart-80069802-f636-42ee-8214-6e94d3f3af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765091850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2765091850
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1180377225
Short name T343
Test name
Test status
Simulation time 35726759951 ps
CPU time 13.87 seconds
Started Jul 11 04:49:43 PM PDT 24
Finished Jul 11 04:49:59 PM PDT 24
Peak memory 195876 kb
Host smart-c5104ec6-1274-4bd7-9dfb-865796d998f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180377225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1180377225
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2916392301
Short name T419
Test name
Test status
Simulation time 955080729 ps
CPU time 2.35 seconds
Started Jul 11 04:49:37 PM PDT 24
Finished Jul 11 04:49:43 PM PDT 24
Peak memory 198340 kb
Host smart-c33dd1ff-c3a9-430f-9229-d96786d10c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916392301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2916392301
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2440480511
Short name T1010
Test name
Test status
Simulation time 270735073764 ps
CPU time 87.9 seconds
Started Jul 11 04:49:49 PM PDT 24
Finished Jul 11 04:51:20 PM PDT 24
Peak memory 199716 kb
Host smart-1d00aae0-17c6-49f9-aff0-fd24c6e4c441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440480511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2440480511
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2422517330
Short name T462
Test name
Test status
Simulation time 18063286394 ps
CPU time 217.42 seconds
Started Jul 11 05:14:09 PM PDT 24
Finished Jul 11 05:17:48 PM PDT 24
Peak memory 215528 kb
Host smart-1db4be4b-a23a-44be-b9f1-889a53b5a3ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422517330 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2422517330
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3000376046
Short name T1132
Test name
Test status
Simulation time 2927019287 ps
CPU time 1.52 seconds
Started Jul 11 04:49:44 PM PDT 24
Finished Jul 11 04:49:48 PM PDT 24
Peak memory 199132 kb
Host smart-81157ba6-4992-4869-99e0-5dada3691ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000376046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3000376046
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2569707281
Short name T1074
Test name
Test status
Simulation time 15685781188 ps
CPU time 13.08 seconds
Started Jul 11 04:49:36 PM PDT 24
Finished Jul 11 04:49:53 PM PDT 24
Peak memory 196888 kb
Host smart-a719509e-e26e-48bd-95e1-af074a3eb961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569707281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2569707281
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3552878099
Short name T820
Test name
Test status
Simulation time 34620255 ps
CPU time 0.57 seconds
Started Jul 11 04:49:43 PM PDT 24
Finished Jul 11 04:49:46 PM PDT 24
Peak memory 195156 kb
Host smart-c33bc6f7-7fbf-4100-846e-c288e17c3647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552878099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3552878099
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2124413469
Short name T597
Test name
Test status
Simulation time 103969261602 ps
CPU time 141.48 seconds
Started Jul 11 05:40:57 PM PDT 24
Finished Jul 11 05:43:20 PM PDT 24
Peak memory 199932 kb
Host smart-075cd466-6289-489d-8513-313f0228f617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124413469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2124413469
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.4129601667
Short name T146
Test name
Test status
Simulation time 88286007323 ps
CPU time 36.04 seconds
Started Jul 11 04:49:42 PM PDT 24
Finished Jul 11 04:50:21 PM PDT 24
Peak memory 199800 kb
Host smart-41bcd295-4739-4d91-837a-8ae713c35a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129601667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.4129601667
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1342937844
Short name T125
Test name
Test status
Simulation time 17197235144 ps
CPU time 18.12 seconds
Started Jul 11 04:49:38 PM PDT 24
Finished Jul 11 04:50:00 PM PDT 24
Peak memory 199788 kb
Host smart-a78ae04a-dc95-4f89-afcf-618cdd408cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342937844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1342937844
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3423545313
Short name T14
Test name
Test status
Simulation time 40404321821 ps
CPU time 67.26 seconds
Started Jul 11 05:23:58 PM PDT 24
Finished Jul 11 05:25:07 PM PDT 24
Peak memory 199036 kb
Host smart-631a78b4-1a48-47b4-b5e9-b2cb585f9453
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423545313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3423545313
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1152181092
Short name T922
Test name
Test status
Simulation time 56310672329 ps
CPU time 189.09 seconds
Started Jul 11 04:49:40 PM PDT 24
Finished Jul 11 04:52:52 PM PDT 24
Peak memory 199868 kb
Host smart-6057b81b-3e81-4e99-af5f-555ecd90c302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152181092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1152181092
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1741394311
Short name T514
Test name
Test status
Simulation time 8061257432 ps
CPU time 2.42 seconds
Started Jul 11 04:49:44 PM PDT 24
Finished Jul 11 04:49:48 PM PDT 24
Peak memory 198792 kb
Host smart-3d7f6f5a-e2c0-465a-83fb-469dac521a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741394311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1741394311
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1392231869
Short name T723
Test name
Test status
Simulation time 17340943854 ps
CPU time 27.44 seconds
Started Jul 11 04:49:42 PM PDT 24
Finished Jul 11 04:50:12 PM PDT 24
Peak memory 196456 kb
Host smart-bba85a97-3400-41c4-b969-0232d1d74c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392231869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1392231869
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.4202930789
Short name T964
Test name
Test status
Simulation time 4732967696 ps
CPU time 144.77 seconds
Started Jul 11 04:49:49 PM PDT 24
Finished Jul 11 04:52:17 PM PDT 24
Peak memory 199792 kb
Host smart-db0a555c-e2ac-48cf-84ab-d18e4346cf2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202930789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4202930789
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1173272722
Short name T766
Test name
Test status
Simulation time 7077436255 ps
CPU time 16.6 seconds
Started Jul 11 05:28:30 PM PDT 24
Finished Jul 11 05:28:48 PM PDT 24
Peak memory 199056 kb
Host smart-3c2cae58-e446-4557-aabc-3ce20fddc79d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1173272722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1173272722
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.207828233
Short name T159
Test name
Test status
Simulation time 72609468182 ps
CPU time 113.49 seconds
Started Jul 11 04:49:44 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 199596 kb
Host smart-4e8f8f09-56ed-4d22-b80f-a6677cf17f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207828233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.207828233
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2999239399
Short name T1082
Test name
Test status
Simulation time 47335377526 ps
CPU time 12.18 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:50:03 PM PDT 24
Peak memory 195916 kb
Host smart-d5f4861c-84a3-4b5f-8430-3528f56b795d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999239399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2999239399
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.259443800
Short name T1025
Test name
Test status
Simulation time 715073719 ps
CPU time 3.1 seconds
Started Jul 11 04:49:40 PM PDT 24
Finished Jul 11 04:49:47 PM PDT 24
Peak memory 198072 kb
Host smart-ac099748-73e6-4db3-ac62-76acfd89f482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259443800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.259443800
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2700260851
Short name T1007
Test name
Test status
Simulation time 21998410603 ps
CPU time 69.39 seconds
Started Jul 11 04:49:42 PM PDT 24
Finished Jul 11 04:50:54 PM PDT 24
Peak memory 199812 kb
Host smart-85cc5e96-ceae-4521-b766-ca108e80c84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700260851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2700260851
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.834745215
Short name T45
Test name
Test status
Simulation time 44022937895 ps
CPU time 390.71 seconds
Started Jul 11 04:49:40 PM PDT 24
Finished Jul 11 04:56:14 PM PDT 24
Peak memory 208204 kb
Host smart-ff32162e-ca5f-4d08-91ac-e0f30a6ec844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834745215 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.834745215
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.180922678
Short name T714
Test name
Test status
Simulation time 3650623102 ps
CPU time 1.52 seconds
Started Jul 11 04:49:42 PM PDT 24
Finished Jul 11 04:49:46 PM PDT 24
Peak memory 198980 kb
Host smart-d49b6c21-cde8-4394-9172-6c2f2d77a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180922678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.180922678
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1318789638
Short name T326
Test name
Test status
Simulation time 20266742067 ps
CPU time 35.97 seconds
Started Jul 11 05:27:47 PM PDT 24
Finished Jul 11 05:28:26 PM PDT 24
Peak memory 199880 kb
Host smart-aeb4d6e9-cc7f-4a1c-8a26-655dfb319764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318789638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1318789638
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.506409788
Short name T533
Test name
Test status
Simulation time 18132016 ps
CPU time 0.61 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:49:53 PM PDT 24
Peak memory 194812 kb
Host smart-71abb637-4e46-4dab-9e82-a780351bb415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506409788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.506409788
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3249209772
Short name T1055
Test name
Test status
Simulation time 76135543683 ps
CPU time 50.18 seconds
Started Jul 11 04:49:49 PM PDT 24
Finished Jul 11 04:50:42 PM PDT 24
Peak memory 199756 kb
Host smart-584ff222-f40a-4d7b-a6a4-6035a9072ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249209772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3249209772
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3135638309
Short name T301
Test name
Test status
Simulation time 142955758266 ps
CPU time 310.06 seconds
Started Jul 11 04:49:46 PM PDT 24
Finished Jul 11 04:54:58 PM PDT 24
Peak memory 199916 kb
Host smart-8f0e6ff8-de2c-4c4f-976c-9cab5a9cc4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135638309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3135638309
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3869036643
Short name T124
Test name
Test status
Simulation time 200582161022 ps
CPU time 296.57 seconds
Started Jul 11 04:49:46 PM PDT 24
Finished Jul 11 04:54:45 PM PDT 24
Peak memory 199812 kb
Host smart-6ff5b5e0-55d4-4fba-9046-1b90fae1794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869036643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3869036643
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1377777900
Short name T939
Test name
Test status
Simulation time 30342310750 ps
CPU time 46.81 seconds
Started Jul 11 04:49:51 PM PDT 24
Finished Jul 11 04:50:41 PM PDT 24
Peak memory 199840 kb
Host smart-05919eba-78b2-4719-bb09-eb51da86eeef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377777900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1377777900
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4014278660
Short name T658
Test name
Test status
Simulation time 99011634060 ps
CPU time 776.82 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 05:02:48 PM PDT 24
Peak memory 199732 kb
Host smart-ebbbe325-5af8-4d80-bd5a-9df76dc49706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014278660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4014278660
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2234828891
Short name T641
Test name
Test status
Simulation time 2215018940 ps
CPU time 4.36 seconds
Started Jul 11 04:49:47 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 198688 kb
Host smart-8c2705ee-b35a-4be7-a491-d0abdfd359bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234828891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2234828891
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.803179607
Short name T873
Test name
Test status
Simulation time 65272007229 ps
CPU time 163.97 seconds
Started Jul 11 04:49:46 PM PDT 24
Finished Jul 11 04:52:32 PM PDT 24
Peak memory 208052 kb
Host smart-73b6d644-6f1f-40f7-a8ce-d9e90f186be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803179607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.803179607
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1801703607
Short name T323
Test name
Test status
Simulation time 1068452956 ps
CPU time 25.89 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:50:17 PM PDT 24
Peak memory 199772 kb
Host smart-bcab075f-ed75-430d-a705-e8913fb7d05d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801703607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1801703607
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1819384269
Short name T681
Test name
Test status
Simulation time 4349917855 ps
CPU time 17.25 seconds
Started Jul 11 04:49:45 PM PDT 24
Finished Jul 11 04:50:05 PM PDT 24
Peak memory 199144 kb
Host smart-0ad18e7d-46e1-45d2-9a01-7889bb45789a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819384269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1819384269
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1874154170
Short name T163
Test name
Test status
Simulation time 56492327124 ps
CPU time 19.02 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:50:09 PM PDT 24
Peak memory 199920 kb
Host smart-1180a316-1082-49e7-878c-a4ce1f652329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874154170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1874154170
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3434109746
Short name T399
Test name
Test status
Simulation time 2844695800 ps
CPU time 2.59 seconds
Started Jul 11 04:49:47 PM PDT 24
Finished Jul 11 04:49:52 PM PDT 24
Peak memory 195888 kb
Host smart-73be37bc-9f99-4270-813a-c9cc48fd2956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434109746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3434109746
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2943733669
Short name T504
Test name
Test status
Simulation time 524428319 ps
CPU time 1.83 seconds
Started Jul 11 04:49:40 PM PDT 24
Finished Jul 11 04:49:45 PM PDT 24
Peak memory 198648 kb
Host smart-1daf5fbb-9cb1-4ce1-94fd-3f32c5289e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943733669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2943733669
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3276355689
Short name T932
Test name
Test status
Simulation time 80900487457 ps
CPU time 819.44 seconds
Started Jul 11 04:49:47 PM PDT 24
Finished Jul 11 05:03:29 PM PDT 24
Peak memory 200024 kb
Host smart-bbef3786-bed2-40f7-8208-608e5ed9291c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276355689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3276355689
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3508312549
Short name T919
Test name
Test status
Simulation time 166707238496 ps
CPU time 1095 seconds
Started Jul 11 04:49:49 PM PDT 24
Finished Jul 11 05:08:07 PM PDT 24
Peak memory 215840 kb
Host smart-143aea8b-0796-469c-bbaa-2c8c9fecb94a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508312549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3508312549
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.303743262
Short name T813
Test name
Test status
Simulation time 2326232414 ps
CPU time 2 seconds
Started Jul 11 04:49:47 PM PDT 24
Finished Jul 11 04:49:52 PM PDT 24
Peak memory 198796 kb
Host smart-18e5ab80-2529-4c35-b223-86bf3693ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303743262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.303743262
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2053223359
Short name T310
Test name
Test status
Simulation time 38587275514 ps
CPU time 14 seconds
Started Jul 11 04:49:43 PM PDT 24
Finished Jul 11 04:50:00 PM PDT 24
Peak memory 199272 kb
Host smart-d8433133-a584-42a4-b01a-52b7bdb868d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053223359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2053223359
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2249035266
Short name T963
Test name
Test status
Simulation time 17494940 ps
CPU time 0.6 seconds
Started Jul 11 04:49:50 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 194560 kb
Host smart-1cffd4a3-7162-49b4-9447-9f4299cb6e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249035266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2249035266
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.517882130
Short name T160
Test name
Test status
Simulation time 13273738319 ps
CPU time 5.82 seconds
Started Jul 11 04:49:50 PM PDT 24
Finished Jul 11 04:49:59 PM PDT 24
Peak memory 199900 kb
Host smart-0b9b6b9f-9d19-4ed2-9cd9-1e0b67a10dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517882130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.517882130
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3540240757
Short name T560
Test name
Test status
Simulation time 144377416093 ps
CPU time 49.23 seconds
Started Jul 11 04:49:46 PM PDT 24
Finished Jul 11 04:50:38 PM PDT 24
Peak memory 199768 kb
Host smart-28ae19f1-4d26-4429-8a06-600ee71d3e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540240757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3540240757
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1508389374
Short name T776
Test name
Test status
Simulation time 6538020969 ps
CPU time 5.47 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:49:57 PM PDT 24
Peak memory 199860 kb
Host smart-3e31c448-cbe1-4252-8a9c-abdcc9341ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508389374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1508389374
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2558820425
Short name T1183
Test name
Test status
Simulation time 29856024485 ps
CPU time 9.04 seconds
Started Jul 11 04:49:45 PM PDT 24
Finished Jul 11 04:49:57 PM PDT 24
Peak memory 199808 kb
Host smart-d507a70c-eba1-4107-bb64-2c0e7bddfb2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558820425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2558820425
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2413553524
Short name T255
Test name
Test status
Simulation time 56730993215 ps
CPU time 394.17 seconds
Started Jul 11 04:49:47 PM PDT 24
Finished Jul 11 04:56:24 PM PDT 24
Peak memory 199828 kb
Host smart-54e65a4e-4981-46e6-92b3-693ac31da1a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413553524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2413553524
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.463253271
Short name T457
Test name
Test status
Simulation time 2633422457 ps
CPU time 2.26 seconds
Started Jul 11 04:49:47 PM PDT 24
Finished Jul 11 04:49:52 PM PDT 24
Peak memory 199724 kb
Host smart-fd772fbc-ce16-46cd-b13d-413faf3b5fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463253271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.463253271
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3510589873
Short name T456
Test name
Test status
Simulation time 59384442595 ps
CPU time 27.14 seconds
Started Jul 11 04:49:47 PM PDT 24
Finished Jul 11 04:50:16 PM PDT 24
Peak memory 198792 kb
Host smart-96910742-7010-4f81-8f18-1c622bcf02c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510589873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3510589873
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2300609007
Short name T288
Test name
Test status
Simulation time 15383687966 ps
CPU time 149.86 seconds
Started Jul 11 04:49:46 PM PDT 24
Finished Jul 11 04:52:19 PM PDT 24
Peak memory 199896 kb
Host smart-072fa2a7-2fec-428c-8260-7373e954bb20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300609007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2300609007
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3372023767
Short name T1056
Test name
Test status
Simulation time 6512939420 ps
CPU time 16.19 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:50:08 PM PDT 24
Peak memory 197992 kb
Host smart-b06022c7-1b60-4e2a-adbb-34eb7bbe709f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372023767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3372023767
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3505565758
Short name T965
Test name
Test status
Simulation time 68740712985 ps
CPU time 103.38 seconds
Started Jul 11 04:49:51 PM PDT 24
Finished Jul 11 04:51:37 PM PDT 24
Peak memory 199784 kb
Host smart-d34e0e47-9104-47da-805a-507f8ae9f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505565758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3505565758
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1506786542
Short name T362
Test name
Test status
Simulation time 6329845520 ps
CPU time 10.38 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:50:02 PM PDT 24
Peak memory 196288 kb
Host smart-950a6e27-388e-46b1-9cf2-ea47dec4a442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506786542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1506786542
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1457569098
Short name T442
Test name
Test status
Simulation time 465101170 ps
CPU time 1.04 seconds
Started Jul 11 04:49:50 PM PDT 24
Finished Jul 11 04:49:54 PM PDT 24
Peak memory 198248 kb
Host smart-9d9c17aa-268b-43c6-a8ab-4b0218f3dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457569098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1457569098
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3266405773
Short name T1165
Test name
Test status
Simulation time 61540401294 ps
CPU time 284.9 seconds
Started Jul 11 04:49:44 PM PDT 24
Finished Jul 11 04:54:31 PM PDT 24
Peak memory 215956 kb
Host smart-fd1b7d93-4eee-4e40-9943-99fb84821eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266405773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3266405773
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2086261162
Short name T1018
Test name
Test status
Simulation time 8062640790 ps
CPU time 10.96 seconds
Started Jul 11 04:49:50 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 199612 kb
Host smart-10fe3c3f-63ac-4053-9d09-8bb25a920be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086261162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2086261162
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1799841103
Short name T998
Test name
Test status
Simulation time 11354088216 ps
CPU time 15.71 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:50:07 PM PDT 24
Peak memory 199788 kb
Host smart-71d1e351-805b-45da-91d0-df6e18ac01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799841103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1799841103
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3420820480
Short name T598
Test name
Test status
Simulation time 31088600 ps
CPU time 0.55 seconds
Started Jul 11 04:49:52 PM PDT 24
Finished Jul 11 04:49:55 PM PDT 24
Peak memory 195144 kb
Host smart-0bef6ea5-7150-4daa-b31d-cbc349369ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420820480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3420820480
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1587203143
Short name T859
Test name
Test status
Simulation time 56314650067 ps
CPU time 43.34 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:42 PM PDT 24
Peak memory 199872 kb
Host smart-ef6d604d-ec39-401d-9ac2-2f711ebf078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587203143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1587203143
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3040752069
Short name T545
Test name
Test status
Simulation time 284145402468 ps
CPU time 240.81 seconds
Started Jul 11 04:49:49 PM PDT 24
Finished Jul 11 04:53:53 PM PDT 24
Peak memory 199720 kb
Host smart-bcf43585-6703-4194-ac02-b5c2d48b404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040752069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3040752069
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.115614908
Short name T852
Test name
Test status
Simulation time 22165702879 ps
CPU time 6.82 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:06 PM PDT 24
Peak memory 199840 kb
Host smart-bc3b2514-8efb-4ff1-b247-73a564a571a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115614908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.115614908
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2824792794
Short name T519
Test name
Test status
Simulation time 236065924774 ps
CPU time 198.43 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:53:18 PM PDT 24
Peak memory 199816 kb
Host smart-9e6e48aa-3247-4898-adc5-67cb8e6496d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824792794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2824792794
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.164233752
Short name T337
Test name
Test status
Simulation time 9207682072 ps
CPU time 9.18 seconds
Started Jul 11 04:49:51 PM PDT 24
Finished Jul 11 04:50:03 PM PDT 24
Peak memory 198724 kb
Host smart-f9234929-4f8f-4160-91db-5ce0a751181a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164233752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.164233752
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3279402796
Short name T747
Test name
Test status
Simulation time 114207375123 ps
CPU time 51.49 seconds
Started Jul 11 04:49:52 PM PDT 24
Finished Jul 11 04:50:47 PM PDT 24
Peak memory 200104 kb
Host smart-54dfde83-2feb-4886-b8f0-80ca291403de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279402796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3279402796
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.917925468
Short name T847
Test name
Test status
Simulation time 11904175155 ps
CPU time 283.76 seconds
Started Jul 11 04:49:51 PM PDT 24
Finished Jul 11 04:54:38 PM PDT 24
Peak memory 199892 kb
Host smart-e4da6f83-6eb4-4ed8-acfc-4c1361736fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917925468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.917925468
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2393751492
Short name T613
Test name
Test status
Simulation time 1700050234 ps
CPU time 6.15 seconds
Started Jul 11 04:49:48 PM PDT 24
Finished Jul 11 04:49:57 PM PDT 24
Peak memory 197904 kb
Host smart-e8780843-e46a-491d-9add-6236d11340ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393751492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2393751492
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1289113124
Short name T307
Test name
Test status
Simulation time 51943812434 ps
CPU time 22.17 seconds
Started Jul 11 04:49:49 PM PDT 24
Finished Jul 11 04:50:14 PM PDT 24
Peak memory 199744 kb
Host smart-83073763-b0c0-47bc-87f6-13309af12123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289113124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1289113124
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1035477138
Short name T451
Test name
Test status
Simulation time 39447357824 ps
CPU time 14.79 seconds
Started Jul 11 04:49:53 PM PDT 24
Finished Jul 11 04:50:11 PM PDT 24
Peak memory 195724 kb
Host smart-6adc6e0a-ad1b-434f-a442-3285c7eda074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035477138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1035477138
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1019432204
Short name T423
Test name
Test status
Simulation time 509111004 ps
CPU time 2.38 seconds
Started Jul 11 04:49:52 PM PDT 24
Finished Jul 11 04:49:57 PM PDT 24
Peak memory 198556 kb
Host smart-9b1ec03c-63fb-4476-b5ea-9437dff59173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019432204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1019432204
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2469177463
Short name T1125
Test name
Test status
Simulation time 278194384544 ps
CPU time 644.37 seconds
Started Jul 11 04:49:53 PM PDT 24
Finished Jul 11 05:00:40 PM PDT 24
Peak memory 199764 kb
Host smart-94b5dee1-86e1-4067-b694-599298965a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469177463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2469177463
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1069578038
Short name T113
Test name
Test status
Simulation time 49695144534 ps
CPU time 628.34 seconds
Started Jul 11 04:49:50 PM PDT 24
Finished Jul 11 05:00:22 PM PDT 24
Peak memory 224672 kb
Host smart-f98fc192-1e5a-445f-8339-f9f05db1bacb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069578038 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1069578038
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1020581249
Short name T532
Test name
Test status
Simulation time 638969479 ps
CPU time 2.12 seconds
Started Jul 11 04:49:50 PM PDT 24
Finished Jul 11 04:49:56 PM PDT 24
Peak memory 199308 kb
Host smart-9fb3ba44-227f-4941-83b4-cbd4a9530d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020581249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1020581249
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3209533791
Short name T745
Test name
Test status
Simulation time 50725773766 ps
CPU time 20.66 seconds
Started Jul 11 04:49:54 PM PDT 24
Finished Jul 11 04:50:17 PM PDT 24
Peak memory 199780 kb
Host smart-7a199cc6-c75e-4141-a292-79da536f479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209533791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3209533791
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3795352025
Short name T599
Test name
Test status
Simulation time 15648752 ps
CPU time 0.6 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:49:59 PM PDT 24
Peak memory 195192 kb
Host smart-df072909-2399-4140-af5f-1484cd29a080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795352025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3795352025
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1975294194
Short name T158
Test name
Test status
Simulation time 99350854600 ps
CPU time 62.17 seconds
Started Jul 11 04:49:55 PM PDT 24
Finished Jul 11 04:51:00 PM PDT 24
Peak memory 199856 kb
Host smart-621c6546-5d79-4d78-8d18-bdf5c10da804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975294194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1975294194
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4076602341
Short name T119
Test name
Test status
Simulation time 72625954401 ps
CPU time 180.25 seconds
Started Jul 11 04:49:53 PM PDT 24
Finished Jul 11 04:52:56 PM PDT 24
Peak memory 199876 kb
Host smart-d6611344-8a88-45e5-bda1-d1ed46dcb3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076602341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4076602341
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2268875816
Short name T761
Test name
Test status
Simulation time 7155136660 ps
CPU time 12.47 seconds
Started Jul 11 04:49:58 PM PDT 24
Finished Jul 11 04:50:14 PM PDT 24
Peak memory 199828 kb
Host smart-368e2b19-fb40-44b4-ab4b-dc6d380fbcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268875816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2268875816
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2821939740
Short name T530
Test name
Test status
Simulation time 16692147936 ps
CPU time 6.99 seconds
Started Jul 11 04:50:01 PM PDT 24
Finished Jul 11 04:50:10 PM PDT 24
Peak memory 197592 kb
Host smart-85afc6d3-b5c8-4ec2-a1e1-400119080637
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821939740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2821939740
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3577906963
Short name T386
Test name
Test status
Simulation time 39723831267 ps
CPU time 236.13 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:53:55 PM PDT 24
Peak memory 199908 kb
Host smart-b1d31e3f-131a-4fa0-974d-20ea1f3dc8aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577906963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3577906963
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1792305195
Short name T1067
Test name
Test status
Simulation time 9174962086 ps
CPU time 5.31 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:05 PM PDT 24
Peak memory 199048 kb
Host smart-cd8bcc02-f338-4bd1-be24-af7ffa7c5028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792305195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1792305195
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2552542548
Short name T1103
Test name
Test status
Simulation time 86617720072 ps
CPU time 44.94 seconds
Started Jul 11 04:50:00 PM PDT 24
Finished Jul 11 04:50:47 PM PDT 24
Peak memory 208072 kb
Host smart-e27fd4e6-0413-4715-84d2-6cadd8ec6a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552542548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2552542548
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3783833612
Short name T765
Test name
Test status
Simulation time 19491370079 ps
CPU time 1118.19 seconds
Started Jul 11 04:49:55 PM PDT 24
Finished Jul 11 05:08:36 PM PDT 24
Peak memory 199856 kb
Host smart-2a0e95e3-6bd1-49aa-b9b2-955dcd41b94a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783833612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3783833612
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.945458258
Short name T697
Test name
Test status
Simulation time 2246367662 ps
CPU time 2.79 seconds
Started Jul 11 04:50:01 PM PDT 24
Finished Jul 11 04:50:06 PM PDT 24
Peak memory 198056 kb
Host smart-d62ea229-12e1-4423-a0e9-d7cb0a57a8c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945458258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.945458258
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3814841996
Short name T573
Test name
Test status
Simulation time 231929506540 ps
CPU time 192.96 seconds
Started Jul 11 04:49:54 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 199792 kb
Host smart-56554382-884e-456b-b99b-5b3a37fec7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814841996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3814841996
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3772295834
Short name T1024
Test name
Test status
Simulation time 5212024844 ps
CPU time 5.05 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:05 PM PDT 24
Peak memory 196340 kb
Host smart-74fc29b8-fccd-4057-9bf4-00b90826faa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772295834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3772295834
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2187864415
Short name T587
Test name
Test status
Simulation time 736910731 ps
CPU time 2.72 seconds
Started Jul 11 04:49:51 PM PDT 24
Finished Jul 11 04:49:57 PM PDT 24
Peak memory 198636 kb
Host smart-6227dba1-f906-4c25-9ca9-b06010579dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187864415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2187864415
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1901996138
Short name T737
Test name
Test status
Simulation time 36008243989 ps
CPU time 60.98 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:51:00 PM PDT 24
Peak memory 199932 kb
Host smart-70e2e4fe-17ec-44c0-a4b2-fb895810cbc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901996138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1901996138
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2813443775
Short name T24
Test name
Test status
Simulation time 42729980224 ps
CPU time 383.23 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:56:23 PM PDT 24
Peak memory 216536 kb
Host smart-ba6f3470-3fbc-4d88-8065-1cd5e7edffc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813443775 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2813443775
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1530697693
Short name T258
Test name
Test status
Simulation time 1452607358 ps
CPU time 2.4 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:02 PM PDT 24
Peak memory 198340 kb
Host smart-353c6b9b-2624-429b-a41e-1afc7d92565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530697693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1530697693
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2445849309
Short name T619
Test name
Test status
Simulation time 118223990257 ps
CPU time 235.8 seconds
Started Jul 11 04:49:54 PM PDT 24
Finished Jul 11 04:53:52 PM PDT 24
Peak memory 199920 kb
Host smart-c8e2f134-e690-4696-9cd7-f5eccfecc9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445849309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2445849309
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3492891476
Short name T694
Test name
Test status
Simulation time 106388232 ps
CPU time 0.61 seconds
Started Jul 11 04:49:58 PM PDT 24
Finished Jul 11 04:50:02 PM PDT 24
Peak memory 195224 kb
Host smart-de2eb29f-b875-401f-b430-a016cc712043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492891476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3492891476
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2834259435
Short name T731
Test name
Test status
Simulation time 67207575250 ps
CPU time 101.49 seconds
Started Jul 11 04:49:55 PM PDT 24
Finished Jul 11 04:51:40 PM PDT 24
Peak memory 199688 kb
Host smart-15551222-d2b3-4515-9ae4-3b1389b67f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834259435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2834259435
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.752729280
Short name T1076
Test name
Test status
Simulation time 20492641606 ps
CPU time 23.15 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:23 PM PDT 24
Peak memory 199940 kb
Host smart-09e63635-89a5-42a4-9eec-e60dca821b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752729280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.752729280
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2310886389
Short name T279
Test name
Test status
Simulation time 181615282550 ps
CPU time 427.15 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:57:07 PM PDT 24
Peak memory 199872 kb
Host smart-a7c6e57d-c80f-4df1-a1fc-cb7fe9e0bf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310886389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2310886389
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3562967852
Short name T276
Test name
Test status
Simulation time 54462636999 ps
CPU time 86.08 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 199896 kb
Host smart-fe3a2736-555b-46a2-b6ff-d22a25d2db8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562967852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3562967852
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1559521160
Short name T458
Test name
Test status
Simulation time 104815327288 ps
CPU time 233.41 seconds
Started Jul 11 04:50:00 PM PDT 24
Finished Jul 11 04:53:56 PM PDT 24
Peak memory 199800 kb
Host smart-3e9fdf21-db3b-4a6b-a053-b5efabe59af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559521160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1559521160
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3500374365
Short name T610
Test name
Test status
Simulation time 8540241400 ps
CPU time 5.91 seconds
Started Jul 11 04:49:59 PM PDT 24
Finished Jul 11 04:50:08 PM PDT 24
Peak memory 199780 kb
Host smart-3a07eac3-2cad-4535-aec3-888bc25307db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500374365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3500374365
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2170840279
Short name T272
Test name
Test status
Simulation time 159442631345 ps
CPU time 78.2 seconds
Started Jul 11 04:49:57 PM PDT 24
Finished Jul 11 04:51:18 PM PDT 24
Peak memory 208104 kb
Host smart-e7bfc622-155d-40d2-9994-3ebacd516b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170840279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2170840279
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.293477495
Short name T617
Test name
Test status
Simulation time 14338970768 ps
CPU time 186.66 seconds
Started Jul 11 04:49:58 PM PDT 24
Finished Jul 11 04:53:08 PM PDT 24
Peak memory 199848 kb
Host smart-7d2ed99d-5c77-4d3f-9dd9-7662cc948237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293477495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.293477495
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2733362603
Short name T491
Test name
Test status
Simulation time 7207027729 ps
CPU time 67.15 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:51:06 PM PDT 24
Peak memory 198032 kb
Host smart-09ae5560-abf0-4a4a-b5ba-79a626cdacf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733362603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2733362603
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.569263091
Short name T567
Test name
Test status
Simulation time 38711096576 ps
CPU time 57.35 seconds
Started Jul 11 04:49:58 PM PDT 24
Finished Jul 11 04:50:58 PM PDT 24
Peak memory 199800 kb
Host smart-63518424-783c-420a-8f90-28a82de37814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569263091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.569263091
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3687768731
Short name T363
Test name
Test status
Simulation time 40756441173 ps
CPU time 30.13 seconds
Started Jul 11 04:50:01 PM PDT 24
Finished Jul 11 04:50:34 PM PDT 24
Peak memory 195632 kb
Host smart-058bac19-77ed-45ea-a9b5-a9a30ae49daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687768731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3687768731
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.362184234
Short name T38
Test name
Test status
Simulation time 567049401 ps
CPU time 0.95 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:01 PM PDT 24
Peak memory 198656 kb
Host smart-bb8ae74b-13b6-4abf-8422-6d74e7e4996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362184234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.362184234
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3518623613
Short name T135
Test name
Test status
Simulation time 128664526482 ps
CPU time 230.2 seconds
Started Jul 11 04:49:59 PM PDT 24
Finished Jul 11 04:53:52 PM PDT 24
Peak memory 199820 kb
Host smart-c9a78e82-ab28-4006-a151-3ccd54a5346b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518623613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3518623613
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2822218005
Short name T218
Test name
Test status
Simulation time 83141086605 ps
CPU time 242.12 seconds
Started Jul 11 04:50:00 PM PDT 24
Finished Jul 11 04:54:05 PM PDT 24
Peak memory 216200 kb
Host smart-68a43b5f-e677-4f07-8d66-ab3eab0cbc16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822218005 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2822218005
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3477604740
Short name T561
Test name
Test status
Simulation time 7628549018 ps
CPU time 7.6 seconds
Started Jul 11 04:49:55 PM PDT 24
Finished Jul 11 04:50:06 PM PDT 24
Peak memory 199532 kb
Host smart-a9ebc9c4-0c2c-49d7-bf37-822d78cfbedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477604740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3477604740
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3603131722
Short name T1163
Test name
Test status
Simulation time 28741926307 ps
CPU time 46.21 seconds
Started Jul 11 04:49:56 PM PDT 24
Finished Jul 11 04:50:46 PM PDT 24
Peak memory 199920 kb
Host smart-09f5cbc3-305e-459f-bded-9a1a0e79f480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603131722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3603131722
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2436387743
Short name T449
Test name
Test status
Simulation time 44986448 ps
CPU time 0.56 seconds
Started Jul 11 04:50:09 PM PDT 24
Finished Jul 11 04:50:13 PM PDT 24
Peak memory 195496 kb
Host smart-1ce09475-faaf-46e2-bc3d-b1e33a49ff86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436387743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2436387743
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.781862976
Short name T825
Test name
Test status
Simulation time 23775240494 ps
CPU time 31.78 seconds
Started Jul 11 04:49:59 PM PDT 24
Finished Jul 11 04:50:34 PM PDT 24
Peak memory 199920 kb
Host smart-9c0cea9a-2a8d-42b7-b2ba-b759afad7f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781862976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.781862976
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.39400586
Short name T286
Test name
Test status
Simulation time 57745262937 ps
CPU time 83.94 seconds
Started Jul 11 04:50:02 PM PDT 24
Finished Jul 11 04:51:28 PM PDT 24
Peak memory 199756 kb
Host smart-2d371d9d-3363-41c0-b16a-8fa00b9a4f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39400586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.39400586
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2248074441
Short name T209
Test name
Test status
Simulation time 139412107950 ps
CPU time 228.85 seconds
Started Jul 11 04:49:58 PM PDT 24
Finished Jul 11 04:53:50 PM PDT 24
Peak memory 199852 kb
Host smart-158fadf0-765b-47d0-955c-9009f9bba118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248074441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2248074441
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1192794639
Short name T620
Test name
Test status
Simulation time 23225969160 ps
CPU time 4.39 seconds
Started Jul 11 04:50:01 PM PDT 24
Finished Jul 11 04:50:08 PM PDT 24
Peak memory 199840 kb
Host smart-ac8f6188-f62d-4dae-9294-65c1e6280a25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192794639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1192794639
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.237111691
Short name T1120
Test name
Test status
Simulation time 100848426116 ps
CPU time 90.42 seconds
Started Jul 11 04:50:03 PM PDT 24
Finished Jul 11 04:51:36 PM PDT 24
Peak memory 199800 kb
Host smart-dfb2ae2f-3806-421e-81f6-a304141e994a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237111691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.237111691
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1562718608
Short name T667
Test name
Test status
Simulation time 6947896995 ps
CPU time 10.67 seconds
Started Jul 11 04:50:00 PM PDT 24
Finished Jul 11 04:50:14 PM PDT 24
Peak memory 199820 kb
Host smart-0016d8f8-5fe4-4618-ad54-1f1764d9bfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562718608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1562718608
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.4045550215
Short name T64
Test name
Test status
Simulation time 85828866092 ps
CPU time 211.83 seconds
Started Jul 11 04:50:02 PM PDT 24
Finished Jul 11 04:53:36 PM PDT 24
Peak memory 199972 kb
Host smart-4581950a-ac06-48ba-8b6a-4ab5683d701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045550215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.4045550215
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2262201375
Short name T422
Test name
Test status
Simulation time 16256666704 ps
CPU time 442.25 seconds
Started Jul 11 04:50:00 PM PDT 24
Finished Jul 11 04:57:25 PM PDT 24
Peak memory 199764 kb
Host smart-8b0eec69-0e59-49f4-8c6c-4a3cd72be48c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262201375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2262201375
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1164586682
Short name T344
Test name
Test status
Simulation time 4537784500 ps
CPU time 2.07 seconds
Started Jul 11 04:50:04 PM PDT 24
Finished Jul 11 04:50:08 PM PDT 24
Peak memory 198532 kb
Host smart-fe87a51c-0a8c-43cb-bc88-4aee3aa901b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164586682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1164586682
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.927739679
Short name T643
Test name
Test status
Simulation time 179001822932 ps
CPU time 54.6 seconds
Started Jul 11 04:50:01 PM PDT 24
Finished Jul 11 04:50:58 PM PDT 24
Peak memory 199920 kb
Host smart-1690004b-5adc-495a-b5de-de039762d3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927739679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.927739679
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3353953005
Short name T467
Test name
Test status
Simulation time 1576975532 ps
CPU time 1.7 seconds
Started Jul 11 04:49:59 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 195416 kb
Host smart-8b62d89f-af45-4da0-b3ed-a6ad3d90655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353953005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3353953005
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1532791950
Short name T768
Test name
Test status
Simulation time 948438604 ps
CPU time 2.23 seconds
Started Jul 11 04:49:58 PM PDT 24
Finished Jul 11 04:50:04 PM PDT 24
Peak memory 199064 kb
Host smart-3c440049-fdfd-4b5e-969e-42b13ec03056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532791950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1532791950
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3227023848
Short name T235
Test name
Test status
Simulation time 43596949845 ps
CPU time 69.45 seconds
Started Jul 11 04:50:10 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 199836 kb
Host smart-f29f41ac-2267-44b0-8fee-446ec61631d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227023848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3227023848
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1323416358
Short name T94
Test name
Test status
Simulation time 6813776340 ps
CPU time 18.86 seconds
Started Jul 11 04:50:03 PM PDT 24
Finished Jul 11 04:50:24 PM PDT 24
Peak memory 199128 kb
Host smart-f952e833-fba0-4815-93f4-a748ec187a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323416358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1323416358
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3210593604
Short name T816
Test name
Test status
Simulation time 367891238009 ps
CPU time 50.3 seconds
Started Jul 11 04:49:59 PM PDT 24
Finished Jul 11 04:50:52 PM PDT 24
Peak memory 199928 kb
Host smart-0b39c673-8623-4614-9c70-738b842ab0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210593604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3210593604
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3898810268
Short name T815
Test name
Test status
Simulation time 16510172 ps
CPU time 0.53 seconds
Started Jul 11 04:48:18 PM PDT 24
Finished Jul 11 04:48:23 PM PDT 24
Peak memory 194208 kb
Host smart-ed868e97-e1f4-43bd-ba8e-3b5cafb40f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898810268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3898810268
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1309366966
Short name T781
Test name
Test status
Simulation time 116980446150 ps
CPU time 193.12 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 04:51:28 PM PDT 24
Peak memory 199784 kb
Host smart-48c8ac6f-54c5-4714-8140-164b9d6a2e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309366966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1309366966
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1958052920
Short name T1118
Test name
Test status
Simulation time 44825959809 ps
CPU time 70.07 seconds
Started Jul 11 04:48:04 PM PDT 24
Finished Jul 11 04:49:18 PM PDT 24
Peak memory 199700 kb
Host smart-ab25c83b-a5ab-4473-81d6-f9fbdfd78bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958052920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1958052920
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2932798439
Short name T986
Test name
Test status
Simulation time 167063041781 ps
CPU time 68.43 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 04:49:23 PM PDT 24
Peak memory 199816 kb
Host smart-6251c298-0e64-45b4-b52b-71ab4fa45c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932798439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2932798439
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1304986793
Short name T96
Test name
Test status
Simulation time 30669993417 ps
CPU time 14.59 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 04:48:29 PM PDT 24
Peak memory 198332 kb
Host smart-a4d6683f-3333-421b-b135-7d9ca9e056ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304986793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1304986793
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2336479301
Short name T538
Test name
Test status
Simulation time 78757934729 ps
CPU time 103.74 seconds
Started Jul 11 04:48:13 PM PDT 24
Finished Jul 11 04:50:01 PM PDT 24
Peak memory 199896 kb
Host smart-4a9dcb3d-80d3-4345-be33-11e99f0b85a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336479301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2336479301
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2556385378
Short name T840
Test name
Test status
Simulation time 9095712364 ps
CPU time 14.16 seconds
Started Jul 11 04:48:00 PM PDT 24
Finished Jul 11 04:48:20 PM PDT 24
Peak memory 198016 kb
Host smart-c946831f-680f-479a-982f-211285423f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556385378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2556385378
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.41260792
Short name T912
Test name
Test status
Simulation time 141769227796 ps
CPU time 60.18 seconds
Started Jul 11 04:48:05 PM PDT 24
Finished Jul 11 04:49:09 PM PDT 24
Peak memory 199572 kb
Host smart-63a904f9-c623-4893-a85f-c75246ea46c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41260792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.41260792
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2751465772
Short name T440
Test name
Test status
Simulation time 10901464076 ps
CPU time 134.39 seconds
Started Jul 11 04:48:09 PM PDT 24
Finished Jul 11 04:50:28 PM PDT 24
Peak memory 199780 kb
Host smart-8f1f98e1-a908-4d75-abd9-fb5aaf441a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751465772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2751465772
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3694101969
Short name T351
Test name
Test status
Simulation time 7049595665 ps
CPU time 17.25 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:19 PM PDT 24
Peak memory 197788 kb
Host smart-c44e74ee-ffb1-47db-bea1-0db9fbc3f6f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694101969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3694101969
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2050195686
Short name T858
Test name
Test status
Simulation time 63390685799 ps
CPU time 52.98 seconds
Started Jul 11 04:48:00 PM PDT 24
Finished Jul 11 04:48:59 PM PDT 24
Peak memory 199808 kb
Host smart-09bce3ba-93a2-417f-ab60-47718e8dde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050195686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2050195686
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.405976682
Short name T1175
Test name
Test status
Simulation time 73054703803 ps
CPU time 73.69 seconds
Started Jul 11 04:48:05 PM PDT 24
Finished Jul 11 04:49:22 PM PDT 24
Peak memory 195948 kb
Host smart-4866534a-1b34-4f9c-8af2-8659b9e79cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405976682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.405976682
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3441231948
Short name T493
Test name
Test status
Simulation time 299656931 ps
CPU time 1.64 seconds
Started Jul 11 04:47:56 PM PDT 24
Finished Jul 11 04:48:04 PM PDT 24
Peak memory 198612 kb
Host smart-bb3fcf55-9a30-4a15-b15f-729b9aa15555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441231948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3441231948
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.4143234232
Short name T552
Test name
Test status
Simulation time 429326128916 ps
CPU time 944.4 seconds
Started Jul 11 04:47:59 PM PDT 24
Finished Jul 11 05:03:49 PM PDT 24
Peak memory 199828 kb
Host smart-bb232845-f6e5-4e9a-880b-0b04cd4ec8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143234232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4143234232
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3283388520
Short name T645
Test name
Test status
Simulation time 40599456215 ps
CPU time 528.62 seconds
Started Jul 11 04:48:03 PM PDT 24
Finished Jul 11 04:56:57 PM PDT 24
Peak memory 216364 kb
Host smart-cc4985ea-5e2d-4b56-b76b-a70d3549b109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283388520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3283388520
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2492982425
Short name T891
Test name
Test status
Simulation time 6038303607 ps
CPU time 17.86 seconds
Started Jul 11 04:48:02 PM PDT 24
Finished Jul 11 04:48:25 PM PDT 24
Peak memory 199876 kb
Host smart-9cc54ec9-503d-4b47-ae34-6863d443e5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492982425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2492982425
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.656046585
Short name T691
Test name
Test status
Simulation time 14073671892 ps
CPU time 17.19 seconds
Started Jul 11 04:47:59 PM PDT 24
Finished Jul 11 04:48:23 PM PDT 24
Peak memory 199860 kb
Host smart-a47685a1-b0b3-419b-83c9-39fc75e98aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656046585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.656046585
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.616392962
Short name T1070
Test name
Test status
Simulation time 80461349572 ps
CPU time 73.38 seconds
Started Jul 11 04:50:05 PM PDT 24
Finished Jul 11 04:51:20 PM PDT 24
Peak memory 199776 kb
Host smart-062f281b-0a64-468e-a2fd-35e18dfede6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616392962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.616392962
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.130066112
Short name T1128
Test name
Test status
Simulation time 8463620826 ps
CPU time 141.7 seconds
Started Jul 11 04:50:03 PM PDT 24
Finished Jul 11 04:52:26 PM PDT 24
Peak memory 208244 kb
Host smart-dcca6ca3-73b8-4adc-8e1b-f0c50c1eb913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130066112 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.130066112
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2257853445
Short name T1114
Test name
Test status
Simulation time 22575776929 ps
CPU time 10.37 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 04:50:21 PM PDT 24
Peak memory 199888 kb
Host smart-de77c981-a1ef-49af-ac34-d373c73093c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257853445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2257853445
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.566260368
Short name T164
Test name
Test status
Simulation time 187691040928 ps
CPU time 620.98 seconds
Started Jul 11 04:50:09 PM PDT 24
Finished Jul 11 05:00:34 PM PDT 24
Peak memory 216344 kb
Host smart-54c87e58-9600-4f9c-ba1c-e910fc8ec4a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566260368 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.566260368
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3986641046
Short name T938
Test name
Test status
Simulation time 130604672635 ps
CPU time 24.35 seconds
Started Jul 11 04:50:06 PM PDT 24
Finished Jul 11 04:50:32 PM PDT 24
Peak memory 199760 kb
Host smart-10e0bce1-ca81-4fc5-9d72-93800984d194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986641046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3986641046
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.58633276
Short name T789
Test name
Test status
Simulation time 118213403190 ps
CPU time 536.39 seconds
Started Jul 11 04:50:09 PM PDT 24
Finished Jul 11 04:59:09 PM PDT 24
Peak memory 224696 kb
Host smart-4bceae9f-abf9-4203-a434-0b6ad7bb3aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58633276 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.58633276
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3163597828
Short name T1110
Test name
Test status
Simulation time 86081038284 ps
CPU time 125.28 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 04:52:16 PM PDT 24
Peak memory 199852 kb
Host smart-c4fcfbd7-164f-4c38-826b-9d8dce9d4b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163597828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3163597828
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1694637699
Short name T48
Test name
Test status
Simulation time 131482616454 ps
CPU time 1203.78 seconds
Started Jul 11 04:51:03 PM PDT 24
Finished Jul 11 05:11:10 PM PDT 24
Peak memory 224944 kb
Host smart-587ba3bc-1a09-4b97-9a36-8b183b05130b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694637699 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1694637699
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2423216460
Short name T639
Test name
Test status
Simulation time 125596910924 ps
CPU time 61.18 seconds
Started Jul 11 04:50:05 PM PDT 24
Finished Jul 11 04:51:08 PM PDT 24
Peak memory 199800 kb
Host smart-0b64eea3-b850-4abb-88a8-fbdfd5e6ba7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423216460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2423216460
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1025725759
Short name T299
Test name
Test status
Simulation time 109042076834 ps
CPU time 330.99 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 04:55:42 PM PDT 24
Peak memory 216528 kb
Host smart-86ed551d-89cb-4901-92b7-a73246ec4a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025725759 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1025725759
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2073499319
Short name T155
Test name
Test status
Simulation time 8268454170 ps
CPU time 13.54 seconds
Started Jul 11 04:50:12 PM PDT 24
Finished Jul 11 04:50:30 PM PDT 24
Peak memory 199668 kb
Host smart-6caebe09-bec8-44e3-95e9-f85fb70b5041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073499319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2073499319
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.4155065289
Short name T147
Test name
Test status
Simulation time 43637588723 ps
CPU time 305.56 seconds
Started Jul 11 04:50:07 PM PDT 24
Finished Jul 11 04:55:15 PM PDT 24
Peak memory 214976 kb
Host smart-e6ef8f33-6f52-4add-84fe-88766271162d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155065289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4155065289
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2494207071
Short name T446
Test name
Test status
Simulation time 133961927564 ps
CPU time 97.09 seconds
Started Jul 11 04:50:04 PM PDT 24
Finished Jul 11 04:51:43 PM PDT 24
Peak memory 199760 kb
Host smart-ac50a61f-272f-4e12-889b-fc8875446da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494207071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2494207071
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.848212923
Short name T795
Test name
Test status
Simulation time 89412469206 ps
CPU time 921.4 seconds
Started Jul 11 04:50:04 PM PDT 24
Finished Jul 11 05:05:28 PM PDT 24
Peak memory 224316 kb
Host smart-6f916a1d-2106-4008-acf1-45c9aeb687bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848212923 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.848212923
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1597545021
Short name T1102
Test name
Test status
Simulation time 58284225696 ps
CPU time 22.6 seconds
Started Jul 11 04:50:04 PM PDT 24
Finished Jul 11 04:50:28 PM PDT 24
Peak memory 199780 kb
Host smart-c5fb6f13-7bc0-437d-8471-994967d45ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597545021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1597545021
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.150263392
Short name T778
Test name
Test status
Simulation time 116182918348 ps
CPU time 825.91 seconds
Started Jul 11 04:50:06 PM PDT 24
Finished Jul 11 05:03:53 PM PDT 24
Peak memory 216352 kb
Host smart-71881072-7513-40d4-9ea0-21c1e738db26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150263392 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.150263392
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3330974183
Short name T178
Test name
Test status
Simulation time 52757685375 ps
CPU time 65.07 seconds
Started Jul 11 04:50:12 PM PDT 24
Finished Jul 11 04:51:21 PM PDT 24
Peak memory 199892 kb
Host smart-a0eb3ff2-352c-4c56-b01e-70623a5112e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330974183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3330974183
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2440484128
Short name T46
Test name
Test status
Simulation time 85377204728 ps
CPU time 703.76 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 05:01:55 PM PDT 24
Peak memory 216360 kb
Host smart-9c862edd-783d-4f65-8022-57287d3d2d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440484128 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2440484128
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3262880843
Short name T1008
Test name
Test status
Simulation time 25566921 ps
CPU time 0.57 seconds
Started Jul 11 04:48:11 PM PDT 24
Finished Jul 11 04:48:16 PM PDT 24
Peak memory 195432 kb
Host smart-e1c83fd9-7d69-4652-9f0b-7c2d2f7dcb07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262880843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3262880843
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2935089924
Short name T935
Test name
Test status
Simulation time 100813152897 ps
CPU time 42.15 seconds
Started Jul 11 04:48:12 PM PDT 24
Finished Jul 11 04:48:58 PM PDT 24
Peak memory 199920 kb
Host smart-0abfc45f-a7c3-4310-ae3a-89b0cc74f49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935089924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2935089924
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.4230388185
Short name T660
Test name
Test status
Simulation time 75135884678 ps
CPU time 250.45 seconds
Started Jul 11 04:48:22 PM PDT 24
Finished Jul 11 04:52:39 PM PDT 24
Peak memory 199784 kb
Host smart-ba69b08e-bca2-49c8-a072-b31dc8e72631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230388185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4230388185
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.810645290
Short name T201
Test name
Test status
Simulation time 342834753794 ps
CPU time 43.5 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:48:53 PM PDT 24
Peak memory 199832 kb
Host smart-863c0d74-9953-4d8b-b748-4c2a6d1e6fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810645290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.810645290
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2183009504
Short name T817
Test name
Test status
Simulation time 10188067707 ps
CPU time 6.13 seconds
Started Jul 11 04:48:12 PM PDT 24
Finished Jul 11 04:48:23 PM PDT 24
Peak memory 199732 kb
Host smart-823d91db-362f-4a13-9e9c-310677c6339a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183009504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2183009504
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1937627018
Short name T925
Test name
Test status
Simulation time 179015725711 ps
CPU time 144.79 seconds
Started Jul 11 04:48:00 PM PDT 24
Finished Jul 11 04:50:31 PM PDT 24
Peak memory 200096 kb
Host smart-c3c4bf60-0f86-496e-8b9c-a2c2f27436ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937627018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1937627018
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.4115479821
Short name T506
Test name
Test status
Simulation time 11464149073 ps
CPU time 9.88 seconds
Started Jul 11 04:48:01 PM PDT 24
Finished Jul 11 04:48:16 PM PDT 24
Peak memory 198932 kb
Host smart-3256cd60-a48d-40ff-9dcf-51f32da1ee97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115479821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.4115479821
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2719729105
Short name T511
Test name
Test status
Simulation time 25705003196 ps
CPU time 47.21 seconds
Started Jul 11 04:47:59 PM PDT 24
Finished Jul 11 04:48:52 PM PDT 24
Peak memory 198664 kb
Host smart-d3b21d53-1b2c-474b-a09e-a97f8f8f8d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719729105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2719729105
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1093507294
Short name T483
Test name
Test status
Simulation time 3012363849 ps
CPU time 37.87 seconds
Started Jul 11 04:47:58 PM PDT 24
Finished Jul 11 04:48:42 PM PDT 24
Peak memory 199900 kb
Host smart-3acd349f-6b7f-491f-b7c2-10446c9837e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093507294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1093507294
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.393804450
Short name T693
Test name
Test status
Simulation time 6355347043 ps
CPU time 55.13 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 04:49:10 PM PDT 24
Peak memory 198972 kb
Host smart-3a36eab2-2c42-4add-88ec-ab04ef715be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393804450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.393804450
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3545153068
Short name T133
Test name
Test status
Simulation time 146083639374 ps
CPU time 69.59 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:49:33 PM PDT 24
Peak memory 199648 kb
Host smart-5db51019-ea3e-4ae4-a664-b38240f87db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545153068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3545153068
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3599810602
Short name T1177
Test name
Test status
Simulation time 4613751857 ps
CPU time 1.14 seconds
Started Jul 11 04:48:11 PM PDT 24
Finished Jul 11 04:48:16 PM PDT 24
Peak memory 196068 kb
Host smart-f6e67cbe-75bd-470f-8efa-bfa9cdf652a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599810602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3599810602
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.746309976
Short name T376
Test name
Test status
Simulation time 671180744 ps
CPU time 1.81 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:48:23 PM PDT 24
Peak memory 198836 kb
Host smart-251cba86-7c30-402e-a216-06c0d30e75cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746309976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.746309976
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3311381956
Short name T464
Test name
Test status
Simulation time 235413473339 ps
CPU time 716.83 seconds
Started Jul 11 04:48:03 PM PDT 24
Finished Jul 11 05:00:05 PM PDT 24
Peak memory 199812 kb
Host smart-7c33414b-c816-497c-81bd-3233cf43f0e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311381956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3311381956
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.843670740
Short name T1062
Test name
Test status
Simulation time 96994241540 ps
CPU time 933.04 seconds
Started Jul 11 04:48:14 PM PDT 24
Finished Jul 11 05:03:51 PM PDT 24
Peak memory 216600 kb
Host smart-f7f3955a-75f1-4abe-9d59-c5b54500576f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843670740 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.843670740
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2155207466
Short name T541
Test name
Test status
Simulation time 405174169 ps
CPU time 1.54 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:48:36 PM PDT 24
Peak memory 198216 kb
Host smart-8880ff8f-b283-45dc-b46e-ff88cf9b1f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155207466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2155207466
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1351609361
Short name T484
Test name
Test status
Simulation time 5479883411 ps
CPU time 8.43 seconds
Started Jul 11 04:48:01 PM PDT 24
Finished Jul 11 04:48:15 PM PDT 24
Peak memory 199840 kb
Host smart-e157e00a-1d27-4771-8049-b8415159e843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351609361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1351609361
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2927428807
Short name T1053
Test name
Test status
Simulation time 14534532176 ps
CPU time 14.4 seconds
Started Jul 11 04:50:09 PM PDT 24
Finished Jul 11 04:50:26 PM PDT 24
Peak memory 199816 kb
Host smart-ca46d308-c55a-458f-9ea9-56a8fa9da57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927428807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2927428807
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2154793825
Short name T1032
Test name
Test status
Simulation time 14134762590 ps
CPU time 164.29 seconds
Started Jul 11 04:50:10 PM PDT 24
Finished Jul 11 04:52:59 PM PDT 24
Peak memory 210100 kb
Host smart-56c2e33d-2c06-40e2-afcd-b7db7f888634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154793825 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2154793825
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3157152690
Short name T180
Test name
Test status
Simulation time 33270208837 ps
CPU time 12.3 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 04:50:23 PM PDT 24
Peak memory 199640 kb
Host smart-7355de0f-ad15-4a50-a86d-970720ba97ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157152690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3157152690
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2267215334
Short name T855
Test name
Test status
Simulation time 89792563698 ps
CPU time 728.25 seconds
Started Jul 11 04:50:10 PM PDT 24
Finished Jul 11 05:02:23 PM PDT 24
Peak memory 224796 kb
Host smart-907c2e10-c43d-4d72-9db8-38c192cef4ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267215334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2267215334
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3453251844
Short name T173
Test name
Test status
Simulation time 187662778793 ps
CPU time 320.47 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 04:55:30 PM PDT 24
Peak memory 209264 kb
Host smart-a9ae5a6e-c22b-46cd-9c11-135da9c97fd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453251844 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3453251844
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1283851572
Short name T207
Test name
Test status
Simulation time 13900527246 ps
CPU time 19.37 seconds
Started Jul 11 04:50:10 PM PDT 24
Finished Jul 11 04:50:34 PM PDT 24
Peak memory 199796 kb
Host smart-4ce47b77-d448-4f96-8b6d-a587eb70519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283851572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1283851572
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4036268858
Short name T148
Test name
Test status
Simulation time 32518843352 ps
CPU time 48.83 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 04:51:00 PM PDT 24
Peak memory 199384 kb
Host smart-cdc187ec-d384-453d-87d2-53eff002c87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036268858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4036268858
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.754238188
Short name T287
Test name
Test status
Simulation time 73414950353 ps
CPU time 241.57 seconds
Started Jul 11 04:50:09 PM PDT 24
Finished Jul 11 04:54:14 PM PDT 24
Peak memory 213976 kb
Host smart-6794f831-84e9-4fa6-b24f-e19b46ea428d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754238188 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.754238188
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1468047023
Short name T481
Test name
Test status
Simulation time 12459122939 ps
CPU time 6.53 seconds
Started Jul 11 04:50:08 PM PDT 24
Finished Jul 11 04:50:18 PM PDT 24
Peak memory 199656 kb
Host smart-9025242b-11f9-41f8-9329-3de2545765b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468047023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1468047023
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3469283976
Short name T49
Test name
Test status
Simulation time 418234807281 ps
CPU time 866.84 seconds
Started Jul 11 04:50:12 PM PDT 24
Finished Jul 11 05:04:43 PM PDT 24
Peak memory 224632 kb
Host smart-ce9a5e26-b5a4-45a8-afdd-86a8f8c9beeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469283976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3469283976
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.153646180
Short name T385
Test name
Test status
Simulation time 39745811764 ps
CPU time 20.92 seconds
Started Jul 11 04:50:12 PM PDT 24
Finished Jul 11 04:50:37 PM PDT 24
Peak memory 199768 kb
Host smart-1dba5695-85fa-4748-b6a6-e20b15f46ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153646180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.153646180
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.420596256
Short name T106
Test name
Test status
Simulation time 19575523359 ps
CPU time 32.21 seconds
Started Jul 11 04:50:30 PM PDT 24
Finished Jul 11 04:51:05 PM PDT 24
Peak memory 199808 kb
Host smart-08c35e11-e779-4fbe-b17b-0567989efe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420596256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.420596256
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1351372513
Short name T1123
Test name
Test status
Simulation time 28394020059 ps
CPU time 174.92 seconds
Started Jul 11 04:50:22 PM PDT 24
Finished Jul 11 04:53:19 PM PDT 24
Peak memory 216336 kb
Host smart-201ddf34-0e44-45b1-9579-6d6f1f1a1687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351372513 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1351372513
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2912221858
Short name T150
Test name
Test status
Simulation time 67661638010 ps
CPU time 38.23 seconds
Started Jul 11 04:50:11 PM PDT 24
Finished Jul 11 04:50:54 PM PDT 24
Peak memory 199900 kb
Host smart-d67e5437-e33b-43a3-a9d7-9665bcbf740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912221858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2912221858
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3072222197
Short name T959
Test name
Test status
Simulation time 88006569749 ps
CPU time 772.27 seconds
Started Jul 11 04:50:17 PM PDT 24
Finished Jul 11 05:03:13 PM PDT 24
Peak memory 231204 kb
Host smart-b4e292fd-cc1e-4d64-8837-f7041e061f52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072222197 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3072222197
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3542712672
Short name T728
Test name
Test status
Simulation time 60916230227 ps
CPU time 46.6 seconds
Started Jul 11 04:50:21 PM PDT 24
Finished Jul 11 04:51:10 PM PDT 24
Peak memory 199832 kb
Host smart-6e4255aa-403a-406e-9cf4-399a2f330a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542712672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3542712672
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.451740443
Short name T874
Test name
Test status
Simulation time 385735634983 ps
CPU time 306.88 seconds
Started Jul 11 04:50:10 PM PDT 24
Finished Jul 11 04:55:22 PM PDT 24
Peak memory 209284 kb
Host smart-cfa044c2-1fd7-4111-8578-5ef3a2e24da9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451740443 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.451740443
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1465574665
Short name T683
Test name
Test status
Simulation time 18613327 ps
CPU time 0.57 seconds
Started Jul 11 04:48:27 PM PDT 24
Finished Jul 11 04:48:37 PM PDT 24
Peak memory 195152 kb
Host smart-b99b50d1-a48c-4bc2-80cc-9ac977390758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465574665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1465574665
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2843255306
Short name T726
Test name
Test status
Simulation time 37949926513 ps
CPU time 70.85 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:49:42 PM PDT 24
Peak memory 199860 kb
Host smart-88f1c42b-0856-4546-abdf-c9c02602df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843255306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2843255306
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.353709403
Short name T1166
Test name
Test status
Simulation time 41599046468 ps
CPU time 30.14 seconds
Started Jul 11 04:48:05 PM PDT 24
Finished Jul 11 04:48:39 PM PDT 24
Peak memory 199776 kb
Host smart-e4719e0f-7529-4e8c-bc32-46f8a331c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353709403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.353709403
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2086034637
Short name T678
Test name
Test status
Simulation time 29635068360 ps
CPU time 62.19 seconds
Started Jul 11 04:48:16 PM PDT 24
Finished Jul 11 04:49:22 PM PDT 24
Peak memory 199848 kb
Host smart-441f8279-ef97-4340-852f-bbd0dfd2112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086034637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2086034637
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3559731383
Short name T374
Test name
Test status
Simulation time 15299244575 ps
CPU time 25.41 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:48:56 PM PDT 24
Peak memory 199896 kb
Host smart-60d45417-bd82-4c22-b5c2-3ce497c7f254
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559731383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3559731383
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3178808540
Short name T1176
Test name
Test status
Simulation time 97287429915 ps
CPU time 700.83 seconds
Started Jul 11 04:48:20 PM PDT 24
Finished Jul 11 05:00:06 PM PDT 24
Peak memory 199852 kb
Host smart-907a6131-729e-43dd-8635-7c0a6e915db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178808540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3178808540
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.4222961368
Short name T842
Test name
Test status
Simulation time 871248207 ps
CPU time 0.95 seconds
Started Jul 11 04:48:08 PM PDT 24
Finished Jul 11 04:48:12 PM PDT 24
Peak memory 195236 kb
Host smart-a2ba63dd-4494-4585-9984-86d46a1ea678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222961368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.4222961368
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.811183505
Short name T637
Test name
Test status
Simulation time 34754678288 ps
CPU time 28.68 seconds
Started Jul 11 04:48:14 PM PDT 24
Finished Jul 11 04:48:47 PM PDT 24
Peak memory 199972 kb
Host smart-eb8d1794-b740-4c66-9bcb-d498e9b345a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811183505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.811183505
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1700975324
Short name T796
Test name
Test status
Simulation time 6351558187 ps
CPU time 95.64 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:49:45 PM PDT 24
Peak memory 199860 kb
Host smart-cf9b0143-13ac-4d6e-97ad-f1f8a5cc2c42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700975324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1700975324
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.156157920
Short name T612
Test name
Test status
Simulation time 2968057242 ps
CPU time 11.18 seconds
Started Jul 11 04:48:02 PM PDT 24
Finished Jul 11 04:48:19 PM PDT 24
Peak memory 198916 kb
Host smart-032fbef4-e032-4ca4-b9cb-446ae2575216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=156157920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.156157920
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1075757833
Short name T121
Test name
Test status
Simulation time 15548913871 ps
CPU time 43.76 seconds
Started Jul 11 04:48:07 PM PDT 24
Finished Jul 11 04:48:54 PM PDT 24
Peak memory 199892 kb
Host smart-4ead6bb7-c73f-4178-b9ff-78e2e34191ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075757833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1075757833
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3396456673
Short name T1153
Test name
Test status
Simulation time 486671545 ps
CPU time 1.42 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 04:48:16 PM PDT 24
Peak memory 195416 kb
Host smart-c22a756f-a210-44f8-bfd9-ac7c803040a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396456673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3396456673
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2752067484
Short name T367
Test name
Test status
Simulation time 246275758 ps
CPU time 1.36 seconds
Started Jul 11 04:48:11 PM PDT 24
Finished Jul 11 04:48:17 PM PDT 24
Peak memory 198320 kb
Host smart-4c05e99e-afc5-4170-a86a-a1e0dda6abac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752067484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2752067484
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.4224995692
Short name T784
Test name
Test status
Simulation time 553326802114 ps
CPU time 2354.74 seconds
Started Jul 11 04:48:20 PM PDT 24
Finished Jul 11 05:27:40 PM PDT 24
Peak memory 199840 kb
Host smart-fb4e32b5-c7b7-47af-8c9b-2697b0fb9d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224995692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.4224995692
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1404307063
Short name T850
Test name
Test status
Simulation time 121547138998 ps
CPU time 443.3 seconds
Started Jul 11 04:48:11 PM PDT 24
Finished Jul 11 04:55:39 PM PDT 24
Peak memory 216296 kb
Host smart-0e416ee7-89ba-40ea-a7b0-bc18f43592fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404307063 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1404307063
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1226573062
Short name T447
Test name
Test status
Simulation time 919207995 ps
CPU time 2.71 seconds
Started Jul 11 04:48:26 PM PDT 24
Finished Jul 11 04:48:38 PM PDT 24
Peak memory 198580 kb
Host smart-38bfd427-9db5-45dd-84fb-5388340449e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226573062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1226573062
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2919259037
Short name T303
Test name
Test status
Simulation time 68079994739 ps
CPU time 64.72 seconds
Started Jul 11 04:48:09 PM PDT 24
Finished Jul 11 04:49:18 PM PDT 24
Peak memory 199932 kb
Host smart-9bf46d47-d0e9-4ce8-8a4e-2461b4d87b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919259037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2919259037
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2387724774
Short name T198
Test name
Test status
Simulation time 32314585153 ps
CPU time 25.11 seconds
Started Jul 11 04:50:14 PM PDT 24
Finished Jul 11 04:50:44 PM PDT 24
Peak memory 199832 kb
Host smart-11545846-e9f2-4466-82ef-8139b8324142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387724774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2387724774
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.709976793
Short name T558
Test name
Test status
Simulation time 51721485704 ps
CPU time 268.51 seconds
Started Jul 11 04:50:12 PM PDT 24
Finished Jul 11 04:54:44 PM PDT 24
Peak memory 215708 kb
Host smart-7d769db8-bd0a-4beb-a050-0b56759d60d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709976793 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.709976793
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1997247408
Short name T202
Test name
Test status
Simulation time 209094758660 ps
CPU time 748.51 seconds
Started Jul 11 04:50:11 PM PDT 24
Finished Jul 11 05:02:44 PM PDT 24
Peak memory 213400 kb
Host smart-570b1b3e-4c72-4cbf-b0e1-a3497fcd2a9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997247408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1997247408
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.365342953
Short name T839
Test name
Test status
Simulation time 124038100359 ps
CPU time 178.2 seconds
Started Jul 11 04:50:14 PM PDT 24
Finished Jul 11 04:53:16 PM PDT 24
Peak memory 199840 kb
Host smart-fa02964a-308a-43b4-a918-b3ed9dd1ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365342953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.365342953
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1153376532
Short name T1127
Test name
Test status
Simulation time 39728436086 ps
CPU time 52.64 seconds
Started Jul 11 04:50:14 PM PDT 24
Finished Jul 11 04:51:11 PM PDT 24
Peak memory 199764 kb
Host smart-f2070388-e20e-47ac-8b44-7c13859cc418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153376532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1153376532
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3132287954
Short name T785
Test name
Test status
Simulation time 38576375248 ps
CPU time 42.87 seconds
Started Jul 11 04:50:20 PM PDT 24
Finished Jul 11 04:51:06 PM PDT 24
Peak memory 199888 kb
Host smart-65a20102-abf6-4a70-aae4-efa29e83dd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132287954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3132287954
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1092854959
Short name T172
Test name
Test status
Simulation time 688175479421 ps
CPU time 1895.78 seconds
Started Jul 11 04:50:14 PM PDT 24
Finished Jul 11 05:21:54 PM PDT 24
Peak memory 241136 kb
Host smart-dade49b8-7c2b-474a-babe-0b7868114535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092854959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1092854959
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2725286806
Short name T122
Test name
Test status
Simulation time 26457817887 ps
CPU time 26.91 seconds
Started Jul 11 04:50:13 PM PDT 24
Finished Jul 11 04:50:44 PM PDT 24
Peak memory 199920 kb
Host smart-2bd0f03b-485b-46ae-a9df-0fdb58422418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725286806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2725286806
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3339151692
Short name T622
Test name
Test status
Simulation time 73676975754 ps
CPU time 222.28 seconds
Started Jul 11 04:50:16 PM PDT 24
Finished Jul 11 04:54:02 PM PDT 24
Peak memory 216860 kb
Host smart-d1f09063-51e8-4525-aa1a-6f1e4d1eedd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339151692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3339151692
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2085363380
Short name T1071
Test name
Test status
Simulation time 22738757276 ps
CPU time 34.05 seconds
Started Jul 11 04:50:11 PM PDT 24
Finished Jul 11 04:50:50 PM PDT 24
Peak memory 199832 kb
Host smart-48b9f328-3442-412c-9641-5a969a50b365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085363380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2085363380
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3104762149
Short name T805
Test name
Test status
Simulation time 76259721291 ps
CPU time 784.76 seconds
Started Jul 11 04:50:11 PM PDT 24
Finished Jul 11 05:03:20 PM PDT 24
Peak memory 216344 kb
Host smart-1fa65b53-da0e-43e2-9c47-441ddf87444d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104762149 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3104762149
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.220549488
Short name T811
Test name
Test status
Simulation time 17184543728 ps
CPU time 14.15 seconds
Started Jul 11 04:50:15 PM PDT 24
Finished Jul 11 04:50:34 PM PDT 24
Peak memory 200108 kb
Host smart-1d9d224a-eceb-4dad-8bbc-3cf8ed0290a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220549488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.220549488
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.12959047
Short name T578
Test name
Test status
Simulation time 216949143422 ps
CPU time 234.95 seconds
Started Jul 11 04:50:20 PM PDT 24
Finished Jul 11 04:54:18 PM PDT 24
Peak memory 216392 kb
Host smart-54db86ea-6a81-4efb-b52a-76d932061068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12959047 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.12959047
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3453517096
Short name T224
Test name
Test status
Simulation time 37749550541 ps
CPU time 51.87 seconds
Started Jul 11 04:50:11 PM PDT 24
Finished Jul 11 04:51:07 PM PDT 24
Peak memory 199904 kb
Host smart-c56ddcf4-52c9-4901-9f1f-e43c436f5a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453517096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3453517096
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1567721442
Short name T1115
Test name
Test status
Simulation time 287539089951 ps
CPU time 783.05 seconds
Started Jul 11 04:50:19 PM PDT 24
Finished Jul 11 05:03:25 PM PDT 24
Peak memory 224760 kb
Host smart-f2766423-3d5b-4349-9de3-4421dbc167a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567721442 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1567721442
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3680991358
Short name T402
Test name
Test status
Simulation time 27533069752 ps
CPU time 32.56 seconds
Started Jul 11 04:50:18 PM PDT 24
Finished Jul 11 04:50:54 PM PDT 24
Peak memory 199864 kb
Host smart-a325bc39-0e95-4c59-856d-0b22df0f465e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680991358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3680991358
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2637945725
Short name T773
Test name
Test status
Simulation time 198553775327 ps
CPU time 500.47 seconds
Started Jul 11 04:50:14 PM PDT 24
Finished Jul 11 04:58:39 PM PDT 24
Peak memory 216640 kb
Host smart-4b65f796-22c3-41ff-931e-95128118de7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637945725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2637945725
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2217533946
Short name T17
Test name
Test status
Simulation time 33086765 ps
CPU time 0.57 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:48:10 PM PDT 24
Peak memory 195508 kb
Host smart-4a31f542-fa4f-414a-a746-b3291e31ecd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217533946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2217533946
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.429410867
Short name T1049
Test name
Test status
Simulation time 44411997689 ps
CPU time 45.3 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:48:55 PM PDT 24
Peak memory 199840 kb
Host smart-3ebef569-56d0-490f-903b-773aaedb08c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429410867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.429410867
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.758084026
Short name T582
Test name
Test status
Simulation time 166041516393 ps
CPU time 320.79 seconds
Started Jul 11 04:48:12 PM PDT 24
Finished Jul 11 04:53:37 PM PDT 24
Peak memory 199856 kb
Host smart-13c100f5-4d39-447a-937f-fdeee6d39e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758084026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.758084026
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3039447053
Short name T238
Test name
Test status
Simulation time 117126943388 ps
CPU time 49.25 seconds
Started Jul 11 04:48:11 PM PDT 24
Finished Jul 11 04:49:05 PM PDT 24
Peak memory 199880 kb
Host smart-bee47962-195a-4dda-9fc3-2f2839782b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039447053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3039447053
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.364512898
Short name T581
Test name
Test status
Simulation time 167624435191 ps
CPU time 85.25 seconds
Started Jul 11 04:48:07 PM PDT 24
Finished Jul 11 04:49:36 PM PDT 24
Peak memory 199748 kb
Host smart-62d98cd1-5547-4445-8bba-1ef32117c6fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364512898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.364512898
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_loopback.1411466108
Short name T466
Test name
Test status
Simulation time 2262542185 ps
CPU time 2.54 seconds
Started Jul 11 04:48:25 PM PDT 24
Finished Jul 11 04:48:36 PM PDT 24
Peak memory 198512 kb
Host smart-449e6450-b1f7-4715-97c6-aec42e8c2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411466108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1411466108
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1970194005
Short name T1061
Test name
Test status
Simulation time 184459938344 ps
CPU time 98.99 seconds
Started Jul 11 04:48:05 PM PDT 24
Finished Jul 11 04:49:48 PM PDT 24
Peak memory 216324 kb
Host smart-62ce5457-7172-465f-9e14-8e0f025d3ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970194005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1970194005
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3075354601
Short name T884
Test name
Test status
Simulation time 26971836000 ps
CPU time 1214.41 seconds
Started Jul 11 04:48:09 PM PDT 24
Finished Jul 11 05:08:29 PM PDT 24
Peak memory 199820 kb
Host smart-98cd2dbc-b1bb-4335-b7d1-3ebde709e87c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075354601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3075354601
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2338556633
Short name T78
Test name
Test status
Simulation time 5100046814 ps
CPU time 19.56 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:48:30 PM PDT 24
Peak memory 199772 kb
Host smart-8707fd16-ea9f-425d-b349-c48ed08f3477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338556633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2338556633
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1402967142
Short name T976
Test name
Test status
Simulation time 31861490382 ps
CPU time 44.71 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:48:55 PM PDT 24
Peak memory 199828 kb
Host smart-48368557-5cbc-458d-8843-e4e5eb5191c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402967142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1402967142
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3254034108
Short name T392
Test name
Test status
Simulation time 1535273152 ps
CPU time 1.06 seconds
Started Jul 11 04:48:21 PM PDT 24
Finished Jul 11 04:48:28 PM PDT 24
Peak memory 195340 kb
Host smart-67a22f5e-0975-4a62-b929-cba6c9017db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254034108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3254034108
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3816743023
Short name T542
Test name
Test status
Simulation time 478631999 ps
CPU time 1.73 seconds
Started Jul 11 04:48:04 PM PDT 24
Finished Jul 11 04:48:10 PM PDT 24
Peak memory 199200 kb
Host smart-e6771314-ec46-4890-90b1-685077d4978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816743023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3816743023
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1236769684
Short name T1026
Test name
Test status
Simulation time 414507990091 ps
CPU time 762.92 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 05:00:58 PM PDT 24
Peak memory 199904 kb
Host smart-c595f5b3-13c6-4a4d-a1cd-56751d1ce399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236769684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1236769684
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3532598227
Short name T166
Test name
Test status
Simulation time 221286439576 ps
CPU time 1025.31 seconds
Started Jul 11 04:48:04 PM PDT 24
Finished Jul 11 05:05:14 PM PDT 24
Peak memory 225580 kb
Host smart-59006587-355e-46f9-b3ee-d9bfaa8f6684
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532598227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3532598227
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3152308980
Short name T882
Test name
Test status
Simulation time 1623437714 ps
CPU time 1.52 seconds
Started Jul 11 04:48:21 PM PDT 24
Finished Jul 11 04:48:29 PM PDT 24
Peak memory 198432 kb
Host smart-4fa5d320-1622-4c54-82e5-03f08cc685b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152308980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3152308980
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3952029995
Short name T872
Test name
Test status
Simulation time 116157039384 ps
CPU time 54.03 seconds
Started Jul 11 04:48:05 PM PDT 24
Finished Jul 11 04:49:03 PM PDT 24
Peak memory 199844 kb
Host smart-47530b8b-deae-438a-b184-3c4d35e9eeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952029995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3952029995
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1542897769
Short name T1072
Test name
Test status
Simulation time 51809479838 ps
CPU time 24.76 seconds
Started Jul 11 04:50:13 PM PDT 24
Finished Jul 11 04:50:42 PM PDT 24
Peak memory 199808 kb
Host smart-4c205fe6-3930-4fdd-b94c-a3b95c47edb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542897769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1542897769
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3682097570
Short name T28
Test name
Test status
Simulation time 40790807615 ps
CPU time 440.41 seconds
Started Jul 11 04:50:12 PM PDT 24
Finished Jul 11 04:57:36 PM PDT 24
Peak memory 216540 kb
Host smart-55aee6b2-fc1a-4d26-a9f7-b83daa067e0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682097570 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3682097570
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3782339579
Short name T725
Test name
Test status
Simulation time 26255086563 ps
CPU time 21.04 seconds
Started Jul 11 04:50:22 PM PDT 24
Finished Jul 11 04:50:45 PM PDT 24
Peak memory 199824 kb
Host smart-f6429efe-eba3-4753-ba9f-865a5e41bf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782339579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3782339579
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1604339815
Short name T136
Test name
Test status
Simulation time 91770140823 ps
CPU time 352.76 seconds
Started Jul 11 04:50:22 PM PDT 24
Finished Jul 11 04:56:18 PM PDT 24
Peak memory 215456 kb
Host smart-7ddba0a2-2c1b-4df2-b6e8-d5997a23c80f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604339815 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1604339815
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1569010653
Short name T1015
Test name
Test status
Simulation time 162976617766 ps
CPU time 64.64 seconds
Started Jul 11 04:50:13 PM PDT 24
Finished Jul 11 04:51:22 PM PDT 24
Peak memory 199880 kb
Host smart-e92e66d2-6de0-4a32-b3d5-4acae429f820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569010653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1569010653
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.838892987
Short name T997
Test name
Test status
Simulation time 74941056619 ps
CPU time 1156.37 seconds
Started Jul 11 04:50:15 PM PDT 24
Finished Jul 11 05:09:36 PM PDT 24
Peak memory 216512 kb
Host smart-f6d8d07e-2b61-4da8-8eba-c3fa8e65c7ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838892987 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.838892987
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.852396274
Short name T1150
Test name
Test status
Simulation time 39742161232 ps
CPU time 33.23 seconds
Started Jul 11 04:50:13 PM PDT 24
Finished Jul 11 04:50:51 PM PDT 24
Peak memory 199844 kb
Host smart-c5ca39c6-b642-42e5-8197-ebf0cf9cdb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852396274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.852396274
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3598447983
Short name T980
Test name
Test status
Simulation time 112621419252 ps
CPU time 291.59 seconds
Started Jul 11 04:50:20 PM PDT 24
Finished Jul 11 04:55:15 PM PDT 24
Peak memory 216300 kb
Host smart-eda4dbab-e297-4838-a4e9-e90d4e824e39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598447983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3598447983
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2812479810
Short name T711
Test name
Test status
Simulation time 56501467886 ps
CPU time 20.49 seconds
Started Jul 11 04:50:24 PM PDT 24
Finished Jul 11 04:50:46 PM PDT 24
Peak memory 199828 kb
Host smart-78ea7993-3daf-4a77-8754-ffb270118f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812479810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2812479810
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1309057649
Short name T459
Test name
Test status
Simulation time 66518197418 ps
CPU time 580.1 seconds
Started Jul 11 04:50:22 PM PDT 24
Finished Jul 11 05:00:05 PM PDT 24
Peak memory 224740 kb
Host smart-85a996bb-afc7-475e-a68c-ea334195deb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309057649 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1309057649
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.736342870
Short name T171
Test name
Test status
Simulation time 21203388629 ps
CPU time 12.97 seconds
Started Jul 11 04:50:20 PM PDT 24
Finished Jul 11 04:50:36 PM PDT 24
Peak memory 199824 kb
Host smart-49391d3d-f58d-46d8-9046-d9548a16ddf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736342870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.736342870
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1470406089
Short name T1143
Test name
Test status
Simulation time 255871835142 ps
CPU time 838.79 seconds
Started Jul 11 04:50:24 PM PDT 24
Finished Jul 11 05:04:24 PM PDT 24
Peak memory 224736 kb
Host smart-90d68bd0-62ce-4b18-8fe6-2f92b3433dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470406089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1470406089
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1210363135
Short name T1181
Test name
Test status
Simulation time 15281096268 ps
CPU time 295.23 seconds
Started Jul 11 04:50:22 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 215436 kb
Host smart-05871c59-f6ba-4f2b-ac88-30f8a339f7f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210363135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1210363135
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1078939100
Short name T415
Test name
Test status
Simulation time 115872617112 ps
CPU time 179.11 seconds
Started Jul 11 04:50:19 PM PDT 24
Finished Jul 11 04:53:21 PM PDT 24
Peak memory 199900 kb
Host smart-fbf49cba-34dc-420d-aa47-2097eaecbdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078939100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1078939100
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3341999813
Short name T290
Test name
Test status
Simulation time 22341268983 ps
CPU time 219.86 seconds
Started Jul 11 04:50:20 PM PDT 24
Finished Jul 11 04:54:03 PM PDT 24
Peak memory 216336 kb
Host smart-ab3c7bb7-870d-4344-a1ce-612e80de0633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341999813 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3341999813
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1934164646
Short name T798
Test name
Test status
Simulation time 6162485917 ps
CPU time 11.82 seconds
Started Jul 11 04:50:24 PM PDT 24
Finished Jul 11 04:50:37 PM PDT 24
Peak memory 199832 kb
Host smart-7e3337d1-5e3d-449f-8e2f-b76a5bd586f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934164646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1934164646
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3543741642
Short name T101
Test name
Test status
Simulation time 39617659671 ps
CPU time 309.61 seconds
Started Jul 11 04:50:24 PM PDT 24
Finished Jul 11 04:55:36 PM PDT 24
Peak memory 209184 kb
Host smart-14a12898-1413-4850-9a3d-580ad2b7cdb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543741642 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3543741642
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2025513956
Short name T571
Test name
Test status
Simulation time 11630053 ps
CPU time 0.55 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:48:23 PM PDT 24
Peak memory 195516 kb
Host smart-e8be648d-b7d0-4ae3-a48b-f5b0bb6e3b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025513956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2025513956
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3705895881
Short name T409
Test name
Test status
Simulation time 17191625081 ps
CPU time 24.01 seconds
Started Jul 11 04:48:19 PM PDT 24
Finished Jul 11 04:48:48 PM PDT 24
Peak memory 199780 kb
Host smart-c9e9871e-3b06-4aad-b5ec-ec6eea91d3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705895881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3705895881
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3752066563
Short name T364
Test name
Test status
Simulation time 117905908412 ps
CPU time 160.66 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:51:03 PM PDT 24
Peak memory 199904 kb
Host smart-8a297d9f-8cbe-40d2-99a7-30e6a3d060b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752066563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3752066563
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.4124581863
Short name T591
Test name
Test status
Simulation time 1475051210 ps
CPU time 2.71 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 04:48:18 PM PDT 24
Peak memory 195528 kb
Host smart-f57832b7-44ec-433b-b14e-b88eb6a69355
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124581863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4124581863
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3021731144
Short name T253
Test name
Test status
Simulation time 119313718457 ps
CPU time 417.06 seconds
Started Jul 11 04:48:18 PM PDT 24
Finished Jul 11 04:55:20 PM PDT 24
Peak memory 199796 kb
Host smart-9ade2171-911e-415f-9a01-22e93c6f9547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021731144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3021731144
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1701720213
Short name T565
Test name
Test status
Simulation time 2878811948 ps
CPU time 5.75 seconds
Started Jul 11 04:48:24 PM PDT 24
Finished Jul 11 04:48:37 PM PDT 24
Peak memory 198768 kb
Host smart-8bbdcc7d-25a6-42d3-92e7-7bd5e24dc981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701720213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1701720213
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1660880006
Short name T705
Test name
Test status
Simulation time 64390936575 ps
CPU time 164.04 seconds
Started Jul 11 04:48:17 PM PDT 24
Finished Jul 11 04:51:06 PM PDT 24
Peak memory 200028 kb
Host smart-497e5151-7295-4303-829f-dd00dbd087d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660880006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1660880006
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2054923471
Short name T470
Test name
Test status
Simulation time 24574943339 ps
CPU time 1060.24 seconds
Started Jul 11 04:48:21 PM PDT 24
Finished Jul 11 05:06:07 PM PDT 24
Peak memory 199900 kb
Host smart-230334d3-96e5-4810-875b-22e4cea358c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054923471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2054923471
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1548354421
Short name T844
Test name
Test status
Simulation time 3567758127 ps
CPU time 29.23 seconds
Started Jul 11 04:48:31 PM PDT 24
Finished Jul 11 04:49:10 PM PDT 24
Peak memory 199100 kb
Host smart-f466b6e2-6642-4a6c-b004-e77574a1a654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1548354421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1548354421
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1161090308
Short name T341
Test name
Test status
Simulation time 9538389583 ps
CPU time 4.74 seconds
Started Jul 11 04:48:06 PM PDT 24
Finished Jul 11 04:48:14 PM PDT 24
Peak memory 197160 kb
Host smart-6e31aacd-f0dc-4ba7-988b-05eb96988900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161090308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1161090308
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2386319294
Short name T688
Test name
Test status
Simulation time 1416463171 ps
CPU time 2.32 seconds
Started Jul 11 04:48:10 PM PDT 24
Finished Jul 11 04:48:17 PM PDT 24
Peak memory 195308 kb
Host smart-af2d430c-bcbe-4baf-820a-22954dd3e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386319294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2386319294
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2373941596
Short name T515
Test name
Test status
Simulation time 841954148 ps
CPU time 3.98 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:48:34 PM PDT 24
Peak memory 198104 kb
Host smart-07dac223-a79f-4046-9be1-86d99db55320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373941596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2373941596
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3026467893
Short name T774
Test name
Test status
Simulation time 54909958229 ps
CPU time 112.98 seconds
Started Jul 11 04:48:23 PM PDT 24
Finished Jul 11 04:50:24 PM PDT 24
Peak memory 199804 kb
Host smart-57874938-c7cb-435f-ac9f-3ea2bf055f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026467893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3026467893
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1716525924
Short name T966
Test name
Test status
Simulation time 42341521858 ps
CPU time 246.37 seconds
Started Jul 11 04:48:43 PM PDT 24
Finished Jul 11 04:52:57 PM PDT 24
Peak memory 216532 kb
Host smart-c5d1c33f-a71b-45e9-a3b2-801ff16dc87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716525924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1716525924
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2969208292
Short name T1154
Test name
Test status
Simulation time 7046304744 ps
CPU time 21.32 seconds
Started Jul 11 04:53:47 PM PDT 24
Finished Jul 11 04:54:17 PM PDT 24
Peak memory 199692 kb
Host smart-dc31df4e-d55d-4f9a-810a-ed5cc2ad146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969208292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2969208292
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3893892515
Short name T1141
Test name
Test status
Simulation time 72277729714 ps
CPU time 127.5 seconds
Started Jul 11 04:48:07 PM PDT 24
Finished Jul 11 04:50:18 PM PDT 24
Peak memory 199780 kb
Host smart-bcd528a7-09e0-4691-af46-ad78bd46bcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893892515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3893892515
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.752362285
Short name T893
Test name
Test status
Simulation time 75060126357 ps
CPU time 149.39 seconds
Started Jul 11 04:50:20 PM PDT 24
Finished Jul 11 04:52:53 PM PDT 24
Peak memory 199940 kb
Host smart-51ed73dd-7454-4228-b6af-bfafe468b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752362285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.752362285
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3991502493
Short name T153
Test name
Test status
Simulation time 124805899378 ps
CPU time 201.75 seconds
Started Jul 11 04:50:24 PM PDT 24
Finished Jul 11 04:53:47 PM PDT 24
Peak memory 215084 kb
Host smart-496cd76a-227d-479f-bc0b-7bec43188230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991502493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3991502493
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1069881992
Short name T411
Test name
Test status
Simulation time 6170424138 ps
CPU time 16.08 seconds
Started Jul 11 04:50:28 PM PDT 24
Finished Jul 11 04:50:46 PM PDT 24
Peak memory 199924 kb
Host smart-78378f87-8c64-4bda-805d-e2a5f6dfe595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069881992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1069881992
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.617573810
Short name T673
Test name
Test status
Simulation time 18073775345 ps
CPU time 180.92 seconds
Started Jul 11 04:50:19 PM PDT 24
Finished Jul 11 04:53:22 PM PDT 24
Peak memory 215352 kb
Host smart-4b2283ea-51af-44dc-b468-c077ff548a67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617573810 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.617573810
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3403604267
Short name T1064
Test name
Test status
Simulation time 37216615735 ps
CPU time 54.67 seconds
Started Jul 11 04:50:27 PM PDT 24
Finished Jul 11 04:51:24 PM PDT 24
Peak memory 199812 kb
Host smart-13674faa-caf5-4482-85c9-65bb513ac802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403604267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3403604267
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1410888062
Short name T699
Test name
Test status
Simulation time 171285471502 ps
CPU time 466.73 seconds
Started Jul 11 04:50:21 PM PDT 24
Finished Jul 11 04:58:10 PM PDT 24
Peak memory 224800 kb
Host smart-3e2d5261-6363-4579-aee8-4b3c7101e2ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410888062 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1410888062
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.4005065627
Short name T690
Test name
Test status
Simulation time 27735303062 ps
CPU time 19.49 seconds
Started Jul 11 04:50:32 PM PDT 24
Finished Jul 11 04:50:55 PM PDT 24
Peak memory 199832 kb
Host smart-cbe223ee-c7cc-445c-b74e-1768c77b227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005065627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.4005065627
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2517875422
Short name T961
Test name
Test status
Simulation time 14831504736 ps
CPU time 165.51 seconds
Started Jul 11 04:50:22 PM PDT 24
Finished Jul 11 04:53:10 PM PDT 24
Peak memory 215376 kb
Host smart-bf20a348-9c63-407b-babd-16ede189259a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517875422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2517875422
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3222684336
Short name T700
Test name
Test status
Simulation time 38338439790 ps
CPU time 33.43 seconds
Started Jul 11 04:50:32 PM PDT 24
Finished Jul 11 04:51:10 PM PDT 24
Peak memory 199840 kb
Host smart-5448e26f-56f4-4e9b-85fb-dacb1700143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222684336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3222684336
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2790273241
Short name T1134
Test name
Test status
Simulation time 123212058987 ps
CPU time 870.82 seconds
Started Jul 11 04:50:27 PM PDT 24
Finished Jul 11 05:04:59 PM PDT 24
Peak memory 224764 kb
Host smart-404636bd-be83-4267-84a8-44ad2a892eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790273241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2790273241
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1561295693
Short name T624
Test name
Test status
Simulation time 31619596435 ps
CPU time 26.85 seconds
Started Jul 11 04:50:32 PM PDT 24
Finished Jul 11 04:51:02 PM PDT 24
Peak memory 199884 kb
Host smart-cdc0fb78-d2a3-49d0-9718-dfe270e7d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561295693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1561295693
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2188532206
Short name T175
Test name
Test status
Simulation time 227521926045 ps
CPU time 538.66 seconds
Started Jul 11 04:50:20 PM PDT 24
Finished Jul 11 04:59:22 PM PDT 24
Peak memory 216640 kb
Host smart-bcd29bcc-9d74-40f1-96df-26692f6fbbf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188532206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2188532206
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3617269437
Short name T604
Test name
Test status
Simulation time 46346561947 ps
CPU time 77.16 seconds
Started Jul 11 04:50:22 PM PDT 24
Finished Jul 11 04:51:41 PM PDT 24
Peak memory 199916 kb
Host smart-fa4538c0-e85c-4dfa-b7a4-3d78be367924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617269437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3617269437
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1376582107
Short name T27
Test name
Test status
Simulation time 93374733763 ps
CPU time 193.83 seconds
Started Jul 11 04:50:19 PM PDT 24
Finished Jul 11 04:53:36 PM PDT 24
Peak memory 215724 kb
Host smart-1b1190e2-825e-4410-8d13-173e0fb5470f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376582107 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1376582107
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1127539106
Short name T225
Test name
Test status
Simulation time 84679230529 ps
CPU time 32.93 seconds
Started Jul 11 04:50:21 PM PDT 24
Finished Jul 11 04:50:56 PM PDT 24
Peak memory 199840 kb
Host smart-f3ff722e-a7eb-46c0-869e-4170da4ed596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127539106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1127539106
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2336422108
Short name T47
Test name
Test status
Simulation time 158918637317 ps
CPU time 895 seconds
Started Jul 11 04:50:23 PM PDT 24
Finished Jul 11 05:05:20 PM PDT 24
Peak memory 216508 kb
Host smart-4bd747a3-8e1a-4600-9082-a691f83d064b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336422108 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2336422108
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2378962215
Short name T429
Test name
Test status
Simulation time 16373893975 ps
CPU time 19.16 seconds
Started Jul 11 04:50:19 PM PDT 24
Finished Jul 11 04:50:41 PM PDT 24
Peak memory 199940 kb
Host smart-c333ac21-f977-47b9-b365-fbe1547b978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378962215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2378962215
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3319223386
Short name T535
Test name
Test status
Simulation time 273246378610 ps
CPU time 982.56 seconds
Started Jul 11 04:50:19 PM PDT 24
Finished Jul 11 05:06:45 PM PDT 24
Peak memory 224640 kb
Host smart-641be66e-e133-48c9-87be-542fae992f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319223386 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3319223386
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2647909654
Short name T29
Test name
Test status
Simulation time 64129706518 ps
CPU time 51.22 seconds
Started Jul 11 04:50:31 PM PDT 24
Finished Jul 11 04:51:26 PM PDT 24
Peak memory 199596 kb
Host smart-b9114354-ac8f-4c2d-a117-f090341bce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647909654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2647909654
Directory /workspace/99.uart_fifo_reset/latest
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