Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	122994	1			T1	95		T2	9		T3	10
all_values[1]	122994	1			T1	95		T2	9		T3	10
all_values[2]	122994	1			T1	95		T2	9		T3	10
all_values[3]	122994	1			T1	95		T2	9		T3	10
all_values[4]	122994	1			T1	95		T2	9		T3	10
all_values[5]	122994	1			T1	95		T2	9		T3	10
all_values[6]	122994	1			T1	95		T2	9		T3	10
all_values[7]	122994	1			T1	95		T2	9		T3	10
all_values[8]	122994	1			T1	95		T2	9		T3	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

568657

1

T1

401

T2

28

T3

40

auto[1]

538289

1

T1

454

T2

53

T3

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011434

1

T1

720

T2

75

T3

67

auto[1]

95512

1

T1

135

T2

6

T3

23

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	40032	1			T1	9		T2	6		T4	19
all_values[0]	auto[0]	auto[1]	24274	1			T1	59		T2	1		T4	3
all_values[0]	auto[1]	auto[0]	34996	1			T1	8		T5	3		T10	415
all_values[0]	auto[1]	auto[1]	23692	1			T1	19		T2	2		T3	10
all_values[1]	auto[0]	auto[0]	58233	1			T1	93		T2	1		T3	8
all_values[1]	auto[0]	auto[1]	1693	1			T3	2		T4	19		T12	10
all_values[1]	auto[1]	auto[0]	61592	1			T1	2		T2	8		T5	3
all_values[1]	auto[1]	auto[1]	1476	1			T41	15		T12	1		T25	5
all_values[2]	auto[0]	auto[0]	58854	1			T1	28		T2	1		T3	5
all_values[2]	auto[0]	auto[1]	2868	1			T1	1		T2	1		T4	3
all_values[2]	auto[1]	auto[0]	58719	1			T1	65		T2	7		T3	5
all_values[2]	auto[1]	auto[1]	2553	1			T1	1		T4	2		T5	5
all_values[3]	auto[0]	auto[0]	61266	1			T1	29		T2	6		T4	25
all_values[3]	auto[0]	auto[1]	324	1			T8	1		T12	10		T14	3
all_values[3]	auto[1]	auto[0]	61104	1			T1	66		T2	3		T3	10
all_values[3]	auto[1]	auto[1]	300	1			T4	1		T12	2		T77	1
all_values[4]	auto[0]	auto[0]	61196	1			T2	2		T3	9		T4	9
all_values[4]	auto[0]	auto[1]	449	1			T3	1		T14	1		T15	2
all_values[4]	auto[1]	auto[0]	60890	1			T1	95		T2	7		T4	19
all_values[4]	auto[1]	auto[1]	459	1			T12	4		T14	7		T15	4
all_values[5]	auto[0]	auto[0]	65620	1			T1	10		T2	1		T3	5
all_values[5]	auto[0]	auto[1]	204	1			T14	4		T15	2		T78	2
all_values[5]	auto[1]	auto[0]	57014	1			T1	85		T2	8		T3	5
all_values[5]	auto[1]	auto[1]	156	1			T14	2		T78	3		T112	2
all_values[6]	auto[0]	auto[0]	64857	1			T1	31		T2	7		T4	25
all_values[6]	auto[0]	auto[1]	173	1			T12	2		T14	3		T78	2
all_values[6]	auto[1]	auto[0]	57813	1			T1	64		T2	2		T3	10
all_values[6]	auto[1]	auto[1]	151	1			T12	1		T14	4		T78	2
all_values[7]	auto[0]	auto[0]	68350	1			T1	56		T2	2		T3	10
all_values[7]	auto[0]	auto[1]	396	1			T12	3		T14	5		T16	9
all_values[7]	auto[1]	auto[0]	53935	1			T1	39		T2	7		T4	22
all_values[7]	auto[1]	auto[1]	313	1			T17	1		T14	3		T252	1
all_values[8]	auto[0]	auto[0]	41244	1			T1	32		T4	19		T8	4
all_values[8]	auto[0]	auto[1]	18624	1			T1	53		T4	3		T6	2
all_values[8]	auto[1]	auto[0]	45719	1			T1	8		T2	7		T5	7
all_values[8]	auto[1]	auto[1]	17407	1			T1	2		T2	2		T3	10