Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
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Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv



Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 22 0 22 100.00


Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dir 2 0 2 100.00 100 1 1 0
cp_rst_pos 11 0 11 100.00 100 1 1 0


Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
uart_reset_cg_cc 22 0 22 100.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] 2517 1 T1 1 T2 1 T3 1
auto[UartRx] 2517 1 T1 1 T2 1 T3 1



Summary for Variable cp_rst_pos

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for cp_rst_pos

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4460 1 T1 2 T2 2 T3 2
values[1] 51 1 T21 2 T18 2 T23 1
values[2] 62 1 T17 1 T35 1 T100 2
values[3] 45 1 T21 1 T17 1 T23 2
values[4] 54 1 T17 1 T14 1 T18 1
values[5] 47 1 T18 1 T78 1 T100 1
values[6] 61 1 T15 1 T23 1 T35 1
values[7] 51 1 T17 1 T23 1 T35 2
values[8] 63 1 T12 1 T25 1 T14 1
values[9] 47 1 T12 1 T21 2 T15 1
values[10] 57 1 T17 1 T15 1 T23 1



Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 22 0 22 100.00


Automatically Generated Cross Bins for uart_reset_cg_cc

Bins
cp_dircp_rst_posCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] values[0] 2321 1 T1 1 T2 1 T3 1
auto[UartTx] values[1] 18 1 T21 1 T99 1 T279 1
auto[UartTx] values[2] 23 1 T100 1 T24 1 T102 1
auto[UartTx] values[3] 18 1 T17 1 T23 1 T110 1
auto[UartTx] values[4] 17 1 T18 1 T23 1 T99 1
auto[UartTx] values[5] 19 1 T18 1 T78 1 T112 1
auto[UartTx] values[6] 18 1 T99 1 T101 1 T229 1
auto[UartTx] values[7] 17 1 T100 1 T112 1 T111 1
auto[UartTx] values[8] 22 1 T14 1 T15 1 T23 1
auto[UartTx] values[9] 17 1 T21 1 T20 1 T112 1
auto[UartTx] values[10] 11 1 T110 2 T194 1 T327 1
auto[UartRx] values[0] 2139 1 T1 1 T2 1 T3 1
auto[UartRx] values[1] 33 1 T21 1 T18 2 T23 1
auto[UartRx] values[2] 39 1 T17 1 T35 1 T100 1
auto[UartRx] values[3] 27 1 T21 1 T23 1 T35 1
auto[UartRx] values[4] 37 1 T17 1 T14 1 T23 1
auto[UartRx] values[5] 28 1 T100 1 T300 1 T279 1
auto[UartRx] values[6] 43 1 T15 1 T23 1 T35 1
auto[UartRx] values[7] 34 1 T17 1 T23 1 T35 2
auto[UartRx] values[8] 41 1 T12 1 T25 1 T15 1
auto[UartRx] values[9] 30 1 T12 1 T21 1 T15 1
auto[UartRx] values[10] 46 1 T17 1 T15 1 T23 1

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