Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2267	1			T1	1		T2	1		T3	1
auto[BaudRate115200]	2018	1			T1	3		T2	1		T4	1
auto[BaudRate230400]	2062	1			T1	2		T2	1		T6	1
auto[BaudRate128Kbps]	2046	1			T3	1		T4	1		T5	2
auto[BaudRate256Kbps]	2175	1			T1	1		T4	1		T5	1
auto[BaudRate1Mbps]	1919	1			T2	1		T4	3		T5	4
auto[BaudRate1p5Mbps]	1287	1			T2	1		T8	2		T10	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1294	1			T39	5		T19	22		T126	8
freqs[25]	1403	1			T3	2		T25	10		T21	47
freqs[48]	852	1			T38	12		T116	6		T34	19
freqs[50]	523	1			T41	5		T42	10		T77	10
freqs[100]	1141	1			T6	2		T10	6		T40	8

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	173	1			T19	4		T281	1		T142	1
auto[BaudRate9600]	freqs[25]	256	1			T3	1		T25	2		T21	4
auto[BaudRate9600]	freqs[48]	114	1			T38	1		T34	1		T35	4
auto[BaudRate9600]	freqs[50]	72	1			T77	3		T119	3		T284	4
auto[BaudRate9600]	freqs[100]	202	1			T40	1		T18	2		T23	4
auto[BaudRate115200]	freqs[24]	190	1			T19	5		T126	4		T281	1
auto[BaudRate115200]	freqs[25]	170	1			T25	2		T21	4		T90	3
auto[BaudRate115200]	freqs[48]	106	1			T38	1		T116	2		T34	2
auto[BaudRate115200]	freqs[50]	68	1			T42	1		T77	2		T16	1
auto[BaudRate115200]	freqs[100]	161	1			T10	1		T40	1		T22	6
auto[BaudRate230400]	freqs[24]	199	1			T19	4		T281	1		T150	4
auto[BaudRate230400]	freqs[25]	212	1			T21	17		T47	3		T90	1
auto[BaudRate230400]	freqs[48]	115	1			T38	3		T34	4		T35	11
auto[BaudRate230400]	freqs[50]	72	1			T42	1		T77	1		T264	5
auto[BaudRate230400]	freqs[100]	145	1			T6	1		T10	2		T23	4
auto[BaudRate128Kbps]	freqs[24]	206	1			T19	1		T150	1		T306	1
auto[BaudRate128Kbps]	freqs[25]	187	1			T3	1		T25	2		T21	7
auto[BaudRate128Kbps]	freqs[48]	144	1			T38	3		T34	5		T35	7
auto[BaudRate128Kbps]	freqs[50]	84	1			T41	1		T42	2		T77	1
auto[BaudRate128Kbps]	freqs[100]	154	1			T10	1		T40	2		T18	1
auto[BaudRate256Kbps]	freqs[24]	209	1			T39	1		T19	4		T126	1
auto[BaudRate256Kbps]	freqs[25]	244	1			T25	1		T21	6		T47	1
auto[BaudRate256Kbps]	freqs[48]	115	1			T38	1		T116	1		T34	4
auto[BaudRate256Kbps]	freqs[50]	71	1			T41	2		T42	1		T77	1
auto[BaudRate256Kbps]	freqs[100]	147	1			T6	1		T10	1		T40	1
auto[BaudRate1Mbps]	freqs[24]	206	1			T39	2		T19	3		T126	2
auto[BaudRate1Mbps]	freqs[25]	243	1			T25	3		T21	7		T47	3
auto[BaudRate1Mbps]	freqs[48]	141	1			T38	1		T116	2		T34	1
auto[BaudRate1Mbps]	freqs[50]	77	1			T42	4		T77	1		T264	1
auto[BaudRate1Mbps]	freqs[100]	158	1			T40	2		T22	3		T18	2
auto[BaudRate1p5Mbps]	freqs[25]	91	1			T21	2		T47	1		T90	2
auto[BaudRate1p5Mbps]	freqs[48]	117	1			T38	2		T116	1		T34	2
auto[BaudRate1p5Mbps]	freqs[50]	79	1			T41	2		T42	1		T77	1
auto[BaudRate1p5Mbps]	freqs[100]	174	1			T10	1		T40	1		T22	9

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded