Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32839551	1			T1	191		T2	18		T3	18
all_levels[1]	201576	1			T1	67		T2	2		T5	10
all_levels[2]	2560	1			T1	10		T2	2		T5	2
all_levels[3]	1037	1			T1	1		T2	1		T5	1
all_levels[4]	736	1			T1	4		T5	3		T25	2
all_levels[5]	542	1			T1	1		T4	1		T5	3
all_levels[6]	453	1			T1	2		T5	1		T9	1
all_levels[7]	357	1			T1	2		T9	2		T25	1
all_levels[8]	332	1			T1	1		T5	1		T8	1
all_levels[9]	259	1			T1	1		T12	1		T17	1
all_levels[10]	243	1			T1	1		T9	1		T40	1
all_levels[11]	189	1			T1	1		T17	1		T116	1
all_levels[12]	205	1			T9	3		T21	1		T19	1
all_levels[13]	154	1			T8	1		T9	1		T21	2
all_levels[14]	145	1			T1	1		T9	1		T36	1
all_levels[15]	138	1			T9	1		T17	2		T23	1
all_levels[16]	93	1			T9	1		T21	1		T23	3
all_levels[17]	99	1			T8	1		T9	2		T12	1
all_levels[18]	122	1			T8	1		T9	2		T23	3
all_levels[19]	87	1			T8	2		T9	1		T90	1
all_levels[20]	84	1			T9	1		T17	1		T23	1
all_levels[21]	60	1			T4	1		T21	1		T47	1
all_levels[22]	51	1			T23	4		T34	1		T117	1
all_levels[23]	84	1			T9	3		T118	3		T23	3
all_levels[24]	71	1			T119	1		T120	1		T121	1
all_levels[25]	44	1			T17	1		T14	1		T23	1
all_levels[26]	54	1			T19	1		T122	1		T119	1
all_levels[27]	38	1			T123	1		T124	1		T125	1
all_levels[28]	43	1			T25	1		T14	1		T122	1
all_levels[29]	32	1			T14	1		T19	1		T117	1
all_levels[30]	47	1			T9	1		T126	1		T127	1
all_levels[31]	36	1			T4	1		T17	1		T23	1
all_levels[32]	35	1			T23	1		T128	1		T129	1
all_levels[33]	39	1			T25	2		T23	1		T47	1
all_levels[34]	36	1			T9	1		T130	1		T131	1
all_levels[35]	28	1			T14	1		T23	2		T34	1
all_levels[36]	37	1			T46	1		T128	1		T132	1
all_levels[37]	34	1			T47	1		T101	1		T128	1
all_levels[38]	24	1			T131	1		T107	1		T133	5
all_levels[39]	29	1			T107	1		T134	1		T125	1
all_levels[40]	28	1			T4	1		T17	1		T47	1
all_levels[41]	20	1			T9	1		T131	1		T135	1
all_levels[42]	19	1			T9	1		T23	1		T34	1
all_levels[43]	7	1			T136	1		T137	1		T138	1
all_levels[44]	18	1			T117	1		T132	1		T139	1
all_levels[45]	17	1			T24	2		T140	1		T101	1
all_levels[46]	14	1			T122	1		T124	1		T128	1
all_levels[47]	20	1			T124	1		T141	1		T48	1
all_levels[48]	28	1			T4	3		T21	1		T127	1
all_levels[49]	17	1			T142	1		T143	1		T144	1
all_levels[50]	9	1			T14	1		T145	1		T146	1
all_levels[51]	12	1			T21	1		T14	1		T96	1
all_levels[52]	8	1			T147	1		T148	1		T149	1
all_levels[53]	18	1			T12	1		T150	1		T151	1
all_levels[54]	9	1			T131	1		T152	1		T153	1
all_levels[55]	9	1			T124	1		T154	1		T155	1
all_levels[56]	13	1			T134	1		T156	1		T157	1
all_levels[57]	6	1			T143	1		T158	1		T159	1
all_levels[58]	6	1			T123	1		T160	1		T161	2
all_levels[59]	6	1			T162	2		T163	1		T164	1
all_levels[60]	6	1			T14	1		T165	1		T166	1
all_levels[61]	8	1			T155	1		T167	1		T168	1
all_levels[62]	13	1			T21	1		T150	1		T169	1
all_levels[63]	6	1			T145	2		T162	1		T170	1
all_levels[64]	105	1			T4	1		T8	2		T12	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33045226

1

T1

279

T2

23

T4

14

auto[1]

4980

1

T1

4

T3

18

T4

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61] , all_levels[62] , all_levels[63]]	[auto[1]]	--	--	4

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32835117	1			T1	188		T2	18		T4	7
all_levels[0]	auto[1]	4434	1			T1	3		T3	18		T4	5
all_levels[1]	auto[0]	201479	1			T1	67		T2	2		T5	10
all_levels[1]	auto[1]	97	1			T12	2		T36	1		T77	2
all_levels[2]	auto[0]	2543	1			T1	10		T2	2		T5	2
all_levels[2]	auto[1]	17	1			T129	2		T171	1		T172	1
all_levels[3]	auto[0]	1019	1			T1	1		T2	1		T5	1
all_levels[3]	auto[1]	18	1			T106	1		T173	1		T174	1
all_levels[4]	auto[0]	706	1			T1	4		T5	3		T25	2
all_levels[4]	auto[1]	30	1			T20	2		T175	1		T176	2
all_levels[5]	auto[0]	532	1			T1	1		T4	1		T5	3
all_levels[5]	auto[1]	10	1			T96	1		T177	1		T178	1
all_levels[6]	auto[0]	428	1			T1	2		T5	1		T9	1
all_levels[6]	auto[1]	25	1			T46	1		T127	1		T154	2
all_levels[7]	auto[0]	339	1			T1	1		T9	2		T25	1
all_levels[7]	auto[1]	18	1			T1	1		T179	1		T180	1
all_levels[8]	auto[0]	311	1			T1	1		T5	1		T8	1
all_levels[8]	auto[1]	21	1			T46	1		T156	1		T181	1
all_levels[9]	auto[0]	250	1			T1	1		T12	1		T17	1
all_levels[9]	auto[1]	9	1			T182	3		T141	1		T183	1
all_levels[10]	auto[0]	224	1			T1	1		T9	1		T40	1
all_levels[10]	auto[1]	19	1			T117	5		T176	1		T184	2
all_levels[11]	auto[0]	174	1			T1	1		T17	1		T116	1
all_levels[11]	auto[1]	15	1			T173	1		T185	1		T174	2
all_levels[12]	auto[0]	175	1			T9	3		T21	1		T19	1
all_levels[12]	auto[1]	30	1			T106	1		T24	15		T186	2
all_levels[13]	auto[0]	146	1			T8	1		T9	1		T21	2
all_levels[13]	auto[1]	8	1			T187	2		T188	1		T189	3
all_levels[14]	auto[0]	136	1			T1	1		T9	1		T36	1
all_levels[14]	auto[1]	9	1			T190	2		T191	2		T192	1
all_levels[15]	auto[0]	130	1			T9	1		T17	2		T23	1
all_levels[15]	auto[1]	8	1			T106	2		T193	1		T194	1
all_levels[16]	auto[0]	89	1			T9	1		T21	1		T23	3
all_levels[16]	auto[1]	4	1			T195	1		T196	2		T197	1
all_levels[17]	auto[0]	91	1			T8	1		T9	2		T12	1
all_levels[17]	auto[1]	8	1			T127	3		T198	1		T199	2
all_levels[18]	auto[0]	98	1			T8	1		T9	1		T23	3
all_levels[18]	auto[1]	24	1			T9	1		T46	2		T182	1
all_levels[19]	auto[0]	78	1			T8	2		T9	1		T90	1
all_levels[19]	auto[1]	9	1			T151	2		T200	2		T201	1
all_levels[20]	auto[0]	81	1			T9	1		T17	1		T23	1
all_levels[20]	auto[1]	3	1			T195	1		T201	1		T202	1
all_levels[21]	auto[0]	55	1			T4	1		T21	1		T47	1
all_levels[21]	auto[1]	5	1			T203	1		T204	3		T205	1
all_levels[22]	auto[0]	49	1			T23	4		T34	1		T117	1
all_levels[22]	auto[1]	2	1			T151	1		T196	1		-	-
all_levels[23]	auto[0]	69	1			T9	1		T118	1		T23	3
all_levels[23]	auto[1]	15	1			T9	2		T118	2		T175	1
all_levels[24]	auto[0]	60	1			T119	1		T120	1		T121	1
all_levels[24]	auto[1]	11	1			T206	2		T207	1		T208	1
all_levels[25]	auto[0]	40	1			T17	1		T14	1		T23	1
all_levels[25]	auto[1]	4	1			T182	1		T145	1		T209	1
all_levels[26]	auto[0]	47	1			T19	1		T122	1		T119	1
all_levels[26]	auto[1]	7	1			T210	1		T211	1		T212	1
all_levels[27]	auto[0]	31	1			T123	1		T124	1		T125	1
all_levels[27]	auto[1]	7	1			T158	1		T213	1		T214	2
all_levels[28]	auto[0]	38	1			T25	1		T14	1		T122	1
all_levels[28]	auto[1]	5	1			T167	1		T215	2		T216	2
all_levels[29]	auto[0]	28	1			T14	1		T19	1		T117	1
all_levels[29]	auto[1]	4	1			T179	1		T217	1		T218	2
all_levels[30]	auto[0]	42	1			T9	1		T126	1		T127	1
all_levels[30]	auto[1]	5	1			T219	2		T168	1		T220	1
all_levels[31]	auto[0]	35	1			T4	1		T17	1		T23	1
all_levels[31]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[32]	auto[0]	33	1			T23	1		T128	1		T129	1
all_levels[32]	auto[1]	2	1			T222	1		T223	1		-	-
all_levels[33]	auto[0]	35	1			T25	1		T23	1		T47	1
all_levels[33]	auto[1]	4	1			T25	1		T117	1		T224	1
all_levels[34]	auto[0]	26	1			T9	1		T130	1		T131	1
all_levels[34]	auto[1]	10	1			T129	2		T225	2		T226	3
all_levels[35]	auto[0]	27	1			T14	1		T23	2		T34	1
all_levels[35]	auto[1]	1	1			T190	1		-	-		-	-
all_levels[36]	auto[0]	32	1			T46	1		T128	1		T132	1
all_levels[36]	auto[1]	5	1			T227	1		T151	2		T228	2
all_levels[37]	auto[0]	34	1			T47	1		T101	1		T128	1
all_levels[38]	auto[0]	19	1			T131	1		T107	1		T133	1
all_levels[38]	auto[1]	5	1			T133	4		T221	1		-	-
all_levels[39]	auto[0]	25	1			T107	1		T134	1		T125	1
all_levels[39]	auto[1]	4	1			T229	1		T207	1		T230	2
all_levels[40]	auto[0]	23	1			T4	1		T17	1		T47	1
all_levels[40]	auto[1]	5	1			T172	2		T231	3		-	-
all_levels[41]	auto[0]	18	1			T9	1		T131	1		T135	1
all_levels[41]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[42]	auto[0]	19	1			T9	1		T23	1		T34	1
all_levels[43]	auto[0]	5	1			T136	1		T137	1		T138	1
all_levels[43]	auto[1]	2	1			T234	2		-	-		-	-
all_levels[44]	auto[0]	14	1			T117	1		T132	1		T139	1
all_levels[44]	auto[1]	4	1			T235	2		T236	1		T237	1
all_levels[45]	auto[0]	14	1			T24	1		T140	1		T101	1
all_levels[45]	auto[1]	3	1			T24	1		T135	2		-	-
all_levels[46]	auto[0]	13	1			T122	1		T124	1		T128	1
all_levels[46]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[47]	auto[0]	10	1			T124	1		T141	1		T48	1
all_levels[47]	auto[1]	10	1			T239	5		T216	4		T240	1
all_levels[48]	auto[0]	17	1			T4	2		T21	1		T127	1
all_levels[48]	auto[1]	11	1			T4	1		T241	2		T242	2
all_levels[49]	auto[0]	16	1			T142	1		T143	1		T144	1
all_levels[49]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[50]	auto[0]	8	1			T14	1		T145	1		T146	1
all_levels[50]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[51]	auto[0]	10	1			T21	1		T14	1		T96	1
all_levels[51]	auto[1]	2	1			T137	1		T245	1		-	-
all_levels[52]	auto[0]	8	1			T147	1		T148	1		T149	1
all_levels[53]	auto[0]	11	1			T12	1		T150	1		T151	1
all_levels[53]	auto[1]	7	1			T246	2		T247	2		T248	3
all_levels[54]	auto[0]	9	1			T131	1		T152	1		T153	1
all_levels[55]	auto[0]	8	1			T124	1		T154	1		T155	1
all_levels[55]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[56]	auto[0]	12	1			T134	1		T156	1		T157	1
all_levels[56]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[57]	auto[0]	6	1			T143	1		T158	1		T159	1
all_levels[58]	auto[0]	5	1			T123	1		T160	1		T161	1
all_levels[58]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[59]	auto[0]	5	1			T162	2		T163	1		T164	1
all_levels[59]	auto[1]	1	1			T251	1		-	-		-	-
all_levels[60]	auto[0]	6	1			T14	1		T165	1		T166	1
all_levels[61]	auto[0]	8	1			T155	1		T167	1		T168	1
all_levels[62]	auto[0]	13	1			T21	1		T150	1		T169	1
all_levels[63]	auto[0]	6	1			T145	2		T162	1		T170	1
all_levels[64]	auto[0]	91	1			T4	1		T8	1		T12	1
all_levels[64]	auto[1]	14	1			T8	1		T190	2		T229	1