Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	122994	1			T1	95		T2	9		T3	10
all_pins[1]	122994	1			T1	95		T2	9		T3	10
all_pins[2]	122994	1			T1	95		T2	9		T3	10
all_pins[3]	122994	1			T1	95		T2	9		T3	10
all_pins[4]	122994	1			T1	95		T2	9		T3	10
all_pins[5]	122994	1			T1	95		T2	9		T3	10
all_pins[6]	122994	1			T1	95		T2	9		T3	10
all_pins[7]	122994	1			T1	95		T2	9		T3	10
all_pins[8]	122994	1			T1	95		T2	9		T3	10

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1059422	1			T1	833		T2	77		T3	70
values[0x1]	47524	1			T1	22		T2	4		T3	20
transitions[0x0=>0x1]	38277	1			T1	22		T2	3		T3	10
transitions[0x1=>0x0]	38063	1			T1	22		T2	2		T3	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99189	1			T1	76		T2	7		T4	22
all_pins[0]	values[0x1]	23805	1			T1	19		T2	2		T3	10
all_pins[0]	transitions[0x0=>0x1]	23224	1			T1	19		T2	2		T3	10
all_pins[0]	transitions[0x1=>0x0]	891	1			T41	14		T12	1		T25	5
all_pins[1]	values[0x0]	121522	1			T1	95		T2	9		T3	10
all_pins[1]	values[0x1]	1472	1			T41	14		T12	1		T25	5
all_pins[1]	transitions[0x0=>0x1]	1379	1			T41	14		T12	1		T25	5
all_pins[1]	transitions[0x1=>0x0]	2555	1			T1	1		T4	2		T5	5
all_pins[2]	values[0x0]	120346	1			T1	94		T2	9		T3	10
all_pins[2]	values[0x1]	2648	1			T1	1		T4	2		T5	5
all_pins[2]	transitions[0x0=>0x1]	2572	1			T1	1		T4	1		T5	5
all_pins[2]	transitions[0x1=>0x0]	224	1			T12	2		T77	1		T14	3
all_pins[3]	values[0x0]	122694	1			T1	95		T2	9		T3	10
all_pins[3]	values[0x1]	300	1			T4	1		T12	2		T77	1
all_pins[3]	transitions[0x0=>0x1]	256	1			T4	1		T77	1		T14	2
all_pins[3]	transitions[0x1=>0x0]	415	1			T12	2		T14	5		T15	4
all_pins[4]	values[0x0]	122535	1			T1	95		T2	9		T3	10
all_pins[4]	values[0x1]	459	1			T12	4		T14	7		T15	4
all_pins[4]	transitions[0x0=>0x1]	390	1			T12	4		T14	6		T15	3
all_pins[4]	transitions[0x1=>0x0]	149	1			T14	1		T78	2		T112	2
all_pins[5]	values[0x0]	122776	1			T1	95		T2	9		T3	10
all_pins[5]	values[0x1]	218	1			T14	2		T15	1		T78	3
all_pins[5]	transitions[0x0=>0x1]	189	1			T14	2		T15	1		T78	3
all_pins[5]	transitions[0x1=>0x0]	780	1			T8	1		T12	1		T116	2
all_pins[6]	values[0x0]	122185	1			T1	95		T2	9		T3	10
all_pins[6]	values[0x1]	809	1			T8	1		T12	1		T116	2
all_pins[6]	transitions[0x0=>0x1]	774	1			T8	1		T12	1		T116	2
all_pins[6]	transitions[0x1=>0x0]	278	1			T17	1		T14	2		T252	1
all_pins[7]	values[0x0]	122681	1			T1	95		T2	9		T3	10
all_pins[7]	values[0x1]	313	1			T17	1		T14	3		T252	1
all_pins[7]	transitions[0x0=>0x1]	162	1			T14	1		T78	1		T24	1
all_pins[7]	transitions[0x1=>0x0]	17349	1			T1	2		T2	2		T3	10
all_pins[8]	values[0x0]	105494	1			T1	93		T2	7		T4	22
all_pins[8]	values[0x1]	17500	1			T1	2		T2	2		T3	10
all_pins[8]	transitions[0x0=>0x1]	9331	1			T1	2		T2	1		T5	2
all_pins[8]	transitions[0x1=>0x0]	15422	1			T1	19		T4	1		T5	4