Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7893839	1			T1	167		T2	4		T3	18
all_levels[1]	2373889	1			T1	3		T4	5		T5	51
all_levels[2]	442166	1			T1	4		T5	9		T10	3463
all_levels[3]	231456	1			T1	2		T5	13		T10	3442
all_levels[4]	276739	1			T1	5		T4	1		T5	5
all_levels[5]	249887	1			T1	5		T9	1		T10	3454
all_levels[6]	228244	1			T1	3		T10	3461		T41	184
all_levels[7]	517487	1			T1	2		T8	11		T9	1
all_levels[8]	432039	1			T1	3		T10	3466		T41	184
all_levels[9]	206652	1			T1	5		T8	2		T10	3405
all_levels[10]	230703	1			T1	3		T10	3446		T41	185
all_levels[11]	218607	1			T1	2		T5	35		T10	3465
all_levels[12]	364098	1			T1	2		T10	169771		T41	184
all_levels[13]	431990	1			T1	5		T8	3		T10	3456
all_levels[14]	212320	1			T1	4		T8	1		T9	2
all_levels[15]	234037	1			T1	2		T9	7		T10	3463
all_levels[16]	241816	1			T1	3		T10	3457		T41	185
all_levels[17]	192154	1			T1	2		T5	4		T8	2
all_levels[18]	245605	1			T1	2		T9	4		T10	3459
all_levels[19]	585916	1			T1	3		T5	47		T8	4
all_levels[20]	195984	1			T1	3		T4	3		T10	3440
all_levels[21]	408163	1			T1	2		T10	4344		T41	185
all_levels[22]	809889	1			T1	5		T9	2		T10	2364
all_levels[23]	247937	1			T1	13		T2	5		T10	2391
all_levels[24]	266545	1			T1	2		T2	1		T10	2369
all_levels[25]	195131	1			T1	4		T2	1		T10	2391
all_levels[26]	400561	1			T1	3		T10	2389		T41	185
all_levels[27]	331960	1			T1	3		T5	3		T9	6
all_levels[28]	681673	1			T2	2		T5	2		T9	1
all_levels[29]	284682	1			T5	1		T10	2390		T41	185
all_levels[30]	293065	1			T2	2		T5	4		T10	2391
all_levels[31]	552207	1			T5	5		T9	1		T10	7952
all_levels[32]	12572335	1			T1	25		T2	8		T5	64

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33045226

1

T1

279

T2

23

T4

14

auto[1]

4550

1

T1

8

T3

18

T4

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7891182	1			T1	162		T2	4		T4	9
all_levels[0]	auto[1]	2657	1			T1	5		T3	18		T4	3
all_levels[1]	auto[0]	2373634	1			T1	3		T4	2		T5	51
all_levels[1]	auto[1]	255	1			T4	3		T36	2		T77	1
all_levels[2]	auto[0]	442139	1			T1	4		T5	9		T10	3463
all_levels[2]	auto[1]	27	1			T261	1		T279	1		T294	1
all_levels[3]	auto[0]	231330	1			T1	2		T5	13		T10	3442
all_levels[3]	auto[1]	126	1			T271	1		T131	1		T24	2
all_levels[4]	auto[0]	276710	1			T1	5		T4	1		T5	5
all_levels[4]	auto[1]	29	1			T329	1		T330	1		T331	1
all_levels[5]	auto[0]	249852	1			T1	5		T9	1		T10	3454
all_levels[5]	auto[1]	35	1			T119	2		T294	1		T191	1
all_levels[6]	auto[0]	228213	1			T1	3		T10	3461		T41	184
all_levels[6]	auto[1]	31	1			T38	1		T77	1		T90	2
all_levels[7]	auto[0]	517331	1			T1	2		T8	10		T9	1
all_levels[7]	auto[1]	156	1			T8	1		T270	1		T172	1
all_levels[8]	auto[0]	432006	1			T1	3		T10	3466		T41	184
all_levels[8]	auto[1]	33	1			T36	1		T118	2		T35	1
all_levels[9]	auto[0]	206627	1			T1	5		T8	2		T10	3405
all_levels[9]	auto[1]	25	1			T175	1		T193	1		T332	1
all_levels[10]	auto[0]	230661	1			T1	3		T10	3446		T41	185
all_levels[10]	auto[1]	42	1			T106	1		T24	14		T301	1
all_levels[11]	auto[0]	218585	1			T1	2		T5	35		T10	3465
all_levels[11]	auto[1]	22	1			T77	2		T127	1		T333	2
all_levels[12]	auto[0]	364078	1			T1	2		T10	169771		T41	184
all_levels[12]	auto[1]	20	1			T332	2		T310	1		T334	1
all_levels[13]	auto[0]	431942	1			T1	5		T8	2		T10	3456
all_levels[13]	auto[1]	48	1			T8	1		T14	1		T93	1
all_levels[14]	auto[0]	212293	1			T1	4		T8	1		T9	2
all_levels[14]	auto[1]	27	1			T126	1		T335	1		T336	1
all_levels[15]	auto[0]	233905	1			T1	2		T9	5		T10	3463
all_levels[15]	auto[1]	132	1			T9	2		T44	8		T35	8
all_levels[16]	auto[0]	241794	1			T1	3		T10	3457		T41	185
all_levels[16]	auto[1]	22	1			T175	2		T101	1		T337	1
all_levels[17]	auto[0]	192131	1			T1	2		T5	4		T8	2
all_levels[17]	auto[1]	23	1			T25	3		T175	1		T291	1
all_levels[18]	auto[0]	245587	1			T1	2		T9	4		T10	3459
all_levels[18]	auto[1]	18	1			T193	1		T173	1		T338	4
all_levels[19]	auto[0]	585894	1			T1	3		T5	47		T8	3
all_levels[19]	auto[1]	22	1			T8	1		T40	2		T18	1
all_levels[20]	auto[0]	195958	1			T1	3		T4	2		T10	3440
all_levels[20]	auto[1]	26	1			T4	1		T262	1		T20	1
all_levels[21]	auto[0]	408136	1			T1	2		T10	4344		T41	185
all_levels[21]	auto[1]	27	1			T43	1		T133	1		T339	1
all_levels[22]	auto[0]	809866	1			T1	5		T9	2		T10	2364
all_levels[22]	auto[1]	23	1			T117	3		T175	2		T292	1
all_levels[23]	auto[0]	247920	1			T1	12		T2	5		T10	2391
all_levels[23]	auto[1]	17	1			T1	1		T119	1		T105	1
all_levels[24]	auto[0]	266531	1			T1	2		T2	1		T10	2369
all_levels[24]	auto[1]	14	1			T182	1		T281	1		T190	1
all_levels[25]	auto[0]	195103	1			T1	4		T2	1		T10	2391
all_levels[25]	auto[1]	28	1			T118	3		T185	1		T340	2
all_levels[26]	auto[0]	400551	1			T1	3		T10	2389		T41	185
all_levels[26]	auto[1]	10	1			T341	1		T165	1		T342	1
all_levels[27]	auto[0]	331938	1			T1	3		T5	3		T9	5
all_levels[27]	auto[1]	22	1			T9	1		T98	1		T154	1
all_levels[28]	auto[0]	681645	1			T2	2		T5	2		T9	1
all_levels[28]	auto[1]	28	1			T19	1		T259	1		T24	1
all_levels[29]	auto[0]	284660	1			T5	1		T10	2390		T41	185
all_levels[29]	auto[1]	22	1			T46	1		T135	5		T132	1
all_levels[30]	auto[0]	293044	1			T2	2		T5	4		T10	2391
all_levels[30]	auto[1]	21	1			T316	2		T343	1		T225	2
all_levels[31]	auto[0]	552170	1			T5	5		T9	1		T10	7952
all_levels[31]	auto[1]	37	1			T101	1		T344	1		T172	2
all_levels[32]	auto[0]	12571810	1			T1	23		T2	8		T5	64
all_levels[32]	auto[1]	525	1			T1	2		T10	1		T39	1