Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	749	1			T12	4		T14	14		T15	4
all_values[1]	749	1			T12	4		T14	14		T15	4
all_values[2]	749	1			T12	4		T14	14		T15	4
all_values[3]	749	1			T12	4		T14	14		T15	4
all_values[4]	749	1			T12	4		T14	14		T15	4
all_values[5]	749	1			T12	4		T14	14		T15	4
all_values[6]	749	1			T12	4		T14	14		T15	4
all_values[7]	749	1			T12	4		T14	14		T15	4
all_values[8]	749	1			T12	4		T14	14		T15	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3643

1

T12

18

T14

61

T15

21

auto[1]

3098

1

T12

18

T14

65

T15

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2248

1

T12

9

T14

34

T15

16

auto[1]

4493

1

T12

27

T14

92

T15

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3977

1

T12

23

T14

64

T15

24

auto[1]

2764

1

T12

13

T14

62

T15

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	214	1			T12	2		T14	10		T15	2
all_values[0]	auto[0]	auto[1]	auto[1]	213	1			T12	2		T14	1		T15	2
all_values[0]	auto[1]	auto[0]	auto[1]	168	1			T14	2		T78	5		T100	1
all_values[0]	auto[1]	auto[1]	auto[1]	154	1			T14	1		T78	2		T100	1
all_values[1]	auto[0]	auto[0]	auto[0]	236	1			T12	1		T14	4		T15	2
all_values[1]	auto[0]	auto[1]	auto[0]	223	1			T12	1		T14	2		T15	1
all_values[1]	auto[1]	auto[0]	auto[1]	159	1			T12	1		T14	3		T15	1
all_values[1]	auto[1]	auto[1]	auto[1]	131	1			T12	1		T14	5		T78	1
all_values[2]	auto[0]	auto[0]	auto[0]	155	1			T14	1		T15	1		T78	4
all_values[2]	auto[0]	auto[0]	auto[1]	55	1			T110	2		T101	1		T111	2
all_values[2]	auto[0]	auto[1]	auto[0]	129	1			T12	1		T14	4		T15	2
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T12	1		T14	1		T112	2
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T12	1		T14	4		T15	1
all_values[2]	auto[1]	auto[1]	auto[1]	133	1			T12	1		T14	4		T78	3
all_values[3]	auto[0]	auto[0]	auto[0]	173	1			T14	1		T15	1		T78	6
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T12	1		T15	1		T24	2
all_values[3]	auto[0]	auto[1]	auto[0]	152	1			T14	3		T15	1		T78	3
all_values[3]	auto[0]	auto[1]	auto[1]	65	1			T12	1		T14	1		T78	2
all_values[3]	auto[1]	auto[0]	auto[1]	161	1			T12	1		T14	3		T78	1
all_values[3]	auto[1]	auto[1]	auto[1]	133	1			T12	1		T14	6		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	170	1			T14	1		T78	1		T112	3
all_values[4]	auto[0]	auto[0]	auto[1]	63	1			T14	1		T78	3		T100	1
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T14	2		T15	1		T78	4
all_values[4]	auto[0]	auto[1]	auto[1]	83	1			T12	1		T14	3		T100	2
all_values[4]	auto[1]	auto[0]	auto[1]	174	1			T12	1		T14	1		T15	3
all_values[4]	auto[1]	auto[1]	auto[1]	126	1			T12	2		T14	6		T78	3
all_values[5]	auto[0]	auto[0]	auto[0]	149	1			T12	1		T14	3		T78	2
all_values[5]	auto[0]	auto[0]	auto[1]	79	1			T14	2		T15	1		T78	1
all_values[5]	auto[0]	auto[1]	auto[0]	123	1			T12	3		T14	3		T15	1
all_values[5]	auto[0]	auto[1]	auto[1]	74	1			T78	2		T112	2		T24	2
all_values[5]	auto[1]	auto[0]	auto[1]	204	1			T14	3		T15	2		T78	3
all_values[5]	auto[1]	auto[1]	auto[1]	120	1			T14	3		T78	4		T110	4
all_values[6]	auto[0]	auto[0]	auto[0]	157	1			T12	1		T14	2		T78	5
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T12	1		T78	1		T112	2
all_values[6]	auto[0]	auto[1]	auto[0]	143	1			T14	3		T15	3		T78	4
all_values[6]	auto[0]	auto[1]	auto[1]	64	1			T14	2		T78	1		T112	1
all_values[6]	auto[1]	auto[0]	auto[1]	168	1			T14	3		T15	1		T78	3
all_values[6]	auto[1]	auto[1]	auto[1]	144	1			T12	2		T14	4		T78	1
all_values[7]	auto[0]	auto[0]	auto[0]	189	1			T12	1		T14	5		T78	4
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T12	2		T14	2		T78	1
all_values[7]	auto[0]	auto[1]	auto[0]	116	1			T15	3		T78	5		T100	1
all_values[7]	auto[0]	auto[1]	auto[1]	60	1			T110	3		T101	2		T111	3
all_values[7]	auto[1]	auto[0]	auto[1]	169	1			T12	1		T14	4		T15	1
all_values[7]	auto[1]	auto[1]	auto[1]	137	1			T14	3		T78	3		T112	2
all_values[8]	auto[0]	auto[0]	auto[1]	236	1			T12	2		T14	3		T15	2
all_values[8]	auto[0]	auto[1]	auto[1]	217	1			T12	1		T14	4		T78	4
all_values[8]	auto[1]	auto[0]	auto[1]	161	1			T12	1		T14	3		T15	2
all_values[8]	auto[1]	auto[1]	auto[1]	135	1			T14	4		T78	3		T100	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal