| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.12 | 99.10 | 97.65 | 100.00 | 98.38 | 100.00 | 99.57 |
| T1260 | /workspace/coverage/cover_reg_top/8.uart_intr_test.4146612013 | Jul 12 04:21:25 PM PDT 24 | Jul 12 04:21:28 PM PDT 24 | 45204301 ps | ||
| T1261 | /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2015387909 | Jul 12 04:22:23 PM PDT 24 | Jul 12 04:22:28 PM PDT 24 | 23119204 ps | ||
| T1262 | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2666826138 | Jul 12 04:21:07 PM PDT 24 | Jul 12 04:21:09 PM PDT 24 | 64871147 ps | ||
| T1263 | /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1351911738 | Jul 12 04:21:32 PM PDT 24 | Jul 12 04:21:35 PM PDT 24 | 64756456 ps | ||
| T115 | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1501075158 | Jul 12 04:16:29 PM PDT 24 | Jul 12 04:16:31 PM PDT 24 | 91807005 ps | ||
| T1264 | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1424441799 | Jul 12 04:16:07 PM PDT 24 | Jul 12 04:16:08 PM PDT 24 | 17855946 ps | ||
| T1265 | /workspace/coverage/cover_reg_top/11.uart_intr_test.1670617210 | Jul 12 04:21:51 PM PDT 24 | Jul 12 04:21:55 PM PDT 24 | 27339316 ps | ||
| T1266 | /workspace/coverage/cover_reg_top/46.uart_intr_test.2595896611 | Jul 12 04:21:45 PM PDT 24 | Jul 12 04:21:49 PM PDT 24 | 22489761 ps | ||
| T1267 | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2502214652 | Jul 12 04:16:04 PM PDT 24 | Jul 12 04:16:06 PM PDT 24 | 182340167 ps | ||
| T1268 | /workspace/coverage/cover_reg_top/14.uart_tl_errors.2812141775 | Jul 12 04:21:22 PM PDT 24 | Jul 12 04:21:25 PM PDT 24 | 67142242 ps | ||
| T1269 | /workspace/coverage/cover_reg_top/18.uart_intr_test.3601812804 | Jul 12 04:22:05 PM PDT 24 | Jul 12 04:22:08 PM PDT 24 | 13196587 ps | ||
| T1270 | /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2201278550 | Jul 12 04:21:14 PM PDT 24 | Jul 12 04:21:15 PM PDT 24 | 19510416 ps | ||
| T1271 | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3779476183 | Jul 12 04:21:48 PM PDT 24 | Jul 12 04:21:52 PM PDT 24 | 15058681 ps | ||
| T1272 | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1545956476 | Jul 12 04:18:09 PM PDT 24 | Jul 12 04:18:11 PM PDT 24 | 48510413 ps | ||
| T1273 | /workspace/coverage/cover_reg_top/26.uart_intr_test.3550369365 | Jul 12 04:20:00 PM PDT 24 | Jul 12 04:20:01 PM PDT 24 | 24112832 ps | ||
| T1274 | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.672549400 | Jul 12 04:21:52 PM PDT 24 | Jul 12 04:21:56 PM PDT 24 | 57511121 ps | ||
| T1275 | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3097281505 | Jul 12 04:22:09 PM PDT 24 | Jul 12 04:22:12 PM PDT 24 | 21690910 ps | ||
| T1276 | /workspace/coverage/cover_reg_top/16.uart_intr_test.744593787 | Jul 12 04:19:13 PM PDT 24 | Jul 12 04:19:14 PM PDT 24 | 14397747 ps | ||
| T1277 | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3729065588 | Jul 12 04:21:14 PM PDT 24 | Jul 12 04:21:15 PM PDT 24 | 40110342 ps | ||
| T1278 | /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3527627064 | Jul 12 04:20:32 PM PDT 24 | Jul 12 04:20:34 PM PDT 24 | 16237124 ps | ||
| T1279 | /workspace/coverage/cover_reg_top/21.uart_intr_test.848156192 | Jul 12 04:17:33 PM PDT 24 | Jul 12 04:17:34 PM PDT 24 | 12334015 ps | ||
| T1280 | /workspace/coverage/cover_reg_top/33.uart_intr_test.1455206414 | Jul 12 04:16:45 PM PDT 24 | Jul 12 04:16:46 PM PDT 24 | 146229681 ps | ||
| T1281 | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2404292968 | Jul 12 04:17:42 PM PDT 24 | Jul 12 04:17:43 PM PDT 24 | 37727485 ps | ||
| T59 | /workspace/coverage/cover_reg_top/19.uart_csr_rw.3467982401 | Jul 12 04:16:35 PM PDT 24 | Jul 12 04:16:36 PM PDT 24 | 38035642 ps | ||
| T1282 | /workspace/coverage/cover_reg_top/11.uart_csr_rw.1335429031 | Jul 12 04:16:52 PM PDT 24 | Jul 12 04:16:53 PM PDT 24 | 13726873 ps | ||
| T60 | /workspace/coverage/cover_reg_top/18.uart_csr_rw.3336542963 | Jul 12 04:18:37 PM PDT 24 | Jul 12 04:18:38 PM PDT 24 | 12546849 ps | ||
| T1283 | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3238502641 | Jul 12 04:21:28 PM PDT 24 | Jul 12 04:21:31 PM PDT 24 | 18517844 ps | ||
| T1284 | /workspace/coverage/cover_reg_top/18.uart_tl_errors.3129943367 | Jul 12 04:19:51 PM PDT 24 | Jul 12 04:19:53 PM PDT 24 | 354075933 ps | ||
| T1285 | /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.394030538 | Jul 12 04:16:08 PM PDT 24 | Jul 12 04:16:10 PM PDT 24 | 92101542 ps | ||
| T1286 | /workspace/coverage/cover_reg_top/12.uart_csr_rw.2663322384 | Jul 12 04:16:52 PM PDT 24 | Jul 12 04:16:53 PM PDT 24 | 12600824 ps | ||
| T1287 | /workspace/coverage/cover_reg_top/19.uart_intr_test.2544965356 | Jul 12 04:22:11 PM PDT 24 | Jul 12 04:22:15 PM PDT 24 | 21410907 ps | ||
| T1288 | /workspace/coverage/cover_reg_top/25.uart_intr_test.1301959394 | Jul 12 04:18:47 PM PDT 24 | Jul 12 04:18:49 PM PDT 24 | 17148218 ps | ||
| T61 | /workspace/coverage/cover_reg_top/8.uart_csr_rw.3069140364 | Jul 12 04:19:52 PM PDT 24 | Jul 12 04:19:53 PM PDT 24 | 14173519 ps | ||
| T1289 | /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.396964821 | Jul 12 04:22:43 PM PDT 24 | Jul 12 04:22:47 PM PDT 24 | 22269251 ps | ||
| T1290 | /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1067555832 | Jul 12 04:22:43 PM PDT 24 | Jul 12 04:22:47 PM PDT 24 | 22590943 ps | ||
| T62 | /workspace/coverage/cover_reg_top/6.uart_csr_rw.3134429450 | Jul 12 04:17:42 PM PDT 24 | Jul 12 04:17:43 PM PDT 24 | 13228933 ps | ||
| T68 | /workspace/coverage/cover_reg_top/2.uart_csr_rw.3069959914 | Jul 12 04:21:57 PM PDT 24 | Jul 12 04:22:00 PM PDT 24 | 48341981 ps | ||
| T1291 | /workspace/coverage/cover_reg_top/5.uart_csr_rw.3744963651 | Jul 12 04:20:01 PM PDT 24 | Jul 12 04:20:02 PM PDT 24 | 13926933 ps | ||
| T1292 | /workspace/coverage/cover_reg_top/6.uart_intr_test.3681504624 | Jul 12 04:16:43 PM PDT 24 | Jul 12 04:16:44 PM PDT 24 | 66995055 ps | ||
| T63 | /workspace/coverage/cover_reg_top/13.uart_csr_rw.3263478085 | Jul 12 04:21:18 PM PDT 24 | Jul 12 04:21:20 PM PDT 24 | 12478447 ps | ||
| T1293 | /workspace/coverage/cover_reg_top/4.uart_intr_test.692522242 | Jul 12 04:21:35 PM PDT 24 | Jul 12 04:21:38 PM PDT 24 | 12060818 ps | ||
| T1294 | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.333954090 | Jul 12 04:21:23 PM PDT 24 | Jul 12 04:21:26 PM PDT 24 | 81144983 ps | ||
| T64 | /workspace/coverage/cover_reg_top/10.uart_csr_rw.2797880871 | Jul 12 04:20:03 PM PDT 24 | Jul 12 04:20:05 PM PDT 24 | 18534020 ps | ||
| T1295 | /workspace/coverage/cover_reg_top/49.uart_intr_test.2554462366 | Jul 12 04:21:28 PM PDT 24 | Jul 12 04:21:31 PM PDT 24 | 20395178 ps | ||
| T1296 | /workspace/coverage/cover_reg_top/19.uart_tl_errors.2202865270 | Jul 12 04:21:47 PM PDT 24 | Jul 12 04:21:53 PM PDT 24 | 123375163 ps | ||
| T1297 | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2982368700 | Jul 12 04:15:56 PM PDT 24 | Jul 12 04:15:57 PM PDT 24 | 75278412 ps | ||
| T1298 | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2267707353 | Jul 12 04:21:59 PM PDT 24 | Jul 12 04:22:04 PM PDT 24 | 225100470 ps | ||
| T1299 | /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.775926391 | Jul 12 04:18:43 PM PDT 24 | Jul 12 04:18:44 PM PDT 24 | 92948158 ps | ||
| T1300 | /workspace/coverage/cover_reg_top/34.uart_intr_test.3952866576 | Jul 12 04:16:49 PM PDT 24 | Jul 12 04:16:50 PM PDT 24 | 48529000 ps | ||
| T1301 | /workspace/coverage/cover_reg_top/16.uart_csr_rw.722404447 | Jul 12 04:17:45 PM PDT 24 | Jul 12 04:17:46 PM PDT 24 | 54030829 ps | ||
| T1302 | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1972045911 | Jul 12 04:21:23 PM PDT 24 | Jul 12 04:21:26 PM PDT 24 | 148671250 ps | ||
| T1303 | /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1942667495 | Jul 12 04:17:33 PM PDT 24 | Jul 12 04:17:34 PM PDT 24 | 42083364 ps | ||
| T1304 | /workspace/coverage/cover_reg_top/6.uart_tl_errors.1912735514 | Jul 12 04:18:04 PM PDT 24 | Jul 12 04:18:07 PM PDT 24 | 211021796 ps | ||
| T1305 | /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3819259176 | Jul 12 04:21:14 PM PDT 24 | Jul 12 04:21:16 PM PDT 24 | 47041940 ps | ||
| T1306 | /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1618774687 | Jul 12 04:21:30 PM PDT 24 | Jul 12 04:21:34 PM PDT 24 | 52305568 ps | ||
| T1307 | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2673707381 | Jul 12 04:19:34 PM PDT 24 | Jul 12 04:19:36 PM PDT 24 | 74343208 ps | ||
| T1308 | /workspace/coverage/cover_reg_top/17.uart_intr_test.452932842 | Jul 12 04:21:28 PM PDT 24 | Jul 12 04:21:31 PM PDT 24 | 14563346 ps | ||
| T65 | /workspace/coverage/cover_reg_top/15.uart_csr_rw.1601640184 | Jul 12 04:21:49 PM PDT 24 | Jul 12 04:21:53 PM PDT 24 | 20375690 ps | ||
| T1309 | /workspace/coverage/cover_reg_top/4.uart_tl_errors.1449296051 | Jul 12 04:22:00 PM PDT 24 | Jul 12 04:22:04 PM PDT 24 | 65232465 ps | ||
| T1310 | /workspace/coverage/cover_reg_top/9.uart_intr_test.1979222859 | Jul 12 04:17:42 PM PDT 24 | Jul 12 04:17:43 PM PDT 24 | 31486461 ps | ||
| T1311 | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1963263851 | Jul 12 04:18:17 PM PDT 24 | Jul 12 04:18:18 PM PDT 24 | 43890966 ps |
| Test location | /workspace/coverage/default/147.uart_fifo_reset.3875609669 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 20188564847 ps |
| CPU time | 25.77 seconds |
| Started | Jul 12 04:41:05 PM PDT 24 |
| Finished | Jul 12 04:41:32 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-9106cfb2-6dc8-444f-84fc-484548c6f4fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875609669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3875609669 |
| Directory | /workspace/147.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3828909023 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 222669842557 ps |
| CPU time | 560.34 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:50:06 PM PDT 24 |
| Peak memory | 216356 kb |
| Host | smart-f9c0c004-9dcc-40e7-a8f7-d62f486d5010 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828909023 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3828909023 |
| Directory | /workspace/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2240943467 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 627256491982 ps |
| CPU time | 781.59 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:52:18 PM PDT 24 |
| Peak memory | 225872 kb |
| Host | smart-3b97b496-5db7-43ae-8a22-67e3688c7e8d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240943467 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2240943467 |
| Directory | /workspace/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.uart_long_xfer_wo_dly.1568114061 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 86886788290 ps |
| CPU time | 763.03 seconds |
| Started | Jul 12 04:40:00 PM PDT 24 |
| Finished | Jul 12 04:52:47 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-272336ea-0c3f-4a77-8708-6d150ac78550 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1568114061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1568114061 |
| Directory | /workspace/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all_with_rand_reset.4206245479 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 83089041438 ps |
| CPU time | 296.35 seconds |
| Started | Jul 12 04:39:23 PM PDT 24 |
| Finished | Jul 12 04:44:23 PM PDT 24 |
| Peak memory | 216400 kb |
| Host | smart-86d29cb0-7c38-4b1f-9b38-67c8a2737754 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206245479 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.4206245479 |
| Directory | /workspace/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all_with_rand_reset.898206047 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 155408245912 ps |
| CPU time | 416.79 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:46:57 PM PDT 24 |
| Peak memory | 215368 kb |
| Host | smart-ceff68b0-1e37-48d3-b7cd-8559fe3350b1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898206047 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.898206047 |
| Directory | /workspace/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2442258232 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 277834035201 ps |
| CPU time | 784.46 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:52:50 PM PDT 24 |
| Peak memory | 226856 kb |
| Host | smart-a2664983-b409-4d49-a293-c5d8ca63014d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442258232 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2442258232 |
| Directory | /workspace/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2136401661 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 94752393714 ps |
| CPU time | 771.34 seconds |
| Started | Jul 12 04:40:46 PM PDT 24 |
| Finished | Jul 12 04:53:38 PM PDT 24 |
| Peak memory | 227392 kb |
| Host | smart-c7a230bf-3ccd-42d7-91c4-4139f64656c2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136401661 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2136401661 |
| Directory | /workspace/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all.3411467336 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 340169016305 ps |
| CPU time | 143.89 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:42:10 PM PDT 24 |
| Peak memory | 216404 kb |
| Host | smart-affd2d9a-818b-4737-8195-58b9e9d1b6e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411467336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3411467336 |
| Directory | /workspace/25.uart_stress_all/latest |
| Test location | /workspace/coverage/default/0.uart_sec_cm.3875830234 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 121802479 ps |
| CPU time | 0.8 seconds |
| Started | Jul 12 04:38:16 PM PDT 24 |
| Finished | Jul 12 04:38:28 PM PDT 24 |
| Peak memory | 218124 kb |
| Host | smart-45482263-3c21-4aae-b534-5eeb74353522 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875830234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3875830234 |
| Directory | /workspace/0.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/268.uart_fifo_reset.3128984894 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 168567961248 ps |
| CPU time | 42.3 seconds |
| Started | Jul 12 04:41:42 PM PDT 24 |
| Finished | Jul 12 04:42:25 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-f1939834-6109-4297-a3da-f0fd77f3a843 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128984894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3128984894 |
| Directory | /workspace/268.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/222.uart_fifo_reset.270690822 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 195745989094 ps |
| CPU time | 204.08 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:44:43 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-dd53f65b-4d85-4531-b713-e67c66718346 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270690822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.270690822 |
| Directory | /workspace/222.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_perf.4118039238 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 20501351657 ps |
| CPU time | 587.12 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:48:54 PM PDT 24 |
| Peak memory | 200020 kb |
| Host | smart-f921a474-7b0e-4bc6-a7cc-d91e823b891d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4118039238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4118039238 |
| Directory | /workspace/13.uart_perf/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all.1299179000 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 280041945108 ps |
| CPU time | 646.09 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:51:09 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-a089a3d3-2a1e-40f3-9727-7ebb8f336d5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299179000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1299179000 |
| Directory | /workspace/45.uart_stress_all/latest |
| Test location | /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1849352179 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 105233150772 ps |
| CPU time | 380.15 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:47:18 PM PDT 24 |
| Peak memory | 216236 kb |
| Host | smart-f377c487-7f21-4a12-a4d2-d7204cb22a79 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849352179 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1849352179 |
| Directory | /workspace/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_rw.1390177090 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 11701692 ps |
| CPU time | 0.61 seconds |
| Started | Jul 12 04:18:26 PM PDT 24 |
| Finished | Jul 12 04:18:29 PM PDT 24 |
| Peak memory | 196372 kb |
| Host | smart-925a5cf7-db3e-4fd4-b243-1a177bdb836b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390177090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1390177090 |
| Directory | /workspace/4.uart_csr_rw/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all.2589041015 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 123217048271 ps |
| CPU time | 236.17 seconds |
| Started | Jul 12 04:39:15 PM PDT 24 |
| Finished | Jul 12 04:43:18 PM PDT 24 |
| Peak memory | 216316 kb |
| Host | smart-e8a8fd43-c3e3-46f3-87be-8998e5d08abc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589041015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2589041015 |
| Directory | /workspace/18.uart_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.529531846 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 92146166 ps |
| CPU time | 1.29 seconds |
| Started | Jul 12 04:21:31 PM PDT 24 |
| Finished | Jul 12 04:21:35 PM PDT 24 |
| Peak memory | 198624 kb |
| Host | smart-3feef895-52e8-4eec-b771-3e4edaaa2b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529531846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.529531846 |
| Directory | /workspace/10.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1387239506 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 77882370594 ps |
| CPU time | 287.76 seconds |
| Started | Jul 12 04:38:13 PM PDT 24 |
| Finished | Jul 12 04:43:12 PM PDT 24 |
| Peak memory | 216288 kb |
| Host | smart-15399182-38ab-4c58-9235-dd7edf27cdd4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387239506 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1387239506 |
| Directory | /workspace/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_full.2922119539 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 156734334593 ps |
| CPU time | 227.19 seconds |
| Started | Jul 12 04:40:13 PM PDT 24 |
| Finished | Jul 12 04:44:03 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-93e1484b-ee11-414f-8259-eb1d12bcf0cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922119539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2922119539 |
| Directory | /workspace/43.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/52.uart_stress_all_with_rand_reset.228189790 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 503807138403 ps |
| CPU time | 1761.2 seconds |
| Started | Jul 12 04:40:43 PM PDT 24 |
| Finished | Jul 12 05:10:06 PM PDT 24 |
| Peak memory | 216372 kb |
| Host | smart-6b8a9802-ae87-4d1a-93ab-0c345740b836 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228189790 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.228189790 |
| Directory | /workspace/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.uart_alert_test.222588841 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 11462171 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:38:32 PM PDT 24 |
| Finished | Jul 12 04:38:39 PM PDT 24 |
| Peak memory | 195488 kb |
| Host | smart-6d751d84-d403-4985-8f1d-ad53e6164f7f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222588841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.222588841 |
| Directory | /workspace/1.uart_alert_test/latest |
| Test location | /workspace/coverage/default/44.uart_noise_filter.2998531124 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 346855076522 ps |
| CPU time | 84.74 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:41:48 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-ea30fd48-455a-4287-be28-e9eceeaca229 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998531124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2998531124 |
| Directory | /workspace/44.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/104.uart_fifo_reset.3197481457 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 245938894014 ps |
| CPU time | 96.33 seconds |
| Started | Jul 12 04:40:55 PM PDT 24 |
| Finished | Jul 12 04:42:37 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-2d167d62-e15e-49f1-b8e0-b80f60d39fb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197481457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3197481457 |
| Directory | /workspace/104.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3929424775 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 241826980352 ps |
| CPU time | 496.79 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:47:31 PM PDT 24 |
| Peak memory | 224824 kb |
| Host | smart-4bcb5346-2dc6-43d8-820b-a389a45f4174 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929424775 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3929424775 |
| Directory | /workspace/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all.1719874786 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 403777299708 ps |
| CPU time | 93.53 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:41:37 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-cf0f36c4-8c4b-4a38-ae92-16f3aa2534e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719874786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1719874786 |
| Directory | /workspace/30.uart_stress_all/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2183787752 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 203181984337 ps |
| CPU time | 960.36 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:55:47 PM PDT 24 |
| Peak memory | 213984 kb |
| Host | smart-e0579d92-acb7-43ef-8079-176cf21e5757 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183787752 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2183787752 |
| Directory | /workspace/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/193.uart_fifo_reset.1965630552 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 68667343537 ps |
| CPU time | 66.35 seconds |
| Started | Jul 12 04:41:20 PM PDT 24 |
| Finished | Jul 12 04:42:28 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-3fdeb5c4-698d-4bf8-aebc-10a216141be8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965630552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1965630552 |
| Directory | /workspace/193.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all.1399922305 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 551620437823 ps |
| CPU time | 1031.16 seconds |
| Started | Jul 12 04:40:00 PM PDT 24 |
| Finished | Jul 12 04:57:15 PM PDT 24 |
| Peak memory | 208104 kb |
| Host | smart-00b9bbed-7a48-4f48-bd62-4b9e4e4670f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399922305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1399922305 |
| Directory | /workspace/39.uart_stress_all/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all.171961352 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 128481735341 ps |
| CPU time | 874.22 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:53:46 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-d3fed7a1-64c4-4012-94d5-a90ca7adb9c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171961352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.171961352 |
| Directory | /workspace/13.uart_stress_all/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_overflow.3993316908 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 85819967795 ps |
| CPU time | 126.75 seconds |
| Started | Jul 12 04:39:54 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-e90314d4-48b7-4395-88f9-304748c63621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993316908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3993316908 |
| Directory | /workspace/35.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2036645976 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1548536840787 ps |
| CPU time | 1358.78 seconds |
| Started | Jul 12 04:40:48 PM PDT 24 |
| Finished | Jul 12 05:03:28 PM PDT 24 |
| Peak memory | 224456 kb |
| Host | smart-dc1cde49-5f94-4057-9b56-9e3118008bf1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036645976 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2036645976 |
| Directory | /workspace/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.697896940 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 95048476 ps |
| CPU time | 1.29 seconds |
| Started | Jul 12 04:22:23 PM PDT 24 |
| Finished | Jul 12 04:22:28 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-e1f3071b-e5af-4579-b347-01800978190c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697896940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.697896940 |
| Directory | /workspace/18.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/100.uart_fifo_reset.2494916533 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 81457828611 ps |
| CPU time | 119.69 seconds |
| Started | Jul 12 04:40:55 PM PDT 24 |
| Finished | Jul 12 04:43:00 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-299ae2e9-5cdc-407c-82a3-fda1ac9492ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494916533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2494916533 |
| Directory | /workspace/100.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/42.uart_rx_parity_err.574159697 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 41524196543 ps |
| CPU time | 26.02 seconds |
| Started | Jul 12 04:40:14 PM PDT 24 |
| Finished | Jul 12 04:40:42 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-0b132ebc-dbe5-4c5e-bab9-58f093c520c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574159697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.574159697 |
| Directory | /workspace/42.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/204.uart_fifo_reset.1206691743 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 13547146824 ps |
| CPU time | 29.72 seconds |
| Started | Jul 12 04:41:17 PM PDT 24 |
| Finished | Jul 12 04:41:48 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-f2e8c721-df72-45d1-a8e7-942cbcebaa55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206691743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1206691743 |
| Directory | /workspace/204.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/240.uart_fifo_reset.1306607495 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 144198080940 ps |
| CPU time | 45.17 seconds |
| Started | Jul 12 04:41:32 PM PDT 24 |
| Finished | Jul 12 04:42:18 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-8ba2edd8-221e-4478-8a93-d6d9c29d44a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306607495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1306607495 |
| Directory | /workspace/240.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_full.1223931945 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 97996405118 ps |
| CPU time | 193.23 seconds |
| Started | Jul 12 04:40:26 PM PDT 24 |
| Finished | Jul 12 04:43:40 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-757721ea-b5f6-4c6a-871e-68fe86a7ff45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223931945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1223931945 |
| Directory | /workspace/46.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/172.uart_fifo_reset.4284782652 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 41256595150 ps |
| CPU time | 62.81 seconds |
| Started | Jul 12 04:41:12 PM PDT 24 |
| Finished | Jul 12 04:42:15 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-d61d7f5c-9ca4-4993-a9b4-2e2b15bbdb92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284782652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.4284782652 |
| Directory | /workspace/172.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/180.uart_fifo_reset.3628546286 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 20075642427 ps |
| CPU time | 21.51 seconds |
| Started | Jul 12 04:41:13 PM PDT 24 |
| Finished | Jul 12 04:41:35 PM PDT 24 |
| Peak memory | 200092 kb |
| Host | smart-e6449dc7-a87d-4092-b27f-a2bf70eb7bb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628546286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3628546286 |
| Directory | /workspace/180.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all.4256594259 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 370921858974 ps |
| CPU time | 170.52 seconds |
| Started | Jul 12 04:38:24 PM PDT 24 |
| Finished | Jul 12 04:41:23 PM PDT 24 |
| Peak memory | 215696 kb |
| Host | smart-1e0a2d50-6e8e-4e21-b7c2-b8775d5695d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256594259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4256594259 |
| Directory | /workspace/1.uart_stress_all/latest |
| Test location | /workspace/coverage/default/133.uart_fifo_reset.828428878 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 54515159139 ps |
| CPU time | 28.02 seconds |
| Started | Jul 12 04:41:05 PM PDT 24 |
| Finished | Jul 12 04:41:35 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-1ee88c87-197f-4a4f-94e3-1ebfd7ee6fc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=828428878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.828428878 |
| Directory | /workspace/133.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_reset.3724072031 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 66186586402 ps |
| CPU time | 112.01 seconds |
| Started | Jul 12 04:39:12 PM PDT 24 |
| Finished | Jul 12 04:41:11 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-f9d196e4-bdd0-46d8-a039-a68fc3792638 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724072031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3724072031 |
| Directory | /workspace/18.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/246.uart_fifo_reset.37931271 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 155363559145 ps |
| CPU time | 68.16 seconds |
| Started | Jul 12 04:41:35 PM PDT 24 |
| Finished | Jul 12 04:42:44 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-2d254ee2-476c-4049-8849-1372bbd4089d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37931271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.37931271 |
| Directory | /workspace/246.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/255.uart_fifo_reset.1581268893 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 25159960652 ps |
| CPU time | 29.12 seconds |
| Started | Jul 12 04:41:35 PM PDT 24 |
| Finished | Jul 12 04:42:06 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-96c31f4d-60ba-4b9d-8db1-8691dfda6251 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581268893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1581268893 |
| Directory | /workspace/255.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/265.uart_fifo_reset.2906766535 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 58971011658 ps |
| CPU time | 47.97 seconds |
| Started | Jul 12 04:41:35 PM PDT 24 |
| Finished | Jul 12 04:42:25 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-59984d5a-84aa-49fc-9542-2b25b0d90f45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906766535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2906766535 |
| Directory | /workspace/265.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_reset.2478987671 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 126217245700 ps |
| CPU time | 49.66 seconds |
| Started | Jul 12 04:38:49 PM PDT 24 |
| Finished | Jul 12 04:39:44 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-1dbd06a7-e287-460c-bf11-9a349c19669f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478987671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2478987671 |
| Directory | /workspace/5.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_reset.2471589058 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 54737185569 ps |
| CPU time | 79.36 seconds |
| Started | Jul 12 04:38:51 PM PDT 24 |
| Finished | Jul 12 04:40:15 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-b2a6e39d-4f12-4e5f-84c6-ff82f3e0b825 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471589058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2471589058 |
| Directory | /workspace/10.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/107.uart_fifo_reset.2264457893 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 36888941656 ps |
| CPU time | 14.78 seconds |
| Started | Jul 12 04:40:57 PM PDT 24 |
| Finished | Jul 12 04:41:16 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-76aa62fa-3b70-4761-a0ad-6fea0d2dc979 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264457893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2264457893 |
| Directory | /workspace/107.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/113.uart_fifo_reset.1514087371 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 86890139388 ps |
| CPU time | 62.36 seconds |
| Started | Jul 12 04:41:03 PM PDT 24 |
| Finished | Jul 12 04:42:07 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-7b12789c-4f79-4517-8d9f-2c573dd2eed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514087371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1514087371 |
| Directory | /workspace/113.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_long_xfer_wo_dly.3653899861 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 130378526152 ps |
| CPU time | 287.27 seconds |
| Started | Jul 12 04:38:57 PM PDT 24 |
| Finished | Jul 12 04:43:49 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-99b9e1ec-fb6a-450e-ac8b-03bcb0699c68 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3653899861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3653899861 |
| Directory | /workspace/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/157.uart_fifo_reset.3003006059 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 28775853499 ps |
| CPU time | 15.97 seconds |
| Started | Jul 12 04:41:06 PM PDT 24 |
| Finished | Jul 12 04:41:23 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-f0a194b2-98d0-43f5-baad-3d2fa16af66a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003006059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3003006059 |
| Directory | /workspace/157.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_full.1156462838 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 89462864981 ps |
| CPU time | 53.5 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:40:26 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-0dfec0fb-6a03-4dca-ab48-9bec736cf5b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156462838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1156462838 |
| Directory | /workspace/20.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/242.uart_fifo_reset.2502504997 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 164480939933 ps |
| CPU time | 33.95 seconds |
| Started | Jul 12 04:41:29 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-2aa12c74-151d-40f8-a604-74929d7fb52e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502504997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2502504997 |
| Directory | /workspace/242.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_reset.3622022192 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 9291480530 ps |
| CPU time | 21.38 seconds |
| Started | Jul 12 04:39:36 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-290b9a09-b83a-4b1c-b884-c44726ff9055 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622022192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3622022192 |
| Directory | /workspace/26.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_reset.1172868792 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 113097148211 ps |
| CPU time | 175.72 seconds |
| Started | Jul 12 04:40:02 PM PDT 24 |
| Finished | Jul 12 04:43:02 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-4c03174b-7c10-412a-9afb-47cb458305b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1172868792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1172868792 |
| Directory | /workspace/37.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/101.uart_fifo_reset.2437155168 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 133056529390 ps |
| CPU time | 103.15 seconds |
| Started | Jul 12 04:40:56 PM PDT 24 |
| Finished | Jul 12 04:42:44 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-3e200859-a18f-45ce-b06f-37b8c3036d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437155168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2437155168 |
| Directory | /workspace/101.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/109.uart_fifo_reset.2116043059 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 22618241068 ps |
| CPU time | 35.22 seconds |
| Started | Jul 12 04:40:59 PM PDT 24 |
| Finished | Jul 12 04:41:37 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-058ab62d-1386-4d51-9445-9efbb60cb3d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116043059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2116043059 |
| Directory | /workspace/109.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/112.uart_fifo_reset.3965589536 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 83881504998 ps |
| CPU time | 163.9 seconds |
| Started | Jul 12 04:40:55 PM PDT 24 |
| Finished | Jul 12 04:43:44 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-ed336575-5e48-4ced-9323-a836e9955795 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965589536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3965589536 |
| Directory | /workspace/112.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/122.uart_fifo_reset.1098981168 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 8709203458 ps |
| CPU time | 25.83 seconds |
| Started | Jul 12 04:41:01 PM PDT 24 |
| Finished | Jul 12 04:41:30 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-f5f304f4-2f41-4a99-b082-b963027e4667 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098981168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1098981168 |
| Directory | /workspace/122.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/127.uart_fifo_reset.346468704 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 37693467332 ps |
| CPU time | 54.07 seconds |
| Started | Jul 12 04:41:01 PM PDT 24 |
| Finished | Jul 12 04:41:58 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-832b748c-ba0b-4f56-b48c-d3046d64dbce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346468704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.346468704 |
| Directory | /workspace/127.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/139.uart_fifo_reset.468575721 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 67832057448 ps |
| CPU time | 29.85 seconds |
| Started | Jul 12 04:41:04 PM PDT 24 |
| Finished | Jul 12 04:41:36 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-8e277670-3a64-4a14-a949-ca06e24bdb90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468575721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.468575721 |
| Directory | /workspace/139.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/145.uart_fifo_reset.4257351492 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 28722539720 ps |
| CPU time | 12.33 seconds |
| Started | Jul 12 04:41:08 PM PDT 24 |
| Finished | Jul 12 04:41:21 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-a4c387ae-aa73-45e4-bcc6-0b28236a9f95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257351492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4257351492 |
| Directory | /workspace/145.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/158.uart_fifo_reset.2962421740 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 65978326730 ps |
| CPU time | 93.17 seconds |
| Started | Jul 12 04:41:06 PM PDT 24 |
| Finished | Jul 12 04:42:41 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-debb041e-8647-4668-b3ce-19fa5c9982dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962421740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2962421740 |
| Directory | /workspace/158.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/183.uart_fifo_reset.1614462612 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 66621418232 ps |
| CPU time | 31.31 seconds |
| Started | Jul 12 04:41:12 PM PDT 24 |
| Finished | Jul 12 04:41:45 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-3366afc5-5f67-4a2b-84c2-9d13d02eef08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614462612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1614462612 |
| Directory | /workspace/183.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/199.uart_fifo_reset.525942335 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 44021230576 ps |
| CPU time | 21.34 seconds |
| Started | Jul 12 04:41:22 PM PDT 24 |
| Finished | Jul 12 04:41:45 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-dab48683-6866-4ab4-be1b-5edab131bdb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525942335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.525942335 |
| Directory | /workspace/199.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3171599082 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 68283034861 ps |
| CPU time | 394.45 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:45:21 PM PDT 24 |
| Peak memory | 224728 kb |
| Host | smart-5acfd24d-0b66-469e-8cce-a724973f9bfb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171599082 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3171599082 |
| Directory | /workspace/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/267.uart_fifo_reset.3167070189 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 27375147024 ps |
| CPU time | 21.39 seconds |
| Started | Jul 12 04:41:37 PM PDT 24 |
| Finished | Jul 12 04:41:59 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-09a3833a-2fb3-4122-98a1-1e7d09ed72f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3167070189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3167070189 |
| Directory | /workspace/267.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all.3673016269 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 227947272236 ps |
| CPU time | 664.13 seconds |
| Started | Jul 12 04:39:33 PM PDT 24 |
| Finished | Jul 12 04:50:43 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-10dec07b-bd9e-4bd2-85db-5e3eb233c046 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673016269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3673016269 |
| Directory | /workspace/27.uart_stress_all/latest |
| Test location | /workspace/coverage/default/56.uart_fifo_reset.1956997935 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 108995134955 ps |
| CPU time | 36.96 seconds |
| Started | Jul 12 04:40:52 PM PDT 24 |
| Finished | Jul 12 04:41:33 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-8636343a-b84b-4b20-b469-efe27662cff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1956997935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1956997935 |
| Directory | /workspace/56.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/83.uart_fifo_reset.1716654436 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 68276618022 ps |
| CPU time | 28.01 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:41:26 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-782d0157-9e1a-46f2-b264-66d66ddadd0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716654436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1716654436 |
| Directory | /workspace/83.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.110684005 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 58764887 ps |
| CPU time | 0.68 seconds |
| Started | Jul 12 04:15:56 PM PDT 24 |
| Finished | Jul 12 04:15:58 PM PDT 24 |
| Peak memory | 194596 kb |
| Host | smart-aa8c7a5f-1036-4d85-a409-3b27e391990e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110684005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.110684005 |
| Directory | /workspace/0.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2502214652 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 182340167 ps |
| CPU time | 1.56 seconds |
| Started | Jul 12 04:16:04 PM PDT 24 |
| Finished | Jul 12 04:16:06 PM PDT 24 |
| Peak memory | 198664 kb |
| Host | smart-f704085a-f0dc-4187-8bbd-6ee8e51472fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502214652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2502214652 |
| Directory | /workspace/0.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.805729680 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 56682775 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:22:06 PM PDT 24 |
| Finished | Jul 12 04:22:08 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-bee383ae-82ee-4ee8-a298-b2d615ba819e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805729680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.805729680 |
| Directory | /workspace/0.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.537458305 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 33765562 ps |
| CPU time | 0.8 seconds |
| Started | Jul 12 04:16:02 PM PDT 24 |
| Finished | Jul 12 04:16:04 PM PDT 24 |
| Peak memory | 197728 kb |
| Host | smart-215e7efe-5882-4831-bda9-611346bb9b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537458305 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.537458305 |
| Directory | /workspace/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_rw.3962163825 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 33001653 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:16:02 PM PDT 24 |
| Finished | Jul 12 04:16:03 PM PDT 24 |
| Peak memory | 196272 kb |
| Host | smart-cba26e9e-caa1-46d9-a59b-f5cd5ce793bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962163825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3962163825 |
| Directory | /workspace/0.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_intr_test.1645916063 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 15400564 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:21:31 PM PDT 24 |
| Finished | Jul 12 04:21:34 PM PDT 24 |
| Peak memory | 194956 kb |
| Host | smart-69e3aa32-afc9-44ca-b72d-324021d88ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645916063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1645916063 |
| Directory | /workspace/0.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2982368700 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 75278412 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:15:56 PM PDT 24 |
| Finished | Jul 12 04:15:57 PM PDT 24 |
| Peak memory | 196372 kb |
| Host | smart-fa00f126-c751-445b-a36e-ad4f42d13ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982368700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.2982368700 |
| Directory | /workspace/0.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_errors.2767309215 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 62378055 ps |
| CPU time | 1.07 seconds |
| Started | Jul 12 04:22:06 PM PDT 24 |
| Finished | Jul 12 04:22:09 PM PDT 24 |
| Peak memory | 200372 kb |
| Host | smart-9b2824a7-4d77-44e2-bba5-55737053f66e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767309215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2767309215 |
| Directory | /workspace/0.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2202210736 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 156662760 ps |
| CPU time | 0.91 seconds |
| Started | Jul 12 04:16:06 PM PDT 24 |
| Finished | Jul 12 04:16:08 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-93fe4aa2-c500-4f28-8242-acef14193426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202210736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2202210736 |
| Directory | /workspace/0.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.893946323 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 20977456 ps |
| CPU time | 0.71 seconds |
| Started | Jul 12 04:16:29 PM PDT 24 |
| Finished | Jul 12 04:16:30 PM PDT 24 |
| Peak memory | 194824 kb |
| Host | smart-4ae42abe-b12f-4f00-a034-32a13c6a6165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893946323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.893946323 |
| Directory | /workspace/1.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3901667545 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 93292669 ps |
| CPU time | 1.41 seconds |
| Started | Jul 12 04:22:16 PM PDT 24 |
| Finished | Jul 12 04:22:23 PM PDT 24 |
| Peak memory | 198004 kb |
| Host | smart-6d233503-1e51-457c-ac00-1cd5b501cd9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901667545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3901667545 |
| Directory | /workspace/1.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.396964821 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 22269251 ps |
| CPU time | 0.61 seconds |
| Started | Jul 12 04:22:43 PM PDT 24 |
| Finished | Jul 12 04:22:47 PM PDT 24 |
| Peak memory | 195948 kb |
| Host | smart-19f89995-3d2d-46d0-b6ac-f86b86e6427b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396964821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.396964821 |
| Directory | /workspace/1.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3527627064 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 16237124 ps |
| CPU time | 0.79 seconds |
| Started | Jul 12 04:20:32 PM PDT 24 |
| Finished | Jul 12 04:20:34 PM PDT 24 |
| Peak memory | 199532 kb |
| Host | smart-472014da-afb5-419f-9a62-c25ab66f061e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527627064 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3527627064 |
| Directory | /workspace/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_rw.2591288655 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 44581929 ps |
| CPU time | 0.66 seconds |
| Started | Jul 12 04:18:07 PM PDT 24 |
| Finished | Jul 12 04:18:08 PM PDT 24 |
| Peak memory | 196048 kb |
| Host | smart-aa368e4f-ac88-441b-89b7-acde771b9b99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591288655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2591288655 |
| Directory | /workspace/1.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_intr_test.2593550863 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 55300632 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:21:29 PM PDT 24 |
| Finished | Jul 12 04:21:32 PM PDT 24 |
| Peak memory | 194544 kb |
| Host | smart-7c92306b-60fe-4f75-864c-ba85bbe34cae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593550863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2593550863 |
| Directory | /workspace/1.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1440815464 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 29977200 ps |
| CPU time | 0.72 seconds |
| Started | Jul 12 04:22:10 PM PDT 24 |
| Finished | Jul 12 04:22:14 PM PDT 24 |
| Peak memory | 197660 kb |
| Host | smart-b9d055df-102b-496b-ab72-ff4c7c20523d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440815464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.1440815464 |
| Directory | /workspace/1.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_errors.449727321 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 203654338 ps |
| CPU time | 2.07 seconds |
| Started | Jul 12 04:16:01 PM PDT 24 |
| Finished | Jul 12 04:16:04 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-2d092e58-dd05-4676-ae8a-76eeeb7ae608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449727321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.449727321 |
| Directory | /workspace/1.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2007482723 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 45765908 ps |
| CPU time | 0.89 seconds |
| Started | Jul 12 04:17:54 PM PDT 24 |
| Finished | Jul 12 04:17:55 PM PDT 24 |
| Peak memory | 199348 kb |
| Host | smart-f1157ae7-048b-4ea5-b8a6-45586cbef200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007482723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2007482723 |
| Directory | /workspace/1.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3097281505 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 21690910 ps |
| CPU time | 0.69 seconds |
| Started | Jul 12 04:22:09 PM PDT 24 |
| Finished | Jul 12 04:22:12 PM PDT 24 |
| Peak memory | 199036 kb |
| Host | smart-86f202af-800a-4ac8-abf2-60e52fba8c83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097281505 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3097281505 |
| Directory | /workspace/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_rw.2797880871 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 18534020 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:20:03 PM PDT 24 |
| Finished | Jul 12 04:20:05 PM PDT 24 |
| Peak memory | 195932 kb |
| Host | smart-659dbb8f-797f-4c4e-8fa6-1a0c95f6a000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797880871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2797880871 |
| Directory | /workspace/10.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_intr_test.383376331 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 15029734 ps |
| CPU time | 0.61 seconds |
| Started | Jul 12 04:18:30 PM PDT 24 |
| Finished | Jul 12 04:18:31 PM PDT 24 |
| Peak memory | 194972 kb |
| Host | smart-8a3c8d54-8910-4492-bec7-2f8e71b11b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383376331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.383376331 |
| Directory | /workspace/10.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1351911738 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 64756456 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:21:32 PM PDT 24 |
| Finished | Jul 12 04:21:35 PM PDT 24 |
| Peak memory | 194716 kb |
| Host | smart-746dc404-8e3d-4794-80ba-5b312e6d4eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351911738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.1351911738 |
| Directory | /workspace/10.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_errors.3441518332 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 183119995 ps |
| CPU time | 1.08 seconds |
| Started | Jul 12 04:21:38 PM PDT 24 |
| Finished | Jul 12 04:21:42 PM PDT 24 |
| Peak memory | 199324 kb |
| Host | smart-7de318f5-5162-41ee-9a8b-d6a6397e6044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441518332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3441518332 |
| Directory | /workspace/10.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2404292968 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 37727485 ps |
| CPU time | 0.72 seconds |
| Started | Jul 12 04:17:42 PM PDT 24 |
| Finished | Jul 12 04:17:43 PM PDT 24 |
| Peak memory | 198448 kb |
| Host | smart-48e8f00e-8a5b-4e13-8faa-27f0c3e9780d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404292968 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2404292968 |
| Directory | /workspace/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_rw.1335429031 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 13726873 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:16:52 PM PDT 24 |
| Finished | Jul 12 04:16:53 PM PDT 24 |
| Peak memory | 196340 kb |
| Host | smart-e9e6bcaa-7a24-490a-8d40-37ab43256626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335429031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1335429031 |
| Directory | /workspace/11.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_intr_test.1670617210 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 27339316 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:21:51 PM PDT 24 |
| Finished | Jul 12 04:21:55 PM PDT 24 |
| Peak memory | 194724 kb |
| Host | smart-08a10a08-089f-4ce9-84ec-d3bf32f43025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670617210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1670617210 |
| Directory | /workspace/11.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3458342837 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 25365394 ps |
| CPU time | 0.73 seconds |
| Started | Jul 12 04:18:19 PM PDT 24 |
| Finished | Jul 12 04:18:20 PM PDT 24 |
| Peak memory | 198300 kb |
| Host | smart-4b037d43-c811-4070-8e25-73875844c636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458342837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.3458342837 |
| Directory | /workspace/11.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_errors.3516684843 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 30548723 ps |
| CPU time | 1.54 seconds |
| Started | Jul 12 04:21:31 PM PDT 24 |
| Finished | Jul 12 04:21:36 PM PDT 24 |
| Peak memory | 199176 kb |
| Host | smart-32638eaa-0f26-4b99-ac0d-2e4f56692af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516684843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3516684843 |
| Directory | /workspace/11.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.700941193 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 161575760 ps |
| CPU time | 0.87 seconds |
| Started | Jul 12 04:21:32 PM PDT 24 |
| Finished | Jul 12 04:21:35 PM PDT 24 |
| Peak memory | 199260 kb |
| Host | smart-6c321950-c579-466b-b11b-2b3a18623009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700941193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.700941193 |
| Directory | /workspace/11.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.775926391 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 92948158 ps |
| CPU time | 0.8 seconds |
| Started | Jul 12 04:18:43 PM PDT 24 |
| Finished | Jul 12 04:18:44 PM PDT 24 |
| Peak memory | 199120 kb |
| Host | smart-24cebd4b-87be-4d78-8ccc-f608de20f98c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775926391 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.775926391 |
| Directory | /workspace/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_rw.2663322384 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 12600824 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:16:52 PM PDT 24 |
| Finished | Jul 12 04:16:53 PM PDT 24 |
| Peak memory | 195980 kb |
| Host | smart-3db913a7-5756-488b-a937-763fa1712a04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663322384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2663322384 |
| Directory | /workspace/12.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_intr_test.2222241756 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 33719733 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:21:52 PM PDT 24 |
| Finished | Jul 12 04:21:56 PM PDT 24 |
| Peak memory | 194848 kb |
| Host | smart-cd199acd-59f0-400a-81bc-cf6a417b6960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222241756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2222241756 |
| Directory | /workspace/12.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2439743970 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 59697398 ps |
| CPU time | 0.77 seconds |
| Started | Jul 12 04:22:19 PM PDT 24 |
| Finished | Jul 12 04:22:25 PM PDT 24 |
| Peak memory | 195004 kb |
| Host | smart-41a569d0-ff71-49f4-8db0-37c1a05b9931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439743970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.2439743970 |
| Directory | /workspace/12.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_errors.1472920728 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 70066412 ps |
| CPU time | 1.33 seconds |
| Started | Jul 12 04:18:16 PM PDT 24 |
| Finished | Jul 12 04:18:19 PM PDT 24 |
| Peak memory | 200624 kb |
| Host | smart-0a9e6291-b53a-401c-b43e-1b92c026a42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472920728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1472920728 |
| Directory | /workspace/12.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1618774687 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 52305568 ps |
| CPU time | 0.97 seconds |
| Started | Jul 12 04:21:30 PM PDT 24 |
| Finished | Jul 12 04:21:34 PM PDT 24 |
| Peak memory | 198528 kb |
| Host | smart-cc215df9-8fd7-4145-a8f9-238bdea9c3ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618774687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1618774687 |
| Directory | /workspace/12.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3262275183 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 63464604 ps |
| CPU time | 1 seconds |
| Started | Jul 12 04:21:18 PM PDT 24 |
| Finished | Jul 12 04:21:21 PM PDT 24 |
| Peak memory | 199376 kb |
| Host | smart-dfdc0e1d-82e6-435d-acdb-63893b502c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262275183 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3262275183 |
| Directory | /workspace/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_rw.3263478085 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 12478447 ps |
| CPU time | 0.54 seconds |
| Started | Jul 12 04:21:18 PM PDT 24 |
| Finished | Jul 12 04:21:20 PM PDT 24 |
| Peak memory | 195800 kb |
| Host | smart-99aae5ff-2623-4d8d-898a-8d196dd76459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263478085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3263478085 |
| Directory | /workspace/13.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_intr_test.3631241478 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 27409330 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:21:08 PM PDT 24 |
| Finished | Jul 12 04:21:10 PM PDT 24 |
| Peak memory | 194636 kb |
| Host | smart-2d39f67a-df81-46ba-ab6e-3111d9d405cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631241478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3631241478 |
| Directory | /workspace/13.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.808402507 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 17462227 ps |
| CPU time | 0.63 seconds |
| Started | Jul 12 04:22:02 PM PDT 24 |
| Finished | Jul 12 04:22:05 PM PDT 24 |
| Peak memory | 196068 kb |
| Host | smart-5711a6fe-b452-4a81-9de4-a82227bed0b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808402507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr _outstanding.808402507 |
| Directory | /workspace/13.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_errors.3742919825 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 170675564 ps |
| CPU time | 1.52 seconds |
| Started | Jul 12 04:22:11 PM PDT 24 |
| Finished | Jul 12 04:22:17 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-3a3b44eb-e412-4052-a353-b5988b7cbca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742919825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3742919825 |
| Directory | /workspace/13.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3380088241 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 257951910 ps |
| CPU time | 1.24 seconds |
| Started | Jul 12 04:21:51 PM PDT 24 |
| Finished | Jul 12 04:21:56 PM PDT 24 |
| Peak memory | 199600 kb |
| Host | smart-99fdedb2-faa9-4875-bb86-921830453e98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380088241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3380088241 |
| Directory | /workspace/13.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3308614615 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 50270846 ps |
| CPU time | 0.73 seconds |
| Started | Jul 12 04:21:58 PM PDT 24 |
| Finished | Jul 12 04:22:02 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-715895f4-d25e-4d26-811a-420534efecde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308614615 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3308614615 |
| Directory | /workspace/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_rw.845961394 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 52868577 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:21:57 PM PDT 24 |
| Finished | Jul 12 04:22:00 PM PDT 24 |
| Peak memory | 196024 kb |
| Host | smart-eeabd5cf-1251-435c-9471-813685520af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845961394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.845961394 |
| Directory | /workspace/14.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_intr_test.1381572183 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 13718808 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:22:13 PM PDT 24 |
| Finished | Jul 12 04:22:18 PM PDT 24 |
| Peak memory | 194768 kb |
| Host | smart-b5b0fd1c-43ac-40dc-a6bb-50797a589714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381572183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1381572183 |
| Directory | /workspace/14.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3356013978 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 16231627 ps |
| CPU time | 0.65 seconds |
| Started | Jul 12 04:21:44 PM PDT 24 |
| Finished | Jul 12 04:21:49 PM PDT 24 |
| Peak memory | 194488 kb |
| Host | smart-20ed67dc-c57e-4116-802c-bf3ef27165e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356013978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.3356013978 |
| Directory | /workspace/14.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_errors.2812141775 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 67142242 ps |
| CPU time | 1.45 seconds |
| Started | Jul 12 04:21:22 PM PDT 24 |
| Finished | Jul 12 04:21:25 PM PDT 24 |
| Peak memory | 200584 kb |
| Host | smart-f4451c9c-f6cf-4ee8-9b1b-a2bf747f8cb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812141775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2812141775 |
| Directory | /workspace/14.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1972045911 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 148671250 ps |
| CPU time | 0.89 seconds |
| Started | Jul 12 04:21:23 PM PDT 24 |
| Finished | Jul 12 04:21:26 PM PDT 24 |
| Peak memory | 199544 kb |
| Host | smart-1314d977-bbfe-42b6-9c35-ce409ae6fb42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972045911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1972045911 |
| Directory | /workspace/14.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3819259176 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 47041940 ps |
| CPU time | 1.04 seconds |
| Started | Jul 12 04:21:14 PM PDT 24 |
| Finished | Jul 12 04:21:16 PM PDT 24 |
| Peak memory | 200256 kb |
| Host | smart-ae168c54-aae7-472b-82b3-07f743dd59d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819259176 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3819259176 |
| Directory | /workspace/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_rw.1601640184 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 20375690 ps |
| CPU time | 0.71 seconds |
| Started | Jul 12 04:21:49 PM PDT 24 |
| Finished | Jul 12 04:21:53 PM PDT 24 |
| Peak memory | 195696 kb |
| Host | smart-04e90aea-b4f3-4d97-a2d6-8e4f2ba109d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601640184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1601640184 |
| Directory | /workspace/15.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_intr_test.876301038 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 13657730 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:19:13 PM PDT 24 |
| Finished | Jul 12 04:19:14 PM PDT 24 |
| Peak memory | 193040 kb |
| Host | smart-d4714fcf-302a-4e84-97e5-4f567627dbed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876301038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.876301038 |
| Directory | /workspace/15.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3163608927 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 55377414 ps |
| CPU time | 0.88 seconds |
| Started | Jul 12 04:19:13 PM PDT 24 |
| Finished | Jul 12 04:19:15 PM PDT 24 |
| Peak memory | 195484 kb |
| Host | smart-40269cca-b390-4237-93eb-dac2ce8e21d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163608927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.3163608927 |
| Directory | /workspace/15.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_errors.2790402981 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 237377842 ps |
| CPU time | 0.94 seconds |
| Started | Jul 12 04:21:58 PM PDT 24 |
| Finished | Jul 12 04:22:02 PM PDT 24 |
| Peak memory | 200396 kb |
| Host | smart-be14adab-40a9-4d06-9a39-def4b757bedb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790402981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2790402981 |
| Directory | /workspace/15.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1942667495 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 42083364 ps |
| CPU time | 0.93 seconds |
| Started | Jul 12 04:17:33 PM PDT 24 |
| Finished | Jul 12 04:17:34 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-72642c93-1c7e-4a9c-b997-8fb0991238c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942667495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1942667495 |
| Directory | /workspace/15.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3729065588 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 40110342 ps |
| CPU time | 0.69 seconds |
| Started | Jul 12 04:21:14 PM PDT 24 |
| Finished | Jul 12 04:21:15 PM PDT 24 |
| Peak memory | 198808 kb |
| Host | smart-6719aebb-8df6-404b-a566-3d69774fcc46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729065588 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3729065588 |
| Directory | /workspace/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_rw.722404447 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 54030829 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:17:45 PM PDT 24 |
| Finished | Jul 12 04:17:46 PM PDT 24 |
| Peak memory | 195980 kb |
| Host | smart-a8c227c5-d126-4d8c-846e-61b64b5e6ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722404447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.722404447 |
| Directory | /workspace/16.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_intr_test.744593787 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 14397747 ps |
| CPU time | 0.64 seconds |
| Started | Jul 12 04:19:13 PM PDT 24 |
| Finished | Jul 12 04:19:14 PM PDT 24 |
| Peak memory | 192324 kb |
| Host | smart-b8bf7bee-d198-47ed-929e-d75a06703019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744593787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.744593787 |
| Directory | /workspace/16.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1478618713 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 14210850 ps |
| CPU time | 0.65 seconds |
| Started | Jul 12 04:16:14 PM PDT 24 |
| Finished | Jul 12 04:16:16 PM PDT 24 |
| Peak memory | 195992 kb |
| Host | smart-24e7d14a-2c8a-40b2-a016-6b4c034a503f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478618713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.1478618713 |
| Directory | /workspace/16.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_errors.829635010 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 683666677 ps |
| CPU time | 1.34 seconds |
| Started | Jul 12 04:19:13 PM PDT 24 |
| Finished | Jul 12 04:19:15 PM PDT 24 |
| Peak memory | 197800 kb |
| Host | smart-ddc6eb5a-18ad-42cc-975d-45f3a93fb70d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829635010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.829635010 |
| Directory | /workspace/16.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1851166953 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 92943258 ps |
| CPU time | 0.95 seconds |
| Started | Jul 12 04:21:44 PM PDT 24 |
| Finished | Jul 12 04:21:49 PM PDT 24 |
| Peak memory | 197852 kb |
| Host | smart-22bdb7dd-8b1d-4393-88a8-ec8730861059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851166953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1851166953 |
| Directory | /workspace/16.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3779476183 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 15058681 ps |
| CPU time | 0.77 seconds |
| Started | Jul 12 04:21:48 PM PDT 24 |
| Finished | Jul 12 04:21:52 PM PDT 24 |
| Peak memory | 200376 kb |
| Host | smart-e2d60fd6-2484-4fdd-aac7-1482628cb8b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779476183 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3779476183 |
| Directory | /workspace/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_rw.516747918 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 32918744 ps |
| CPU time | 0.65 seconds |
| Started | Jul 12 04:21:15 PM PDT 24 |
| Finished | Jul 12 04:21:16 PM PDT 24 |
| Peak memory | 195824 kb |
| Host | smart-789a8e46-9e0c-4849-8cf6-5a5ee43048f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516747918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.516747918 |
| Directory | /workspace/17.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_intr_test.452932842 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 14563346 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:21:28 PM PDT 24 |
| Finished | Jul 12 04:21:31 PM PDT 24 |
| Peak memory | 194856 kb |
| Host | smart-bcbd2f14-c707-42ac-b681-e1a4d18cb801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452932842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.452932842 |
| Directory | /workspace/17.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2201278550 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 19510416 ps |
| CPU time | 0.74 seconds |
| Started | Jul 12 04:21:14 PM PDT 24 |
| Finished | Jul 12 04:21:15 PM PDT 24 |
| Peak memory | 193652 kb |
| Host | smart-26134845-7a9f-4c89-8c30-f8a95b47a3c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201278550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.2201278550 |
| Directory | /workspace/17.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_errors.3793456927 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 40553761 ps |
| CPU time | 0.94 seconds |
| Started | Jul 12 04:17:56 PM PDT 24 |
| Finished | Jul 12 04:17:58 PM PDT 24 |
| Peak memory | 200316 kb |
| Host | smart-83336310-ee7a-41b5-81ff-5f43abecd841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793456927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3793456927 |
| Directory | /workspace/17.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2479675721 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 68887039 ps |
| CPU time | 1.28 seconds |
| Started | Jul 12 04:21:15 PM PDT 24 |
| Finished | Jul 12 04:21:17 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-5f541f94-b62f-4627-8af2-77997fdc970c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479675721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2479675721 |
| Directory | /workspace/17.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1581695244 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 46782234 ps |
| CPU time | 1.32 seconds |
| Started | Jul 12 04:17:19 PM PDT 24 |
| Finished | Jul 12 04:17:21 PM PDT 24 |
| Peak memory | 200604 kb |
| Host | smart-752c59b6-c808-48d0-9ada-9b4c160e028c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581695244 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1581695244 |
| Directory | /workspace/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_rw.3336542963 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 12546849 ps |
| CPU time | 0.63 seconds |
| Started | Jul 12 04:18:37 PM PDT 24 |
| Finished | Jul 12 04:18:38 PM PDT 24 |
| Peak memory | 196032 kb |
| Host | smart-0f322b14-04bb-43f7-8911-27c2947458c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336542963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3336542963 |
| Directory | /workspace/18.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_intr_test.3601812804 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 13196587 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:22:05 PM PDT 24 |
| Finished | Jul 12 04:22:08 PM PDT 24 |
| Peak memory | 194120 kb |
| Host | smart-9aa145da-ec73-44bc-8921-3bd16db0f574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601812804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3601812804 |
| Directory | /workspace/18.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1873763412 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 64431932 ps |
| CPU time | 0.79 seconds |
| Started | Jul 12 04:17:28 PM PDT 24 |
| Finished | Jul 12 04:17:29 PM PDT 24 |
| Peak memory | 196376 kb |
| Host | smart-efd96d68-ad1d-4776-8695-561b5b584652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873763412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.1873763412 |
| Directory | /workspace/18.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_errors.3129943367 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 354075933 ps |
| CPU time | 1.59 seconds |
| Started | Jul 12 04:19:51 PM PDT 24 |
| Finished | Jul 12 04:19:53 PM PDT 24 |
| Peak memory | 200624 kb |
| Host | smart-56c329b3-3217-4a10-9c7e-dba7398c45ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129943367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3129943367 |
| Directory | /workspace/18.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1963263851 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 43890966 ps |
| CPU time | 0.83 seconds |
| Started | Jul 12 04:18:17 PM PDT 24 |
| Finished | Jul 12 04:18:18 PM PDT 24 |
| Peak memory | 200712 kb |
| Host | smart-63cfd953-9bdc-44a9-a3e9-985bf0d83f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963263851 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1963263851 |
| Directory | /workspace/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_rw.3467982401 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 38035642 ps |
| CPU time | 0.61 seconds |
| Started | Jul 12 04:16:35 PM PDT 24 |
| Finished | Jul 12 04:16:36 PM PDT 24 |
| Peak memory | 196004 kb |
| Host | smart-df6e2895-f982-4b47-836e-b783005da9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467982401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3467982401 |
| Directory | /workspace/19.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_intr_test.2544965356 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 21410907 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:22:11 PM PDT 24 |
| Finished | Jul 12 04:22:15 PM PDT 24 |
| Peak memory | 194696 kb |
| Host | smart-4fda5cd3-3a2f-4e63-9fc1-62810291b27f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544965356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2544965356 |
| Directory | /workspace/19.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4120159476 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 35347474 ps |
| CPU time | 0.66 seconds |
| Started | Jul 12 04:16:40 PM PDT 24 |
| Finished | Jul 12 04:16:41 PM PDT 24 |
| Peak memory | 196452 kb |
| Host | smart-b207492a-52be-452b-a377-cf244bdeb926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120159476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.4120159476 |
| Directory | /workspace/19.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_errors.2202865270 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 123375163 ps |
| CPU time | 2.56 seconds |
| Started | Jul 12 04:21:47 PM PDT 24 |
| Finished | Jul 12 04:21:53 PM PDT 24 |
| Peak memory | 200620 kb |
| Host | smart-aa255893-96cd-412f-9871-ea6e61936b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202865270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2202865270 |
| Directory | /workspace/19.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1501075158 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 91807005 ps |
| CPU time | 1.39 seconds |
| Started | Jul 12 04:16:29 PM PDT 24 |
| Finished | Jul 12 04:16:31 PM PDT 24 |
| Peak memory | 199044 kb |
| Host | smart-e24857bc-f030-4dda-b207-676112aa1bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501075158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1501075158 |
| Directory | /workspace/19.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1847707101 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 25914209 ps |
| CPU time | 0.65 seconds |
| Started | Jul 12 04:21:35 PM PDT 24 |
| Finished | Jul 12 04:21:39 PM PDT 24 |
| Peak memory | 194112 kb |
| Host | smart-f5b191a7-dd62-4818-ae45-3d3761fa620b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847707101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1847707101 |
| Directory | /workspace/2.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.394030538 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 92101542 ps |
| CPU time | 1.52 seconds |
| Started | Jul 12 04:16:08 PM PDT 24 |
| Finished | Jul 12 04:16:10 PM PDT 24 |
| Peak memory | 198616 kb |
| Host | smart-65861a79-974f-4903-bb93-0a3cdf016f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394030538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.394030538 |
| Directory | /workspace/2.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2037125033 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 31445385 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:17:22 PM PDT 24 |
| Finished | Jul 12 04:17:23 PM PDT 24 |
| Peak memory | 195976 kb |
| Host | smart-99305104-deb2-423d-960b-81e2845666d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037125033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2037125033 |
| Directory | /workspace/2.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3238502641 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 18517844 ps |
| CPU time | 0.64 seconds |
| Started | Jul 12 04:21:28 PM PDT 24 |
| Finished | Jul 12 04:21:31 PM PDT 24 |
| Peak memory | 197832 kb |
| Host | smart-ffeb526f-be6d-4cff-8f5d-10c5570582c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238502641 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3238502641 |
| Directory | /workspace/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_rw.3069959914 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 48341981 ps |
| CPU time | 0.58 seconds |
| Started | Jul 12 04:21:57 PM PDT 24 |
| Finished | Jul 12 04:22:00 PM PDT 24 |
| Peak memory | 195936 kb |
| Host | smart-25f687c0-e89c-4cd5-83be-70c381447259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069959914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3069959914 |
| Directory | /workspace/2.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_intr_test.1845382318 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 37216200 ps |
| CPU time | 0.54 seconds |
| Started | Jul 12 04:21:51 PM PDT 24 |
| Finished | Jul 12 04:21:55 PM PDT 24 |
| Peak memory | 194912 kb |
| Host | smart-e5d5f893-e1b5-442f-87f4-ed75e757f89e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845382318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1845382318 |
| Directory | /workspace/2.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3805824534 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 30852190 ps |
| CPU time | 0.77 seconds |
| Started | Jul 12 04:21:23 PM PDT 24 |
| Finished | Jul 12 04:21:26 PM PDT 24 |
| Peak memory | 196396 kb |
| Host | smart-6375da18-14f8-4422-9b4d-2f1068e56d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805824534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.3805824534 |
| Directory | /workspace/2.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_errors.4191225923 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 142512240 ps |
| CPU time | 1.95 seconds |
| Started | Jul 12 04:21:51 PM PDT 24 |
| Finished | Jul 12 04:21:56 PM PDT 24 |
| Peak memory | 200576 kb |
| Host | smart-66815821-21e1-477a-9d6f-4af8c1ea9b59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191225923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4191225923 |
| Directory | /workspace/2.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1545956476 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 48510413 ps |
| CPU time | 1.01 seconds |
| Started | Jul 12 04:18:09 PM PDT 24 |
| Finished | Jul 12 04:18:11 PM PDT 24 |
| Peak memory | 199500 kb |
| Host | smart-e27f5595-077c-4f26-81f1-8c8f47b18dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545956476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1545956476 |
| Directory | /workspace/2.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.uart_intr_test.430994155 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 19311246 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:16:53 PM PDT 24 |
| Finished | Jul 12 04:16:54 PM PDT 24 |
| Peak memory | 194892 kb |
| Host | smart-0f466146-05a0-4583-897d-471316ba9bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430994155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.430994155 |
| Directory | /workspace/20.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.uart_intr_test.848156192 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 12334015 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:17:33 PM PDT 24 |
| Finished | Jul 12 04:17:34 PM PDT 24 |
| Peak memory | 195248 kb |
| Host | smart-6eecf704-9684-426a-b9f3-41bcf58ff7c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848156192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.848156192 |
| Directory | /workspace/21.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.uart_intr_test.2539044661 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 15400358 ps |
| CPU time | 0.65 seconds |
| Started | Jul 12 04:16:45 PM PDT 24 |
| Finished | Jul 12 04:16:46 PM PDT 24 |
| Peak memory | 194040 kb |
| Host | smart-7ff27569-3e6d-45d6-99a0-c25750b821fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539044661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2539044661 |
| Directory | /workspace/22.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.uart_intr_test.2043677810 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 45005039 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:16:37 PM PDT 24 |
| Finished | Jul 12 04:16:37 PM PDT 24 |
| Peak memory | 195352 kb |
| Host | smart-850e681d-656c-44bc-bc31-fec2707762d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043677810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2043677810 |
| Directory | /workspace/23.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.uart_intr_test.4205096582 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 22830395 ps |
| CPU time | 0.58 seconds |
| Started | Jul 12 04:16:40 PM PDT 24 |
| Finished | Jul 12 04:16:41 PM PDT 24 |
| Peak memory | 194892 kb |
| Host | smart-eebc6bdb-586f-48c4-8dff-3a5f2a246ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205096582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4205096582 |
| Directory | /workspace/24.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.uart_intr_test.1301959394 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 17148218 ps |
| CPU time | 0.63 seconds |
| Started | Jul 12 04:18:47 PM PDT 24 |
| Finished | Jul 12 04:18:49 PM PDT 24 |
| Peak memory | 194956 kb |
| Host | smart-1f775985-aced-48e8-a86d-66f6828a6db2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301959394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1301959394 |
| Directory | /workspace/25.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.uart_intr_test.3550369365 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 24112832 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:20:00 PM PDT 24 |
| Finished | Jul 12 04:20:01 PM PDT 24 |
| Peak memory | 194888 kb |
| Host | smart-1efdd27d-1bb5-4166-9bf2-8de5a1451463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550369365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3550369365 |
| Directory | /workspace/26.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.uart_intr_test.1924253572 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 11857532 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:17:58 PM PDT 24 |
| Finished | Jul 12 04:18:00 PM PDT 24 |
| Peak memory | 195296 kb |
| Host | smart-c7c6f8c5-cfc5-41d8-805f-97d6c90a15ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924253572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1924253572 |
| Directory | /workspace/27.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.uart_intr_test.3356620796 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 14033701 ps |
| CPU time | 0.63 seconds |
| Started | Jul 12 04:16:42 PM PDT 24 |
| Finished | Jul 12 04:16:43 PM PDT 24 |
| Peak memory | 194968 kb |
| Host | smart-1d7d471c-9fc2-42ab-adde-a2d9f1b84536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356620796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3356620796 |
| Directory | /workspace/28.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.uart_intr_test.3077185367 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 27464407 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:16:42 PM PDT 24 |
| Finished | Jul 12 04:16:43 PM PDT 24 |
| Peak memory | 194972 kb |
| Host | smart-ba0a0c10-66d0-4aad-bed3-5777eeaa17ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077185367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3077185367 |
| Directory | /workspace/29.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1887120560 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 52141503 ps |
| CPU time | 0.92 seconds |
| Started | Jul 12 04:16:30 PM PDT 24 |
| Finished | Jul 12 04:16:32 PM PDT 24 |
| Peak memory | 196388 kb |
| Host | smart-97dfbe7a-26b3-4f29-80bf-ed53e4cb0f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887120560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1887120560 |
| Directory | /workspace/3.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2040300561 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 750240706 ps |
| CPU time | 2.55 seconds |
| Started | Jul 12 04:22:08 PM PDT 24 |
| Finished | Jul 12 04:22:12 PM PDT 24 |
| Peak memory | 196352 kb |
| Host | smart-0fef0c81-8b99-48d6-b985-81f8cc4deb45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040300561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2040300561 |
| Directory | /workspace/3.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2543327159 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 14754687 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:21:37 PM PDT 24 |
| Finished | Jul 12 04:21:40 PM PDT 24 |
| Peak memory | 195984 kb |
| Host | smart-d9e451c3-c36a-473b-a02d-972a279fb60c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543327159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2543327159 |
| Directory | /workspace/3.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.333954090 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 81144983 ps |
| CPU time | 1.09 seconds |
| Started | Jul 12 04:21:23 PM PDT 24 |
| Finished | Jul 12 04:21:26 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-7688561c-2f1e-46a5-8946-8bf65bf0bd23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333954090 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.333954090 |
| Directory | /workspace/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_rw.2730517034 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 60025230 ps |
| CPU time | 0.7 seconds |
| Started | Jul 12 04:21:39 PM PDT 24 |
| Finished | Jul 12 04:21:44 PM PDT 24 |
| Peak memory | 195308 kb |
| Host | smart-c255b429-5d36-4394-98f1-0533843b77de |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730517034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2730517034 |
| Directory | /workspace/3.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_intr_test.1017642081 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 51196502 ps |
| CPU time | 0.63 seconds |
| Started | Jul 12 04:21:23 PM PDT 24 |
| Finished | Jul 12 04:21:26 PM PDT 24 |
| Peak memory | 193852 kb |
| Host | smart-e69e93b7-c0e6-47c9-93de-9e0c72463bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017642081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1017642081 |
| Directory | /workspace/3.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3675675158 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 51921255 ps |
| CPU time | 0.66 seconds |
| Started | Jul 12 04:21:23 PM PDT 24 |
| Finished | Jul 12 04:21:25 PM PDT 24 |
| Peak memory | 194216 kb |
| Host | smart-68f04ec6-f72a-4108-a2da-22d89d89e38e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675675158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.3675675158 |
| Directory | /workspace/3.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_errors.1702332868 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 376109358 ps |
| CPU time | 1.97 seconds |
| Started | Jul 12 04:21:32 PM PDT 24 |
| Finished | Jul 12 04:21:37 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-05a98111-add4-4409-adcd-38eb82fc58ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702332868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1702332868 |
| Directory | /workspace/3.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2660996053 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 379719611 ps |
| CPU time | 1.28 seconds |
| Started | Jul 12 04:17:30 PM PDT 24 |
| Finished | Jul 12 04:17:31 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-8aa447fe-1949-4b08-b460-5c24301c14f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660996053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2660996053 |
| Directory | /workspace/3.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.uart_intr_test.3974214436 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 46660995 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:17:33 PM PDT 24 |
| Finished | Jul 12 04:17:34 PM PDT 24 |
| Peak memory | 194976 kb |
| Host | smart-c4e036af-ab04-4cff-8343-f28fa7941aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974214436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3974214436 |
| Directory | /workspace/30.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.uart_intr_test.1211012405 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 51817481 ps |
| CPU time | 0.63 seconds |
| Started | Jul 12 04:16:42 PM PDT 24 |
| Finished | Jul 12 04:16:43 PM PDT 24 |
| Peak memory | 194972 kb |
| Host | smart-c18cae14-d3a5-4a26-b577-84eec8ef2618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211012405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1211012405 |
| Directory | /workspace/31.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.uart_intr_test.1297167821 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 23223873 ps |
| CPU time | 0.58 seconds |
| Started | Jul 12 04:19:02 PM PDT 24 |
| Finished | Jul 12 04:19:03 PM PDT 24 |
| Peak memory | 194972 kb |
| Host | smart-84a210be-7858-4115-a5da-12dac2c66cb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297167821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1297167821 |
| Directory | /workspace/32.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.uart_intr_test.1455206414 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 146229681 ps |
| CPU time | 0.58 seconds |
| Started | Jul 12 04:16:45 PM PDT 24 |
| Finished | Jul 12 04:16:46 PM PDT 24 |
| Peak memory | 194888 kb |
| Host | smart-d1bdae62-aab5-4083-8104-c01de1403856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455206414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1455206414 |
| Directory | /workspace/33.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.uart_intr_test.3952866576 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 48529000 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:16:49 PM PDT 24 |
| Finished | Jul 12 04:16:50 PM PDT 24 |
| Peak memory | 195292 kb |
| Host | smart-d1df6da5-f27a-4464-9348-ccb596b43a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952866576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3952866576 |
| Directory | /workspace/34.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.uart_intr_test.4267799500 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 13945991 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:16:51 PM PDT 24 |
| Finished | Jul 12 04:16:52 PM PDT 24 |
| Peak memory | 194976 kb |
| Host | smart-1186d96c-ab50-4006-8eff-23f89156d7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267799500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4267799500 |
| Directory | /workspace/35.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.uart_intr_test.3104039060 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 13453072 ps |
| CPU time | 0.64 seconds |
| Started | Jul 12 04:16:48 PM PDT 24 |
| Finished | Jul 12 04:16:49 PM PDT 24 |
| Peak memory | 194944 kb |
| Host | smart-ae785410-2e05-4ef1-8915-a95c09b1da03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104039060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3104039060 |
| Directory | /workspace/36.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.uart_intr_test.274683625 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 22869537 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:16:51 PM PDT 24 |
| Finished | Jul 12 04:16:52 PM PDT 24 |
| Peak memory | 195264 kb |
| Host | smart-a3af1832-4a92-48ea-8212-4c8b30339dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274683625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.274683625 |
| Directory | /workspace/37.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.uart_intr_test.3499633789 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 25258978 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:21:40 PM PDT 24 |
| Finished | Jul 12 04:21:44 PM PDT 24 |
| Peak memory | 194964 kb |
| Host | smart-1850d905-2477-4bec-ab3a-14c72818b7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499633789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3499633789 |
| Directory | /workspace/38.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.uart_intr_test.174502712 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 44771858 ps |
| CPU time | 0.63 seconds |
| Started | Jul 12 04:17:03 PM PDT 24 |
| Finished | Jul 12 04:17:05 PM PDT 24 |
| Peak memory | 194960 kb |
| Host | smart-76f9105d-aace-4dd0-a6ff-37dd0ae9b5e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174502712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.174502712 |
| Directory | /workspace/39.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2160575517 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 38410907 ps |
| CPU time | 0.69 seconds |
| Started | Jul 12 04:17:06 PM PDT 24 |
| Finished | Jul 12 04:17:07 PM PDT 24 |
| Peak memory | 196060 kb |
| Host | smart-095df6b1-4c7b-4f57-a373-d6faefeeb3d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160575517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2160575517 |
| Directory | /workspace/4.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2267707353 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 225100470 ps |
| CPU time | 2.14 seconds |
| Started | Jul 12 04:21:59 PM PDT 24 |
| Finished | Jul 12 04:22:04 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-2ef853ad-fc34-4bc6-9f7d-54d9360bfa37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267707353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2267707353 |
| Directory | /workspace/4.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.681189547 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 15950729 ps |
| CPU time | 0.64 seconds |
| Started | Jul 12 04:21:43 PM PDT 24 |
| Finished | Jul 12 04:21:47 PM PDT 24 |
| Peak memory | 195056 kb |
| Host | smart-a21a5dcc-daa1-4791-9b4f-1a1b2d75603c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681189547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.681189547 |
| Directory | /workspace/4.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2666826138 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 64871147 ps |
| CPU time | 0.84 seconds |
| Started | Jul 12 04:21:07 PM PDT 24 |
| Finished | Jul 12 04:21:09 PM PDT 24 |
| Peak memory | 199384 kb |
| Host | smart-3378dc0a-3e9e-42f5-b3fb-e812d2e33940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666826138 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2666826138 |
| Directory | /workspace/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_intr_test.692522242 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 12060818 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:21:35 PM PDT 24 |
| Finished | Jul 12 04:21:38 PM PDT 24 |
| Peak memory | 193820 kb |
| Host | smart-dd30f8ee-047e-43ec-bfbf-b0cb46669901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692522242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.692522242 |
| Directory | /workspace/4.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2730523662 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 14168292 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:21:44 PM PDT 24 |
| Finished | Jul 12 04:21:48 PM PDT 24 |
| Peak memory | 194788 kb |
| Host | smart-647603a9-a2da-4d84-9f3e-be81a886f434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730523662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.2730523662 |
| Directory | /workspace/4.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_errors.1449296051 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 65232465 ps |
| CPU time | 1.7 seconds |
| Started | Jul 12 04:22:00 PM PDT 24 |
| Finished | Jul 12 04:22:04 PM PDT 24 |
| Peak memory | 200596 kb |
| Host | smart-f95c4451-547c-4c42-95f9-0f51c45bb42c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449296051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1449296051 |
| Directory | /workspace/4.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1535643976 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1326993587 ps |
| CPU time | 1.33 seconds |
| Started | Jul 12 04:21:44 PM PDT 24 |
| Finished | Jul 12 04:21:49 PM PDT 24 |
| Peak memory | 199556 kb |
| Host | smart-e8060e52-eb36-472c-a18c-1d7773d8c446 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535643976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1535643976 |
| Directory | /workspace/4.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.uart_intr_test.931155313 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 23443378 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:21:44 PM PDT 24 |
| Finished | Jul 12 04:21:48 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-a6be7e00-7d3d-43be-a7a1-15b87c95c039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931155313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.931155313 |
| Directory | /workspace/40.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.uart_intr_test.1158886169 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 172534334 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:16:57 PM PDT 24 |
| Finished | Jul 12 04:16:58 PM PDT 24 |
| Peak memory | 194972 kb |
| Host | smart-696cb015-64c1-48fc-ad5a-f71509643b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158886169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1158886169 |
| Directory | /workspace/41.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.uart_intr_test.2765766256 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 44167720 ps |
| CPU time | 0.64 seconds |
| Started | Jul 12 04:16:57 PM PDT 24 |
| Finished | Jul 12 04:16:58 PM PDT 24 |
| Peak memory | 194960 kb |
| Host | smart-a9f47f74-b00b-46fa-b061-0f5519a9add4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765766256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2765766256 |
| Directory | /workspace/42.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.uart_intr_test.2670559206 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 14507782 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:16:55 PM PDT 24 |
| Finished | Jul 12 04:16:56 PM PDT 24 |
| Peak memory | 194888 kb |
| Host | smart-32015011-5ebd-4923-b6ae-b9e458f3cc2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670559206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2670559206 |
| Directory | /workspace/43.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.uart_intr_test.3821114731 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 32591229 ps |
| CPU time | 0.58 seconds |
| Started | Jul 12 04:21:36 PM PDT 24 |
| Finished | Jul 12 04:21:40 PM PDT 24 |
| Peak memory | 193816 kb |
| Host | smart-55d388e4-1d99-40b1-9e16-bc13dd3095c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821114731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3821114731 |
| Directory | /workspace/44.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.uart_intr_test.3485990337 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 16805932 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:16:55 PM PDT 24 |
| Finished | Jul 12 04:16:56 PM PDT 24 |
| Peak memory | 194964 kb |
| Host | smart-be81d883-6109-4d23-aa73-4628349db535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485990337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3485990337 |
| Directory | /workspace/45.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.uart_intr_test.2595896611 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 22489761 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:21:45 PM PDT 24 |
| Finished | Jul 12 04:21:49 PM PDT 24 |
| Peak memory | 194848 kb |
| Host | smart-9a493886-e59d-4dfd-92b1-6700f9540604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595896611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2595896611 |
| Directory | /workspace/46.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.uart_intr_test.1908524421 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 30061971 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:18:19 PM PDT 24 |
| Finished | Jul 12 04:18:21 PM PDT 24 |
| Peak memory | 194952 kb |
| Host | smart-08663251-d278-4bab-861d-c0c9548c8a75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908524421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1908524421 |
| Directory | /workspace/47.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.uart_intr_test.3115161112 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 35014428 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:18:19 PM PDT 24 |
| Finished | Jul 12 04:18:20 PM PDT 24 |
| Peak memory | 194896 kb |
| Host | smart-7bbe2530-4e23-4ed2-a6c4-f7b3724a5645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115161112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3115161112 |
| Directory | /workspace/48.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.uart_intr_test.2554462366 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 20395178 ps |
| CPU time | 0.61 seconds |
| Started | Jul 12 04:21:28 PM PDT 24 |
| Finished | Jul 12 04:21:31 PM PDT 24 |
| Peak memory | 193888 kb |
| Host | smart-6f611564-66d4-4cab-ada1-74f47a6af123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554462366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2554462366 |
| Directory | /workspace/49.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1182348855 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 107263073 ps |
| CPU time | 0.8 seconds |
| Started | Jul 12 04:21:52 PM PDT 24 |
| Finished | Jul 12 04:21:56 PM PDT 24 |
| Peak memory | 200392 kb |
| Host | smart-b93fcaba-6ee6-471a-bea9-570b8e0dedb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182348855 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1182348855 |
| Directory | /workspace/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_rw.3744963651 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 13926933 ps |
| CPU time | 0.67 seconds |
| Started | Jul 12 04:20:01 PM PDT 24 |
| Finished | Jul 12 04:20:02 PM PDT 24 |
| Peak memory | 196380 kb |
| Host | smart-1ae1530c-5ed7-4ced-880e-65c4271b10c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744963651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3744963651 |
| Directory | /workspace/5.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_intr_test.2542820881 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 12439538 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:20:02 PM PDT 24 |
| Finished | Jul 12 04:20:04 PM PDT 24 |
| Peak memory | 194908 kb |
| Host | smart-abec3f1d-c2a7-49e5-99bd-094cb65d74ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542820881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2542820881 |
| Directory | /workspace/5.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1424441799 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 17855946 ps |
| CPU time | 0.65 seconds |
| Started | Jul 12 04:16:07 PM PDT 24 |
| Finished | Jul 12 04:16:08 PM PDT 24 |
| Peak memory | 196184 kb |
| Host | smart-82d78f9f-555b-40f2-822a-d5490846389a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424441799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.1424441799 |
| Directory | /workspace/5.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_errors.2995783986 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 55141673 ps |
| CPU time | 0.98 seconds |
| Started | Jul 12 04:17:15 PM PDT 24 |
| Finished | Jul 12 04:17:17 PM PDT 24 |
| Peak memory | 200340 kb |
| Host | smart-cc7736b9-c867-48e5-a911-76b152cbb60c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995783986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2995783986 |
| Directory | /workspace/5.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.672549400 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 57511121 ps |
| CPU time | 0.97 seconds |
| Started | Jul 12 04:21:52 PM PDT 24 |
| Finished | Jul 12 04:21:56 PM PDT 24 |
| Peak memory | 199288 kb |
| Host | smart-27ace0fe-1270-4a0d-b5bd-19874f14ff76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672549400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.672549400 |
| Directory | /workspace/5.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3532951536 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 285355842 ps |
| CPU time | 0.73 seconds |
| Started | Jul 12 04:18:15 PM PDT 24 |
| Finished | Jul 12 04:18:16 PM PDT 24 |
| Peak memory | 198760 kb |
| Host | smart-f4a579b9-b8ae-4eb7-931b-22daedc28027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532951536 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3532951536 |
| Directory | /workspace/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_rw.3134429450 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 13228933 ps |
| CPU time | 0.61 seconds |
| Started | Jul 12 04:17:42 PM PDT 24 |
| Finished | Jul 12 04:17:43 PM PDT 24 |
| Peak memory | 196052 kb |
| Host | smart-0777fe01-b796-4e8e-9f21-97f5b178c249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134429450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3134429450 |
| Directory | /workspace/6.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_intr_test.3681504624 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 66995055 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:16:43 PM PDT 24 |
| Finished | Jul 12 04:16:44 PM PDT 24 |
| Peak memory | 194888 kb |
| Host | smart-6903e346-3b66-4b83-9541-2cf17e2dbf47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681504624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3681504624 |
| Directory | /workspace/6.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.701605737 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 119538770 ps |
| CPU time | 0.73 seconds |
| Started | Jul 12 04:19:13 PM PDT 24 |
| Finished | Jul 12 04:19:14 PM PDT 24 |
| Peak memory | 197456 kb |
| Host | smart-7d29b52c-04ea-42de-b74d-746feaa1bf80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701605737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_ outstanding.701605737 |
| Directory | /workspace/6.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_errors.1912735514 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 211021796 ps |
| CPU time | 2 seconds |
| Started | Jul 12 04:18:04 PM PDT 24 |
| Finished | Jul 12 04:18:07 PM PDT 24 |
| Peak memory | 200608 kb |
| Host | smart-1bb509a9-488c-433c-8bb4-f5d92e7c40cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912735514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1912735514 |
| Directory | /workspace/6.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2673707381 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 74343208 ps |
| CPU time | 1.41 seconds |
| Started | Jul 12 04:19:34 PM PDT 24 |
| Finished | Jul 12 04:19:36 PM PDT 24 |
| Peak memory | 200440 kb |
| Host | smart-22574fc9-615c-4312-9a59-1e3e07fad4ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673707381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2673707381 |
| Directory | /workspace/6.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1067555832 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 22590943 ps |
| CPU time | 1.04 seconds |
| Started | Jul 12 04:22:43 PM PDT 24 |
| Finished | Jul 12 04:22:47 PM PDT 24 |
| Peak memory | 200596 kb |
| Host | smart-96c4e344-b101-4b03-963f-d4c9bbc74298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067555832 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1067555832 |
| Directory | /workspace/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_rw.3357603992 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 34730816 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:22:24 PM PDT 24 |
| Finished | Jul 12 04:22:30 PM PDT 24 |
| Peak memory | 194988 kb |
| Host | smart-89d298ad-5ba7-4fda-b5b1-59f273c0af01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357603992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3357603992 |
| Directory | /workspace/7.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_intr_test.2794027805 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 16072677 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:21:26 PM PDT 24 |
| Finished | Jul 12 04:21:28 PM PDT 24 |
| Peak memory | 194584 kb |
| Host | smart-3d34cf9e-d0a9-498f-885a-b80233bb7d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794027805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2794027805 |
| Directory | /workspace/7.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.989312255 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 24817629 ps |
| CPU time | 0.7 seconds |
| Started | Jul 12 04:21:25 PM PDT 24 |
| Finished | Jul 12 04:21:28 PM PDT 24 |
| Peak memory | 197112 kb |
| Host | smart-c7486318-d06b-4d3b-9991-ed58432ead83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989312255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_ outstanding.989312255 |
| Directory | /workspace/7.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_errors.1173312402 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 114316603 ps |
| CPU time | 1.99 seconds |
| Started | Jul 12 04:19:47 PM PDT 24 |
| Finished | Jul 12 04:19:50 PM PDT 24 |
| Peak memory | 200616 kb |
| Host | smart-f5d9777e-33aa-4935-85c9-c1a6a631ffdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173312402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1173312402 |
| Directory | /workspace/7.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.369239084 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 79876831 ps |
| CPU time | 1.26 seconds |
| Started | Jul 12 04:22:44 PM PDT 24 |
| Finished | Jul 12 04:22:49 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-5b6ea287-74fb-40c7-aafa-0c6e91d80d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369239084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.369239084 |
| Directory | /workspace/7.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.321679249 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 19943052 ps |
| CPU time | 0.73 seconds |
| Started | Jul 12 04:21:57 PM PDT 24 |
| Finished | Jul 12 04:22:00 PM PDT 24 |
| Peak memory | 198864 kb |
| Host | smart-5f81c805-1c48-4160-9dd5-55fc0d01070b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321679249 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.321679249 |
| Directory | /workspace/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_rw.3069140364 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 14173519 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:19:52 PM PDT 24 |
| Finished | Jul 12 04:19:53 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-32f15834-3e14-420a-b688-d33349fea463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069140364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3069140364 |
| Directory | /workspace/8.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_intr_test.4146612013 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 45204301 ps |
| CPU time | 0.54 seconds |
| Started | Jul 12 04:21:25 PM PDT 24 |
| Finished | Jul 12 04:21:28 PM PDT 24 |
| Peak memory | 194488 kb |
| Host | smart-2bb77ce8-eaaf-4558-908f-1be0f0f228d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146612013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4146612013 |
| Directory | /workspace/8.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.768317256 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 19507612 ps |
| CPU time | 0.81 seconds |
| Started | Jul 12 04:21:15 PM PDT 24 |
| Finished | Jul 12 04:21:17 PM PDT 24 |
| Peak memory | 197196 kb |
| Host | smart-58bd6ee9-cb55-4df3-b1cb-ba8ef37e0950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768317256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_ outstanding.768317256 |
| Directory | /workspace/8.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_errors.1841055475 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 23591095 ps |
| CPU time | 1.17 seconds |
| Started | Jul 12 04:21:25 PM PDT 24 |
| Finished | Jul 12 04:21:28 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-74210e51-c935-45a8-80d7-f76c387217f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841055475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1841055475 |
| Directory | /workspace/8.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2421572645 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 103166863 ps |
| CPU time | 1.33 seconds |
| Started | Jul 12 04:22:10 PM PDT 24 |
| Finished | Jul 12 04:22:15 PM PDT 24 |
| Peak memory | 200112 kb |
| Host | smart-684677cc-50f5-48e3-b8e8-ffe58f277760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421572645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2421572645 |
| Directory | /workspace/8.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2015387909 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 23119204 ps |
| CPU time | 0.69 seconds |
| Started | Jul 12 04:22:23 PM PDT 24 |
| Finished | Jul 12 04:22:28 PM PDT 24 |
| Peak memory | 198696 kb |
| Host | smart-9e65ce00-85a2-4807-b85b-9fcfcbe7a238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015387909 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2015387909 |
| Directory | /workspace/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_rw.1008845511 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 42075943 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:16:30 PM PDT 24 |
| Finished | Jul 12 04:16:31 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-18d77438-ef7f-439a-ac7b-b78ac2af24fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008845511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1008845511 |
| Directory | /workspace/9.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_intr_test.1979222859 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 31486461 ps |
| CPU time | 0.73 seconds |
| Started | Jul 12 04:17:42 PM PDT 24 |
| Finished | Jul 12 04:17:43 PM PDT 24 |
| Peak memory | 195324 kb |
| Host | smart-4c561d35-4660-43ba-ad91-209a68387982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979222859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1979222859 |
| Directory | /workspace/9.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3809413807 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 16163958 ps |
| CPU time | 0.63 seconds |
| Started | Jul 12 04:21:45 PM PDT 24 |
| Finished | Jul 12 04:21:49 PM PDT 24 |
| Peak memory | 196088 kb |
| Host | smart-75bf6f16-b3d7-47da-9485-1f8a2d15eafa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809413807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.3809413807 |
| Directory | /workspace/9.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_errors.103238420 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 176249952 ps |
| CPU time | 1.93 seconds |
| Started | Jul 12 04:20:47 PM PDT 24 |
| Finished | Jul 12 04:20:49 PM PDT 24 |
| Peak memory | 200544 kb |
| Host | smart-f18d66f2-e4df-4328-ae7c-fa4ea0de502d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103238420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.103238420 |
| Directory | /workspace/9.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4246217534 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 176106621 ps |
| CPU time | 1.02 seconds |
| Started | Jul 12 04:22:09 PM PDT 24 |
| Finished | Jul 12 04:22:14 PM PDT 24 |
| Peak memory | 198684 kb |
| Host | smart-863cbb97-c157-42f6-8efe-f43247e7d070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246217534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.4246217534 |
| Directory | /workspace/9.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_alert_test.4015289002 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 13943373 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:38:18 PM PDT 24 |
| Finished | Jul 12 04:38:29 PM PDT 24 |
| Peak memory | 195140 kb |
| Host | smart-6103fd9c-acaa-4f6e-9abf-4f841f1b1cc3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015289002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.4015289002 |
| Directory | /workspace/0.uart_alert_test/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_full.1377082755 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 35761332701 ps |
| CPU time | 15.01 seconds |
| Started | Jul 12 04:38:34 PM PDT 24 |
| Finished | Jul 12 04:38:55 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-348fcec1-7c9d-4c24-99ed-b32013fc0438 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377082755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1377082755 |
| Directory | /workspace/0.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_overflow.1104227829 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 108207364054 ps |
| CPU time | 53.81 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:39:35 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-2cfce0bb-d43b-41d7-8187-2bd3988b994b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104227829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1104227829 |
| Directory | /workspace/0.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_reset.1950570035 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 37517627948 ps |
| CPU time | 16.78 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:38:59 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-f43155a6-adbe-469a-9f87-bcba510a929c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950570035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1950570035 |
| Directory | /workspace/0.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/0.uart_intr.1562388805 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 12937517955 ps |
| CPU time | 22.74 seconds |
| Started | Jul 12 04:38:40 PM PDT 24 |
| Finished | Jul 12 04:39:08 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-cc97fae2-6acc-41cf-9300-21e773bfac50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562388805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1562388805 |
| Directory | /workspace/0.uart_intr/latest |
| Test location | /workspace/coverage/default/0.uart_long_xfer_wo_dly.3404615988 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 169896660040 ps |
| CPU time | 1343.16 seconds |
| Started | Jul 12 04:38:16 PM PDT 24 |
| Finished | Jul 12 05:00:57 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-fc2e376e-3f30-4e16-9c65-fa444a17d592 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3404615988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3404615988 |
| Directory | /workspace/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/0.uart_loopback.690093325 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 2936520470 ps |
| CPU time | 5.21 seconds |
| Started | Jul 12 04:38:22 PM PDT 24 |
| Finished | Jul 12 04:38:37 PM PDT 24 |
| Peak memory | 197408 kb |
| Host | smart-68c94bcb-2c52-428b-916d-431ebd1c10d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690093325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.690093325 |
| Directory | /workspace/0.uart_loopback/latest |
| Test location | /workspace/coverage/default/0.uart_noise_filter.4143271596 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 44976985619 ps |
| CPU time | 70.42 seconds |
| Started | Jul 12 04:38:19 PM PDT 24 |
| Finished | Jul 12 04:39:40 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-17cb73de-df57-4ddf-9ce6-258dd04499cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4143271596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4143271596 |
| Directory | /workspace/0.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/0.uart_perf.2499700707 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 16270843561 ps |
| CPU time | 180.17 seconds |
| Started | Jul 12 04:38:32 PM PDT 24 |
| Finished | Jul 12 04:41:38 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-638fa270-04a4-4fa6-bd16-baf9d1b5903f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2499700707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2499700707 |
| Directory | /workspace/0.uart_perf/latest |
| Test location | /workspace/coverage/default/0.uart_rx_oversample.3155619062 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 6446854236 ps |
| CPU time | 10.86 seconds |
| Started | Jul 12 04:38:29 PM PDT 24 |
| Finished | Jul 12 04:38:46 PM PDT 24 |
| Peak memory | 199128 kb |
| Host | smart-574f6eee-841e-445a-bbba-d005cdaa6cdb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3155619062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3155619062 |
| Directory | /workspace/0.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/0.uart_rx_parity_err.294961531 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 87655047236 ps |
| CPU time | 20.34 seconds |
| Started | Jul 12 04:38:38 PM PDT 24 |
| Finished | Jul 12 04:39:04 PM PDT 24 |
| Peak memory | 199632 kb |
| Host | smart-7765e103-6464-425d-93ab-9f9213763bdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294961531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.294961531 |
| Directory | /workspace/0.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/0.uart_rx_start_bit_filter.1819483889 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4808861569 ps |
| CPU time | 2.14 seconds |
| Started | Jul 12 04:38:17 PM PDT 24 |
| Finished | Jul 12 04:38:29 PM PDT 24 |
| Peak memory | 196092 kb |
| Host | smart-a7ee06e1-4bcd-4633-8031-de85b182eef6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1819483889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1819483889 |
| Directory | /workspace/0.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/0.uart_smoke.3498284088 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 908667412 ps |
| CPU time | 1.97 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:38:42 PM PDT 24 |
| Peak memory | 199344 kb |
| Host | smart-2acc2071-01c1-4dc1-a488-cd995f355145 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498284088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3498284088 |
| Directory | /workspace/0.uart_smoke/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all.2328997207 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 413369219404 ps |
| CPU time | 491.75 seconds |
| Started | Jul 12 04:38:30 PM PDT 24 |
| Finished | Jul 12 04:46:48 PM PDT 24 |
| Peak memory | 199696 kb |
| Host | smart-eda0bb2b-8aaa-4240-bdc6-85fc7375ef32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328997207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2328997207 |
| Directory | /workspace/0.uart_stress_all/latest |
| Test location | /workspace/coverage/default/0.uart_tx_ovrd.4209766334 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 417692841 ps |
| CPU time | 1.69 seconds |
| Started | Jul 12 04:38:24 PM PDT 24 |
| Finished | Jul 12 04:38:34 PM PDT 24 |
| Peak memory | 198128 kb |
| Host | smart-86ca6c8e-f248-4e33-8b5a-acf95997a373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209766334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.4209766334 |
| Directory | /workspace/0.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/0.uart_tx_rx.4266692415 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 10958758876 ps |
| CPU time | 16.01 seconds |
| Started | Jul 12 04:38:14 PM PDT 24 |
| Finished | Jul 12 04:38:49 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-310fea01-81ec-4933-b037-b92842faf59c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266692415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.4266692415 |
| Directory | /workspace/0.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_full.256606678 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 51372889109 ps |
| CPU time | 20.65 seconds |
| Started | Jul 12 04:38:17 PM PDT 24 |
| Finished | Jul 12 04:38:48 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-d71d1e73-0226-4adb-b6ac-00850e9aa897 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256606678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.256606678 |
| Directory | /workspace/1.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_overflow.3192585714 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 30396441415 ps |
| CPU time | 49.99 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:39:33 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-adaa6100-6447-47d2-a7fe-7f688dab6f92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192585714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3192585714 |
| Directory | /workspace/1.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_reset.1204145114 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 136708120582 ps |
| CPU time | 97.92 seconds |
| Started | Jul 12 04:38:33 PM PDT 24 |
| Finished | Jul 12 04:40:17 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-7da97626-b576-488a-ad33-92aba997ecbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204145114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1204145114 |
| Directory | /workspace/1.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_intr.2001851803 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 27912867859 ps |
| CPU time | 45.13 seconds |
| Started | Jul 12 04:38:39 PM PDT 24 |
| Finished | Jul 12 04:39:30 PM PDT 24 |
| Peak memory | 198812 kb |
| Host | smart-3b8be73f-1fd1-4f45-8ebc-008839c78081 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001851803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2001851803 |
| Directory | /workspace/1.uart_intr/latest |
| Test location | /workspace/coverage/default/1.uart_long_xfer_wo_dly.1724837168 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 120682686930 ps |
| CPU time | 904.79 seconds |
| Started | Jul 12 04:38:32 PM PDT 24 |
| Finished | Jul 12 04:53:43 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-f32e9316-9d17-4fc0-a468-464520296e7e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1724837168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1724837168 |
| Directory | /workspace/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/1.uart_loopback.925104445 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 5280671425 ps |
| CPU time | 5.43 seconds |
| Started | Jul 12 04:38:16 PM PDT 24 |
| Finished | Jul 12 04:38:32 PM PDT 24 |
| Peak memory | 198708 kb |
| Host | smart-62609619-f71a-43cc-9da0-8bcf0e2341e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925104445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.925104445 |
| Directory | /workspace/1.uart_loopback/latest |
| Test location | /workspace/coverage/default/1.uart_noise_filter.1879773613 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 16609726886 ps |
| CPU time | 6.49 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:38:47 PM PDT 24 |
| Peak memory | 199332 kb |
| Host | smart-c0c9210d-b977-4003-ab78-211aab352c8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879773613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1879773613 |
| Directory | /workspace/1.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/1.uart_perf.1262969576 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 9502828230 ps |
| CPU time | 567.78 seconds |
| Started | Jul 12 04:38:34 PM PDT 24 |
| Finished | Jul 12 04:48:08 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-2bfad030-8187-4ed7-90e9-4e498a8d7603 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1262969576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1262969576 |
| Directory | /workspace/1.uart_perf/latest |
| Test location | /workspace/coverage/default/1.uart_rx_oversample.2843900093 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 7210774931 ps |
| CPU time | 8.39 seconds |
| Started | Jul 12 04:38:17 PM PDT 24 |
| Finished | Jul 12 04:38:36 PM PDT 24 |
| Peak memory | 197956 kb |
| Host | smart-39722d86-a41a-4190-a955-9f34a09dca8f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2843900093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2843900093 |
| Directory | /workspace/1.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/1.uart_rx_parity_err.2979404538 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 8943356605 ps |
| CPU time | 14.59 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:38:56 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-4c0949f0-03e9-4a38-9e5c-6ba165a982ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979404538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2979404538 |
| Directory | /workspace/1.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/1.uart_rx_start_bit_filter.325205886 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 44734820907 ps |
| CPU time | 67.26 seconds |
| Started | Jul 12 04:38:13 PM PDT 24 |
| Finished | Jul 12 04:39:30 PM PDT 24 |
| Peak memory | 195852 kb |
| Host | smart-7adc5f26-dae6-4a94-950e-15c9373796f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325205886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.325205886 |
| Directory | /workspace/1.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/1.uart_sec_cm.636287990 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 35213640 ps |
| CPU time | 0.74 seconds |
| Started | Jul 12 04:38:28 PM PDT 24 |
| Finished | Jul 12 04:38:36 PM PDT 24 |
| Peak memory | 218232 kb |
| Host | smart-67238f6b-7e1b-47e1-a0a0-03038981572a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636287990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.636287990 |
| Directory | /workspace/1.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/1.uart_smoke.4263811109 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 985372347 ps |
| CPU time | 1.11 seconds |
| Started | Jul 12 04:38:17 PM PDT 24 |
| Finished | Jul 12 04:38:28 PM PDT 24 |
| Peak memory | 198448 kb |
| Host | smart-f872f5bc-4d9e-4194-8d74-c7cd8143287a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263811109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4263811109 |
| Directory | /workspace/1.uart_smoke/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all_with_rand_reset.68240056 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 95278111958 ps |
| CPU time | 362.95 seconds |
| Started | Jul 12 04:38:39 PM PDT 24 |
| Finished | Jul 12 04:44:48 PM PDT 24 |
| Peak memory | 216524 kb |
| Host | smart-4e7c7cc1-9ade-4bd8-9d7b-499851f01344 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68240056 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.68240056 |
| Directory | /workspace/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.uart_tx_ovrd.925102311 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 473636632 ps |
| CPU time | 1.6 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:38:44 PM PDT 24 |
| Peak memory | 198660 kb |
| Host | smart-abe805e5-fe14-4a46-a4e0-474086507a87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925102311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.925102311 |
| Directory | /workspace/1.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/1.uart_tx_rx.271093197 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3743472795 ps |
| CPU time | 3.6 seconds |
| Started | Jul 12 04:38:19 PM PDT 24 |
| Finished | Jul 12 04:38:33 PM PDT 24 |
| Peak memory | 196828 kb |
| Host | smart-4fd87001-701e-4062-956a-629d6949ec48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271093197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.271093197 |
| Directory | /workspace/1.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/10.uart_alert_test.1560558594 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 12820819 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:38:56 PM PDT 24 |
| Finished | Jul 12 04:39:01 PM PDT 24 |
| Peak memory | 195180 kb |
| Host | smart-d091f77a-97f2-4ac6-b7a6-b1bc5c092b62 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560558594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1560558594 |
| Directory | /workspace/10.uart_alert_test/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_full.2033979772 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 165223042075 ps |
| CPU time | 118.59 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:41:12 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-87d32793-73eb-4630-b772-7ec0d26249a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033979772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2033979772 |
| Directory | /workspace/10.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_overflow.3685936863 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 300680694869 ps |
| CPU time | 264.34 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:43:38 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-872def83-9fda-4345-84dc-00a4943160b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685936863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3685936863 |
| Directory | /workspace/10.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/10.uart_intr.616661297 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 27601957046 ps |
| CPU time | 78.51 seconds |
| Started | Jul 12 04:38:42 PM PDT 24 |
| Finished | Jul 12 04:40:05 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-bbe1d3ac-7c99-4853-8aa9-3aecfb0048f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616661297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.616661297 |
| Directory | /workspace/10.uart_intr/latest |
| Test location | /workspace/coverage/default/10.uart_long_xfer_wo_dly.1045513110 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 145767904025 ps |
| CPU time | 632.38 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:49:37 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-f7eea1e7-b75a-4b28-8282-6658538e6643 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1045513110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1045513110 |
| Directory | /workspace/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/10.uart_loopback.2205016982 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5916113208 ps |
| CPU time | 5.53 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:11 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-63c8b237-0adc-458c-9f0c-caae9925f40c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205016982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2205016982 |
| Directory | /workspace/10.uart_loopback/latest |
| Test location | /workspace/coverage/default/10.uart_noise_filter.216980902 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 92958241120 ps |
| CPU time | 26.27 seconds |
| Started | Jul 12 04:38:54 PM PDT 24 |
| Finished | Jul 12 04:39:26 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-2273d2ca-43f7-435e-a04e-ae202db801bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216980902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.216980902 |
| Directory | /workspace/10.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/10.uart_perf.2327506060 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 20553625400 ps |
| CPU time | 711.72 seconds |
| Started | Jul 12 04:39:14 PM PDT 24 |
| Finished | Jul 12 04:51:12 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-4df927b3-a619-410e-827f-611d013cf869 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2327506060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2327506060 |
| Directory | /workspace/10.uart_perf/latest |
| Test location | /workspace/coverage/default/10.uart_rx_oversample.1716944326 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 7093162270 ps |
| CPU time | 29.92 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:39:34 PM PDT 24 |
| Peak memory | 199124 kb |
| Host | smart-6cdd477e-cb52-4bbc-93ff-d0a25717defe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1716944326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1716944326 |
| Directory | /workspace/10.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/10.uart_rx_parity_err.2687191391 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 84024045553 ps |
| CPU time | 64.14 seconds |
| Started | Jul 12 04:38:52 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-265d135e-fe9b-4997-8ab7-b006f79aee42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687191391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2687191391 |
| Directory | /workspace/10.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/10.uart_rx_start_bit_filter.2302129288 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 42491943770 ps |
| CPU time | 31.17 seconds |
| Started | Jul 12 04:39:00 PM PDT 24 |
| Finished | Jul 12 04:39:34 PM PDT 24 |
| Peak memory | 195720 kb |
| Host | smart-92fa98e0-3d10-4513-8bff-d69c920b508c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302129288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2302129288 |
| Directory | /workspace/10.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/10.uart_smoke.839104926 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 316303586 ps |
| CPU time | 0.95 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:39:17 PM PDT 24 |
| Peak memory | 198992 kb |
| Host | smart-8059aef5-056d-4faa-95c7-1121f2a7fc6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839104926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.839104926 |
| Directory | /workspace/10.uart_smoke/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all.267730423 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 179887865719 ps |
| CPU time | 881.43 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:53:53 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-2ab09f84-1e24-4816-816b-4ed9aafa0876 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267730423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.267730423 |
| Directory | /workspace/10.uart_stress_all/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1318358246 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 4905014327 ps |
| CPU time | 140.7 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:41:37 PM PDT 24 |
| Peak memory | 200120 kb |
| Host | smart-d1046809-617c-4a1c-9743-6ef3b85026da |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318358246 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1318358246 |
| Directory | /workspace/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.uart_tx_ovrd.2606228408 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 8134920169 ps |
| CPU time | 5.06 seconds |
| Started | Jul 12 04:38:52 PM PDT 24 |
| Finished | Jul 12 04:39:03 PM PDT 24 |
| Peak memory | 199300 kb |
| Host | smart-74e0eafd-2b2f-45d2-a29d-e862fb86b866 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606228408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2606228408 |
| Directory | /workspace/10.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/10.uart_tx_rx.2964405433 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 12042059976 ps |
| CPU time | 17.63 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:30 PM PDT 24 |
| Peak memory | 198516 kb |
| Host | smart-fcba5944-df9e-45b9-ab99-1ecf6268f581 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2964405433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2964405433 |
| Directory | /workspace/10.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/102.uart_fifo_reset.2120820051 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 111464662843 ps |
| CPU time | 36.35 seconds |
| Started | Jul 12 04:40:58 PM PDT 24 |
| Finished | Jul 12 04:41:38 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-f4f5c096-b670-4c39-9df0-3f42997bd081 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120820051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2120820051 |
| Directory | /workspace/102.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/103.uart_fifo_reset.280512269 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 29544476396 ps |
| CPU time | 11.69 seconds |
| Started | Jul 12 04:40:57 PM PDT 24 |
| Finished | Jul 12 04:41:13 PM PDT 24 |
| Peak memory | 199536 kb |
| Host | smart-94408eeb-ec6f-4708-ae46-24a3feec7003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280512269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.280512269 |
| Directory | /workspace/103.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/105.uart_fifo_reset.3187085440 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 110139426040 ps |
| CPU time | 167.76 seconds |
| Started | Jul 12 04:40:56 PM PDT 24 |
| Finished | Jul 12 04:43:49 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-d4415ee6-f935-4f80-96fe-8960bb57d6c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3187085440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3187085440 |
| Directory | /workspace/105.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/106.uart_fifo_reset.3888499196 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 53420737034 ps |
| CPU time | 45.56 seconds |
| Started | Jul 12 04:40:57 PM PDT 24 |
| Finished | Jul 12 04:41:47 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-319ec1d0-979b-483f-8276-b9fb5b907653 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888499196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3888499196 |
| Directory | /workspace/106.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/108.uart_fifo_reset.2125969742 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 7363420920 ps |
| CPU time | 11.6 seconds |
| Started | Jul 12 04:40:54 PM PDT 24 |
| Finished | Jul 12 04:41:11 PM PDT 24 |
| Peak memory | 199452 kb |
| Host | smart-5582e8ac-3406-4dab-a60a-300abf741de0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125969742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2125969742 |
| Directory | /workspace/108.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_alert_test.2092277070 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 13744214 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:11 PM PDT 24 |
| Peak memory | 195352 kb |
| Host | smart-45bd8052-5b4c-42c6-960a-4f5552969e86 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092277070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2092277070 |
| Directory | /workspace/11.uart_alert_test/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_full.2305479374 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 71165359494 ps |
| CPU time | 110.07 seconds |
| Started | Jul 12 04:38:56 PM PDT 24 |
| Finished | Jul 12 04:40:51 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-91b0e133-5b7c-45c8-84e8-8340fed3f088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2305479374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2305479374 |
| Directory | /workspace/11.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_overflow.3943140505 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 143120655221 ps |
| CPU time | 99.88 seconds |
| Started | Jul 12 04:38:42 PM PDT 24 |
| Finished | Jul 12 04:40:26 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-9ee1f7c1-d05c-4b04-b18c-b3fb489ae182 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943140505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3943140505 |
| Directory | /workspace/11.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_reset.958248342 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 44240823434 ps |
| CPU time | 31.59 seconds |
| Started | Jul 12 04:38:50 PM PDT 24 |
| Finished | Jul 12 04:39:27 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-0b755ac2-e511-4127-83ea-5f9ba32322f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958248342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.958248342 |
| Directory | /workspace/11.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_intr.625775288 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 15495152446 ps |
| CPU time | 29.75 seconds |
| Started | Jul 12 04:38:43 PM PDT 24 |
| Finished | Jul 12 04:39:17 PM PDT 24 |
| Peak memory | 199308 kb |
| Host | smart-c49a89a9-2773-43bb-92f7-f1646cbb2b3f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625775288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.625775288 |
| Directory | /workspace/11.uart_intr/latest |
| Test location | /workspace/coverage/default/11.uart_long_xfer_wo_dly.3122060715 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 32934235833 ps |
| CPU time | 78.17 seconds |
| Started | Jul 12 04:38:56 PM PDT 24 |
| Finished | Jul 12 04:40:18 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-7693cfd6-fa59-4e02-8dc3-af5d7729e419 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3122060715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3122060715 |
| Directory | /workspace/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/11.uart_loopback.772237727 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 6335494381 ps |
| CPU time | 11.59 seconds |
| Started | Jul 12 04:38:56 PM PDT 24 |
| Finished | Jul 12 04:39:12 PM PDT 24 |
| Peak memory | 197592 kb |
| Host | smart-1dc233f3-7553-4f8f-9b13-099dba3d7d01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772237727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.772237727 |
| Directory | /workspace/11.uart_loopback/latest |
| Test location | /workspace/coverage/default/11.uart_noise_filter.157081722 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 23915060970 ps |
| CPU time | 37.27 seconds |
| Started | Jul 12 04:39:00 PM PDT 24 |
| Finished | Jul 12 04:39:41 PM PDT 24 |
| Peak memory | 197484 kb |
| Host | smart-a55275c0-4590-45e6-8051-e95e46855bf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157081722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.157081722 |
| Directory | /workspace/11.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/11.uart_perf.1295101026 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 6301393915 ps |
| CPU time | 78.88 seconds |
| Started | Jul 12 04:38:46 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-90824d50-01f3-4bf0-b6e5-7ab5ae9d0197 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1295101026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1295101026 |
| Directory | /workspace/11.uart_perf/latest |
| Test location | /workspace/coverage/default/11.uart_rx_oversample.3062640216 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 5147914119 ps |
| CPU time | 43.45 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:39:49 PM PDT 24 |
| Peak memory | 199128 kb |
| Host | smart-17d5da01-8533-4111-893c-d489c5327c0c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3062640216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3062640216 |
| Directory | /workspace/11.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/11.uart_rx_parity_err.1592896570 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 59174855763 ps |
| CPU time | 52.6 seconds |
| Started | Jul 12 04:38:49 PM PDT 24 |
| Finished | Jul 12 04:39:47 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-9453295c-5b45-464e-99c8-57aaa09fd337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592896570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1592896570 |
| Directory | /workspace/11.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/11.uart_rx_start_bit_filter.2246347725 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2777806056 ps |
| CPU time | 2.57 seconds |
| Started | Jul 12 04:38:52 PM PDT 24 |
| Finished | Jul 12 04:39:00 PM PDT 24 |
| Peak memory | 195848 kb |
| Host | smart-29947a06-3b45-4e85-91e1-bef8d54080d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246347725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2246347725 |
| Directory | /workspace/11.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/11.uart_smoke.1338494392 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 716348950 ps |
| CPU time | 1.76 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:38:48 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-93b1edfc-626b-4160-a1df-d86866c29fb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338494392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1338494392 |
| Directory | /workspace/11.uart_smoke/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all.2716327740 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 366792080610 ps |
| CPU time | 234.87 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:43:02 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-3b9666bc-4655-415b-9816-6777952d4f25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716327740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2716327740 |
| Directory | /workspace/11.uart_stress_all/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1919161130 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 39743850466 ps |
| CPU time | 221.59 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:42:48 PM PDT 24 |
| Peak memory | 216416 kb |
| Host | smart-bb6be952-8a3a-460d-862a-ac1e0a86356f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919161130 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1919161130 |
| Directory | /workspace/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.uart_tx_ovrd.464356855 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 12247213036 ps |
| CPU time | 44.75 seconds |
| Started | Jul 12 04:38:42 PM PDT 24 |
| Finished | Jul 12 04:39:32 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-14e742e8-3e2f-410e-9bfb-c90373b026cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464356855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.464356855 |
| Directory | /workspace/11.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/11.uart_tx_rx.3526769922 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 24503957463 ps |
| CPU time | 40.08 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:50 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-cc97800a-d9aa-4cdb-af6e-e4c7303d9881 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526769922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3526769922 |
| Directory | /workspace/11.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/110.uart_fifo_reset.1889423223 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 25445675304 ps |
| CPU time | 9.78 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:41:08 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-eaa9b30e-ea78-42a7-82bc-f933053177fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889423223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1889423223 |
| Directory | /workspace/110.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/111.uart_fifo_reset.663802695 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 74248399743 ps |
| CPU time | 26.87 seconds |
| Started | Jul 12 04:40:57 PM PDT 24 |
| Finished | Jul 12 04:41:28 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-9db4711c-7eda-4edf-a7bb-437b2132c3c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663802695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.663802695 |
| Directory | /workspace/111.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/114.uart_fifo_reset.519858912 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 15825203200 ps |
| CPU time | 26.01 seconds |
| Started | Jul 12 04:41:00 PM PDT 24 |
| Finished | Jul 12 04:41:29 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-2aa52b11-4241-4542-a23b-080e3ef04d1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519858912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.519858912 |
| Directory | /workspace/114.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/115.uart_fifo_reset.1054682087 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 16509941493 ps |
| CPU time | 25.45 seconds |
| Started | Jul 12 04:41:02 PM PDT 24 |
| Finished | Jul 12 04:41:30 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-ec265097-4fd6-4cc3-93c3-c61c8525f72b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054682087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1054682087 |
| Directory | /workspace/115.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/116.uart_fifo_reset.955216977 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 24628714678 ps |
| CPU time | 51.7 seconds |
| Started | Jul 12 04:41:02 PM PDT 24 |
| Finished | Jul 12 04:41:56 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-9b2601f8-3ed2-4208-93d4-af34497442fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955216977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.955216977 |
| Directory | /workspace/116.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/117.uart_fifo_reset.953887129 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 15920757395 ps |
| CPU time | 26.67 seconds |
| Started | Jul 12 04:41:00 PM PDT 24 |
| Finished | Jul 12 04:41:30 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-ef2df4a0-2bd0-4126-aa48-7417a5a96d1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953887129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.953887129 |
| Directory | /workspace/117.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/118.uart_fifo_reset.960298546 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 49782588585 ps |
| CPU time | 21.84 seconds |
| Started | Jul 12 04:41:04 PM PDT 24 |
| Finished | Jul 12 04:41:28 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-d918b823-36fd-4271-a21c-16f2aa7483c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960298546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.960298546 |
| Directory | /workspace/118.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/119.uart_fifo_reset.1722375417 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 107131923280 ps |
| CPU time | 48.07 seconds |
| Started | Jul 12 04:41:00 PM PDT 24 |
| Finished | Jul 12 04:41:51 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-9b3a7001-f196-4eb5-8a47-2756f9bf43bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1722375417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1722375417 |
| Directory | /workspace/119.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_alert_test.1277079082 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 44541190 ps |
| CPU time | 0.54 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:39:17 PM PDT 24 |
| Peak memory | 195160 kb |
| Host | smart-888dd402-0e48-490e-bcc8-dbe671872884 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277079082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1277079082 |
| Directory | /workspace/12.uart_alert_test/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_full.251784649 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 86786446055 ps |
| CPU time | 138.46 seconds |
| Started | Jul 12 04:38:58 PM PDT 24 |
| Finished | Jul 12 04:41:20 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-4bd1bdca-b810-4251-aa72-c43f7513d320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251784649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.251784649 |
| Directory | /workspace/12.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_overflow.3860830274 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 68643362651 ps |
| CPU time | 25.26 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:34 PM PDT 24 |
| Peak memory | 199492 kb |
| Host | smart-56308a77-9cd0-4f82-845a-2c8c08cf7dad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860830274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3860830274 |
| Directory | /workspace/12.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_reset.192313942 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 11638740206 ps |
| CPU time | 4.84 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:15 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-82bf658a-ec7f-4474-a99b-3dc466b8dd9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192313942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.192313942 |
| Directory | /workspace/12.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_intr.1097666918 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 32783966524 ps |
| CPU time | 64.38 seconds |
| Started | Jul 12 04:38:51 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-3cac1780-393c-453e-886a-56a584bf3bed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097666918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1097666918 |
| Directory | /workspace/12.uart_intr/latest |
| Test location | /workspace/coverage/default/12.uart_long_xfer_wo_dly.1562281824 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 72305505898 ps |
| CPU time | 215.29 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:42:44 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-734526bf-00ef-49fa-97e7-95ec8c413ecc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1562281824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1562281824 |
| Directory | /workspace/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/12.uart_loopback.384719627 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 6043710342 ps |
| CPU time | 2.91 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:39:07 PM PDT 24 |
| Peak memory | 195556 kb |
| Host | smart-421318f2-4ffd-4e13-a4c0-96fa657d4503 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384719627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.384719627 |
| Directory | /workspace/12.uart_loopback/latest |
| Test location | /workspace/coverage/default/12.uart_noise_filter.282008850 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 633908446 ps |
| CPU time | 1.06 seconds |
| Started | Jul 12 04:38:44 PM PDT 24 |
| Finished | Jul 12 04:38:55 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-a7df0053-a91e-470f-b6df-daa05527ab06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282008850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.282008850 |
| Directory | /workspace/12.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/12.uart_perf.2942061518 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 20242003708 ps |
| CPU time | 1106.57 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:57:43 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-7241fe54-8134-49ef-85a2-786bbc00a20d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2942061518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2942061518 |
| Directory | /workspace/12.uart_perf/latest |
| Test location | /workspace/coverage/default/12.uart_rx_oversample.2035213730 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 6042063853 ps |
| CPU time | 27.55 seconds |
| Started | Jul 12 04:39:00 PM PDT 24 |
| Finished | Jul 12 04:39:31 PM PDT 24 |
| Peak memory | 197932 kb |
| Host | smart-2caaba54-61ec-4370-837c-d0136665500e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2035213730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2035213730 |
| Directory | /workspace/12.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/12.uart_rx_parity_err.1507339540 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 22477961877 ps |
| CPU time | 41.44 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:39:28 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-c068d266-2e87-48e9-aa83-88ae6dc77046 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507339540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1507339540 |
| Directory | /workspace/12.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/12.uart_rx_start_bit_filter.486073800 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 4869345250 ps |
| CPU time | 7.28 seconds |
| Started | Jul 12 04:38:56 PM PDT 24 |
| Finished | Jul 12 04:39:08 PM PDT 24 |
| Peak memory | 196308 kb |
| Host | smart-77c7d546-2dbb-408c-8ccd-88749eb6e34b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486073800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.486073800 |
| Directory | /workspace/12.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/12.uart_smoke.1962622738 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 10544943761 ps |
| CPU time | 22.61 seconds |
| Started | Jul 12 04:38:55 PM PDT 24 |
| Finished | Jul 12 04:39:23 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-5bc50e9d-3bea-4580-a3be-4f2672e3b680 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962622738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1962622738 |
| Directory | /workspace/12.uart_smoke/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all.595482880 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 312509888842 ps |
| CPU time | 1605.14 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 05:05:56 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-abb685cb-8c13-4308-a9fa-2c8fdc6e8c48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595482880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.595482880 |
| Directory | /workspace/12.uart_stress_all/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all_with_rand_reset.590015726 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 96634062909 ps |
| CPU time | 523.35 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:47:57 PM PDT 24 |
| Peak memory | 212900 kb |
| Host | smart-7f4995b6-a141-463e-9c44-cf33da0d6efb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590015726 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.590015726 |
| Directory | /workspace/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.uart_tx_ovrd.3895598172 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 1695736695 ps |
| CPU time | 1.7 seconds |
| Started | Jul 12 04:38:55 PM PDT 24 |
| Finished | Jul 12 04:39:01 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-5d2519d6-3cdf-4317-8c28-fd4b92042a10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895598172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3895598172 |
| Directory | /workspace/12.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/12.uart_tx_rx.1386543937 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 49541928798 ps |
| CPU time | 41.13 seconds |
| Started | Jul 12 04:38:57 PM PDT 24 |
| Finished | Jul 12 04:39:42 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-c86cb439-6893-45a8-b517-593b8edd0fa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386543937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1386543937 |
| Directory | /workspace/12.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/120.uart_fifo_reset.2008770495 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 24073883683 ps |
| CPU time | 28.09 seconds |
| Started | Jul 12 04:40:58 PM PDT 24 |
| Finished | Jul 12 04:41:30 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-35121776-ff18-4ecf-bccb-14ff63d6229e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2008770495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2008770495 |
| Directory | /workspace/120.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/121.uart_fifo_reset.2534892232 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 13727367083 ps |
| CPU time | 23.43 seconds |
| Started | Jul 12 04:41:04 PM PDT 24 |
| Finished | Jul 12 04:41:29 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-689ca41f-e213-4ba7-bfaf-8d9b9e153589 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534892232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2534892232 |
| Directory | /workspace/121.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/123.uart_fifo_reset.3859430582 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 40971763806 ps |
| CPU time | 64.41 seconds |
| Started | Jul 12 04:41:00 PM PDT 24 |
| Finished | Jul 12 04:42:07 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-0ec75e36-83a5-4a4b-85ec-e03517563c93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3859430582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3859430582 |
| Directory | /workspace/123.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/124.uart_fifo_reset.3986380644 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 39637327962 ps |
| CPU time | 48.53 seconds |
| Started | Jul 12 04:41:03 PM PDT 24 |
| Finished | Jul 12 04:41:54 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-e48b7ac7-2acc-4e32-aae4-4dd53aa49fb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986380644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3986380644 |
| Directory | /workspace/124.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/125.uart_fifo_reset.119993575 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 233658456247 ps |
| CPU time | 209.07 seconds |
| Started | Jul 12 04:41:00 PM PDT 24 |
| Finished | Jul 12 04:44:32 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-a1e9d544-d80f-49c7-a85f-7a03b50c5400 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119993575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.119993575 |
| Directory | /workspace/125.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/126.uart_fifo_reset.2838343801 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 111625617927 ps |
| CPU time | 38.59 seconds |
| Started | Jul 12 04:41:03 PM PDT 24 |
| Finished | Jul 12 04:41:44 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-3b50df92-1a0c-49ad-b10a-52a2cfd1f5ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838343801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2838343801 |
| Directory | /workspace/126.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/128.uart_fifo_reset.3046829782 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 28223291509 ps |
| CPU time | 48.3 seconds |
| Started | Jul 12 04:41:01 PM PDT 24 |
| Finished | Jul 12 04:41:52 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-6dddcf76-95de-4524-8880-79dadc15d5e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046829782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3046829782 |
| Directory | /workspace/128.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/129.uart_fifo_reset.1484144357 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 60586092690 ps |
| CPU time | 21.65 seconds |
| Started | Jul 12 04:41:02 PM PDT 24 |
| Finished | Jul 12 04:41:26 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-9e17b891-f720-4327-8924-e3f3b9417a3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484144357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1484144357 |
| Directory | /workspace/129.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_alert_test.561391900 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 40544525 ps |
| CPU time | 0.54 seconds |
| Started | Jul 12 04:38:59 PM PDT 24 |
| Finished | Jul 12 04:39:03 PM PDT 24 |
| Peak memory | 195092 kb |
| Host | smart-90647516-11f5-48e4-bcf4-407a8bf0681a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561391900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.561391900 |
| Directory | /workspace/13.uart_alert_test/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_full.2980810148 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 33216590589 ps |
| CPU time | 57.47 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-5f95ecf7-589f-40b3-a2cb-06ae14e94f41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980810148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2980810148 |
| Directory | /workspace/13.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_overflow.256155766 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 34762283992 ps |
| CPU time | 53.61 seconds |
| Started | Jul 12 04:39:09 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-ff4f9e65-a92c-4cda-aa25-65e5ae2c7e98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256155766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.256155766 |
| Directory | /workspace/13.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_reset.935095209 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 33661391897 ps |
| CPU time | 54.43 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:40:06 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-122282e8-6d27-40c8-afc2-ddef389630a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935095209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.935095209 |
| Directory | /workspace/13.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_intr.1566146983 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 79072632038 ps |
| CPU time | 148.29 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:41:43 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-150ecd44-dc74-45f9-bd00-3c5587f74f26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566146983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1566146983 |
| Directory | /workspace/13.uart_intr/latest |
| Test location | /workspace/coverage/default/13.uart_loopback.3074035263 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2674971671 ps |
| CPU time | 2.41 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:09 PM PDT 24 |
| Peak memory | 198720 kb |
| Host | smart-3bfcbaf1-790e-4443-9f9f-2af98646c47e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074035263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3074035263 |
| Directory | /workspace/13.uart_loopback/latest |
| Test location | /workspace/coverage/default/13.uart_noise_filter.4073038788 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 87481165558 ps |
| CPU time | 27.1 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:39 PM PDT 24 |
| Peak memory | 199516 kb |
| Host | smart-4a4a0dcd-e0cd-4985-b3ec-0f3972beb2d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073038788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.4073038788 |
| Directory | /workspace/13.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/13.uart_rx_oversample.4122032027 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5786085356 ps |
| CPU time | 10.3 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:39:24 PM PDT 24 |
| Peak memory | 199240 kb |
| Host | smart-bc91ed81-97ff-4c1c-aeb5-d562eebe2d7a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4122032027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4122032027 |
| Directory | /workspace/13.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/13.uart_rx_parity_err.32430923 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 30635603842 ps |
| CPU time | 32.4 seconds |
| Started | Jul 12 04:38:57 PM PDT 24 |
| Finished | Jul 12 04:39:34 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-68ae4abe-0277-4593-80b7-2f6e0d29e915 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32430923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.32430923 |
| Directory | /workspace/13.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/13.uart_rx_start_bit_filter.1684200604 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 4419286422 ps |
| CPU time | 2.13 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:11 PM PDT 24 |
| Peak memory | 196140 kb |
| Host | smart-f0dc5098-1c87-437b-8525-20ffce9b28b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684200604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1684200604 |
| Directory | /workspace/13.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/13.uart_smoke.2135868959 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 448239966 ps |
| CPU time | 2.29 seconds |
| Started | Jul 12 04:38:54 PM PDT 24 |
| Finished | Jul 12 04:39:01 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-42ac5c34-ae3d-4f25-a608-a3b3b063add8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135868959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2135868959 |
| Directory | /workspace/13.uart_smoke/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3156534711 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 58883688653 ps |
| CPU time | 603.71 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:49:17 PM PDT 24 |
| Peak memory | 228396 kb |
| Host | smart-fe9970a3-dcef-48e5-9c9c-4852155978b4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156534711 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3156534711 |
| Directory | /workspace/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.uart_tx_ovrd.1825478070 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 770956100 ps |
| CPU time | 2.11 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:08 PM PDT 24 |
| Peak memory | 198312 kb |
| Host | smart-be406cbe-f997-415f-9db1-d627c079ee44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825478070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1825478070 |
| Directory | /workspace/13.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/13.uart_tx_rx.2794384410 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 55759929813 ps |
| CPU time | 47.78 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:39:53 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-25002506-b7e3-441c-aaeb-330841f30fc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794384410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2794384410 |
| Directory | /workspace/13.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/130.uart_fifo_reset.1087525822 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 17284334694 ps |
| CPU time | 25.21 seconds |
| Started | Jul 12 04:41:01 PM PDT 24 |
| Finished | Jul 12 04:41:29 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-c35510bf-9135-4d2a-87e3-d5413b4528da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087525822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1087525822 |
| Directory | /workspace/130.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/131.uart_fifo_reset.2044921267 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 23737913297 ps |
| CPU time | 16 seconds |
| Started | Jul 12 04:41:01 PM PDT 24 |
| Finished | Jul 12 04:41:20 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-533b356f-67f4-46d8-96f2-9d91f54572ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044921267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2044921267 |
| Directory | /workspace/131.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/132.uart_fifo_reset.591853348 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 39487325760 ps |
| CPU time | 28.82 seconds |
| Started | Jul 12 04:41:03 PM PDT 24 |
| Finished | Jul 12 04:41:34 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-9bd0c237-ad05-472c-96ea-bf4fd4b9d250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591853348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.591853348 |
| Directory | /workspace/132.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/134.uart_fifo_reset.1050356987 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 21763919360 ps |
| CPU time | 13.66 seconds |
| Started | Jul 12 04:41:06 PM PDT 24 |
| Finished | Jul 12 04:41:21 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-393bcead-aa31-4d76-a696-fddfbfaf1604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050356987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1050356987 |
| Directory | /workspace/134.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/135.uart_fifo_reset.986401509 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 143095390903 ps |
| CPU time | 102.31 seconds |
| Started | Jul 12 04:41:04 PM PDT 24 |
| Finished | Jul 12 04:42:48 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-fa1dec9b-c05e-40bd-8ff0-a5ca0c32d7a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986401509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.986401509 |
| Directory | /workspace/135.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/136.uart_fifo_reset.2872077205 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 45900273911 ps |
| CPU time | 89.64 seconds |
| Started | Jul 12 04:41:02 PM PDT 24 |
| Finished | Jul 12 04:42:34 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-fcd9ec9d-06dc-4de8-b8a4-506ba8950816 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872077205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2872077205 |
| Directory | /workspace/136.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/137.uart_fifo_reset.1600049599 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 62814513712 ps |
| CPU time | 85.18 seconds |
| Started | Jul 12 04:41:02 PM PDT 24 |
| Finished | Jul 12 04:42:30 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-874d3bf8-db7d-4397-9fae-8c8e4b23ea64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600049599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1600049599 |
| Directory | /workspace/137.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/138.uart_fifo_reset.1765442817 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 101776668904 ps |
| CPU time | 88.98 seconds |
| Started | Jul 12 04:41:01 PM PDT 24 |
| Finished | Jul 12 04:42:33 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-4dcd8f2d-fe81-4f74-917c-f9715e325d39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765442817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1765442817 |
| Directory | /workspace/138.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_alert_test.283252256 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 65608292 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:18 PM PDT 24 |
| Peak memory | 195504 kb |
| Host | smart-a0830751-20b4-4b11-9f18-e9e188d0d8cc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283252256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.283252256 |
| Directory | /workspace/14.uart_alert_test/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_full.1060527111 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 156206463145 ps |
| CPU time | 162.08 seconds |
| Started | Jul 12 04:38:59 PM PDT 24 |
| Finished | Jul 12 04:41:44 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-07464ed2-2644-43fd-a9f8-45bc5d910747 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060527111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1060527111 |
| Directory | /workspace/14.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_overflow.2770377871 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 26271338471 ps |
| CPU time | 39.46 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:47 PM PDT 24 |
| Peak memory | 198660 kb |
| Host | smart-ba76cbd4-2d64-43f9-b307-0f763c9e26cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770377871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2770377871 |
| Directory | /workspace/14.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_reset.903468152 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 113515755433 ps |
| CPU time | 149.59 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:41:40 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-d6d177fe-a7d8-448a-acf7-93ab2daae02b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903468152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.903468152 |
| Directory | /workspace/14.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_intr.3033996716 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 178155796412 ps |
| CPU time | 157.81 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:41:49 PM PDT 24 |
| Peak memory | 199340 kb |
| Host | smart-7e8e079f-b4f7-48fd-9114-1d57e2d47d69 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033996716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3033996716 |
| Directory | /workspace/14.uart_intr/latest |
| Test location | /workspace/coverage/default/14.uart_long_xfer_wo_dly.3035172125 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 169880972100 ps |
| CPU time | 465.48 seconds |
| Started | Jul 12 04:38:58 PM PDT 24 |
| Finished | Jul 12 04:46:47 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-037c8367-0f2e-4fb6-930f-b13a9e4b4a89 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3035172125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3035172125 |
| Directory | /workspace/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/14.uart_loopback.812282243 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 14607351858 ps |
| CPU time | 10.86 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:24 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-126ac692-1842-4de0-a546-9e8437c31ec4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812282243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.812282243 |
| Directory | /workspace/14.uart_loopback/latest |
| Test location | /workspace/coverage/default/14.uart_noise_filter.1842119778 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 88267425220 ps |
| CPU time | 35.09 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:49 PM PDT 24 |
| Peak memory | 198300 kb |
| Host | smart-76a7bf14-3a6a-405e-9195-789d51dac45d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842119778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1842119778 |
| Directory | /workspace/14.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/14.uart_perf.2457400947 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4815614275 ps |
| CPU time | 234.67 seconds |
| Started | Jul 12 04:38:52 PM PDT 24 |
| Finished | Jul 12 04:42:52 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-97cb7ca4-e583-4184-82e3-eebe24a9998e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2457400947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2457400947 |
| Directory | /workspace/14.uart_perf/latest |
| Test location | /workspace/coverage/default/14.uart_rx_oversample.3993593449 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 6592887795 ps |
| CPU time | 62.64 seconds |
| Started | Jul 12 04:38:50 PM PDT 24 |
| Finished | Jul 12 04:39:59 PM PDT 24 |
| Peak memory | 198256 kb |
| Host | smart-2c32fb08-0cc6-48ad-9806-cafbf11895a7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3993593449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3993593449 |
| Directory | /workspace/14.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/14.uart_rx_parity_err.282858530 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 163643404775 ps |
| CPU time | 68.04 seconds |
| Started | Jul 12 04:38:57 PM PDT 24 |
| Finished | Jul 12 04:40:09 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-169e0923-7db9-4cd9-9d1e-568ce2c48840 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282858530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.282858530 |
| Directory | /workspace/14.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/14.uart_rx_start_bit_filter.4126946417 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 88861052498 ps |
| CPU time | 139.13 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:41:32 PM PDT 24 |
| Peak memory | 195856 kb |
| Host | smart-3c36b9f2-8fc3-4f5f-836d-72e3ff353ac9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126946417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4126946417 |
| Directory | /workspace/14.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/14.uart_smoke.94697206 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 313247985 ps |
| CPU time | 0.92 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:39:05 PM PDT 24 |
| Peak memory | 198488 kb |
| Host | smart-1b55496b-a024-4deb-8f97-60baf9f164c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94697206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.94697206 |
| Directory | /workspace/14.uart_smoke/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all.2312808785 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 504339659622 ps |
| CPU time | 2550.3 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 05:21:43 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-a558219d-c3d3-424f-b8f7-e0e27448f776 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312808785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2312808785 |
| Directory | /workspace/14.uart_stress_all/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2483292380 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 216960815652 ps |
| CPU time | 536.3 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:48:13 PM PDT 24 |
| Peak memory | 224900 kb |
| Host | smart-84b1482d-6103-42eb-b863-fb7116f1ffd7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483292380 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2483292380 |
| Directory | /workspace/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.uart_tx_ovrd.451933314 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 739715978 ps |
| CPU time | 4.09 seconds |
| Started | Jul 12 04:39:10 PM PDT 24 |
| Finished | Jul 12 04:39:22 PM PDT 24 |
| Peak memory | 198132 kb |
| Host | smart-1558c383-9044-4e89-a8af-8bf7f6c6958e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451933314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.451933314 |
| Directory | /workspace/14.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/14.uart_tx_rx.737324351 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 28086581818 ps |
| CPU time | 21.64 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:35 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-0f14dfd6-5121-4591-97ed-5146b078b065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737324351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.737324351 |
| Directory | /workspace/14.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/140.uart_fifo_reset.803258825 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 70118292152 ps |
| CPU time | 173.79 seconds |
| Started | Jul 12 04:41:01 PM PDT 24 |
| Finished | Jul 12 04:43:58 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-e85bce67-0cc5-4838-865a-a0a76bc6c6b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803258825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.803258825 |
| Directory | /workspace/140.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/141.uart_fifo_reset.2394464542 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5310554904 ps |
| CPU time | 14.37 seconds |
| Started | Jul 12 04:41:04 PM PDT 24 |
| Finished | Jul 12 04:41:20 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-8f156e9e-6947-41f6-bd8e-226653f45373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394464542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2394464542 |
| Directory | /workspace/141.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/142.uart_fifo_reset.3538262846 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 35048583254 ps |
| CPU time | 30.78 seconds |
| Started | Jul 12 04:41:02 PM PDT 24 |
| Finished | Jul 12 04:41:36 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-d4eeaa11-c930-4dda-af80-dd82ddd4e630 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538262846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3538262846 |
| Directory | /workspace/142.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/143.uart_fifo_reset.2043046977 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 113071606185 ps |
| CPU time | 78.86 seconds |
| Started | Jul 12 04:41:03 PM PDT 24 |
| Finished | Jul 12 04:42:24 PM PDT 24 |
| Peak memory | 199404 kb |
| Host | smart-5e64d0b9-11c8-4f24-9f95-849f7b66fd4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043046977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2043046977 |
| Directory | /workspace/143.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/144.uart_fifo_reset.3777542351 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 44888523282 ps |
| CPU time | 16.16 seconds |
| Started | Jul 12 04:41:00 PM PDT 24 |
| Finished | Jul 12 04:41:20 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-295c9376-fbaa-4177-a5b2-598617c97ecd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777542351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3777542351 |
| Directory | /workspace/144.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/146.uart_fifo_reset.2953825701 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 99827000318 ps |
| CPU time | 166.72 seconds |
| Started | Jul 12 04:41:05 PM PDT 24 |
| Finished | Jul 12 04:43:53 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-d0f7c3e1-4d92-4fdc-ba1e-01e26031f1c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2953825701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2953825701 |
| Directory | /workspace/146.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/148.uart_fifo_reset.3273854355 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 102693606562 ps |
| CPU time | 155.38 seconds |
| Started | Jul 12 04:41:06 PM PDT 24 |
| Finished | Jul 12 04:43:43 PM PDT 24 |
| Peak memory | 199956 kb |
| Host | smart-4f39e3e6-9299-4d1f-8a9b-4921e5b7c4c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273854355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3273854355 |
| Directory | /workspace/148.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/149.uart_fifo_reset.4088710816 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 8861251932 ps |
| CPU time | 15.39 seconds |
| Started | Jul 12 04:41:07 PM PDT 24 |
| Finished | Jul 12 04:41:23 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-98edd973-0e72-424a-9869-65f5179e5d74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4088710816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4088710816 |
| Directory | /workspace/149.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_alert_test.2055553759 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 11599031 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:11 PM PDT 24 |
| Peak memory | 195108 kb |
| Host | smart-0834f161-84df-4687-9287-af447d3b4167 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055553759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2055553759 |
| Directory | /workspace/15.uart_alert_test/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_full.2157056456 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 221991131411 ps |
| CPU time | 215.69 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:42:43 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-d4550e0a-1586-48bd-8d42-4c0e2e783a34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157056456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2157056456 |
| Directory | /workspace/15.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_overflow.780483746 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 145832261481 ps |
| CPU time | 82.36 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:40:35 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-75ddb363-f4d5-4668-8d68-ba8cb0bd15fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780483746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.780483746 |
| Directory | /workspace/15.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_reset.3308766050 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 25068869117 ps |
| CPU time | 38.92 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:39:53 PM PDT 24 |
| Peak memory | 199960 kb |
| Host | smart-7df5fe8b-97da-45cd-baf3-f3e9c86d8fd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308766050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3308766050 |
| Directory | /workspace/15.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_intr.1216699613 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 26592576849 ps |
| CPU time | 43.16 seconds |
| Started | Jul 12 04:39:14 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 199584 kb |
| Host | smart-7941a7a2-c7d2-4433-a9e7-1270c00b4b4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216699613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1216699613 |
| Directory | /workspace/15.uart_intr/latest |
| Test location | /workspace/coverage/default/15.uart_long_xfer_wo_dly.809466700 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 99727652366 ps |
| CPU time | 172.46 seconds |
| Started | Jul 12 04:39:12 PM PDT 24 |
| Finished | Jul 12 04:42:12 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-1d2164e1-40c5-41d1-bd1d-cc9211240eb2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=809466700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.809466700 |
| Directory | /workspace/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/15.uart_loopback.484277754 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3794119870 ps |
| CPU time | 2.62 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:39:21 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-c9db95da-cc57-42c3-8883-328181ab4480 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=484277754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.484277754 |
| Directory | /workspace/15.uart_loopback/latest |
| Test location | /workspace/coverage/default/15.uart_noise_filter.3321704132 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 162317504656 ps |
| CPU time | 323.86 seconds |
| Started | Jul 12 04:39:10 PM PDT 24 |
| Finished | Jul 12 04:44:41 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-25fa2376-a5d3-4651-a0e0-d1811d286b96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321704132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3321704132 |
| Directory | /workspace/15.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/15.uart_perf.3568917067 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 7584461291 ps |
| CPU time | 219.48 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:42:50 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-d2177f92-0c2f-4b10-88f6-a53ea89bfd9a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3568917067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3568917067 |
| Directory | /workspace/15.uart_perf/latest |
| Test location | /workspace/coverage/default/15.uart_rx_oversample.444197459 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1606874994 ps |
| CPU time | 1.87 seconds |
| Started | Jul 12 04:38:55 PM PDT 24 |
| Finished | Jul 12 04:39:02 PM PDT 24 |
| Peak memory | 198220 kb |
| Host | smart-58684cb5-cfde-44b6-b42f-0a5e44d92340 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=444197459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.444197459 |
| Directory | /workspace/15.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/15.uart_rx_parity_err.3352834816 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 151471826921 ps |
| CPU time | 160.52 seconds |
| Started | Jul 12 04:38:57 PM PDT 24 |
| Finished | Jul 12 04:41:42 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-ed35d29a-8814-4399-b5a5-13de37792cc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352834816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3352834816 |
| Directory | /workspace/15.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/15.uart_rx_start_bit_filter.385843051 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 4105646249 ps |
| CPU time | 6.82 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:13 PM PDT 24 |
| Peak memory | 196032 kb |
| Host | smart-18b31dd0-84be-43cf-a955-81adaa746e18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385843051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.385843051 |
| Directory | /workspace/15.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/15.uart_smoke.2568900619 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 719892702 ps |
| CPU time | 1.65 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:39:16 PM PDT 24 |
| Peak memory | 198104 kb |
| Host | smart-435d62fd-eb4e-43f4-9d8d-ee38db7ca5fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568900619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2568900619 |
| Directory | /workspace/15.uart_smoke/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all.1785207108 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 397138260260 ps |
| CPU time | 936.94 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:54:46 PM PDT 24 |
| Peak memory | 200000 kb |
| Host | smart-0ede7094-8048-46c9-b071-b52f850cc380 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785207108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1785207108 |
| Directory | /workspace/15.uart_stress_all/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1929626076 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 1502000741 ps |
| CPU time | 16.15 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:39:35 PM PDT 24 |
| Peak memory | 208084 kb |
| Host | smart-1e0bf911-d0ce-49db-9b88-924b01760d2f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929626076 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1929626076 |
| Directory | /workspace/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.uart_tx_ovrd.3888622919 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 2681377057 ps |
| CPU time | 1.8 seconds |
| Started | Jul 12 04:39:07 PM PDT 24 |
| Finished | Jul 12 04:39:17 PM PDT 24 |
| Peak memory | 198704 kb |
| Host | smart-863e632e-0389-4a24-931e-f2168ba75c17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888622919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3888622919 |
| Directory | /workspace/15.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/15.uart_tx_rx.165602030 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 8952865971 ps |
| CPU time | 17.04 seconds |
| Started | Jul 12 04:39:19 PM PDT 24 |
| Finished | Jul 12 04:39:41 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-c7fb5998-d8af-422b-868a-8c4249222766 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165602030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.165602030 |
| Directory | /workspace/15.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/150.uart_fifo_reset.2401052101 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 200759702536 ps |
| CPU time | 83.62 seconds |
| Started | Jul 12 04:41:06 PM PDT 24 |
| Finished | Jul 12 04:42:31 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-ca8a2f9d-ba21-430c-b8a2-858f269679df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2401052101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2401052101 |
| Directory | /workspace/150.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/151.uart_fifo_reset.850560875 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 17027774670 ps |
| CPU time | 21.82 seconds |
| Started | Jul 12 04:41:09 PM PDT 24 |
| Finished | Jul 12 04:41:31 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-fb14f6cc-0e57-48a2-ae07-493b3a849b9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850560875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.850560875 |
| Directory | /workspace/151.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/152.uart_fifo_reset.2280251527 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 118796024920 ps |
| CPU time | 37.82 seconds |
| Started | Jul 12 04:41:48 PM PDT 24 |
| Finished | Jul 12 04:42:27 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-c514ce89-bf08-45ec-bc8e-1755e0bf0898 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280251527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2280251527 |
| Directory | /workspace/152.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/153.uart_fifo_reset.1634665567 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 23345989813 ps |
| CPU time | 48.11 seconds |
| Started | Jul 12 04:41:13 PM PDT 24 |
| Finished | Jul 12 04:42:02 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-79258dd1-2517-4265-a81c-5df8006afab1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634665567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1634665567 |
| Directory | /workspace/153.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/154.uart_fifo_reset.4068839754 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 27433573599 ps |
| CPU time | 45.66 seconds |
| Started | Jul 12 04:41:05 PM PDT 24 |
| Finished | Jul 12 04:41:52 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-b2c36a88-2736-466f-b71c-8a25af1420cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068839754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4068839754 |
| Directory | /workspace/154.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/155.uart_fifo_reset.2899929866 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 50322970613 ps |
| CPU time | 35.54 seconds |
| Started | Jul 12 04:41:07 PM PDT 24 |
| Finished | Jul 12 04:41:43 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-7c1ca15f-5af8-4d6c-8922-63780c086a50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899929866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2899929866 |
| Directory | /workspace/155.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/156.uart_fifo_reset.2815361664 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 24952370040 ps |
| CPU time | 11.54 seconds |
| Started | Jul 12 04:41:10 PM PDT 24 |
| Finished | Jul 12 04:41:23 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-c6db7e11-3c3d-498a-a5f1-54aa4feb615e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815361664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2815361664 |
| Directory | /workspace/156.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/159.uart_fifo_reset.2961317618 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 15604940437 ps |
| CPU time | 25.46 seconds |
| Started | Jul 12 04:41:05 PM PDT 24 |
| Finished | Jul 12 04:41:32 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-0bae5f36-3b17-4ea9-89a9-94f6fd7b78a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961317618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2961317618 |
| Directory | /workspace/159.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_alert_test.3428761710 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 67505367 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:39:10 PM PDT 24 |
| Finished | Jul 12 04:39:18 PM PDT 24 |
| Peak memory | 195180 kb |
| Host | smart-f6421bc6-5e19-40fd-93ce-dbbd72284f39 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428761710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3428761710 |
| Directory | /workspace/16.uart_alert_test/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_full.3773027981 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 46313773280 ps |
| CPU time | 32.23 seconds |
| Started | Jul 12 04:39:19 PM PDT 24 |
| Finished | Jul 12 04:39:56 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-42e9c358-1337-4e4d-b1bf-339c2749bd6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773027981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3773027981 |
| Directory | /workspace/16.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_overflow.2614362331 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 58468577327 ps |
| CPU time | 30.3 seconds |
| Started | Jul 12 04:39:10 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-1074fa7e-08a9-4943-bb3e-c28e1b9adab1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614362331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2614362331 |
| Directory | /workspace/16.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_reset.1415151917 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 205981756595 ps |
| CPU time | 20.74 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:34 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-d168469a-5d17-411b-9b8e-e6c1c8fd2f40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415151917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1415151917 |
| Directory | /workspace/16.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_intr.3355433250 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 17116052816 ps |
| CPU time | 7.3 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:20 PM PDT 24 |
| Peak memory | 196800 kb |
| Host | smart-f4eb023a-0acd-4888-8a16-02719c68ea96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355433250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3355433250 |
| Directory | /workspace/16.uart_intr/latest |
| Test location | /workspace/coverage/default/16.uart_long_xfer_wo_dly.2455880986 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 90115148130 ps |
| CPU time | 564.69 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:48:41 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-267e43c7-5350-4a1c-a449-a71832cdab94 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2455880986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2455880986 |
| Directory | /workspace/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/16.uart_loopback.3829154900 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4779837159 ps |
| CPU time | 7.5 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:39:24 PM PDT 24 |
| Peak memory | 198768 kb |
| Host | smart-9b7518ec-b169-487f-bef2-a92d5d414487 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829154900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3829154900 |
| Directory | /workspace/16.uart_loopback/latest |
| Test location | /workspace/coverage/default/16.uart_noise_filter.2389063356 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 7189656185 ps |
| CPU time | 10.96 seconds |
| Started | Jul 12 04:39:14 PM PDT 24 |
| Finished | Jul 12 04:39:31 PM PDT 24 |
| Peak memory | 194976 kb |
| Host | smart-ebce5cb5-2f3c-4b9b-a65c-9e7960a3e787 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389063356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2389063356 |
| Directory | /workspace/16.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/16.uart_perf.2291691802 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 18786041550 ps |
| CPU time | 167.59 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199956 kb |
| Host | smart-50a494bb-b306-4949-bf7e-68fe4a7c64f3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2291691802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2291691802 |
| Directory | /workspace/16.uart_perf/latest |
| Test location | /workspace/coverage/default/16.uart_rx_oversample.1901616061 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2222184379 ps |
| CPU time | 6.95 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:39:21 PM PDT 24 |
| Peak memory | 198024 kb |
| Host | smart-23bd1e26-2be0-47d9-b397-769cfdbac630 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1901616061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1901616061 |
| Directory | /workspace/16.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/16.uart_rx_parity_err.1729599130 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 130451532455 ps |
| CPU time | 43.33 seconds |
| Started | Jul 12 04:39:24 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-a3d124b8-e989-43ca-bf5b-d1b155ac65f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729599130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1729599130 |
| Directory | /workspace/16.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/16.uart_rx_start_bit_filter.2294269907 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 1892737339 ps |
| CPU time | 3.29 seconds |
| Started | Jul 12 04:39:10 PM PDT 24 |
| Finished | Jul 12 04:39:21 PM PDT 24 |
| Peak memory | 195336 kb |
| Host | smart-31913ca5-7981-4277-a74a-eb5530761d71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294269907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2294269907 |
| Directory | /workspace/16.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/16.uart_smoke.827681802 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5794375835 ps |
| CPU time | 14.92 seconds |
| Started | Jul 12 04:38:56 PM PDT 24 |
| Finished | Jul 12 04:39:15 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-55bed75a-d82e-476f-bc1a-77e9bac167cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827681802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.827681802 |
| Directory | /workspace/16.uart_smoke/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all.34549772 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 123928563109 ps |
| CPU time | 713.58 seconds |
| Started | Jul 12 04:39:07 PM PDT 24 |
| Finished | Jul 12 04:51:09 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-0d84a884-6e94-4ed1-b7b3-5da56ce9e93f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34549772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.34549772 |
| Directory | /workspace/16.uart_stress_all/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2625207350 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 37279516238 ps |
| CPU time | 307.07 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:44:21 PM PDT 24 |
| Peak memory | 208096 kb |
| Host | smart-49fe2528-47cd-4596-8bbf-80b5b87153cc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625207350 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2625207350 |
| Directory | /workspace/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.uart_tx_ovrd.4045097642 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 6106544300 ps |
| CPU time | 17.43 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:28 PM PDT 24 |
| Peak memory | 199248 kb |
| Host | smart-f9f30e14-c20f-4c7c-afff-614714daa693 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045097642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4045097642 |
| Directory | /workspace/16.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/16.uart_tx_rx.2014958131 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 7696037705 ps |
| CPU time | 12.14 seconds |
| Started | Jul 12 04:38:56 PM PDT 24 |
| Finished | Jul 12 04:39:13 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-ae739ffa-9025-4ad0-a8a8-5866ab865147 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014958131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2014958131 |
| Directory | /workspace/16.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/160.uart_fifo_reset.611028856 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 67451810179 ps |
| CPU time | 27.74 seconds |
| Started | Jul 12 04:41:09 PM PDT 24 |
| Finished | Jul 12 04:41:37 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-b9b98f90-2493-4dc1-8e6e-279f61ce44be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=611028856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.611028856 |
| Directory | /workspace/160.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/161.uart_fifo_reset.1871350684 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 58893036296 ps |
| CPU time | 93.84 seconds |
| Started | Jul 12 04:41:07 PM PDT 24 |
| Finished | Jul 12 04:42:42 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-4d2ef62f-fdc7-4ea0-9d53-7a973ee8e021 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871350684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1871350684 |
| Directory | /workspace/161.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/162.uart_fifo_reset.3004851032 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 17894751539 ps |
| CPU time | 16.49 seconds |
| Started | Jul 12 04:41:06 PM PDT 24 |
| Finished | Jul 12 04:41:24 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-527a0a9d-9f22-46dc-85ae-357d70e29918 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004851032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3004851032 |
| Directory | /workspace/162.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/163.uart_fifo_reset.4123254955 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 18483350666 ps |
| CPU time | 32.44 seconds |
| Started | Jul 12 04:41:08 PM PDT 24 |
| Finished | Jul 12 04:41:41 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-b68c6663-824c-4267-9d74-d8a419cbde39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123254955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4123254955 |
| Directory | /workspace/163.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/164.uart_fifo_reset.1027612029 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 162398764014 ps |
| CPU time | 23.43 seconds |
| Started | Jul 12 04:41:11 PM PDT 24 |
| Finished | Jul 12 04:41:35 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-cb2b6e38-08e7-4f2a-a009-6f9859ddaaa2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027612029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1027612029 |
| Directory | /workspace/164.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/165.uart_fifo_reset.25082186 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 80497972454 ps |
| CPU time | 59.21 seconds |
| Started | Jul 12 04:41:07 PM PDT 24 |
| Finished | Jul 12 04:42:07 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-2f4d707f-5afb-4ab3-800b-1fcd4dcde3fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25082186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.25082186 |
| Directory | /workspace/165.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/166.uart_fifo_reset.1321476260 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 21045828610 ps |
| CPU time | 43.95 seconds |
| Started | Jul 12 04:41:13 PM PDT 24 |
| Finished | Jul 12 04:41:57 PM PDT 24 |
| Peak memory | 199964 kb |
| Host | smart-ed769bb1-3743-4e52-ad43-e21d91d579d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321476260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1321476260 |
| Directory | /workspace/166.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/167.uart_fifo_reset.1938121612 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 71677828105 ps |
| CPU time | 38.17 seconds |
| Started | Jul 12 04:41:11 PM PDT 24 |
| Finished | Jul 12 04:41:50 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-cd713b04-c347-4676-8854-18688723d137 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938121612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1938121612 |
| Directory | /workspace/167.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/168.uart_fifo_reset.1303176546 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 92851701537 ps |
| CPU time | 27.3 seconds |
| Started | Jul 12 04:41:05 PM PDT 24 |
| Finished | Jul 12 04:41:34 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-b9db52b4-d5ae-4ff0-925d-346e8f7507dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303176546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1303176546 |
| Directory | /workspace/168.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/169.uart_fifo_reset.165584996 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 87150825160 ps |
| CPU time | 27.08 seconds |
| Started | Jul 12 04:41:15 PM PDT 24 |
| Finished | Jul 12 04:41:43 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-559311bf-6458-4b7c-ba55-fae356e54593 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165584996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.165584996 |
| Directory | /workspace/169.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_alert_test.1299271843 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 14639151 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:39:19 PM PDT 24 |
| Peak memory | 195188 kb |
| Host | smart-d64ece9f-964b-44fd-accb-eb8c39c392b6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299271843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1299271843 |
| Directory | /workspace/17.uart_alert_test/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_full.1771285129 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 171479023466 ps |
| CPU time | 141.26 seconds |
| Started | Jul 12 04:39:18 PM PDT 24 |
| Finished | Jul 12 04:41:44 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-5f2ae94f-79b4-44b6-b025-71bbdab12d2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771285129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1771285129 |
| Directory | /workspace/17.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_overflow.753880442 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 170389460001 ps |
| CPU time | 78.65 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:40:38 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-20a4039a-6353-4dbe-984f-d76cfaa43e5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753880442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.753880442 |
| Directory | /workspace/17.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_reset.4115094391 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 181629958269 ps |
| CPU time | 14.4 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:26 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-74127202-300e-440b-be5a-a45c6a42fd98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115094391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.4115094391 |
| Directory | /workspace/17.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_intr.352298300 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 36432886081 ps |
| CPU time | 36.77 seconds |
| Started | Jul 12 04:39:07 PM PDT 24 |
| Finished | Jul 12 04:39:52 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-56c11a67-2dc3-4881-a0ca-a0dbaa9f090c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352298300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.352298300 |
| Directory | /workspace/17.uart_intr/latest |
| Test location | /workspace/coverage/default/17.uart_long_xfer_wo_dly.3681109392 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 60511483519 ps |
| CPU time | 172.57 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:42:05 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-fba2ccc2-d609-4fcf-a1e2-328763fef9f0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3681109392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3681109392 |
| Directory | /workspace/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/17.uart_loopback.915770132 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3785473633 ps |
| CPU time | 2.4 seconds |
| Started | Jul 12 04:39:22 PM PDT 24 |
| Finished | Jul 12 04:39:28 PM PDT 24 |
| Peak memory | 195716 kb |
| Host | smart-04f61489-58fd-4ef4-abd0-bf270f871300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915770132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.915770132 |
| Directory | /workspace/17.uart_loopback/latest |
| Test location | /workspace/coverage/default/17.uart_noise_filter.1239387303 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 83545199741 ps |
| CPU time | 185.08 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:42:23 PM PDT 24 |
| Peak memory | 200036 kb |
| Host | smart-e3b575d4-fae4-4076-88f5-e9b6e54fea9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239387303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1239387303 |
| Directory | /workspace/17.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/17.uart_perf.673727397 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 8772274945 ps |
| CPU time | 258.41 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:43:28 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-b35c26e8-7a3d-4bb2-ab68-74b78bfe37b7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=673727397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.673727397 |
| Directory | /workspace/17.uart_perf/latest |
| Test location | /workspace/coverage/default/17.uart_rx_oversample.4264793704 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 5744603397 ps |
| CPU time | 47.53 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 198020 kb |
| Host | smart-1f80b08b-910a-4b11-be42-2e7c98ae6bca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4264793704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4264793704 |
| Directory | /workspace/17.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/17.uart_rx_parity_err.1907455808 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 57035557845 ps |
| CPU time | 92.56 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:40:38 PM PDT 24 |
| Peak memory | 199688 kb |
| Host | smart-dd7f7ff9-527a-4791-b5a5-1acb761b9159 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907455808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1907455808 |
| Directory | /workspace/17.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/17.uart_rx_start_bit_filter.3228136780 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 4324329486 ps |
| CPU time | 2.39 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:14 PM PDT 24 |
| Peak memory | 196320 kb |
| Host | smart-1fc65562-7329-4833-8971-c417499f873d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228136780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3228136780 |
| Directory | /workspace/17.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/17.uart_smoke.3959799347 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 532941649 ps |
| CPU time | 1.46 seconds |
| Started | Jul 12 04:39:07 PM PDT 24 |
| Finished | Jul 12 04:39:17 PM PDT 24 |
| Peak memory | 198560 kb |
| Host | smart-249c4752-c5ea-4302-981c-fef592e62a0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959799347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3959799347 |
| Directory | /workspace/17.uart_smoke/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all.1178960142 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 640299974245 ps |
| CPU time | 78.19 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:40:32 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-3ed2f31d-6fdf-4101-a3b5-ed60405f812b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178960142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1178960142 |
| Directory | /workspace/17.uart_stress_all/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1308629071 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 71469563694 ps |
| CPU time | 383.58 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:45:42 PM PDT 24 |
| Peak memory | 208320 kb |
| Host | smart-2990372c-d7ec-4af3-8a89-079bfdcac1b0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308629071 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1308629071 |
| Directory | /workspace/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.uart_tx_ovrd.1366703292 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 6541121240 ps |
| CPU time | 1.5 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:07 PM PDT 24 |
| Peak memory | 199344 kb |
| Host | smart-40fa667e-159e-4dfd-8ea4-3b9f6a8cd4da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366703292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1366703292 |
| Directory | /workspace/17.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/17.uart_tx_rx.1372943875 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 91191307085 ps |
| CPU time | 52.3 seconds |
| Started | Jul 12 04:39:14 PM PDT 24 |
| Finished | Jul 12 04:40:13 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-fbbe1df1-9b32-4358-a68b-118a4e032f5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372943875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1372943875 |
| Directory | /workspace/17.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/170.uart_fifo_reset.4172153496 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 27566384465 ps |
| CPU time | 40.16 seconds |
| Started | Jul 12 04:41:16 PM PDT 24 |
| Finished | Jul 12 04:41:57 PM PDT 24 |
| Peak memory | 199544 kb |
| Host | smart-2f45f5cb-dac6-4f6c-9727-aa9c217386dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172153496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4172153496 |
| Directory | /workspace/170.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/171.uart_fifo_reset.3180262453 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 98862137545 ps |
| CPU time | 160.41 seconds |
| Started | Jul 12 04:41:15 PM PDT 24 |
| Finished | Jul 12 04:43:56 PM PDT 24 |
| Peak memory | 199964 kb |
| Host | smart-f6d8b8f3-3d52-497a-b464-42e0129ab4f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180262453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3180262453 |
| Directory | /workspace/171.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/173.uart_fifo_reset.3047587396 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 48493299386 ps |
| CPU time | 83.54 seconds |
| Started | Jul 12 04:41:14 PM PDT 24 |
| Finished | Jul 12 04:42:38 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-cb6faa26-e651-483b-892a-f240bb05c937 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047587396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3047587396 |
| Directory | /workspace/173.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/174.uart_fifo_reset.3398095558 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 10741480937 ps |
| CPU time | 19.02 seconds |
| Started | Jul 12 04:41:17 PM PDT 24 |
| Finished | Jul 12 04:41:37 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-2fc89291-522d-4d01-914a-e4dc00a2981e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398095558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3398095558 |
| Directory | /workspace/174.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/175.uart_fifo_reset.376387049 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 107712465385 ps |
| CPU time | 117.48 seconds |
| Started | Jul 12 04:41:13 PM PDT 24 |
| Finished | Jul 12 04:43:12 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-4afa41c9-2000-4ed4-93eb-8ffa85a20c62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376387049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.376387049 |
| Directory | /workspace/175.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/176.uart_fifo_reset.2755469528 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 13356152478 ps |
| CPU time | 6.89 seconds |
| Started | Jul 12 04:41:11 PM PDT 24 |
| Finished | Jul 12 04:41:18 PM PDT 24 |
| Peak memory | 198408 kb |
| Host | smart-8c943afa-789d-4a38-b782-27292091f3ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755469528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2755469528 |
| Directory | /workspace/176.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/177.uart_fifo_reset.690640124 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 60115222119 ps |
| CPU time | 28.09 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:41:47 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-acf25e72-7a24-4547-9668-8ef48fda9f5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690640124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.690640124 |
| Directory | /workspace/177.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/178.uart_fifo_reset.2081156275 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 160519391215 ps |
| CPU time | 362.32 seconds |
| Started | Jul 12 04:41:15 PM PDT 24 |
| Finished | Jul 12 04:47:18 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-ca81b1fa-9dc7-46e0-a854-9bae81b14cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081156275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2081156275 |
| Directory | /workspace/178.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/179.uart_fifo_reset.3659425899 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 260888732725 ps |
| CPU time | 91.47 seconds |
| Started | Jul 12 04:41:13 PM PDT 24 |
| Finished | Jul 12 04:42:45 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-3b24832a-4189-4844-877f-74b55653c3d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659425899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3659425899 |
| Directory | /workspace/179.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_alert_test.3094607160 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 32475988 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:39:07 PM PDT 24 |
| Finished | Jul 12 04:39:16 PM PDT 24 |
| Peak memory | 195496 kb |
| Host | smart-39b9ee3a-85cf-4bc8-bab5-c10968470f81 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094607160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3094607160 |
| Directory | /workspace/18.uart_alert_test/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_full.2695914138 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 204389459007 ps |
| CPU time | 254.26 seconds |
| Started | Jul 12 04:39:15 PM PDT 24 |
| Finished | Jul 12 04:43:36 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-fe50b58d-fc17-494d-80e3-555b6c8a0969 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695914138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2695914138 |
| Directory | /workspace/18.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_overflow.2372592711 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 22508590668 ps |
| CPU time | 16.98 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:39:33 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-78216379-6f36-4593-9863-042d6b968a6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372592711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2372592711 |
| Directory | /workspace/18.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/18.uart_intr.3756371697 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 29893588978 ps |
| CPU time | 40.61 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 199476 kb |
| Host | smart-1ecb75fd-2a7e-4bad-8510-ccae36724c77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756371697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3756371697 |
| Directory | /workspace/18.uart_intr/latest |
| Test location | /workspace/coverage/default/18.uart_long_xfer_wo_dly.2854832418 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 48653325802 ps |
| CPU time | 387.94 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:46:08 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-2a42bded-4e0b-4448-9994-4c963d1f07df |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2854832418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2854832418 |
| Directory | /workspace/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/18.uart_loopback.2985203615 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 5906526305 ps |
| CPU time | 19.14 seconds |
| Started | Jul 12 04:39:21 PM PDT 24 |
| Finished | Jul 12 04:39:44 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-50b60904-2c27-4cdc-b2e9-b1db4d65a92f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985203615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2985203615 |
| Directory | /workspace/18.uart_loopback/latest |
| Test location | /workspace/coverage/default/18.uart_noise_filter.365007267 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 41389175832 ps |
| CPU time | 17.9 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:25 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-ab468178-fb41-4851-8ad3-24aa965fa4d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365007267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.365007267 |
| Directory | /workspace/18.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/18.uart_perf.3800329707 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 36959829372 ps |
| CPU time | 277.07 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:44:14 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-8c0115ee-422d-4211-a517-a3bf65b4e8bf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3800329707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3800329707 |
| Directory | /workspace/18.uart_perf/latest |
| Test location | /workspace/coverage/default/18.uart_rx_oversample.1009839699 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3391107525 ps |
| CPU time | 25.69 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:36 PM PDT 24 |
| Peak memory | 198468 kb |
| Host | smart-0c212684-d368-45b6-a751-e6fb31696c17 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1009839699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1009839699 |
| Directory | /workspace/18.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/18.uart_rx_parity_err.3517007068 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 203044306471 ps |
| CPU time | 216.43 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:42:50 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-3ebde87e-703c-4b75-9308-65e1aa435871 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517007068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3517007068 |
| Directory | /workspace/18.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/18.uart_rx_start_bit_filter.325813677 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 3900394540 ps |
| CPU time | 1.99 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:19 PM PDT 24 |
| Peak memory | 196144 kb |
| Host | smart-f5b79df7-51b1-40f8-95fb-d1af235e60ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325813677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.325813677 |
| Directory | /workspace/18.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/18.uart_smoke.1342542088 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 604693469 ps |
| CPU time | 3.12 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:12 PM PDT 24 |
| Peak memory | 199484 kb |
| Host | smart-d05e74ca-8c65-4b1e-87ca-6191d6cb8eb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342542088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1342542088 |
| Directory | /workspace/18.uart_smoke/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3843084198 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 109726835891 ps |
| CPU time | 483.98 seconds |
| Started | Jul 12 04:39:15 PM PDT 24 |
| Finished | Jul 12 04:47:25 PM PDT 24 |
| Peak memory | 224748 kb |
| Host | smart-74c87a25-a368-4ed3-b367-262bd8a5a7c9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843084198 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3843084198 |
| Directory | /workspace/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.uart_tx_ovrd.2718639514 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 6644906041 ps |
| CPU time | 24.22 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:36 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-5030fde6-3e88-4818-8bb2-79e4506368aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2718639514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2718639514 |
| Directory | /workspace/18.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/18.uart_tx_rx.2069946651 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 60069753084 ps |
| CPU time | 24.13 seconds |
| Started | Jul 12 04:39:14 PM PDT 24 |
| Finished | Jul 12 04:39:45 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-f3afff0e-e8df-4682-aefe-990eb1a0b0c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069946651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2069946651 |
| Directory | /workspace/18.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/181.uart_fifo_reset.2190480163 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 21858584591 ps |
| CPU time | 33.9 seconds |
| Started | Jul 12 04:41:13 PM PDT 24 |
| Finished | Jul 12 04:41:47 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-4b99f3d7-5427-4655-8d8c-78df44236855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190480163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2190480163 |
| Directory | /workspace/181.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/182.uart_fifo_reset.560718568 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 127327140728 ps |
| CPU time | 197.21 seconds |
| Started | Jul 12 04:41:12 PM PDT 24 |
| Finished | Jul 12 04:44:30 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-65bcf1df-df1a-4eb3-8c2a-e191d0f55255 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560718568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.560718568 |
| Directory | /workspace/182.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/184.uart_fifo_reset.2497725486 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 23427358810 ps |
| CPU time | 16.95 seconds |
| Started | Jul 12 04:41:12 PM PDT 24 |
| Finished | Jul 12 04:41:29 PM PDT 24 |
| Peak memory | 199540 kb |
| Host | smart-08914acd-7f7f-40a6-b9f7-d5ccd173eb53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2497725486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2497725486 |
| Directory | /workspace/184.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/185.uart_fifo_reset.4201227138 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 127183235543 ps |
| CPU time | 195.49 seconds |
| Started | Jul 12 04:41:16 PM PDT 24 |
| Finished | Jul 12 04:44:32 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-6c4116a8-4460-40d0-af76-52039e19138d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201227138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.4201227138 |
| Directory | /workspace/185.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/186.uart_fifo_reset.4056580752 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 36926049127 ps |
| CPU time | 48.12 seconds |
| Started | Jul 12 04:41:15 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-3efd680d-a87b-4774-8331-92931a25aba3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056580752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4056580752 |
| Directory | /workspace/186.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/187.uart_fifo_reset.1838047322 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 63241935408 ps |
| CPU time | 27.57 seconds |
| Started | Jul 12 04:41:14 PM PDT 24 |
| Finished | Jul 12 04:41:42 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-ff7f3383-ed67-4d40-83b8-668c9351fe7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838047322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1838047322 |
| Directory | /workspace/187.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/188.uart_fifo_reset.3173194356 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 87246403589 ps |
| CPU time | 54.77 seconds |
| Started | Jul 12 04:41:12 PM PDT 24 |
| Finished | Jul 12 04:42:07 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-e659550e-9c95-4414-8d13-d8b984b05720 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173194356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3173194356 |
| Directory | /workspace/188.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/189.uart_fifo_reset.635539523 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 27538048073 ps |
| CPU time | 40.44 seconds |
| Started | Jul 12 04:41:16 PM PDT 24 |
| Finished | Jul 12 04:41:57 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-7ae747ca-390e-492e-ba04-8e0f01be9540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635539523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.635539523 |
| Directory | /workspace/189.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_alert_test.4277454054 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 15684035 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:39:14 PM PDT 24 |
| Peak memory | 195152 kb |
| Host | smart-5119673c-e61e-4ba6-b0cc-ff72c1f02662 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277454054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.4277454054 |
| Directory | /workspace/19.uart_alert_test/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_full.3299783985 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 38671332413 ps |
| CPU time | 37.77 seconds |
| Started | Jul 12 04:39:05 PM PDT 24 |
| Finished | Jul 12 04:39:50 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-2fc2da20-7a90-412c-bdeb-5558a808631a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299783985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3299783985 |
| Directory | /workspace/19.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_overflow.3658245193 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 100769802030 ps |
| CPU time | 81.55 seconds |
| Started | Jul 12 04:39:27 PM PDT 24 |
| Finished | Jul 12 04:40:52 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-7b148bb5-f2f9-40d1-a44e-5cc3ad2ebc5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658245193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3658245193 |
| Directory | /workspace/19.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_reset.1228487210 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 57840217705 ps |
| CPU time | 23.19 seconds |
| Started | Jul 12 04:39:24 PM PDT 24 |
| Finished | Jul 12 04:39:50 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-9bc5e504-d48a-4b3b-a9e1-b7c64f0b92c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228487210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1228487210 |
| Directory | /workspace/19.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_intr.3658344342 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 38285563379 ps |
| CPU time | 95.69 seconds |
| Started | Jul 12 04:39:25 PM PDT 24 |
| Finished | Jul 12 04:41:04 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-6422394b-a737-4142-8edd-eb4a06414f3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658344342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3658344342 |
| Directory | /workspace/19.uart_intr/latest |
| Test location | /workspace/coverage/default/19.uart_long_xfer_wo_dly.3951435732 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 72777716859 ps |
| CPU time | 382.18 seconds |
| Started | Jul 12 04:39:12 PM PDT 24 |
| Finished | Jul 12 04:45:42 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-72184781-b9d0-4c4f-872f-5b0a3f6ffb60 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3951435732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3951435732 |
| Directory | /workspace/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/19.uart_loopback.2162060270 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 4142240750 ps |
| CPU time | 2.42 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:19 PM PDT 24 |
| Peak memory | 198492 kb |
| Host | smart-5e65dcbc-22d6-46f6-bb93-376a0739c2e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162060270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2162060270 |
| Directory | /workspace/19.uart_loopback/latest |
| Test location | /workspace/coverage/default/19.uart_noise_filter.396929134 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 13554942962 ps |
| CPU time | 25.25 seconds |
| Started | Jul 12 04:39:24 PM PDT 24 |
| Finished | Jul 12 04:39:52 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-5faa5d44-54b7-4833-9f27-26e3457851a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396929134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.396929134 |
| Directory | /workspace/19.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/19.uart_perf.3668309127 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 9762744135 ps |
| CPU time | 368.15 seconds |
| Started | Jul 12 04:39:17 PM PDT 24 |
| Finished | Jul 12 04:45:31 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-4070c347-184b-4166-a267-24dbccc5b22a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3668309127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3668309127 |
| Directory | /workspace/19.uart_perf/latest |
| Test location | /workspace/coverage/default/19.uart_rx_oversample.4257612176 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 6936228648 ps |
| CPU time | 69.94 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:40:44 PM PDT 24 |
| Peak memory | 198188 kb |
| Host | smart-5b541efb-275e-4838-81a1-b6093d503605 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4257612176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.4257612176 |
| Directory | /workspace/19.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/19.uart_rx_parity_err.1654736711 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 42642818807 ps |
| CPU time | 63.68 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:40:47 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-da002a5e-4e46-428d-a342-6995ff68720c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654736711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1654736711 |
| Directory | /workspace/19.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/19.uart_rx_start_bit_filter.4292019821 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 5021511130 ps |
| CPU time | 7.38 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 196596 kb |
| Host | smart-545c0bc7-086a-4554-a8e9-412aff487a08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292019821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4292019821 |
| Directory | /workspace/19.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/19.uart_smoke.2789235673 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 682187820 ps |
| CPU time | 2.19 seconds |
| Started | Jul 12 04:39:07 PM PDT 24 |
| Finished | Jul 12 04:39:18 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-a260a986-f646-451a-b9ff-508aabff5273 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789235673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2789235673 |
| Directory | /workspace/19.uart_smoke/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all.50150958 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 190515264969 ps |
| CPU time | 40.75 seconds |
| Started | Jul 12 04:39:18 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 208112 kb |
| Host | smart-3d90f170-5322-4567-8a28-100480e32c4b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50150958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.50150958 |
| Directory | /workspace/19.uart_stress_all/latest |
| Test location | /workspace/coverage/default/19.uart_tx_ovrd.2212254632 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 7382959994 ps |
| CPU time | 23.61 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:40:09 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-19e52bf0-63d2-4bb3-aaba-750277ecc0d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212254632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2212254632 |
| Directory | /workspace/19.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/19.uart_tx_rx.1673258888 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 126064767549 ps |
| CPU time | 62.7 seconds |
| Started | Jul 12 04:39:27 PM PDT 24 |
| Finished | Jul 12 04:40:34 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-d1a4acc9-7608-4b64-98ed-2f2a1dfd6ce4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673258888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1673258888 |
| Directory | /workspace/19.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/190.uart_fifo_reset.3516746315 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 76758572843 ps |
| CPU time | 67.54 seconds |
| Started | Jul 12 04:41:19 PM PDT 24 |
| Finished | Jul 12 04:42:29 PM PDT 24 |
| Peak memory | 199484 kb |
| Host | smart-cb284e71-3fad-4b8a-9b21-253fd5fd07d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516746315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3516746315 |
| Directory | /workspace/190.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/191.uart_fifo_reset.8549827 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 50320153036 ps |
| CPU time | 20.8 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:41:40 PM PDT 24 |
| Peak memory | 199112 kb |
| Host | smart-f61b4c7f-5f08-41a0-a485-1b13b31c177d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8549827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.8549827 |
| Directory | /workspace/191.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/192.uart_fifo_reset.3581856952 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 97481268577 ps |
| CPU time | 43.73 seconds |
| Started | Jul 12 04:41:19 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199356 kb |
| Host | smart-d6cf46e0-5024-4856-bb0a-98d0bb691be8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3581856952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3581856952 |
| Directory | /workspace/192.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/194.uart_fifo_reset.2990593757 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 13877368380 ps |
| CPU time | 9.77 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:41:29 PM PDT 24 |
| Peak memory | 198396 kb |
| Host | smart-e4a87fcf-22eb-4316-82a8-a39f1a507926 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990593757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2990593757 |
| Directory | /workspace/194.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/195.uart_fifo_reset.2543787714 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 137672587973 ps |
| CPU time | 96.84 seconds |
| Started | Jul 12 04:41:20 PM PDT 24 |
| Finished | Jul 12 04:42:58 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-e08ea6d5-0fa8-4696-b6a0-968863a28e8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543787714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2543787714 |
| Directory | /workspace/195.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/196.uart_fifo_reset.3761804093 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 86258757602 ps |
| CPU time | 146.91 seconds |
| Started | Jul 12 04:41:16 PM PDT 24 |
| Finished | Jul 12 04:43:43 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-14a94942-758b-4b70-a7f3-883f7647f105 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761804093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3761804093 |
| Directory | /workspace/196.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/197.uart_fifo_reset.9538082 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 31822110743 ps |
| CPU time | 42.32 seconds |
| Started | Jul 12 04:41:22 PM PDT 24 |
| Finished | Jul 12 04:42:05 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-d142b150-fa51-49a8-b2e3-4286140bff03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9538082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.9538082 |
| Directory | /workspace/197.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/198.uart_fifo_reset.490992700 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 98406836321 ps |
| CPU time | 249.86 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:45:30 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-63bb59d6-c636-4919-9a8a-e06b65c25483 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490992700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.490992700 |
| Directory | /workspace/198.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_alert_test.307171882 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 63486800 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:38:19 PM PDT 24 |
| Finished | Jul 12 04:38:30 PM PDT 24 |
| Peak memory | 195432 kb |
| Host | smart-edc5f671-d013-445c-b6ce-6d2bcf234355 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307171882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.307171882 |
| Directory | /workspace/2.uart_alert_test/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_full.1658151929 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 36628060974 ps |
| CPU time | 6.88 seconds |
| Started | Jul 12 04:38:53 PM PDT 24 |
| Finished | Jul 12 04:39:05 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-d2212626-11d2-483d-9451-3f495d299bfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658151929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1658151929 |
| Directory | /workspace/2.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_overflow.336067275 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 94401417634 ps |
| CPU time | 21.68 seconds |
| Started | Jul 12 04:38:37 PM PDT 24 |
| Finished | Jul 12 04:39:04 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-dd1d0117-91db-4ead-bcde-ded3a5ff1bc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336067275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.336067275 |
| Directory | /workspace/2.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_reset.2054736839 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 92630912323 ps |
| CPU time | 133.12 seconds |
| Started | Jul 12 04:38:34 PM PDT 24 |
| Finished | Jul 12 04:40:53 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-07459a26-4b9b-4de4-b58f-b02f6f5731a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054736839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2054736839 |
| Directory | /workspace/2.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_intr.1739272463 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 17088856428 ps |
| CPU time | 11.15 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:38:57 PM PDT 24 |
| Peak memory | 199612 kb |
| Host | smart-4252dc9d-6b3a-494e-bbd5-b8d6faac7a26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739272463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1739272463 |
| Directory | /workspace/2.uart_intr/latest |
| Test location | /workspace/coverage/default/2.uart_long_xfer_wo_dly.4034700262 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 56661970819 ps |
| CPU time | 484.7 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:46:57 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-2ef9a653-bc45-4199-9ee2-ca6974a07159 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4034700262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4034700262 |
| Directory | /workspace/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/2.uart_loopback.1115797513 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 4626701334 ps |
| CPU time | 10.48 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:38:52 PM PDT 24 |
| Peak memory | 198568 kb |
| Host | smart-418bd491-7e98-4058-99e6-69f3aa0d98f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1115797513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1115797513 |
| Directory | /workspace/2.uart_loopback/latest |
| Test location | /workspace/coverage/default/2.uart_noise_filter.4079729372 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 275532524022 ps |
| CPU time | 170.46 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:41:32 PM PDT 24 |
| Peak memory | 200060 kb |
| Host | smart-41eb08d3-ecd5-41f5-88f7-06c72187109d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079729372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.4079729372 |
| Directory | /workspace/2.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/2.uart_perf.115156362 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 20016178270 ps |
| CPU time | 155.74 seconds |
| Started | Jul 12 04:38:34 PM PDT 24 |
| Finished | Jul 12 04:41:16 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-209d60d2-c3c0-45d4-9b52-d3b5cd961afe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=115156362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.115156362 |
| Directory | /workspace/2.uart_perf/latest |
| Test location | /workspace/coverage/default/2.uart_rx_oversample.2468102736 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3766912239 ps |
| CPU time | 9.95 seconds |
| Started | Jul 12 04:38:42 PM PDT 24 |
| Finished | Jul 12 04:39:03 PM PDT 24 |
| Peak memory | 197868 kb |
| Host | smart-9885fb59-de4f-4483-a362-45f67add683a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2468102736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2468102736 |
| Directory | /workspace/2.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/2.uart_rx_parity_err.1253216007 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 155665598565 ps |
| CPU time | 71.55 seconds |
| Started | Jul 12 04:38:19 PM PDT 24 |
| Finished | Jul 12 04:39:41 PM PDT 24 |
| Peak memory | 200116 kb |
| Host | smart-9c7f2d15-4354-443d-a878-331ebb434f7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253216007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1253216007 |
| Directory | /workspace/2.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/2.uart_rx_start_bit_filter.1169571938 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 4338631647 ps |
| CPU time | 2.18 seconds |
| Started | Jul 12 04:38:46 PM PDT 24 |
| Finished | Jul 12 04:38:54 PM PDT 24 |
| Peak memory | 196012 kb |
| Host | smart-e5416cf8-1875-4e3b-bd11-86ed1ebb657c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169571938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1169571938 |
| Directory | /workspace/2.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/2.uart_sec_cm.2278609619 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 51219539 ps |
| CPU time | 0.8 seconds |
| Started | Jul 12 04:38:26 PM PDT 24 |
| Finished | Jul 12 04:38:34 PM PDT 24 |
| Peak memory | 218156 kb |
| Host | smart-cb6791fa-589a-4965-981c-6711ebfc6fc5 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278609619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2278609619 |
| Directory | /workspace/2.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/2.uart_smoke.2217695364 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 461895035 ps |
| CPU time | 2.15 seconds |
| Started | Jul 12 04:38:29 PM PDT 24 |
| Finished | Jul 12 04:38:37 PM PDT 24 |
| Peak memory | 198440 kb |
| Host | smart-67b21e98-6073-47f5-8429-d4ee751ce3c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217695364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2217695364 |
| Directory | /workspace/2.uart_smoke/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all.3466630291 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 150972213355 ps |
| CPU time | 562.51 seconds |
| Started | Jul 12 04:38:52 PM PDT 24 |
| Finished | Jul 12 04:48:20 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-0a3fd1aa-f341-4b29-8290-4724cb646319 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466630291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3466630291 |
| Directory | /workspace/2.uart_stress_all/latest |
| Test location | /workspace/coverage/default/2.uart_tx_ovrd.4472975 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 6486048003 ps |
| CPU time | 17.2 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:39:00 PM PDT 24 |
| Peak memory | 199432 kb |
| Host | smart-ffd248f9-a5d4-4298-8cea-626330b65305 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4472975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.4472975 |
| Directory | /workspace/2.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/2.uart_tx_rx.1660081928 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 5623694427 ps |
| CPU time | 8.43 seconds |
| Started | Jul 12 04:38:39 PM PDT 24 |
| Finished | Jul 12 04:38:53 PM PDT 24 |
| Peak memory | 197624 kb |
| Host | smart-ab028651-b94d-414a-a9b6-a0e9ad267700 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660081928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1660081928 |
| Directory | /workspace/2.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/20.uart_alert_test.682478573 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 23042205 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:19 PM PDT 24 |
| Finished | Jul 12 04:39:24 PM PDT 24 |
| Peak memory | 195404 kb |
| Host | smart-8df6533f-45f6-4035-83d7-366ea6e322b2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682478573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.682478573 |
| Directory | /workspace/20.uart_alert_test/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_overflow.3376464734 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 105344551620 ps |
| CPU time | 128.15 seconds |
| Started | Jul 12 04:39:26 PM PDT 24 |
| Finished | Jul 12 04:41:38 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-dff81804-8568-4bc9-9d43-85a756e22fb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376464734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3376464734 |
| Directory | /workspace/20.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_reset.3220044214 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 38410147504 ps |
| CPU time | 50.78 seconds |
| Started | Jul 12 04:39:20 PM PDT 24 |
| Finished | Jul 12 04:40:15 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-3cdaa162-703f-4eb7-9e3d-629342aa1f0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220044214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3220044214 |
| Directory | /workspace/20.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/20.uart_intr.3145460511 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 56768035606 ps |
| CPU time | 40.55 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:40:00 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-33c702db-3ee3-4d84-b71b-a8273e16d04b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145460511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3145460511 |
| Directory | /workspace/20.uart_intr/latest |
| Test location | /workspace/coverage/default/20.uart_long_xfer_wo_dly.1404674299 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 138297955795 ps |
| CPU time | 275.34 seconds |
| Started | Jul 12 04:39:18 PM PDT 24 |
| Finished | Jul 12 04:43:58 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-77167b56-5568-42db-b470-ab23e20ca2c3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1404674299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1404674299 |
| Directory | /workspace/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/20.uart_loopback.2498775443 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 5742327491 ps |
| CPU time | 12.28 seconds |
| Started | Jul 12 04:39:18 PM PDT 24 |
| Finished | Jul 12 04:39:35 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-34882208-b9fb-44bb-9f8f-b79a99395d96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498775443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2498775443 |
| Directory | /workspace/20.uart_loopback/latest |
| Test location | /workspace/coverage/default/20.uart_noise_filter.549380102 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 42232838879 ps |
| CPU time | 86.13 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:40:43 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-c1a3c145-7ddb-4b13-9f4e-3703ab9c3221 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=549380102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.549380102 |
| Directory | /workspace/20.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/20.uart_perf.4248310021 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 29314406364 ps |
| CPU time | 498.82 seconds |
| Started | Jul 12 04:39:19 PM PDT 24 |
| Finished | Jul 12 04:47:43 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-b3a6da5f-0e22-4438-9fa6-b7e819df2180 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4248310021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4248310021 |
| Directory | /workspace/20.uart_perf/latest |
| Test location | /workspace/coverage/default/20.uart_rx_oversample.420852836 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 7323641176 ps |
| CPU time | 16.8 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:39:51 PM PDT 24 |
| Peak memory | 198036 kb |
| Host | smart-be212b4a-4405-4c5f-8b82-59ef7e7e3335 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=420852836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.420852836 |
| Directory | /workspace/20.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/20.uart_rx_parity_err.763467572 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 63527625098 ps |
| CPU time | 52.48 seconds |
| Started | Jul 12 04:39:23 PM PDT 24 |
| Finished | Jul 12 04:40:19 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-2d4a6237-2569-4c4b-b0d2-32ed5db77fb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=763467572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.763467572 |
| Directory | /workspace/20.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/20.uart_rx_start_bit_filter.2426678454 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3808649275 ps |
| CPU time | 1.96 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:39:46 PM PDT 24 |
| Peak memory | 196328 kb |
| Host | smart-9bfc7374-1fa5-4178-abcc-5008800db5be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426678454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2426678454 |
| Directory | /workspace/20.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/20.uart_smoke.932109828 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 664076152 ps |
| CPU time | 2.95 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:39:40 PM PDT 24 |
| Peak memory | 198040 kb |
| Host | smart-86a832b4-df89-462f-a0b5-aa9ee4482bdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932109828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.932109828 |
| Directory | /workspace/20.uart_smoke/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all.163401239 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 92072350600 ps |
| CPU time | 112.89 seconds |
| Started | Jul 12 04:39:20 PM PDT 24 |
| Finished | Jul 12 04:41:17 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-ee5875ea-de85-4629-9c67-19fdb49f1e38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163401239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.163401239 |
| Directory | /workspace/20.uart_stress_all/latest |
| Test location | /workspace/coverage/default/20.uart_tx_ovrd.2125362500 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 664186216 ps |
| CPU time | 1.52 seconds |
| Started | Jul 12 04:39:24 PM PDT 24 |
| Finished | Jul 12 04:39:29 PM PDT 24 |
| Peak memory | 198160 kb |
| Host | smart-e02ddc23-b7f5-4129-a704-45faf45a951b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125362500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2125362500 |
| Directory | /workspace/20.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/20.uart_tx_rx.1244461951 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 28474484669 ps |
| CPU time | 14 seconds |
| Started | Jul 12 04:39:22 PM PDT 24 |
| Finished | Jul 12 04:39:39 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-e1d30f66-c4b5-49f3-abcc-a61a91793e21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244461951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1244461951 |
| Directory | /workspace/20.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/200.uart_fifo_reset.1104320656 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 10936244785 ps |
| CPU time | 16.24 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:41:35 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-c9875e78-bc88-457b-9d87-bf9704304496 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104320656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1104320656 |
| Directory | /workspace/200.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/201.uart_fifo_reset.4245716923 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 108049299406 ps |
| CPU time | 254.04 seconds |
| Started | Jul 12 04:41:19 PM PDT 24 |
| Finished | Jul 12 04:45:35 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-f21185eb-91dc-43b4-becc-0f3a772a2c69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245716923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.4245716923 |
| Directory | /workspace/201.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/202.uart_fifo_reset.2928889306 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 10903999127 ps |
| CPU time | 7.15 seconds |
| Started | Jul 12 04:41:17 PM PDT 24 |
| Finished | Jul 12 04:41:25 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-a32077e1-a3d3-495f-9e6c-371caca108e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2928889306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2928889306 |
| Directory | /workspace/202.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/203.uart_fifo_reset.2227595678 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 34226445897 ps |
| CPU time | 12.53 seconds |
| Started | Jul 12 04:41:23 PM PDT 24 |
| Finished | Jul 12 04:41:37 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-d4079e99-6863-4b82-8733-b1dcdccadb80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2227595678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2227595678 |
| Directory | /workspace/203.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/205.uart_fifo_reset.603069933 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 13489591203 ps |
| CPU time | 20.37 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:41:40 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-d98f49f6-5dd9-42ac-af03-db69fad30e21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=603069933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.603069933 |
| Directory | /workspace/205.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/206.uart_fifo_reset.404148984 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 217916971278 ps |
| CPU time | 37.06 seconds |
| Started | Jul 12 04:41:23 PM PDT 24 |
| Finished | Jul 12 04:42:01 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-aa1c6655-3e10-4a87-8e91-a223f2517852 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404148984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.404148984 |
| Directory | /workspace/206.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/207.uart_fifo_reset.3148241947 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 172127941853 ps |
| CPU time | 204.43 seconds |
| Started | Jul 12 04:41:19 PM PDT 24 |
| Finished | Jul 12 04:44:46 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-df7e998a-9f8d-4aa9-950c-83044259467e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148241947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3148241947 |
| Directory | /workspace/207.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/208.uart_fifo_reset.1329552391 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 49955823358 ps |
| CPU time | 46.06 seconds |
| Started | Jul 12 04:41:17 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-95fbe223-e60d-4191-8c31-735a5573f09c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329552391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1329552391 |
| Directory | /workspace/208.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/209.uart_fifo_reset.3127025708 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 61558367487 ps |
| CPU time | 20.35 seconds |
| Started | Jul 12 04:41:21 PM PDT 24 |
| Finished | Jul 12 04:41:42 PM PDT 24 |
| Peak memory | 199548 kb |
| Host | smart-96d6faaf-06cf-448d-ba5f-fef3f066dfdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127025708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3127025708 |
| Directory | /workspace/209.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_alert_test.1769306639 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 14258882 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:22 PM PDT 24 |
| Finished | Jul 12 04:39:25 PM PDT 24 |
| Peak memory | 195224 kb |
| Host | smart-280b6e9b-3125-47bc-99b8-4beacfd8179e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769306639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1769306639 |
| Directory | /workspace/21.uart_alert_test/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_full.2029725860 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 19841211811 ps |
| CPU time | 10.8 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:39:29 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-c3b2bb05-f5cf-4358-9147-a92ebad7bc4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029725860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2029725860 |
| Directory | /workspace/21.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_overflow.2213583536 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 58934971557 ps |
| CPU time | 23.57 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:39:59 PM PDT 24 |
| Peak memory | 199612 kb |
| Host | smart-48e78e6d-daa8-41e8-a22f-45966507e35a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213583536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2213583536 |
| Directory | /workspace/21.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_reset.132824066 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 117254169751 ps |
| CPU time | 92.8 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:40:44 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-37e1b44b-8ca2-4bde-a177-37ae795e5fde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132824066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.132824066 |
| Directory | /workspace/21.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_intr.1729975224 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 33692831344 ps |
| CPU time | 14.53 seconds |
| Started | Jul 12 04:39:19 PM PDT 24 |
| Finished | Jul 12 04:39:38 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-c3a52f58-9553-4f7d-ab06-545f838562c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729975224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1729975224 |
| Directory | /workspace/21.uart_intr/latest |
| Test location | /workspace/coverage/default/21.uart_long_xfer_wo_dly.233330050 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 67963209811 ps |
| CPU time | 238.8 seconds |
| Started | Jul 12 04:39:43 PM PDT 24 |
| Finished | Jul 12 04:43:48 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-3c6447fc-0eb4-4e52-a92e-d9285dfff3ec |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=233330050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.233330050 |
| Directory | /workspace/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/21.uart_loopback.1102421399 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 9006705220 ps |
| CPU time | 4.95 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:39:21 PM PDT 24 |
| Peak memory | 199024 kb |
| Host | smart-0fbbf29a-566b-42ac-9f92-d451ee48aa57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102421399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1102421399 |
| Directory | /workspace/21.uart_loopback/latest |
| Test location | /workspace/coverage/default/21.uart_noise_filter.3017888063 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 9290766647 ps |
| CPU time | 4.56 seconds |
| Started | Jul 12 04:39:20 PM PDT 24 |
| Finished | Jul 12 04:39:29 PM PDT 24 |
| Peak memory | 195008 kb |
| Host | smart-69f50cb1-88dc-475c-b12c-ba0104b5b334 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017888063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3017888063 |
| Directory | /workspace/21.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/21.uart_perf.1842251226 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 8944300833 ps |
| CPU time | 119.5 seconds |
| Started | Jul 12 04:39:25 PM PDT 24 |
| Finished | Jul 12 04:41:28 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-c92053b5-547e-41ab-884a-dbbf9a59b080 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1842251226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1842251226 |
| Directory | /workspace/21.uart_perf/latest |
| Test location | /workspace/coverage/default/21.uart_rx_oversample.1314266359 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2537429569 ps |
| CPU time | 9.74 seconds |
| Started | Jul 12 04:39:27 PM PDT 24 |
| Finished | Jul 12 04:39:41 PM PDT 24 |
| Peak memory | 199008 kb |
| Host | smart-6ee65b4e-c21d-4bf6-a5b9-d4db7fcb8329 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1314266359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1314266359 |
| Directory | /workspace/21.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/21.uart_rx_parity_err.4060530856 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 101779094448 ps |
| CPU time | 22.23 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:40:02 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-3e40887e-a084-44d1-95b1-65efecce2906 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4060530856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4060530856 |
| Directory | /workspace/21.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/21.uart_rx_start_bit_filter.3905194778 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3189384620 ps |
| CPU time | 1.89 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:39:38 PM PDT 24 |
| Peak memory | 196612 kb |
| Host | smart-2868225c-8e23-4272-9dd9-25d6c7d9c18e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905194778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3905194778 |
| Directory | /workspace/21.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/21.uart_smoke.101281294 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 699961156 ps |
| CPU time | 2.07 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:13 PM PDT 24 |
| Peak memory | 198632 kb |
| Host | smart-d0250aa6-086b-4713-bce6-43dbb9f1a52d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101281294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.101281294 |
| Directory | /workspace/21.uart_smoke/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all.2735384460 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 40926480492 ps |
| CPU time | 51.4 seconds |
| Started | Jul 12 04:39:07 PM PDT 24 |
| Finished | Jul 12 04:40:07 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-878d704c-e198-46d3-9dcd-b1c2b6c0a453 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735384460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2735384460 |
| Directory | /workspace/21.uart_stress_all/latest |
| Test location | /workspace/coverage/default/21.uart_tx_ovrd.2001043100 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 471570462 ps |
| CPU time | 2.1 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:39:45 PM PDT 24 |
| Peak memory | 199460 kb |
| Host | smart-4e3cecad-2d5d-4d2f-9d13-1573055d7dd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001043100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2001043100 |
| Directory | /workspace/21.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/21.uart_tx_rx.2722600209 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 89778366714 ps |
| CPU time | 142.2 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:41:57 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-b94a4561-261c-4390-b79c-59111de5da5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722600209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2722600209 |
| Directory | /workspace/21.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/210.uart_fifo_reset.207839458 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 71382122853 ps |
| CPU time | 55.45 seconds |
| Started | Jul 12 04:41:19 PM PDT 24 |
| Finished | Jul 12 04:42:16 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-b5ba3c3d-be2b-4309-9f8c-8455732b3a5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207839458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.207839458 |
| Directory | /workspace/210.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/211.uart_fifo_reset.822595861 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 180261764179 ps |
| CPU time | 296.81 seconds |
| Started | Jul 12 04:41:19 PM PDT 24 |
| Finished | Jul 12 04:46:18 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-4597d8dd-bb24-4014-aa13-9073439e51cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822595861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.822595861 |
| Directory | /workspace/211.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/212.uart_fifo_reset.736661965 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 135682430484 ps |
| CPU time | 253.39 seconds |
| Started | Jul 12 04:41:20 PM PDT 24 |
| Finished | Jul 12 04:45:35 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-0f7d4d1f-5415-4c22-a53c-6516e2f49b97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736661965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.736661965 |
| Directory | /workspace/212.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/213.uart_fifo_reset.919678285 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 301104905685 ps |
| CPU time | 449.71 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:48:49 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-701c3a7f-718f-4843-8d6c-54eff83f3a80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919678285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.919678285 |
| Directory | /workspace/213.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/214.uart_fifo_reset.3785154504 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 64331573464 ps |
| CPU time | 29.52 seconds |
| Started | Jul 12 04:41:19 PM PDT 24 |
| Finished | Jul 12 04:41:51 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-01a42ec2-b018-42f2-910d-f5bc285fb27d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785154504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3785154504 |
| Directory | /workspace/214.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/215.uart_fifo_reset.2715667520 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 136042363514 ps |
| CPU time | 55.43 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:42:14 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-dcf89f10-44ae-4000-b0d5-963aca1abbd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715667520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2715667520 |
| Directory | /workspace/215.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/216.uart_fifo_reset.3127895395 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 16897716656 ps |
| CPU time | 14.27 seconds |
| Started | Jul 12 04:41:19 PM PDT 24 |
| Finished | Jul 12 04:41:35 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-004029dc-53a4-4e1b-8bb7-a19ea2363e26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127895395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3127895395 |
| Directory | /workspace/216.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/217.uart_fifo_reset.1808614549 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 120903440239 ps |
| CPU time | 170.54 seconds |
| Started | Jul 12 04:41:22 PM PDT 24 |
| Finished | Jul 12 04:44:14 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-0570b4e3-8c49-4203-873f-d7d6570a907c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808614549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1808614549 |
| Directory | /workspace/217.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/218.uart_fifo_reset.2637719279 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 79247991576 ps |
| CPU time | 73.13 seconds |
| Started | Jul 12 04:41:17 PM PDT 24 |
| Finished | Jul 12 04:42:30 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-c74a02ee-ea99-425d-a867-0e718eca05ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637719279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2637719279 |
| Directory | /workspace/218.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/219.uart_fifo_reset.439921970 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 6048701398 ps |
| CPU time | 9.99 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:41:29 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-ad5347df-b6fd-4e2a-803f-d138a8dd1cb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439921970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.439921970 |
| Directory | /workspace/219.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_alert_test.2078388781 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 14312226 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:39:20 PM PDT 24 |
| Finished | Jul 12 04:39:25 PM PDT 24 |
| Peak memory | 195220 kb |
| Host | smart-697952a8-314b-43ff-90df-923a71d7e67d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078388781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2078388781 |
| Directory | /workspace/22.uart_alert_test/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_full.1643391045 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 44200396076 ps |
| CPU time | 66.42 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:40:48 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-363429f1-58e7-41c0-addc-863f1a739a03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643391045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1643391045 |
| Directory | /workspace/22.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_overflow.3381747719 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 35502926459 ps |
| CPU time | 16.16 seconds |
| Started | Jul 12 04:39:16 PM PDT 24 |
| Finished | Jul 12 04:39:38 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-288eacb0-01cc-47cd-a12b-680802392620 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3381747719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3381747719 |
| Directory | /workspace/22.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_reset.817954220 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 134750680646 ps |
| CPU time | 45.21 seconds |
| Started | Jul 12 04:39:36 PM PDT 24 |
| Finished | Jul 12 04:40:28 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-2d231317-a925-4fce-8afc-fc4e3cf26ea2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817954220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.817954220 |
| Directory | /workspace/22.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_intr.1941179090 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 36815978595 ps |
| CPU time | 53.21 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:40:02 PM PDT 24 |
| Peak memory | 197924 kb |
| Host | smart-092ffc7e-bf86-4cf1-917e-44dc6d7b13ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941179090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1941179090 |
| Directory | /workspace/22.uart_intr/latest |
| Test location | /workspace/coverage/default/22.uart_long_xfer_wo_dly.3005579424 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 123100567059 ps |
| CPU time | 184.87 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:42:38 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-ee064158-34e7-43e0-83fe-fdb5e4b1b90d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3005579424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3005579424 |
| Directory | /workspace/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/22.uart_loopback.1023509773 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3731060904 ps |
| CPU time | 6.83 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:49 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-cf348523-b810-403a-935b-d7969472e271 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023509773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1023509773 |
| Directory | /workspace/22.uart_loopback/latest |
| Test location | /workspace/coverage/default/22.uart_noise_filter.107965154 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 115484462101 ps |
| CPU time | 141.25 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:41:58 PM PDT 24 |
| Peak memory | 208292 kb |
| Host | smart-8d21e6ae-4b0a-4295-8b91-62b9518c7639 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107965154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.107965154 |
| Directory | /workspace/22.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/22.uart_perf.3768104076 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 15321112571 ps |
| CPU time | 401.77 seconds |
| Started | Jul 12 04:39:23 PM PDT 24 |
| Finished | Jul 12 04:46:09 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-63d515e2-bf59-4453-bb98-5d69a5130ea2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3768104076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3768104076 |
| Directory | /workspace/22.uart_perf/latest |
| Test location | /workspace/coverage/default/22.uart_rx_oversample.1365610168 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 4978694637 ps |
| CPU time | 11.19 seconds |
| Started | Jul 12 04:39:18 PM PDT 24 |
| Finished | Jul 12 04:39:34 PM PDT 24 |
| Peak memory | 199136 kb |
| Host | smart-5ac122e2-27f0-4a5c-980d-fcc8de67f453 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1365610168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1365610168 |
| Directory | /workspace/22.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/22.uart_rx_parity_err.2441790851 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 75930651090 ps |
| CPU time | 61.45 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:40:18 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-70437730-19c1-489f-a5a1-2c9d15b547cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441790851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2441790851 |
| Directory | /workspace/22.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/22.uart_rx_start_bit_filter.4293622259 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 25107234807 ps |
| CPU time | 18.61 seconds |
| Started | Jul 12 04:39:36 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 195780 kb |
| Host | smart-cdbca990-429b-49c8-a469-b92d4bcdd1cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293622259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4293622259 |
| Directory | /workspace/22.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/22.uart_smoke.2203889763 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 350947856 ps |
| CPU time | 1.17 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:39:20 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-022aebbb-9efa-4151-bf70-f505b487bcb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203889763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2203889763 |
| Directory | /workspace/22.uart_smoke/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all.2437154183 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 243876806781 ps |
| CPU time | 1032.92 seconds |
| Started | Jul 12 04:39:43 PM PDT 24 |
| Finished | Jul 12 04:57:02 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-5af464a1-bfe0-44ed-8ebf-7aa0f692b6ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437154183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2437154183 |
| Directory | /workspace/22.uart_stress_all/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2483688448 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 36145666377 ps |
| CPU time | 357.24 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:45:34 PM PDT 24 |
| Peak memory | 215840 kb |
| Host | smart-3c6c92a8-9d05-4c5e-bddf-b0ac90bbb9ef |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483688448 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2483688448 |
| Directory | /workspace/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.uart_tx_ovrd.1831182321 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 439280155 ps |
| CPU time | 1.83 seconds |
| Started | Jul 12 04:39:36 PM PDT 24 |
| Finished | Jul 12 04:39:49 PM PDT 24 |
| Peak memory | 199348 kb |
| Host | smart-40077234-66a4-4da0-858d-bac01b2f38d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831182321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1831182321 |
| Directory | /workspace/22.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/22.uart_tx_rx.1128701586 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 35569695370 ps |
| CPU time | 69.63 seconds |
| Started | Jul 12 04:39:19 PM PDT 24 |
| Finished | Jul 12 04:40:34 PM PDT 24 |
| Peak memory | 200080 kb |
| Host | smart-dc2cb159-cdee-4400-910e-f59fbe297bfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128701586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1128701586 |
| Directory | /workspace/22.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/220.uart_fifo_reset.775309502 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 74966807476 ps |
| CPU time | 143.69 seconds |
| Started | Jul 12 04:41:17 PM PDT 24 |
| Finished | Jul 12 04:43:41 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-0123bad2-9546-4135-80ed-fc6893a3525f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775309502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.775309502 |
| Directory | /workspace/220.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/221.uart_fifo_reset.1985995757 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 26542868964 ps |
| CPU time | 11.01 seconds |
| Started | Jul 12 04:41:18 PM PDT 24 |
| Finished | Jul 12 04:41:30 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-987fa4c0-ae56-47ee-a5c9-c2dacf67a117 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985995757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1985995757 |
| Directory | /workspace/221.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/223.uart_fifo_reset.1790636711 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 121667400215 ps |
| CPU time | 33.63 seconds |
| Started | Jul 12 04:41:20 PM PDT 24 |
| Finished | Jul 12 04:41:55 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-f949382e-a7e2-4b2c-8ccb-0d48589c8510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790636711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1790636711 |
| Directory | /workspace/223.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/224.uart_fifo_reset.504302418 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 101472353036 ps |
| CPU time | 32.27 seconds |
| Started | Jul 12 04:41:23 PM PDT 24 |
| Finished | Jul 12 04:41:57 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-c0d3e00f-e58f-44ee-afc3-d2104e187dad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504302418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.504302418 |
| Directory | /workspace/224.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/225.uart_fifo_reset.2790950731 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 13400130848 ps |
| CPU time | 19.9 seconds |
| Started | Jul 12 04:41:22 PM PDT 24 |
| Finished | Jul 12 04:41:42 PM PDT 24 |
| Peak memory | 199456 kb |
| Host | smart-e6590baa-de8b-4b03-9309-0f39c9261719 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790950731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2790950731 |
| Directory | /workspace/225.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/226.uart_fifo_reset.3911894520 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 115904508230 ps |
| CPU time | 192.86 seconds |
| Started | Jul 12 04:41:24 PM PDT 24 |
| Finished | Jul 12 04:44:38 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-03f5cac3-2837-4c3d-921c-f115acd71242 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911894520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3911894520 |
| Directory | /workspace/226.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/227.uart_fifo_reset.3206077387 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 50802427285 ps |
| CPU time | 35.45 seconds |
| Started | Jul 12 04:41:38 PM PDT 24 |
| Finished | Jul 12 04:42:14 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-066c905a-a5dd-4d5a-a06f-e96838eed44f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206077387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3206077387 |
| Directory | /workspace/227.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/228.uart_fifo_reset.3174794962 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 96113126045 ps |
| CPU time | 39.36 seconds |
| Started | Jul 12 04:41:24 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-a032d9a6-03d6-4f36-a6c5-d0650109bc73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174794962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3174794962 |
| Directory | /workspace/228.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/229.uart_fifo_reset.3089237608 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 89393431421 ps |
| CPU time | 105.99 seconds |
| Started | Jul 12 04:41:25 PM PDT 24 |
| Finished | Jul 12 04:43:12 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-d69e287f-a9f1-409d-85da-cbc8641ddb30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089237608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3089237608 |
| Directory | /workspace/229.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_alert_test.1823854430 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 52757249 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:39:35 PM PDT 24 |
| Peak memory | 195252 kb |
| Host | smart-c691e812-7fc1-4edf-92e5-14adbe018ff5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823854430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1823854430 |
| Directory | /workspace/23.uart_alert_test/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_full.1182482687 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 58522423297 ps |
| CPU time | 99.66 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:41:25 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-65de0cb9-f39b-4a3b-9c3b-6ea99c5d73f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182482687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1182482687 |
| Directory | /workspace/23.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_overflow.4162124009 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 237279982626 ps |
| CPU time | 391.51 seconds |
| Started | Jul 12 04:39:38 PM PDT 24 |
| Finished | Jul 12 04:46:16 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-17a17ecc-a912-487f-942e-53890e6d7735 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4162124009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4162124009 |
| Directory | /workspace/23.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_reset.4112541126 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 58989105693 ps |
| CPU time | 79.57 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:40:55 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-cabfb847-2743-4053-8f6d-09eb86afce6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112541126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4112541126 |
| Directory | /workspace/23.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_intr.1130526944 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 28909917165 ps |
| CPU time | 25.91 seconds |
| Started | Jul 12 04:39:44 PM PDT 24 |
| Finished | Jul 12 04:40:15 PM PDT 24 |
| Peak memory | 199540 kb |
| Host | smart-83aa0059-35c2-4c80-9271-e41d03239918 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130526944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1130526944 |
| Directory | /workspace/23.uart_intr/latest |
| Test location | /workspace/coverage/default/23.uart_long_xfer_wo_dly.759662203 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 73973043287 ps |
| CPU time | 170.91 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:42:27 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-c95c4b54-229d-4ca5-84e7-278cac75206d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=759662203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.759662203 |
| Directory | /workspace/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/23.uart_loopback.1789965902 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2871456869 ps |
| CPU time | 5.93 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:39:40 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-04f51a08-15b1-45c5-a6bd-3187820eafe7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789965902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1789965902 |
| Directory | /workspace/23.uart_loopback/latest |
| Test location | /workspace/coverage/default/23.uart_noise_filter.1561462953 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 52439836002 ps |
| CPU time | 131.15 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:41:45 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-4df7b689-7f39-4faf-83c4-754d1908fd45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561462953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1561462953 |
| Directory | /workspace/23.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/23.uart_perf.2265648826 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 12420438263 ps |
| CPU time | 257.6 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:44:03 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-75665ac1-ade3-494c-8452-5b87e582a1d8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2265648826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2265648826 |
| Directory | /workspace/23.uart_perf/latest |
| Test location | /workspace/coverage/default/23.uart_rx_oversample.3559290001 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 5741344803 ps |
| CPU time | 24.03 seconds |
| Started | Jul 12 04:39:25 PM PDT 24 |
| Finished | Jul 12 04:39:53 PM PDT 24 |
| Peak memory | 198128 kb |
| Host | smart-cd2d0e32-737d-4eaa-9580-9bb5be83bda9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3559290001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3559290001 |
| Directory | /workspace/23.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/23.uart_rx_parity_err.3015517306 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 203319098950 ps |
| CPU time | 183.7 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:42:39 PM PDT 24 |
| Peak memory | 200076 kb |
| Host | smart-c5431039-d5ea-4d0d-bc24-673528aaa198 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015517306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3015517306 |
| Directory | /workspace/23.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/23.uart_rx_start_bit_filter.3195631634 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 4569525063 ps |
| CPU time | 1.21 seconds |
| Started | Jul 12 04:39:26 PM PDT 24 |
| Finished | Jul 12 04:39:32 PM PDT 24 |
| Peak memory | 196232 kb |
| Host | smart-0f9a6849-24da-41ce-b7e9-95b0a7e856d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195631634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3195631634 |
| Directory | /workspace/23.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/23.uart_smoke.3141728851 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 691983645 ps |
| CPU time | 2.55 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 198564 kb |
| Host | smart-8b16dfb5-b7ae-40ef-96a4-1aecd4d55644 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3141728851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3141728851 |
| Directory | /workspace/23.uart_smoke/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all.4258468729 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 366483798997 ps |
| CPU time | 400.93 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:46:25 PM PDT 24 |
| Peak memory | 215468 kb |
| Host | smart-395056ba-fdb2-490d-aaca-6b3825197b93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258468729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4258468729 |
| Directory | /workspace/23.uart_stress_all/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2364834078 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 190212774333 ps |
| CPU time | 822.09 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:53:17 PM PDT 24 |
| Peak memory | 224680 kb |
| Host | smart-f3bdae57-0252-48cb-8776-df2086e6ba8c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364834078 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2364834078 |
| Directory | /workspace/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.uart_tx_ovrd.2932494534 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 647474025 ps |
| CPU time | 2.28 seconds |
| Started | Jul 12 04:39:23 PM PDT 24 |
| Finished | Jul 12 04:39:29 PM PDT 24 |
| Peak memory | 198196 kb |
| Host | smart-300e832f-21b6-4ebb-bd47-08afc2242038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932494534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2932494534 |
| Directory | /workspace/23.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/23.uart_tx_rx.3740427874 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 121234504949 ps |
| CPU time | 374.55 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:45:58 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-567a200d-bffc-41cc-9ae3-42629d2ae996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740427874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3740427874 |
| Directory | /workspace/23.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/230.uart_fifo_reset.23660872 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 78439648359 ps |
| CPU time | 30.82 seconds |
| Started | Jul 12 04:41:26 PM PDT 24 |
| Finished | Jul 12 04:41:57 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-1d147e66-6162-4815-bd6b-86bcc36a67bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23660872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.23660872 |
| Directory | /workspace/230.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/231.uart_fifo_reset.3649929035 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 15568208445 ps |
| CPU time | 35.58 seconds |
| Started | Jul 12 04:41:24 PM PDT 24 |
| Finished | Jul 12 04:42:01 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-6aee11f2-d63e-4261-9df1-05fee7f0c19b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3649929035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3649929035 |
| Directory | /workspace/231.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/232.uart_fifo_reset.856398786 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 130046052610 ps |
| CPU time | 195.4 seconds |
| Started | Jul 12 04:41:24 PM PDT 24 |
| Finished | Jul 12 04:44:40 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-60fd19b6-7bc0-4be4-aad7-a7ae723484f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856398786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.856398786 |
| Directory | /workspace/232.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/233.uart_fifo_reset.612966279 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 62740543197 ps |
| CPU time | 53 seconds |
| Started | Jul 12 04:41:29 PM PDT 24 |
| Finished | Jul 12 04:42:23 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-8890d0b9-ffc9-409c-b1d9-90e55ec66ae4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612966279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.612966279 |
| Directory | /workspace/233.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/234.uart_fifo_reset.117777725 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 24968997963 ps |
| CPU time | 31.77 seconds |
| Started | Jul 12 04:41:26 PM PDT 24 |
| Finished | Jul 12 04:41:58 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-8cf7df8e-e721-4bd5-9b24-97a8e4b83c55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117777725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.117777725 |
| Directory | /workspace/234.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/235.uart_fifo_reset.4114325370 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 109279703947 ps |
| CPU time | 54.1 seconds |
| Started | Jul 12 04:41:25 PM PDT 24 |
| Finished | Jul 12 04:42:20 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-b255afef-2626-4cc1-b09c-837599fbfdda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114325370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.4114325370 |
| Directory | /workspace/235.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/236.uart_fifo_reset.3599861278 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 26742892276 ps |
| CPU time | 15.38 seconds |
| Started | Jul 12 04:41:24 PM PDT 24 |
| Finished | Jul 12 04:41:41 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-67106e68-a3b6-47c1-a0b3-82fd36807cf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599861278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3599861278 |
| Directory | /workspace/236.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/237.uart_fifo_reset.2727004188 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 77819753127 ps |
| CPU time | 21.94 seconds |
| Started | Jul 12 04:41:27 PM PDT 24 |
| Finished | Jul 12 04:41:50 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-eb20eaf3-5f61-4bc1-adb5-259aa6cb907f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727004188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2727004188 |
| Directory | /workspace/237.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/238.uart_fifo_reset.4008635989 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 35093128619 ps |
| CPU time | 19.41 seconds |
| Started | Jul 12 04:41:23 PM PDT 24 |
| Finished | Jul 12 04:41:44 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-00e8b29e-323c-41e8-88a5-2323b229e9f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008635989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4008635989 |
| Directory | /workspace/238.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/239.uart_fifo_reset.2687288904 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 26024281166 ps |
| CPU time | 45.33 seconds |
| Started | Jul 12 04:41:25 PM PDT 24 |
| Finished | Jul 12 04:42:11 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-2129d3ac-0187-421d-8ae0-ce915cb292db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687288904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2687288904 |
| Directory | /workspace/239.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_alert_test.1264343464 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 68068065 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:39:10 PM PDT 24 |
| Finished | Jul 12 04:39:18 PM PDT 24 |
| Peak memory | 195436 kb |
| Host | smart-c3b19aeb-468d-4013-a664-a1ed977a8506 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264343464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1264343464 |
| Directory | /workspace/24.uart_alert_test/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_full.185596629 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 111611584833 ps |
| CPU time | 121.55 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:41:47 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-922b1804-7438-40cc-a309-89aa1be92c68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185596629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.185596629 |
| Directory | /workspace/24.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_overflow.2477800869 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 219033701645 ps |
| CPU time | 290.18 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:44:09 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-4e9ad294-808c-408c-9c59-ecc3ac271f8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2477800869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2477800869 |
| Directory | /workspace/24.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_reset.122954466 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 87018416158 ps |
| CPU time | 75.01 seconds |
| Started | Jul 12 04:39:33 PM PDT 24 |
| Finished | Jul 12 04:40:54 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-1458f3bc-a33f-4f50-a8b0-d4fb78bc5503 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=122954466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.122954466 |
| Directory | /workspace/24.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_intr.1886533249 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 158749158255 ps |
| CPU time | 18.12 seconds |
| Started | Jul 12 04:39:32 PM PDT 24 |
| Finished | Jul 12 04:39:56 PM PDT 24 |
| Peak memory | 199312 kb |
| Host | smart-55c917f8-8950-45e2-ac00-ed7f2fc92ff9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886533249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1886533249 |
| Directory | /workspace/24.uart_intr/latest |
| Test location | /workspace/coverage/default/24.uart_long_xfer_wo_dly.3813646098 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 103033420777 ps |
| CPU time | 179.02 seconds |
| Started | Jul 12 04:39:43 PM PDT 24 |
| Finished | Jul 12 04:42:48 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-74d7aa04-53b1-4fb5-9896-be88cb7b5143 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3813646098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3813646098 |
| Directory | /workspace/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/24.uart_loopback.3896301116 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 4573974782 ps |
| CPU time | 2.75 seconds |
| Started | Jul 12 04:39:24 PM PDT 24 |
| Finished | Jul 12 04:39:30 PM PDT 24 |
| Peak memory | 198044 kb |
| Host | smart-56bafcb1-013a-483f-baea-d2c62aea1a12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896301116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3896301116 |
| Directory | /workspace/24.uart_loopback/latest |
| Test location | /workspace/coverage/default/24.uart_noise_filter.3199454352 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 404067165300 ps |
| CPU time | 135.85 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:41:51 PM PDT 24 |
| Peak memory | 200012 kb |
| Host | smart-78c4669a-cb8a-441d-8365-d1545f8be85b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199454352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3199454352 |
| Directory | /workspace/24.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/24.uart_perf.4006680351 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 13162025801 ps |
| CPU time | 703.99 seconds |
| Started | Jul 12 04:39:26 PM PDT 24 |
| Finished | Jul 12 04:51:14 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-eab85e11-a6c3-4d22-8509-089216104ac0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4006680351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4006680351 |
| Directory | /workspace/24.uart_perf/latest |
| Test location | /workspace/coverage/default/24.uart_rx_oversample.3745591674 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 5609985818 ps |
| CPU time | 54.96 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:40:28 PM PDT 24 |
| Peak memory | 197952 kb |
| Host | smart-5a11e07b-260f-465a-b4e1-908c43cac970 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3745591674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3745591674 |
| Directory | /workspace/24.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/24.uart_rx_parity_err.3815283173 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 140594229004 ps |
| CPU time | 452.89 seconds |
| Started | Jul 12 04:39:41 PM PDT 24 |
| Finished | Jul 12 04:47:20 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-f406d95c-189c-4a25-8005-a4cd73c1bd66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815283173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3815283173 |
| Directory | /workspace/24.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/24.uart_rx_start_bit_filter.131787181 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1599573582 ps |
| CPU time | 1.88 seconds |
| Started | Jul 12 04:39:25 PM PDT 24 |
| Finished | Jul 12 04:39:30 PM PDT 24 |
| Peak memory | 195372 kb |
| Host | smart-3dbc957c-6b47-44a1-bbef-26609cc7f1ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131787181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.131787181 |
| Directory | /workspace/24.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/24.uart_smoke.2468224732 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 6208208869 ps |
| CPU time | 8.89 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:50 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-3e89c7e8-d34a-4f0a-8cbc-5b9dea19c651 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468224732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2468224732 |
| Directory | /workspace/24.uart_smoke/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all.3307889869 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 126006030770 ps |
| CPU time | 228.4 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:43:23 PM PDT 24 |
| Peak memory | 208120 kb |
| Host | smart-c7cdd129-0ee0-400e-9f3a-c86564248385 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307889869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3307889869 |
| Directory | /workspace/24.uart_stress_all/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1980682980 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 303497505002 ps |
| CPU time | 946.07 seconds |
| Started | Jul 12 04:39:25 PM PDT 24 |
| Finished | Jul 12 04:55:14 PM PDT 24 |
| Peak memory | 224692 kb |
| Host | smart-b7c21dd1-e0d0-49a5-b250-d62d8b89075b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980682980 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1980682980 |
| Directory | /workspace/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.uart_tx_ovrd.1060835217 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3037087482 ps |
| CPU time | 2.31 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:39:37 PM PDT 24 |
| Peak memory | 198352 kb |
| Host | smart-35899e5f-785c-42be-8277-2b00a8e4abd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060835217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1060835217 |
| Directory | /workspace/24.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/24.uart_tx_rx.2737219489 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 101087387708 ps |
| CPU time | 44.6 seconds |
| Started | Jul 12 04:39:23 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-956c1207-6f28-4f85-91bf-471aecf3fee4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737219489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2737219489 |
| Directory | /workspace/24.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/241.uart_fifo_reset.387030868 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 47157202763 ps |
| CPU time | 44.24 seconds |
| Started | Jul 12 04:41:31 PM PDT 24 |
| Finished | Jul 12 04:42:17 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-2f207166-48df-4ea2-9bd7-ebabfb6ad1f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387030868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.387030868 |
| Directory | /workspace/241.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/243.uart_fifo_reset.2139305128 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 131054866510 ps |
| CPU time | 123.51 seconds |
| Started | Jul 12 04:41:30 PM PDT 24 |
| Finished | Jul 12 04:43:36 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-a2e12306-badc-44e1-93a8-52e473df6f36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139305128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2139305128 |
| Directory | /workspace/243.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/244.uart_fifo_reset.287052612 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 34586437579 ps |
| CPU time | 53.23 seconds |
| Started | Jul 12 04:41:30 PM PDT 24 |
| Finished | Jul 12 04:42:24 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-788b61f4-3041-40e4-92cf-477cbb17153c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287052612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.287052612 |
| Directory | /workspace/244.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/245.uart_fifo_reset.3279749191 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 301013410320 ps |
| CPU time | 277.72 seconds |
| Started | Jul 12 04:41:31 PM PDT 24 |
| Finished | Jul 12 04:46:10 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-a12252f1-8255-4a61-b06c-408a21c8e605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279749191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3279749191 |
| Directory | /workspace/245.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/247.uart_fifo_reset.1236567615 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 20148023238 ps |
| CPU time | 32.1 seconds |
| Started | Jul 12 04:41:30 PM PDT 24 |
| Finished | Jul 12 04:42:03 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-0ce1615e-b214-4574-8ff5-3c5c77f31d25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236567615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1236567615 |
| Directory | /workspace/247.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/248.uart_fifo_reset.2735773382 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 258755003327 ps |
| CPU time | 78.89 seconds |
| Started | Jul 12 04:41:31 PM PDT 24 |
| Finished | Jul 12 04:42:51 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-07ee1e90-4126-40bb-83af-961aad372ff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735773382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2735773382 |
| Directory | /workspace/248.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/249.uart_fifo_reset.1101739739 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 96664531904 ps |
| CPU time | 81.71 seconds |
| Started | Jul 12 04:41:28 PM PDT 24 |
| Finished | Jul 12 04:42:51 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-4ba75692-ec6a-40c5-bc56-47c6ed802ffb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101739739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1101739739 |
| Directory | /workspace/249.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_alert_test.2621452133 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 49668259 ps |
| CPU time | 0.61 seconds |
| Started | Jul 12 04:39:19 PM PDT 24 |
| Finished | Jul 12 04:39:24 PM PDT 24 |
| Peak memory | 195384 kb |
| Host | smart-46939050-9071-4e02-9ee1-c539d36969b5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621452133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2621452133 |
| Directory | /workspace/25.uart_alert_test/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_full.607447057 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 27414860357 ps |
| CPU time | 21.21 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:39:58 PM PDT 24 |
| Peak memory | 199492 kb |
| Host | smart-ff0e838e-e61d-47f7-aa2d-ae43f6afb7df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607447057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.607447057 |
| Directory | /workspace/25.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_overflow.260052409 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 26645011695 ps |
| CPU time | 45.68 seconds |
| Started | Jul 12 04:39:33 PM PDT 24 |
| Finished | Jul 12 04:40:25 PM PDT 24 |
| Peak memory | 199632 kb |
| Host | smart-431ca2c9-8598-4076-b9be-775dc85c6cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260052409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.260052409 |
| Directory | /workspace/25.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_reset.4164103452 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 100992401721 ps |
| CPU time | 138.6 seconds |
| Started | Jul 12 04:39:19 PM PDT 24 |
| Finished | Jul 12 04:41:42 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-05608425-cd4c-4c8c-be7e-18aa19cf9d9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164103452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.4164103452 |
| Directory | /workspace/25.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_intr.2879380452 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 134162492267 ps |
| CPU time | 70.08 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:40:44 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-575eaa59-bb8f-4838-8bf4-a7bfa52d91a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879380452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2879380452 |
| Directory | /workspace/25.uart_intr/latest |
| Test location | /workspace/coverage/default/25.uart_long_xfer_wo_dly.1106734393 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 199031414278 ps |
| CPU time | 521.79 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:48:16 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-268281c7-2a4c-49f8-a3e8-f2cf19698ecb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1106734393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1106734393 |
| Directory | /workspace/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/25.uart_loopback.2267274827 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 21886301 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:39:10 PM PDT 24 |
| Finished | Jul 12 04:39:18 PM PDT 24 |
| Peak memory | 195928 kb |
| Host | smart-16f88a84-859d-4ce3-97e6-233a32264bb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267274827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2267274827 |
| Directory | /workspace/25.uart_loopback/latest |
| Test location | /workspace/coverage/default/25.uart_noise_filter.1680702232 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 22716398519 ps |
| CPU time | 20.37 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:40:05 PM PDT 24 |
| Peak memory | 198780 kb |
| Host | smart-65383143-4158-44e7-a500-f6d255986c46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680702232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1680702232 |
| Directory | /workspace/25.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/25.uart_perf.3865529215 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 6444202174 ps |
| CPU time | 164.31 seconds |
| Started | Jul 12 04:39:20 PM PDT 24 |
| Finished | Jul 12 04:42:08 PM PDT 24 |
| Peak memory | 199696 kb |
| Host | smart-26581d46-7e37-4797-a2a6-da122a0c8f87 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3865529215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3865529215 |
| Directory | /workspace/25.uart_perf/latest |
| Test location | /workspace/coverage/default/25.uart_rx_oversample.853813513 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 5535609312 ps |
| CPU time | 12.49 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 198740 kb |
| Host | smart-69ae082b-0921-4bd7-b3b0-219aa3ec2131 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=853813513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.853813513 |
| Directory | /workspace/25.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/25.uart_rx_parity_err.3028703621 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 83658820584 ps |
| CPU time | 161.65 seconds |
| Started | Jul 12 04:39:32 PM PDT 24 |
| Finished | Jul 12 04:42:19 PM PDT 24 |
| Peak memory | 199636 kb |
| Host | smart-b554c695-cb44-4e6c-bda4-d0dd05bd1396 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028703621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3028703621 |
| Directory | /workspace/25.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/25.uart_rx_start_bit_filter.3981791847 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5926950493 ps |
| CPU time | 2.4 seconds |
| Started | Jul 12 04:39:25 PM PDT 24 |
| Finished | Jul 12 04:39:30 PM PDT 24 |
| Peak memory | 195880 kb |
| Host | smart-b16b686e-ad83-46b6-966e-1b90cfc230c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981791847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3981791847 |
| Directory | /workspace/25.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/25.uart_smoke.2637618332 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 5991221653 ps |
| CPU time | 8.62 seconds |
| Started | Jul 12 04:39:26 PM PDT 24 |
| Finished | Jul 12 04:39:39 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-2c5a650c-fb2b-4b57-b36b-7a63ab68ca8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637618332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2637618332 |
| Directory | /workspace/25.uart_smoke/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1390171514 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 60863581629 ps |
| CPU time | 169.56 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:42:32 PM PDT 24 |
| Peak memory | 215228 kb |
| Host | smart-84bb9466-49e7-4002-a8c9-ac25b292d522 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390171514 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1390171514 |
| Directory | /workspace/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.uart_tx_ovrd.738966238 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 6508371161 ps |
| CPU time | 16.98 seconds |
| Started | Jul 12 04:39:27 PM PDT 24 |
| Finished | Jul 12 04:39:49 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-7faa119a-e632-4041-8f25-3e5d433af182 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738966238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.738966238 |
| Directory | /workspace/25.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/25.uart_tx_rx.1318195684 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 24541516752 ps |
| CPU time | 10.93 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:39:44 PM PDT 24 |
| Peak memory | 197696 kb |
| Host | smart-17d1e8da-cc02-4e60-86ca-99b9cc151d5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1318195684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1318195684 |
| Directory | /workspace/25.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/250.uart_fifo_reset.751272947 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 32982331051 ps |
| CPU time | 30.31 seconds |
| Started | Jul 12 04:41:30 PM PDT 24 |
| Finished | Jul 12 04:42:01 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-82d97ea0-9f32-4200-8f5e-b8a75690848e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751272947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.751272947 |
| Directory | /workspace/250.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/251.uart_fifo_reset.2809392205 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 102931377796 ps |
| CPU time | 17.29 seconds |
| Started | Jul 12 04:41:31 PM PDT 24 |
| Finished | Jul 12 04:41:50 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-5f7c2362-c154-40a2-b1f3-433e3ca88861 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809392205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2809392205 |
| Directory | /workspace/251.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/252.uart_fifo_reset.1003240839 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 264991025277 ps |
| CPU time | 27.1 seconds |
| Started | Jul 12 04:41:32 PM PDT 24 |
| Finished | Jul 12 04:42:00 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-8e3e27de-5c93-4415-8a61-ddfd957150b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003240839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1003240839 |
| Directory | /workspace/252.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/253.uart_fifo_reset.3595464145 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 39519950214 ps |
| CPU time | 26.74 seconds |
| Started | Jul 12 04:41:34 PM PDT 24 |
| Finished | Jul 12 04:42:02 PM PDT 24 |
| Peak memory | 200016 kb |
| Host | smart-9339514e-76a6-43f3-84a6-df1504256e2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595464145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3595464145 |
| Directory | /workspace/253.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/254.uart_fifo_reset.2276957994 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 12784965742 ps |
| CPU time | 11.69 seconds |
| Started | Jul 12 04:41:34 PM PDT 24 |
| Finished | Jul 12 04:41:46 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-aebac3d4-b827-4d01-a996-7e083ae8033b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276957994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2276957994 |
| Directory | /workspace/254.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/256.uart_fifo_reset.2397346578 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 35283335934 ps |
| CPU time | 16.31 seconds |
| Started | Jul 12 04:41:36 PM PDT 24 |
| Finished | Jul 12 04:41:53 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-bcea6e43-1f33-41e4-ba3d-f564bc834783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2397346578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2397346578 |
| Directory | /workspace/256.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/257.uart_fifo_reset.3744600587 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 62182501928 ps |
| CPU time | 188.31 seconds |
| Started | Jul 12 04:41:36 PM PDT 24 |
| Finished | Jul 12 04:44:45 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-4831b754-b780-4755-a9cc-7878ed836596 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744600587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3744600587 |
| Directory | /workspace/257.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/258.uart_fifo_reset.2617950130 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 75578682693 ps |
| CPU time | 58.43 seconds |
| Started | Jul 12 04:41:35 PM PDT 24 |
| Finished | Jul 12 04:42:35 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-ccc50ca1-582f-42c8-9414-5d5a50469207 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617950130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2617950130 |
| Directory | /workspace/258.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/259.uart_fifo_reset.235271460 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 7516601667 ps |
| CPU time | 17.25 seconds |
| Started | Jul 12 04:41:35 PM PDT 24 |
| Finished | Jul 12 04:41:54 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-d48d6b3c-3774-4e5e-9cc5-2e7729dffc55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235271460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.235271460 |
| Directory | /workspace/259.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_alert_test.2512578639 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 23241099 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:39:47 PM PDT 24 |
| Peak memory | 195476 kb |
| Host | smart-e59423bc-3139-44fe-bc3c-041855a304c2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512578639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2512578639 |
| Directory | /workspace/26.uart_alert_test/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_full.1365567499 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 50061681596 ps |
| CPU time | 38.21 seconds |
| Started | Jul 12 04:39:27 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-d8a91361-101b-4307-8575-7d458c328b54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365567499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1365567499 |
| Directory | /workspace/26.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_overflow.260152628 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 38499371035 ps |
| CPU time | 11.65 seconds |
| Started | Jul 12 04:39:41 PM PDT 24 |
| Finished | Jul 12 04:39:59 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-28780c98-2aaf-4fd9-90ff-79fe51bce133 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260152628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.260152628 |
| Directory | /workspace/26.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/26.uart_long_xfer_wo_dly.3798159868 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 270506729327 ps |
| CPU time | 644.17 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:50:20 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-440a3c6c-7ed6-4b44-aeb0-59351e8e3dbe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3798159868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3798159868 |
| Directory | /workspace/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/26.uart_loopback.2564744259 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 6635348630 ps |
| CPU time | 16.33 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:39:57 PM PDT 24 |
| Peak memory | 199528 kb |
| Host | smart-701d7a4c-3b98-47e1-a227-847202120d03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564744259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2564744259 |
| Directory | /workspace/26.uart_loopback/latest |
| Test location | /workspace/coverage/default/26.uart_noise_filter.1783197929 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 82339100676 ps |
| CPU time | 42.18 seconds |
| Started | Jul 12 04:39:24 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 208232 kb |
| Host | smart-83f7d6ef-4a08-4a24-bf5c-c6b4491b2878 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783197929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1783197929 |
| Directory | /workspace/26.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/26.uart_perf.2205262554 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 8994526104 ps |
| CPU time | 225.36 seconds |
| Started | Jul 12 04:39:42 PM PDT 24 |
| Finished | Jul 12 04:43:34 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-72d16f22-135f-49b9-85c4-c7c2aef43de2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2205262554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2205262554 |
| Directory | /workspace/26.uart_perf/latest |
| Test location | /workspace/coverage/default/26.uart_rx_oversample.2796253068 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4911197829 ps |
| CPU time | 41.81 seconds |
| Started | Jul 12 04:39:26 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 197808 kb |
| Host | smart-bae2cf2c-aa00-45fc-901e-9bbd398474b7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2796253068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2796253068 |
| Directory | /workspace/26.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/26.uart_rx_parity_err.863864642 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 45721915704 ps |
| CPU time | 23.1 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:40:09 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-45fc9613-1fb4-4dd2-9a8e-ed3be89c2604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863864642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.863864642 |
| Directory | /workspace/26.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/26.uart_rx_start_bit_filter.583815561 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 453838260 ps |
| CPU time | 1.27 seconds |
| Started | Jul 12 04:39:41 PM PDT 24 |
| Finished | Jul 12 04:39:49 PM PDT 24 |
| Peak memory | 195324 kb |
| Host | smart-1d08d4a4-6985-4956-b04a-50a8c27973ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583815561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.583815561 |
| Directory | /workspace/26.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/26.uart_smoke.2081306064 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 490712874 ps |
| CPU time | 1.35 seconds |
| Started | Jul 12 04:39:41 PM PDT 24 |
| Finished | Jul 12 04:39:49 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-19f9a95d-7b98-403f-a8d1-bee33572c273 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081306064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2081306064 |
| Directory | /workspace/26.uart_smoke/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all.3640912304 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 4294608640 ps |
| CPU time | 3.79 seconds |
| Started | Jul 12 04:39:36 PM PDT 24 |
| Finished | Jul 12 04:39:46 PM PDT 24 |
| Peak memory | 199696 kb |
| Host | smart-5d1cd2bb-34db-4cad-bd6b-820c639390ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640912304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3640912304 |
| Directory | /workspace/26.uart_stress_all/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3394734275 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 66926743992 ps |
| CPU time | 319.72 seconds |
| Started | Jul 12 04:39:41 PM PDT 24 |
| Finished | Jul 12 04:45:07 PM PDT 24 |
| Peak memory | 216688 kb |
| Host | smart-2ec4f10a-21e2-4162-86e5-921cc675a53f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394734275 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3394734275 |
| Directory | /workspace/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.uart_tx_ovrd.468466474 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 1162997323 ps |
| CPU time | 1.13 seconds |
| Started | Jul 12 04:39:41 PM PDT 24 |
| Finished | Jul 12 04:39:49 PM PDT 24 |
| Peak memory | 196828 kb |
| Host | smart-615f0338-3e2e-4318-949e-0d7bfc582d09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468466474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.468466474 |
| Directory | /workspace/26.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/26.uart_tx_rx.2738361764 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 18903923084 ps |
| CPU time | 28.22 seconds |
| Started | Jul 12 04:39:32 PM PDT 24 |
| Finished | Jul 12 04:40:05 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-14ec7c9d-d7ea-445b-b16d-68ed8f0716ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2738361764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2738361764 |
| Directory | /workspace/26.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/260.uart_fifo_reset.1243034567 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 49569292297 ps |
| CPU time | 105.07 seconds |
| Started | Jul 12 04:41:38 PM PDT 24 |
| Finished | Jul 12 04:43:24 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-b27290de-ba2c-49f3-b580-cf0364a3e23c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243034567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1243034567 |
| Directory | /workspace/260.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/261.uart_fifo_reset.3243029211 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 29090702564 ps |
| CPU time | 19.48 seconds |
| Started | Jul 12 04:41:35 PM PDT 24 |
| Finished | Jul 12 04:41:55 PM PDT 24 |
| Peak memory | 199404 kb |
| Host | smart-7fbfb092-184e-410d-9be3-dee5022feb96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243029211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3243029211 |
| Directory | /workspace/261.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/262.uart_fifo_reset.3698089714 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 37632390438 ps |
| CPU time | 10.97 seconds |
| Started | Jul 12 04:41:36 PM PDT 24 |
| Finished | Jul 12 04:41:48 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-2db3bf9e-53b5-457d-a154-c19d8b9ce405 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698089714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3698089714 |
| Directory | /workspace/262.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/263.uart_fifo_reset.2929236446 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 170928711001 ps |
| CPU time | 67.01 seconds |
| Started | Jul 12 04:41:34 PM PDT 24 |
| Finished | Jul 12 04:42:43 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-707374b4-2f95-4f65-90ae-df8dc9aab747 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929236446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2929236446 |
| Directory | /workspace/263.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/264.uart_fifo_reset.3915609500 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 181145240786 ps |
| CPU time | 108.73 seconds |
| Started | Jul 12 04:41:34 PM PDT 24 |
| Finished | Jul 12 04:43:24 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-28db3b15-ae16-4291-a8e1-662c5cef41fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915609500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3915609500 |
| Directory | /workspace/264.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/266.uart_fifo_reset.1076868647 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 167946597912 ps |
| CPU time | 99.13 seconds |
| Started | Jul 12 04:41:35 PM PDT 24 |
| Finished | Jul 12 04:43:16 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-453e2a4a-62e1-4c38-bf2c-dd7c9cb91615 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1076868647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1076868647 |
| Directory | /workspace/266.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/269.uart_fifo_reset.2877224952 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 232647053868 ps |
| CPU time | 109.23 seconds |
| Started | Jul 12 04:41:40 PM PDT 24 |
| Finished | Jul 12 04:43:30 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-5a9afdec-5722-42cf-813d-9c508c8c33bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877224952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2877224952 |
| Directory | /workspace/269.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_alert_test.2439257366 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 21200576 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:39:26 PM PDT 24 |
| Finished | Jul 12 04:39:30 PM PDT 24 |
| Peak memory | 195188 kb |
| Host | smart-c5c1f56d-566d-4ea5-8b22-728432751aa8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439257366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2439257366 |
| Directory | /workspace/27.uart_alert_test/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_full.2739659117 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 25594300618 ps |
| CPU time | 37.49 seconds |
| Started | Jul 12 04:39:25 PM PDT 24 |
| Finished | Jul 12 04:40:06 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-031a2a9c-6ae1-4a01-a5c5-0bb0e3aba57b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739659117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2739659117 |
| Directory | /workspace/27.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_overflow.954377053 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 50550373193 ps |
| CPU time | 18.13 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:39:55 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-185453ec-a120-4df1-8e9f-86f5cfe199dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954377053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.954377053 |
| Directory | /workspace/27.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_reset.2915557696 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 109773040739 ps |
| CPU time | 89.45 seconds |
| Started | Jul 12 04:39:23 PM PDT 24 |
| Finished | Jul 12 04:40:56 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-85ed5e6f-4c4c-4f3d-ad0f-4e1074ac049c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915557696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2915557696 |
| Directory | /workspace/27.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_intr.2082585750 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 181355991498 ps |
| CPU time | 157.97 seconds |
| Started | Jul 12 04:39:42 PM PDT 24 |
| Finished | Jul 12 04:42:26 PM PDT 24 |
| Peak memory | 199572 kb |
| Host | smart-3d4bcb2a-de2b-4bdb-895f-521ad5efdcc1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082585750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2082585750 |
| Directory | /workspace/27.uart_intr/latest |
| Test location | /workspace/coverage/default/27.uart_long_xfer_wo_dly.3334956302 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 61637671471 ps |
| CPU time | 152.19 seconds |
| Started | Jul 12 04:39:38 PM PDT 24 |
| Finished | Jul 12 04:42:16 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-02091629-ae50-4f35-aef8-b6e5d047945e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3334956302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3334956302 |
| Directory | /workspace/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/27.uart_loopback.1086776635 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 2333044671 ps |
| CPU time | 1.76 seconds |
| Started | Jul 12 04:39:48 PM PDT 24 |
| Finished | Jul 12 04:39:55 PM PDT 24 |
| Peak memory | 195972 kb |
| Host | smart-82b2c377-d036-4adf-9fb3-cecfa68a8723 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086776635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1086776635 |
| Directory | /workspace/27.uart_loopback/latest |
| Test location | /workspace/coverage/default/27.uart_noise_filter.118283976 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 52471436291 ps |
| CPU time | 91.67 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:41:08 PM PDT 24 |
| Peak memory | 208256 kb |
| Host | smart-ab654868-9b18-4d04-992b-11b449ebbe5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118283976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.118283976 |
| Directory | /workspace/27.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/27.uart_perf.4112687919 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 32430037485 ps |
| CPU time | 955.11 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:55:32 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-37d10d6b-1d96-4925-a45c-2443c65773da |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4112687919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4112687919 |
| Directory | /workspace/27.uart_perf/latest |
| Test location | /workspace/coverage/default/27.uart_rx_oversample.4116358474 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 7390382396 ps |
| CPU time | 18.36 seconds |
| Started | Jul 12 04:39:36 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 199200 kb |
| Host | smart-df24b6f3-7c56-4016-ad78-c56f656b41a2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4116358474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4116358474 |
| Directory | /workspace/27.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/27.uart_rx_parity_err.3947876206 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 24520473610 ps |
| CPU time | 20.23 seconds |
| Started | Jul 12 04:39:23 PM PDT 24 |
| Finished | Jul 12 04:39:47 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-4507d09a-33bb-487a-8814-a00107f8e508 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947876206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3947876206 |
| Directory | /workspace/27.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/27.uart_rx_start_bit_filter.341264959 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 2737052830 ps |
| CPU time | 4.88 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:39:41 PM PDT 24 |
| Peak memory | 196328 kb |
| Host | smart-0ffd2e7b-33dc-44c2-a1d9-8f5356397bd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=341264959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.341264959 |
| Directory | /workspace/27.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/27.uart_smoke.3339587363 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 714433227 ps |
| CPU time | 2.85 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:39:37 PM PDT 24 |
| Peak memory | 199572 kb |
| Host | smart-8690a668-15a9-4c8e-9605-5af044f6e404 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339587363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3339587363 |
| Directory | /workspace/27.uart_smoke/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2284602698 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 89416942757 ps |
| CPU time | 249.31 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:43:46 PM PDT 24 |
| Peak memory | 216548 kb |
| Host | smart-5eabd475-fb33-49c4-8d82-e1436e7a1b29 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284602698 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2284602698 |
| Directory | /workspace/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.uart_tx_ovrd.2138997489 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1840643337 ps |
| CPU time | 1.97 seconds |
| Started | Jul 12 04:39:27 PM PDT 24 |
| Finished | Jul 12 04:39:34 PM PDT 24 |
| Peak memory | 198624 kb |
| Host | smart-c620996f-e28c-4bf1-8ecf-042feab7d81a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138997489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2138997489 |
| Directory | /workspace/27.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/27.uart_tx_rx.2996780050 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 104766474488 ps |
| CPU time | 140.78 seconds |
| Started | Jul 12 04:39:29 PM PDT 24 |
| Finished | Jul 12 04:41:55 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-079cfa30-b8cb-4c0e-85f7-4ff5f24c5452 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996780050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2996780050 |
| Directory | /workspace/27.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/270.uart_fifo_reset.3866766442 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 38687341006 ps |
| CPU time | 16.5 seconds |
| Started | Jul 12 04:41:41 PM PDT 24 |
| Finished | Jul 12 04:41:59 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-02364fb8-d747-434c-b015-db39ccf2e43d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866766442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3866766442 |
| Directory | /workspace/270.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/271.uart_fifo_reset.443220478 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 18619181949 ps |
| CPU time | 13.82 seconds |
| Started | Jul 12 04:41:40 PM PDT 24 |
| Finished | Jul 12 04:41:55 PM PDT 24 |
| Peak memory | 197524 kb |
| Host | smart-b50d4840-cda5-4471-874f-8eda68f4c876 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443220478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.443220478 |
| Directory | /workspace/271.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/272.uart_fifo_reset.3213733205 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 101571864573 ps |
| CPU time | 137.09 seconds |
| Started | Jul 12 04:41:39 PM PDT 24 |
| Finished | Jul 12 04:43:57 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-2936c9ef-ac52-4fde-bd05-72f4ad086d96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3213733205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3213733205 |
| Directory | /workspace/272.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/273.uart_fifo_reset.2863333932 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 101664958654 ps |
| CPU time | 149.84 seconds |
| Started | Jul 12 04:41:40 PM PDT 24 |
| Finished | Jul 12 04:44:10 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-68be9e51-9349-4a44-9a3d-ea7bdfe110ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863333932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2863333932 |
| Directory | /workspace/273.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/274.uart_fifo_reset.1879452116 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 21365689674 ps |
| CPU time | 44.97 seconds |
| Started | Jul 12 04:41:42 PM PDT 24 |
| Finished | Jul 12 04:42:28 PM PDT 24 |
| Peak memory | 199668 kb |
| Host | smart-103d9984-721e-4bb1-ad37-7f97f4085039 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879452116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1879452116 |
| Directory | /workspace/274.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/275.uart_fifo_reset.2177616574 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 151635647107 ps |
| CPU time | 17.18 seconds |
| Started | Jul 12 04:41:41 PM PDT 24 |
| Finished | Jul 12 04:41:59 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-202bf961-f892-4f04-a900-eb1a6df6a3c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2177616574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2177616574 |
| Directory | /workspace/275.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/276.uart_fifo_reset.1336760288 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 250673861554 ps |
| CPU time | 69.88 seconds |
| Started | Jul 12 04:41:40 PM PDT 24 |
| Finished | Jul 12 04:42:50 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-bd0a36bf-c22d-4437-bd58-f1cb98458ab7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336760288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1336760288 |
| Directory | /workspace/276.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/277.uart_fifo_reset.4188178285 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 10917593225 ps |
| CPU time | 13.91 seconds |
| Started | Jul 12 04:41:44 PM PDT 24 |
| Finished | Jul 12 04:41:58 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-c18995a2-1a37-4fb9-8afb-f776c250640e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188178285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.4188178285 |
| Directory | /workspace/277.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/278.uart_fifo_reset.845492260 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 130780101577 ps |
| CPU time | 39.9 seconds |
| Started | Jul 12 04:41:41 PM PDT 24 |
| Finished | Jul 12 04:42:22 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-2099966f-e92e-48dd-8697-2981af5467e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845492260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.845492260 |
| Directory | /workspace/278.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/279.uart_fifo_reset.1679970969 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 188075605525 ps |
| CPU time | 47.82 seconds |
| Started | Jul 12 04:41:40 PM PDT 24 |
| Finished | Jul 12 04:42:29 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-d306d030-1d0d-462f-9d3f-ac2d35750643 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1679970969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1679970969 |
| Directory | /workspace/279.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_alert_test.983449091 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 44537431 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:32 PM PDT 24 |
| Finished | Jul 12 04:39:38 PM PDT 24 |
| Peak memory | 195424 kb |
| Host | smart-8a0c67e4-036f-4f63-80fe-3617aac96f4e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983449091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.983449091 |
| Directory | /workspace/28.uart_alert_test/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_full.3020876412 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 26522264934 ps |
| CPU time | 44.43 seconds |
| Started | Jul 12 04:39:31 PM PDT 24 |
| Finished | Jul 12 04:40:21 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-41f2883f-9f16-4b1e-92b2-99a7ef664035 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020876412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3020876412 |
| Directory | /workspace/28.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_overflow.2154845568 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 27270035062 ps |
| CPU time | 20.05 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-f0a70b32-1fb7-4b25-a7f9-ca87e7f103b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154845568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2154845568 |
| Directory | /workspace/28.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_reset.2559433943 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 31620856026 ps |
| CPU time | 14.26 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:40:00 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-a785d57b-437b-4fb5-a207-4da858620ba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559433943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2559433943 |
| Directory | /workspace/28.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_intr.887496275 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 37395028764 ps |
| CPU time | 74.63 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:40:54 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-05ab4499-d20f-4ba3-bc5f-c15e510084e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887496275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.887496275 |
| Directory | /workspace/28.uart_intr/latest |
| Test location | /workspace/coverage/default/28.uart_long_xfer_wo_dly.3515469988 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 134850238560 ps |
| CPU time | 381.65 seconds |
| Started | Jul 12 04:39:23 PM PDT 24 |
| Finished | Jul 12 04:45:49 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-4dcfde73-0023-4457-84fa-c9d3f80e9d2f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3515469988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3515469988 |
| Directory | /workspace/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/28.uart_loopback.3388788207 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 4779648270 ps |
| CPU time | 7.4 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 196080 kb |
| Host | smart-039c4be9-9490-4d1c-9222-6267dc324702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388788207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3388788207 |
| Directory | /workspace/28.uart_loopback/latest |
| Test location | /workspace/coverage/default/28.uart_noise_filter.710151681 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 167074758221 ps |
| CPU time | 84.22 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:41:05 PM PDT 24 |
| Peak memory | 208196 kb |
| Host | smart-98a46b91-bcad-4a01-a3b1-119679b09c37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710151681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.710151681 |
| Directory | /workspace/28.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/28.uart_perf.787390903 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 13248429341 ps |
| CPU time | 732.44 seconds |
| Started | Jul 12 04:39:38 PM PDT 24 |
| Finished | Jul 12 04:51:57 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-4cfa36fc-93fe-4c71-aa4c-14cecf3f1fcf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=787390903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.787390903 |
| Directory | /workspace/28.uart_perf/latest |
| Test location | /workspace/coverage/default/28.uart_rx_oversample.3397573896 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 6846141502 ps |
| CPU time | 14.63 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:55 PM PDT 24 |
| Peak memory | 198320 kb |
| Host | smart-626db42a-73e8-4816-aaeb-07d33b072bb5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3397573896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3397573896 |
| Directory | /workspace/28.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/28.uart_rx_parity_err.2905314866 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 84827508687 ps |
| CPU time | 136.4 seconds |
| Started | Jul 12 04:39:26 PM PDT 24 |
| Finished | Jul 12 04:41:47 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-62bed158-2ce0-4a23-878a-7143c6490ce7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905314866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2905314866 |
| Directory | /workspace/28.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/28.uart_rx_start_bit_filter.4216471655 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 48656083663 ps |
| CPU time | 65.05 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:40:48 PM PDT 24 |
| Peak memory | 195720 kb |
| Host | smart-7fd061a7-329d-4878-9648-3585e44900a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216471655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4216471655 |
| Directory | /workspace/28.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/28.uart_smoke.283920991 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 6073137278 ps |
| CPU time | 12.03 seconds |
| Started | Jul 12 04:39:33 PM PDT 24 |
| Finished | Jul 12 04:39:51 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-aee257c5-ae60-4b33-b3c9-c991e945bf9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283920991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.283920991 |
| Directory | /workspace/28.uart_smoke/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all.3123737374 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 185630142727 ps |
| CPU time | 95.79 seconds |
| Started | Jul 12 04:39:36 PM PDT 24 |
| Finished | Jul 12 04:41:18 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-c5e7c06b-b5e8-4d20-ad09-9c8514a51caa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123737374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3123737374 |
| Directory | /workspace/28.uart_stress_all/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3745401727 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 73522524688 ps |
| CPU time | 1039.16 seconds |
| Started | Jul 12 04:39:25 PM PDT 24 |
| Finished | Jul 12 04:56:48 PM PDT 24 |
| Peak memory | 216380 kb |
| Host | smart-1c878867-693a-4a1d-a7f1-e6329565e55a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745401727 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3745401727 |
| Directory | /workspace/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.uart_tx_ovrd.579433804 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 1665146599 ps |
| CPU time | 2.74 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:39:38 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-eab505d9-4577-4ca0-b97f-f26ca6438741 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579433804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.579433804 |
| Directory | /workspace/28.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/28.uart_tx_rx.3469100444 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 10169836368 ps |
| CPU time | 8.94 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:39:44 PM PDT 24 |
| Peak memory | 197572 kb |
| Host | smart-f5b5a1fc-ce9d-4e25-a815-1b66b6daeb56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469100444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3469100444 |
| Directory | /workspace/28.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/280.uart_fifo_reset.3318137625 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 6492079669 ps |
| CPU time | 4.19 seconds |
| Started | Jul 12 04:41:40 PM PDT 24 |
| Finished | Jul 12 04:41:45 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-1d60b4d8-a44f-40e0-aebd-c0a3252dffbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3318137625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3318137625 |
| Directory | /workspace/280.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/281.uart_fifo_reset.1700704669 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 33989964532 ps |
| CPU time | 15.58 seconds |
| Started | Jul 12 04:41:42 PM PDT 24 |
| Finished | Jul 12 04:41:58 PM PDT 24 |
| Peak memory | 199544 kb |
| Host | smart-c0da49ce-75a6-4fda-8fb9-810bb40113c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700704669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1700704669 |
| Directory | /workspace/281.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/282.uart_fifo_reset.3385663261 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 179305409252 ps |
| CPU time | 170.08 seconds |
| Started | Jul 12 04:41:47 PM PDT 24 |
| Finished | Jul 12 04:44:38 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-668a2016-123a-46a4-aa7d-3db072083fb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3385663261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3385663261 |
| Directory | /workspace/282.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/283.uart_fifo_reset.4170896596 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 113419543914 ps |
| CPU time | 52.07 seconds |
| Started | Jul 12 04:41:49 PM PDT 24 |
| Finished | Jul 12 04:42:42 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-83060ad9-1c82-4938-a30b-3e4200efb4fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170896596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4170896596 |
| Directory | /workspace/283.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/284.uart_fifo_reset.1340859656 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 49313516912 ps |
| CPU time | 21.96 seconds |
| Started | Jul 12 04:41:50 PM PDT 24 |
| Finished | Jul 12 04:42:12 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-29f44413-e997-4b77-9745-d14211b48391 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340859656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1340859656 |
| Directory | /workspace/284.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/285.uart_fifo_reset.2845846717 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 36592647933 ps |
| CPU time | 10.95 seconds |
| Started | Jul 12 04:41:49 PM PDT 24 |
| Finished | Jul 12 04:42:00 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-f7a60be8-937f-46d1-8987-9ed822fa0f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2845846717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2845846717 |
| Directory | /workspace/285.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/286.uart_fifo_reset.1971866687 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 96958565456 ps |
| CPU time | 55.53 seconds |
| Started | Jul 12 04:41:49 PM PDT 24 |
| Finished | Jul 12 04:42:45 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-1362e51b-398f-45ef-bde4-c392a4109d46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971866687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1971866687 |
| Directory | /workspace/286.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/287.uart_fifo_reset.346257726 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 16454801499 ps |
| CPU time | 7.38 seconds |
| Started | Jul 12 04:41:46 PM PDT 24 |
| Finished | Jul 12 04:41:54 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-509cd745-cfc4-4201-b8cb-03a65552df9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346257726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.346257726 |
| Directory | /workspace/287.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/288.uart_fifo_reset.3139853823 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 21606665889 ps |
| CPU time | 14.29 seconds |
| Started | Jul 12 04:41:46 PM PDT 24 |
| Finished | Jul 12 04:42:01 PM PDT 24 |
| Peak memory | 199312 kb |
| Host | smart-bfbbe1b2-57f1-44cf-94c1-b56292661b0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139853823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3139853823 |
| Directory | /workspace/288.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/289.uart_fifo_reset.2161859411 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 135794582768 ps |
| CPU time | 81.82 seconds |
| Started | Jul 12 04:41:48 PM PDT 24 |
| Finished | Jul 12 04:43:11 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-e596657d-c104-4652-84f9-60ef3d41d963 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2161859411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2161859411 |
| Directory | /workspace/289.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_alert_test.3934395801 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 17766894 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:39:36 PM PDT 24 |
| Peak memory | 194484 kb |
| Host | smart-6ff84b2c-e981-4ee2-ab03-3418cbd49fe6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934395801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3934395801 |
| Directory | /workspace/29.uart_alert_test/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_overflow.3580722596 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 94608177682 ps |
| CPU time | 85.16 seconds |
| Started | Jul 12 04:39:32 PM PDT 24 |
| Finished | Jul 12 04:41:02 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-e0372c02-3126-4bf0-99a4-f0c3bbc8bda1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580722596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3580722596 |
| Directory | /workspace/29.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_reset.1866726700 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 13930605527 ps |
| CPU time | 25.86 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-68ac7748-d0ec-4830-8127-2ea5b56e6e61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866726700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1866726700 |
| Directory | /workspace/29.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_intr.3086184789 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 52362417795 ps |
| CPU time | 23.26 seconds |
| Started | Jul 12 04:39:38 PM PDT 24 |
| Finished | Jul 12 04:40:07 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-27e9bdc3-bc85-41b5-8a74-f3ce30eb53ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086184789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3086184789 |
| Directory | /workspace/29.uart_intr/latest |
| Test location | /workspace/coverage/default/29.uart_long_xfer_wo_dly.1267777238 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 164625463434 ps |
| CPU time | 433.78 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:47:00 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-3701785c-4d50-42cb-854a-69ac593ae0a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1267777238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1267777238 |
| Directory | /workspace/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/29.uart_loopback.1734083247 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 10365411511 ps |
| CPU time | 11.76 seconds |
| Started | Jul 12 04:39:38 PM PDT 24 |
| Finished | Jul 12 04:39:56 PM PDT 24 |
| Peak memory | 198436 kb |
| Host | smart-548aecb9-f403-4370-bf1a-406c274a506f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734083247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1734083247 |
| Directory | /workspace/29.uart_loopback/latest |
| Test location | /workspace/coverage/default/29.uart_noise_filter.2549877221 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 152581124709 ps |
| CPU time | 268.29 seconds |
| Started | Jul 12 04:39:27 PM PDT 24 |
| Finished | Jul 12 04:44:00 PM PDT 24 |
| Peak memory | 199340 kb |
| Host | smart-7b98baec-ceb2-445c-91ee-535ff651bd0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549877221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2549877221 |
| Directory | /workspace/29.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/29.uart_perf.1566764394 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 36791915108 ps |
| CPU time | 1654.52 seconds |
| Started | Jul 12 04:39:32 PM PDT 24 |
| Finished | Jul 12 05:07:12 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-2f5e0236-c98d-4f25-b2cf-3d027feba489 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1566764394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1566764394 |
| Directory | /workspace/29.uart_perf/latest |
| Test location | /workspace/coverage/default/29.uart_rx_oversample.3341546578 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6104730911 ps |
| CPU time | 46.03 seconds |
| Started | Jul 12 04:39:32 PM PDT 24 |
| Finished | Jul 12 04:40:24 PM PDT 24 |
| Peak memory | 198568 kb |
| Host | smart-c8caad5a-37a9-4dca-898d-372b00d34515 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3341546578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3341546578 |
| Directory | /workspace/29.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/29.uart_rx_parity_err.3132668322 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 160285148418 ps |
| CPU time | 250.47 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:43:55 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-bffc2f41-5714-449f-bef8-94516bdac16f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3132668322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3132668322 |
| Directory | /workspace/29.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/29.uart_rx_start_bit_filter.243473804 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 6159226095 ps |
| CPU time | 7.13 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 196076 kb |
| Host | smart-7cbc3401-e1ca-4c77-8806-4603919c6ce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243473804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.243473804 |
| Directory | /workspace/29.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/29.uart_smoke.1384866288 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 647597654 ps |
| CPU time | 1.86 seconds |
| Started | Jul 12 04:39:30 PM PDT 24 |
| Finished | Jul 12 04:39:37 PM PDT 24 |
| Peak memory | 198124 kb |
| Host | smart-65aa5d35-7375-41af-be40-73b07e5f3c1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384866288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1384866288 |
| Directory | /workspace/29.uart_smoke/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all.2972723702 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 100691993526 ps |
| CPU time | 339.82 seconds |
| Started | Jul 12 04:39:42 PM PDT 24 |
| Finished | Jul 12 04:45:28 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-24d09660-736f-499a-9406-112b4ec289da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972723702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2972723702 |
| Directory | /workspace/29.uart_stress_all/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all_with_rand_reset.905430782 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 39699274752 ps |
| CPU time | 811.47 seconds |
| Started | Jul 12 04:39:45 PM PDT 24 |
| Finished | Jul 12 04:53:22 PM PDT 24 |
| Peak memory | 216592 kb |
| Host | smart-7e77e4ac-89dc-45bf-be8e-70383df276b1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905430782 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.905430782 |
| Directory | /workspace/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.uart_tx_ovrd.649425300 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 7765613389 ps |
| CPU time | 10.5 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:39:44 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-3d89e0e1-cae4-41a1-8471-e2614e5ab964 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649425300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.649425300 |
| Directory | /workspace/29.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/29.uart_tx_rx.215558882 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3559517211 ps |
| CPU time | 5.72 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:39:46 PM PDT 24 |
| Peak memory | 197368 kb |
| Host | smart-bbd6a7e9-8a88-4aa4-b3c7-e0d47852c98a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215558882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.215558882 |
| Directory | /workspace/29.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/290.uart_fifo_reset.2040528668 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 153776481492 ps |
| CPU time | 248.29 seconds |
| Started | Jul 12 04:41:48 PM PDT 24 |
| Finished | Jul 12 04:45:57 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-0d35a260-15ac-4fde-b001-c425c2ea515e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040528668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2040528668 |
| Directory | /workspace/290.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/291.uart_fifo_reset.3670440748 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 29035277405 ps |
| CPU time | 10.14 seconds |
| Started | Jul 12 04:41:47 PM PDT 24 |
| Finished | Jul 12 04:41:59 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-dbe50f45-81ef-446c-a4f7-1eabecfd486d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670440748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3670440748 |
| Directory | /workspace/291.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/292.uart_fifo_reset.1637623224 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 65008320622 ps |
| CPU time | 74.48 seconds |
| Started | Jul 12 04:41:47 PM PDT 24 |
| Finished | Jul 12 04:43:03 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-33d0e531-3ce2-47a6-b95a-239bd48a75a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637623224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1637623224 |
| Directory | /workspace/292.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/293.uart_fifo_reset.374268996 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 78521930779 ps |
| CPU time | 28.61 seconds |
| Started | Jul 12 04:41:49 PM PDT 24 |
| Finished | Jul 12 04:42:18 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-daaed626-2ba6-4f21-956a-f6d62ec0e6a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=374268996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.374268996 |
| Directory | /workspace/293.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/294.uart_fifo_reset.2941030832 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 17344130511 ps |
| CPU time | 27.25 seconds |
| Started | Jul 12 04:41:47 PM PDT 24 |
| Finished | Jul 12 04:42:15 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-7eef1bf4-7a15-4932-8c9e-dd3ba7fd7775 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941030832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2941030832 |
| Directory | /workspace/294.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/295.uart_fifo_reset.1884739646 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 89450142196 ps |
| CPU time | 19.69 seconds |
| Started | Jul 12 04:41:49 PM PDT 24 |
| Finished | Jul 12 04:42:09 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-0b0725c8-63f1-465c-b1d8-f5e4c6cf35b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884739646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1884739646 |
| Directory | /workspace/295.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/296.uart_fifo_reset.3051435349 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 70987808380 ps |
| CPU time | 28.5 seconds |
| Started | Jul 12 04:41:48 PM PDT 24 |
| Finished | Jul 12 04:42:17 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-3c6b093e-d6fd-4d31-8a34-8f6332e60332 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051435349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3051435349 |
| Directory | /workspace/296.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/297.uart_fifo_reset.2277266988 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 116109830379 ps |
| CPU time | 165.1 seconds |
| Started | Jul 12 04:41:49 PM PDT 24 |
| Finished | Jul 12 04:44:34 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-23ecb77d-0f70-4faa-8cc2-0110a8c1895d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2277266988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2277266988 |
| Directory | /workspace/297.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/298.uart_fifo_reset.656263753 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 18042679305 ps |
| CPU time | 27.18 seconds |
| Started | Jul 12 04:41:47 PM PDT 24 |
| Finished | Jul 12 04:42:15 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-0831aa0f-be42-42ae-9898-ab33f6337c84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=656263753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.656263753 |
| Directory | /workspace/298.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/299.uart_fifo_reset.3546156617 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 71506793394 ps |
| CPU time | 16.41 seconds |
| Started | Jul 12 04:41:47 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199584 kb |
| Host | smart-5c30e97c-5716-40f7-9ce9-78bdf96f21c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546156617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3546156617 |
| Directory | /workspace/299.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_alert_test.1641686876 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 29971456 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:38:51 PM PDT 24 |
| Finished | Jul 12 04:38:57 PM PDT 24 |
| Peak memory | 195220 kb |
| Host | smart-b355d298-4ba8-444b-b990-f87efe5afb26 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641686876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1641686876 |
| Directory | /workspace/3.uart_alert_test/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_full.576955250 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 156377871106 ps |
| CPU time | 226.52 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:42:32 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-ca0e6ebc-37dd-475f-bd52-a78fc7ee2a40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576955250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.576955250 |
| Directory | /workspace/3.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_overflow.1685325959 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 16256482496 ps |
| CPU time | 23.22 seconds |
| Started | Jul 12 04:38:37 PM PDT 24 |
| Finished | Jul 12 04:39:06 PM PDT 24 |
| Peak memory | 199460 kb |
| Host | smart-0b231832-0960-441b-bfed-945264906ada |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685325959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1685325959 |
| Directory | /workspace/3.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_reset.2532283261 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 12043818811 ps |
| CPU time | 26.73 seconds |
| Started | Jul 12 04:38:38 PM PDT 24 |
| Finished | Jul 12 04:39:10 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-77580a6d-76fa-4573-a526-8d075097e9fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532283261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2532283261 |
| Directory | /workspace/3.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_long_xfer_wo_dly.2153704891 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 97279024086 ps |
| CPU time | 258.23 seconds |
| Started | Jul 12 04:38:44 PM PDT 24 |
| Finished | Jul 12 04:43:07 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-717dac9f-ca30-4d3e-8b1b-af7520658d81 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2153704891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2153704891 |
| Directory | /workspace/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/3.uart_loopback.777578960 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 1017999506 ps |
| CPU time | 2.55 seconds |
| Started | Jul 12 04:38:34 PM PDT 24 |
| Finished | Jul 12 04:38:43 PM PDT 24 |
| Peak memory | 198532 kb |
| Host | smart-e3cba579-4bc4-44f7-839a-20ed55b59688 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777578960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.777578960 |
| Directory | /workspace/3.uart_loopback/latest |
| Test location | /workspace/coverage/default/3.uart_noise_filter.4068942545 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 105775965335 ps |
| CPU time | 139.29 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:41:05 PM PDT 24 |
| Peak memory | 200020 kb |
| Host | smart-06f30792-c228-481a-8643-66756f255377 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068942545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4068942545 |
| Directory | /workspace/3.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/3.uart_perf.2748264418 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 21469019844 ps |
| CPU time | 138 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:41:22 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-3486ac31-21c8-4ec0-91f4-8985a3ba92ec |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2748264418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2748264418 |
| Directory | /workspace/3.uart_perf/latest |
| Test location | /workspace/coverage/default/3.uart_rx_oversample.765134429 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 6918549892 ps |
| CPU time | 17.35 seconds |
| Started | Jul 12 04:38:24 PM PDT 24 |
| Finished | Jul 12 04:38:50 PM PDT 24 |
| Peak memory | 199088 kb |
| Host | smart-169da7f2-f31f-4b97-8307-cbd5ef16faf2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=765134429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.765134429 |
| Directory | /workspace/3.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/3.uart_rx_parity_err.3052426774 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 70856252788 ps |
| CPU time | 187.82 seconds |
| Started | Jul 12 04:38:44 PM PDT 24 |
| Finished | Jul 12 04:41:57 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-d7789d26-b5de-42d9-adc8-533779721968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3052426774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3052426774 |
| Directory | /workspace/3.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/3.uart_rx_start_bit_filter.2444628752 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 4820582506 ps |
| CPU time | 1.74 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:39:06 PM PDT 24 |
| Peak memory | 195872 kb |
| Host | smart-e9dfa942-ee23-49f5-9341-7b72025acf28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444628752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2444628752 |
| Directory | /workspace/3.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/3.uart_sec_cm.1170910198 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 134868743 ps |
| CPU time | 0.79 seconds |
| Started | Jul 12 04:38:37 PM PDT 24 |
| Finished | Jul 12 04:38:44 PM PDT 24 |
| Peak memory | 218104 kb |
| Host | smart-89b8992d-70d2-4b80-9957-840b999a9a7d |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170910198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1170910198 |
| Directory | /workspace/3.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/3.uart_smoke.1057695309 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 627532190 ps |
| CPU time | 2.17 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:38:43 PM PDT 24 |
| Peak memory | 198384 kb |
| Host | smart-384ce6e8-00dd-489a-98a0-e3fd960404c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057695309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1057695309 |
| Directory | /workspace/3.uart_smoke/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all.190544384 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 50609298142 ps |
| CPU time | 148.44 seconds |
| Started | Jul 12 04:38:55 PM PDT 24 |
| Finished | Jul 12 04:41:28 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-ef41be0a-ea23-4c53-a563-f716de38b70c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190544384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.190544384 |
| Directory | /workspace/3.uart_stress_all/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1573983929 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 110801492687 ps |
| CPU time | 1011.11 seconds |
| Started | Jul 12 04:38:43 PM PDT 24 |
| Finished | Jul 12 04:55:39 PM PDT 24 |
| Peak memory | 230232 kb |
| Host | smart-658f4ba8-d070-4603-b49a-5f469eacafe2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573983929 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1573983929 |
| Directory | /workspace/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.uart_tx_ovrd.1781852333 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 10240865185 ps |
| CPU time | 6.89 seconds |
| Started | Jul 12 04:38:34 PM PDT 24 |
| Finished | Jul 12 04:38:47 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-633d9df6-3148-4e0f-b0d6-ebaf549f8023 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781852333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1781852333 |
| Directory | /workspace/3.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/3.uart_tx_rx.2473971773 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 58068631320 ps |
| CPU time | 25.2 seconds |
| Started | Jul 12 04:38:37 PM PDT 24 |
| Finished | Jul 12 04:39:08 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-611bff1e-7287-4db7-955f-cecdf1e3ec3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473971773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2473971773 |
| Directory | /workspace/3.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/30.uart_alert_test.1910048296 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 44961957 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:39:47 PM PDT 24 |
| Peak memory | 195416 kb |
| Host | smart-fd5fec1b-2f16-4bd3-a929-337e294f74ec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910048296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1910048296 |
| Directory | /workspace/30.uart_alert_test/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_full.1292815381 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 25069674536 ps |
| CPU time | 36.38 seconds |
| Started | Jul 12 04:39:49 PM PDT 24 |
| Finished | Jul 12 04:40:29 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-7f3543a1-4682-4f7c-bd90-e3adbf55bcc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292815381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1292815381 |
| Directory | /workspace/30.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_overflow.722196797 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 52430848501 ps |
| CPU time | 81.51 seconds |
| Started | Jul 12 04:39:44 PM PDT 24 |
| Finished | Jul 12 04:41:12 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-c1a46792-d605-4f91-9efc-2f494a5759de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722196797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.722196797 |
| Directory | /workspace/30.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_reset.2158720511 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 34029456034 ps |
| CPU time | 20.74 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:40:00 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-7d921c51-be96-420a-9517-4b1b3176a41b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158720511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2158720511 |
| Directory | /workspace/30.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/30.uart_intr.493620364 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 7589870836 ps |
| CPU time | 11.45 seconds |
| Started | Jul 12 04:39:38 PM PDT 24 |
| Finished | Jul 12 04:39:56 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-162843ed-7f86-4c01-9d91-d01f0937d3fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493620364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.493620364 |
| Directory | /workspace/30.uart_intr/latest |
| Test location | /workspace/coverage/default/30.uart_long_xfer_wo_dly.1607086207 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 106844032746 ps |
| CPU time | 282.83 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:44:23 PM PDT 24 |
| Peak memory | 200088 kb |
| Host | smart-80901f74-ddc1-44ff-947e-d9ab8db94e0a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1607086207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1607086207 |
| Directory | /workspace/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/30.uart_loopback.227148791 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 56733314 ps |
| CPU time | 0.67 seconds |
| Started | Jul 12 04:39:33 PM PDT 24 |
| Finished | Jul 12 04:39:39 PM PDT 24 |
| Peak memory | 195616 kb |
| Host | smart-6bffd415-e7f0-417f-b9c4-8315b6d0077e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=227148791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.227148791 |
| Directory | /workspace/30.uart_loopback/latest |
| Test location | /workspace/coverage/default/30.uart_noise_filter.1227284487 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 81151574168 ps |
| CPU time | 36.82 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:40:20 PM PDT 24 |
| Peak memory | 208292 kb |
| Host | smart-beeb4e32-7064-4610-81cb-ec8981aa94c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227284487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1227284487 |
| Directory | /workspace/30.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/30.uart_perf.3446764384 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10522695967 ps |
| CPU time | 628.11 seconds |
| Started | Jul 12 04:39:52 PM PDT 24 |
| Finished | Jul 12 04:50:24 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-5400091c-73aa-47fd-a4f7-15c849d568dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3446764384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3446764384 |
| Directory | /workspace/30.uart_perf/latest |
| Test location | /workspace/coverage/default/30.uart_rx_oversample.1648951278 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3707893748 ps |
| CPU time | 28.33 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:40:14 PM PDT 24 |
| Peak memory | 198132 kb |
| Host | smart-460fb866-d23b-44a9-90db-69654b8b4ce0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1648951278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1648951278 |
| Directory | /workspace/30.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/30.uart_rx_parity_err.1056511731 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 31797493379 ps |
| CPU time | 17.43 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 199576 kb |
| Host | smart-a0578f0b-50a2-4cf7-befe-a65ef81e33a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056511731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1056511731 |
| Directory | /workspace/30.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/30.uart_rx_start_bit_filter.1156425203 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 545515839 ps |
| CPU time | 1.67 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 195316 kb |
| Host | smart-578c2a69-7cc6-4a42-a495-459afcb2e002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156425203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1156425203 |
| Directory | /workspace/30.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/30.uart_smoke.786135072 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 459760566 ps |
| CPU time | 2 seconds |
| Started | Jul 12 04:39:28 PM PDT 24 |
| Finished | Jul 12 04:39:35 PM PDT 24 |
| Peak memory | 198556 kb |
| Host | smart-ac14e4b2-f243-443c-bdb8-dd4e9065702d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786135072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.786135072 |
| Directory | /workspace/30.uart_smoke/latest |
| Test location | /workspace/coverage/default/30.uart_tx_ovrd.2632194340 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 624003964 ps |
| CPU time | 2.89 seconds |
| Started | Jul 12 04:39:41 PM PDT 24 |
| Finished | Jul 12 04:39:50 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-48610901-563d-4e80-91c0-ad5332d949b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632194340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2632194340 |
| Directory | /workspace/30.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/30.uart_tx_rx.1082298116 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 96205329254 ps |
| CPU time | 31.92 seconds |
| Started | Jul 12 04:39:43 PM PDT 24 |
| Finished | Jul 12 04:40:21 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-70cbf0d6-df5a-414a-9646-91599f44e213 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082298116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1082298116 |
| Directory | /workspace/30.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/31.uart_alert_test.2216522412 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 25915199 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:49 PM PDT 24 |
| Finished | Jul 12 04:39:54 PM PDT 24 |
| Peak memory | 195088 kb |
| Host | smart-95a06710-fc66-4ea8-b4c4-2c4f67408bd6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216522412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2216522412 |
| Directory | /workspace/31.uart_alert_test/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_full.34381932 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 74978105251 ps |
| CPU time | 35.92 seconds |
| Started | Jul 12 04:39:38 PM PDT 24 |
| Finished | Jul 12 04:40:20 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-6c4beafb-a52d-40a3-9d1e-5c94c5d773c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34381932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.34381932 |
| Directory | /workspace/31.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_overflow.1270614890 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 154402728772 ps |
| CPU time | 20.16 seconds |
| Started | Jul 12 04:39:32 PM PDT 24 |
| Finished | Jul 12 04:39:57 PM PDT 24 |
| Peak memory | 199572 kb |
| Host | smart-d5f6837c-eb4a-4b07-8800-090da03aebb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1270614890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1270614890 |
| Directory | /workspace/31.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_reset.1958086026 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 17894043866 ps |
| CPU time | 8.75 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:50 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-0d0c93ba-0594-4cc5-9940-86b50fe338f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1958086026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1958086026 |
| Directory | /workspace/31.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/31.uart_intr.93739940 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 39490394848 ps |
| CPU time | 15.67 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:40:02 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-f2da2c73-0031-48d7-8e7f-88f4753d27b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93739940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.93739940 |
| Directory | /workspace/31.uart_intr/latest |
| Test location | /workspace/coverage/default/31.uart_long_xfer_wo_dly.2938201039 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 91801600626 ps |
| CPU time | 255.89 seconds |
| Started | Jul 12 04:39:45 PM PDT 24 |
| Finished | Jul 12 04:44:06 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-11c845fd-aef7-464a-97e3-191b99b788d8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2938201039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2938201039 |
| Directory | /workspace/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/31.uart_loopback.3619133274 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2757179179 ps |
| CPU time | 2.13 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:39:42 PM PDT 24 |
| Peak memory | 198752 kb |
| Host | smart-b3929fa5-5b02-4cec-bdbc-a4e8a41d8d1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619133274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3619133274 |
| Directory | /workspace/31.uart_loopback/latest |
| Test location | /workspace/coverage/default/31.uart_noise_filter.3866764529 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 255780019009 ps |
| CPU time | 107.91 seconds |
| Started | Jul 12 04:39:44 PM PDT 24 |
| Finished | Jul 12 04:41:38 PM PDT 24 |
| Peak memory | 200084 kb |
| Host | smart-4738a791-2f0d-4fd6-9fb9-0d4c55098cfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866764529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3866764529 |
| Directory | /workspace/31.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/31.uart_perf.633722352 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 26027487439 ps |
| CPU time | 351.73 seconds |
| Started | Jul 12 04:39:47 PM PDT 24 |
| Finished | Jul 12 04:45:44 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-c289ea54-8e7a-4213-8e48-c3eb957c7138 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=633722352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.633722352 |
| Directory | /workspace/31.uart_perf/latest |
| Test location | /workspace/coverage/default/31.uart_rx_oversample.1863325760 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3466263698 ps |
| CPU time | 7.05 seconds |
| Started | Jul 12 04:39:34 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 198944 kb |
| Host | smart-94fb4160-0a62-4893-91b5-f9421ce00480 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1863325760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1863325760 |
| Directory | /workspace/31.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/31.uart_rx_parity_err.1699028599 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 93016554936 ps |
| CPU time | 124.86 seconds |
| Started | Jul 12 04:39:46 PM PDT 24 |
| Finished | Jul 12 04:41:56 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-1f05fc39-e194-409c-877f-8d0071f7cc23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1699028599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1699028599 |
| Directory | /workspace/31.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/31.uart_rx_start_bit_filter.3713450841 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 590657327 ps |
| CPU time | 0.85 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:39:47 PM PDT 24 |
| Peak memory | 195208 kb |
| Host | smart-065dc1ba-8d73-4c38-9b95-501f8363af29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713450841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3713450841 |
| Directory | /workspace/31.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/31.uart_smoke.2938021790 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 931625475 ps |
| CPU time | 3.87 seconds |
| Started | Jul 12 04:39:43 PM PDT 24 |
| Finished | Jul 12 04:39:53 PM PDT 24 |
| Peak memory | 199612 kb |
| Host | smart-144634eb-ae71-42f7-8dfd-c72d01db3b38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2938021790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2938021790 |
| Directory | /workspace/31.uart_smoke/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all.2171318681 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 80369311798 ps |
| CPU time | 39.64 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:40:34 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-15c5737c-ca0a-4c84-8130-f6c6f5f8e450 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171318681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2171318681 |
| Directory | /workspace/31.uart_stress_all/latest |
| Test location | /workspace/coverage/default/31.uart_tx_ovrd.842227332 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1106794084 ps |
| CPU time | 1.6 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:43 PM PDT 24 |
| Peak memory | 199000 kb |
| Host | smart-bad04f51-3726-4d2c-832a-841ba9a4f031 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842227332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.842227332 |
| Directory | /workspace/31.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/31.uart_tx_rx.843237096 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 27769043386 ps |
| CPU time | 42.88 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:40:37 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-3c0dd950-81a1-4d9d-9367-489008c1fcfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843237096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.843237096 |
| Directory | /workspace/31.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/32.uart_alert_test.2588117 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 29521795 ps |
| CPU time | 0.54 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:40:03 PM PDT 24 |
| Peak memory | 195524 kb |
| Host | smart-430d0227-0389-437e-b611-5a1156a1ab37 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2588117 |
| Directory | /workspace/32.uart_alert_test/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_full.3791969939 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 145130292284 ps |
| CPU time | 475.93 seconds |
| Started | Jul 12 04:39:54 PM PDT 24 |
| Finished | Jul 12 04:47:53 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-13d45d77-b14d-4bd4-b04a-9a1dc62d5c89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791969939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3791969939 |
| Directory | /workspace/32.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_overflow.309684005 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 39427422809 ps |
| CPU time | 13.84 seconds |
| Started | Jul 12 04:39:33 PM PDT 24 |
| Finished | Jul 12 04:39:53 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-0da23473-49f1-4a4c-853b-66b68b51c8ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309684005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.309684005 |
| Directory | /workspace/32.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_reset.1280649244 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 82120398703 ps |
| CPU time | 68.39 seconds |
| Started | Jul 12 04:39:37 PM PDT 24 |
| Finished | Jul 12 04:40:52 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-f32c3793-8897-482f-b2fd-ec23bc916e14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280649244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1280649244 |
| Directory | /workspace/32.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/32.uart_intr.1348968034 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 10597449203 ps |
| CPU time | 8.55 seconds |
| Started | Jul 12 04:39:47 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-bd8f28be-94d7-43dd-88c7-72f13daa6bc5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348968034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1348968034 |
| Directory | /workspace/32.uart_intr/latest |
| Test location | /workspace/coverage/default/32.uart_long_xfer_wo_dly.585142823 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 67365821702 ps |
| CPU time | 400 seconds |
| Started | Jul 12 04:39:39 PM PDT 24 |
| Finished | Jul 12 04:46:26 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-ae4c575c-bc85-419f-99d5-80a9938c149e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=585142823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.585142823 |
| Directory | /workspace/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/32.uart_loopback.2158285929 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 6244909628 ps |
| CPU time | 4.35 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:39:59 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-bf949561-8560-4578-b269-439b38a4f9b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158285929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2158285929 |
| Directory | /workspace/32.uart_loopback/latest |
| Test location | /workspace/coverage/default/32.uart_noise_filter.1449661660 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 86594609991 ps |
| CPU time | 31.08 seconds |
| Started | Jul 12 04:39:33 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 200112 kb |
| Host | smart-6c26c181-f0a2-48c2-ac9c-c33467a6b038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449661660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1449661660 |
| Directory | /workspace/32.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/32.uart_perf.331492032 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 20906748053 ps |
| CPU time | 48 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:40:43 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-41a7fbf4-fda3-48dd-8ace-37b32f46dc29 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=331492032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.331492032 |
| Directory | /workspace/32.uart_perf/latest |
| Test location | /workspace/coverage/default/32.uart_rx_oversample.4165056825 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1483970386 ps |
| CPU time | 3.25 seconds |
| Started | Jul 12 04:39:45 PM PDT 24 |
| Finished | Jul 12 04:39:54 PM PDT 24 |
| Peak memory | 197908 kb |
| Host | smart-04aad215-b015-48b3-baf1-55d25fd0320d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4165056825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4165056825 |
| Directory | /workspace/32.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/32.uart_rx_parity_err.3496474669 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 42191832069 ps |
| CPU time | 17.89 seconds |
| Started | Jul 12 04:39:47 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 198104 kb |
| Host | smart-de3fb930-ccc1-4e38-a8cd-b1ef3970ae69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496474669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3496474669 |
| Directory | /workspace/32.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/32.uart_rx_start_bit_filter.2527471027 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 4542328515 ps |
| CPU time | 3.76 seconds |
| Started | Jul 12 04:39:51 PM PDT 24 |
| Finished | Jul 12 04:39:59 PM PDT 24 |
| Peak memory | 195928 kb |
| Host | smart-3b1c9e66-0ca2-4d92-bbe4-3025a7069137 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527471027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2527471027 |
| Directory | /workspace/32.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/32.uart_smoke.4271586444 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 6290567143 ps |
| CPU time | 8.43 seconds |
| Started | Jul 12 04:39:45 PM PDT 24 |
| Finished | Jul 12 04:39:59 PM PDT 24 |
| Peak memory | 199152 kb |
| Host | smart-13c0f7cb-8bc1-4ac6-a747-6a12da4d2e17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271586444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.4271586444 |
| Directory | /workspace/32.uart_smoke/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all.558782367 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 322674315624 ps |
| CPU time | 859.35 seconds |
| Started | Jul 12 04:39:45 PM PDT 24 |
| Finished | Jul 12 04:54:10 PM PDT 24 |
| Peak memory | 199064 kb |
| Host | smart-e43f6402-cbf1-432c-8a0c-df4d6d6cc5d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558782367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.558782367 |
| Directory | /workspace/32.uart_stress_all/latest |
| Test location | /workspace/coverage/default/32.uart_tx_ovrd.3072676487 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 6034316125 ps |
| CPU time | 16.81 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-5f0ded76-3e8c-4bfa-855e-a296015a7c73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072676487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3072676487 |
| Directory | /workspace/32.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/32.uart_tx_rx.3067256488 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 50548055608 ps |
| CPU time | 34.3 seconds |
| Started | Jul 12 04:40:01 PM PDT 24 |
| Finished | Jul 12 04:40:39 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-73d0e2a5-e410-40d6-a016-b435b703b390 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067256488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3067256488 |
| Directory | /workspace/32.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/33.uart_alert_test.1971036020 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 35350865 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:39:48 PM PDT 24 |
| Finished | Jul 12 04:39:54 PM PDT 24 |
| Peak memory | 195228 kb |
| Host | smart-efc5f7e9-2a94-4db8-af69-d1022d8490a8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971036020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1971036020 |
| Directory | /workspace/33.uart_alert_test/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_full.768452350 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 22176712069 ps |
| CPU time | 47.68 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:40:29 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-20ae874c-97fd-4047-a6f8-1caaccfeb94e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768452350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.768452350 |
| Directory | /workspace/33.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_overflow.3996820366 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 24051570065 ps |
| CPU time | 86.08 seconds |
| Started | Jul 12 04:39:49 PM PDT 24 |
| Finished | Jul 12 04:41:19 PM PDT 24 |
| Peak memory | 199668 kb |
| Host | smart-3ac80ddf-3bae-4eb5-b145-41623db62b61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996820366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3996820366 |
| Directory | /workspace/33.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_reset.1733157107 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 24452890529 ps |
| CPU time | 12.73 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:40:13 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-b6eacf4e-ce3e-45d3-a969-ef437f5c19af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733157107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1733157107 |
| Directory | /workspace/33.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/33.uart_intr.3923428555 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 19928218048 ps |
| CPU time | 4.31 seconds |
| Started | Jul 12 04:39:55 PM PDT 24 |
| Finished | Jul 12 04:40:02 PM PDT 24 |
| Peak memory | 199424 kb |
| Host | smart-5ad50702-befb-4dcd-808e-406ca3b8821e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923428555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3923428555 |
| Directory | /workspace/33.uart_intr/latest |
| Test location | /workspace/coverage/default/33.uart_long_xfer_wo_dly.513409840 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 72948395469 ps |
| CPU time | 102.67 seconds |
| Started | Jul 12 04:39:51 PM PDT 24 |
| Finished | Jul 12 04:41:38 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-9115bcc3-e97b-428d-a910-e73d7b947fbd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=513409840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.513409840 |
| Directory | /workspace/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/33.uart_loopback.3120503509 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4144595264 ps |
| CPU time | 7.07 seconds |
| Started | Jul 12 04:39:48 PM PDT 24 |
| Finished | Jul 12 04:40:00 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-970b5956-efaf-45fc-869e-e93f617f0585 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120503509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3120503509 |
| Directory | /workspace/33.uart_loopback/latest |
| Test location | /workspace/coverage/default/33.uart_noise_filter.1383357072 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 6845862869 ps |
| CPU time | 11.95 seconds |
| Started | Jul 12 04:39:49 PM PDT 24 |
| Finished | Jul 12 04:40:05 PM PDT 24 |
| Peak memory | 197336 kb |
| Host | smart-0bd3dd2e-2a15-49aa-a66d-2366385d0312 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1383357072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1383357072 |
| Directory | /workspace/33.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/33.uart_perf.383567474 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 10392087617 ps |
| CPU time | 93.6 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:41:28 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-6ec03194-e13f-45c8-b5f5-8f11515c8e2c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=383567474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.383567474 |
| Directory | /workspace/33.uart_perf/latest |
| Test location | /workspace/coverage/default/33.uart_rx_oversample.1341266730 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 3336825657 ps |
| CPU time | 10.24 seconds |
| Started | Jul 12 04:39:49 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 198780 kb |
| Host | smart-09dfa9d0-7eee-44ac-94cf-363a5f7cfd57 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1341266730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1341266730 |
| Directory | /workspace/33.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/33.uart_rx_parity_err.2558113602 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 9266375552 ps |
| CPU time | 14.31 seconds |
| Started | Jul 12 04:39:43 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-681e742e-81f1-426c-9ac8-692bdb9fa174 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558113602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2558113602 |
| Directory | /workspace/33.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/33.uart_rx_start_bit_filter.1881635778 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 1493444004 ps |
| CPU time | 1.42 seconds |
| Started | Jul 12 04:39:55 PM PDT 24 |
| Finished | Jul 12 04:39:59 PM PDT 24 |
| Peak memory | 195216 kb |
| Host | smart-9144acb4-7b73-4479-8ea9-03af23c1d812 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881635778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1881635778 |
| Directory | /workspace/33.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/33.uart_smoke.1368365898 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5662628147 ps |
| CPU time | 8.6 seconds |
| Started | Jul 12 04:39:45 PM PDT 24 |
| Finished | Jul 12 04:39:59 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-f5167c90-5781-42d8-94d7-1bf3f972c963 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1368365898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1368365898 |
| Directory | /workspace/33.uart_smoke/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all.2019821706 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 473755145596 ps |
| CPU time | 437.94 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:47:12 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-dc103cd1-e99f-4019-b6a7-9d7e909948c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019821706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2019821706 |
| Directory | /workspace/33.uart_stress_all/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3743712640 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 129222797780 ps |
| CPU time | 362.91 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:45:49 PM PDT 24 |
| Peak memory | 209940 kb |
| Host | smart-de8d965d-0c83-49c6-a01c-e0769d388692 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743712640 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3743712640 |
| Directory | /workspace/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.uart_tx_ovrd.785313554 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2158068106 ps |
| CPU time | 1.49 seconds |
| Started | Jul 12 04:39:40 PM PDT 24 |
| Finished | Jul 12 04:39:48 PM PDT 24 |
| Peak memory | 198328 kb |
| Host | smart-b8215e58-7af9-4cbe-9bb9-1d1e5ee6147f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785313554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.785313554 |
| Directory | /workspace/33.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/33.uart_tx_rx.915669307 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 34598643607 ps |
| CPU time | 13.54 seconds |
| Started | Jul 12 04:39:35 PM PDT 24 |
| Finished | Jul 12 04:39:55 PM PDT 24 |
| Peak memory | 199648 kb |
| Host | smart-21ce3aa3-ccf7-479c-affd-b6e52d2ea3df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915669307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.915669307 |
| Directory | /workspace/33.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/34.uart_alert_test.3212053777 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 20221218 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:40:03 PM PDT 24 |
| Peak memory | 195212 kb |
| Host | smart-c9007b8e-950f-47f5-bdfe-8205f5da9cc2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212053777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3212053777 |
| Directory | /workspace/34.uart_alert_test/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_full.1770401882 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 161154437112 ps |
| CPU time | 236.4 seconds |
| Started | Jul 12 04:39:47 PM PDT 24 |
| Finished | Jul 12 04:43:49 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-3605f1f1-f0ed-426c-a1a1-9262e27d694b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770401882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1770401882 |
| Directory | /workspace/34.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_overflow.1974237761 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 14434568599 ps |
| CPU time | 13.72 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:40:08 PM PDT 24 |
| Peak memory | 199676 kb |
| Host | smart-47e2785c-bdf7-41fa-ae35-820a898c7537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974237761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1974237761 |
| Directory | /workspace/34.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_reset.1866299760 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 64518201976 ps |
| CPU time | 27.47 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:40:29 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-9c011416-225f-4931-893a-1223f495466b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866299760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1866299760 |
| Directory | /workspace/34.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/34.uart_intr.326009053 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 55910423728 ps |
| CPU time | 24.06 seconds |
| Started | Jul 12 04:39:53 PM PDT 24 |
| Finished | Jul 12 04:40:20 PM PDT 24 |
| Peak memory | 199652 kb |
| Host | smart-06a15a5a-b703-4fbd-b686-4783010824b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326009053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.326009053 |
| Directory | /workspace/34.uart_intr/latest |
| Test location | /workspace/coverage/default/34.uart_long_xfer_wo_dly.2772457359 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 238026761209 ps |
| CPU time | 284.68 seconds |
| Started | Jul 12 04:39:52 PM PDT 24 |
| Finished | Jul 12 04:44:41 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-de63fbbe-cc01-490e-a514-9c020d052f30 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2772457359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2772457359 |
| Directory | /workspace/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/34.uart_loopback.1343679840 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 5383209187 ps |
| CPU time | 11.57 seconds |
| Started | Jul 12 04:39:52 PM PDT 24 |
| Finished | Jul 12 04:40:07 PM PDT 24 |
| Peak memory | 198740 kb |
| Host | smart-a2a8a61a-6c9a-45c4-bf47-eb0fffff4a52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343679840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1343679840 |
| Directory | /workspace/34.uart_loopback/latest |
| Test location | /workspace/coverage/default/34.uart_noise_filter.3540478913 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 60943515150 ps |
| CPU time | 26.57 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:40:29 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-f6cfb260-8388-4f35-b793-d8ee21c3d614 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540478913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3540478913 |
| Directory | /workspace/34.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/34.uart_perf.2000585741 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 9100798217 ps |
| CPU time | 95.11 seconds |
| Started | Jul 12 04:40:00 PM PDT 24 |
| Finished | Jul 12 04:41:40 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-12e273d9-e966-4b3e-ba9a-8b8b99ab6b6c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2000585741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2000585741 |
| Directory | /workspace/34.uart_perf/latest |
| Test location | /workspace/coverage/default/34.uart_rx_oversample.1089439174 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1999535119 ps |
| CPU time | 11.65 seconds |
| Started | Jul 12 04:39:56 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 197896 kb |
| Host | smart-10b2e108-7c01-4e53-abd1-5c4df6cda83e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1089439174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1089439174 |
| Directory | /workspace/34.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/34.uart_rx_parity_err.1835179710 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 120273236951 ps |
| CPU time | 246.28 seconds |
| Started | Jul 12 04:39:49 PM PDT 24 |
| Finished | Jul 12 04:43:59 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-c00b699c-f152-433a-add7-e73931242366 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835179710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1835179710 |
| Directory | /workspace/34.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/34.uart_rx_start_bit_filter.2250730439 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 622580830 ps |
| CPU time | 1.45 seconds |
| Started | Jul 12 04:39:48 PM PDT 24 |
| Finished | Jul 12 04:39:54 PM PDT 24 |
| Peak memory | 195380 kb |
| Host | smart-50dbc364-2254-41f7-8d0f-05d4c05b5abd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2250730439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2250730439 |
| Directory | /workspace/34.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/34.uart_smoke.2334739834 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 802683002 ps |
| CPU time | 3.39 seconds |
| Started | Jul 12 04:39:45 PM PDT 24 |
| Finished | Jul 12 04:39:54 PM PDT 24 |
| Peak memory | 198292 kb |
| Host | smart-df25e760-efdd-4612-b82d-fd9d2e1044a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334739834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2334739834 |
| Directory | /workspace/34.uart_smoke/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all.4025351033 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 217307307052 ps |
| CPU time | 495.44 seconds |
| Started | Jul 12 04:39:51 PM PDT 24 |
| Finished | Jul 12 04:48:11 PM PDT 24 |
| Peak memory | 208256 kb |
| Host | smart-37592f8f-d3ba-4fca-8859-089819c0ae22 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025351033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4025351033 |
| Directory | /workspace/34.uart_stress_all/latest |
| Test location | /workspace/coverage/default/34.uart_tx_ovrd.1683277004 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1055647554 ps |
| CPU time | 3.53 seconds |
| Started | Jul 12 04:39:41 PM PDT 24 |
| Finished | Jul 12 04:39:50 PM PDT 24 |
| Peak memory | 198900 kb |
| Host | smart-839f9934-9a1b-4e31-a90c-e3a7d970d751 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683277004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1683277004 |
| Directory | /workspace/34.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/34.uart_tx_rx.1110942166 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 146307835672 ps |
| CPU time | 109.02 seconds |
| Started | Jul 12 04:39:45 PM PDT 24 |
| Finished | Jul 12 04:41:40 PM PDT 24 |
| Peak memory | 199068 kb |
| Host | smart-2fcb0213-2ed0-4c84-b643-f05852b2eda2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110942166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1110942166 |
| Directory | /workspace/34.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/35.uart_alert_test.1924663116 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 20719173 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:39:52 PM PDT 24 |
| Finished | Jul 12 04:39:57 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-95dbd927-6ff4-430d-8edb-f9912e27f9e0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924663116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1924663116 |
| Directory | /workspace/35.uart_alert_test/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_full.2248290304 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 135709103817 ps |
| CPU time | 227.49 seconds |
| Started | Jul 12 04:40:00 PM PDT 24 |
| Finished | Jul 12 04:43:52 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-60cd197d-28fd-42a8-9ad5-3b70bd00c925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248290304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2248290304 |
| Directory | /workspace/35.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_reset.1019624962 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 71116342846 ps |
| CPU time | 99.31 seconds |
| Started | Jul 12 04:39:52 PM PDT 24 |
| Finished | Jul 12 04:41:35 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-a94b4de7-0aa2-4b6d-8b13-4ed28d979a80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019624962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1019624962 |
| Directory | /workspace/35.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/35.uart_intr.2538029591 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4365144581 ps |
| CPU time | 6.94 seconds |
| Started | Jul 12 04:39:53 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 196896 kb |
| Host | smart-a2329945-bcf4-457e-9740-a0fe28cdf170 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538029591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2538029591 |
| Directory | /workspace/35.uart_intr/latest |
| Test location | /workspace/coverage/default/35.uart_long_xfer_wo_dly.722300325 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 36483107389 ps |
| CPU time | 105.81 seconds |
| Started | Jul 12 04:40:01 PM PDT 24 |
| Finished | Jul 12 04:41:51 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-8c103399-3203-40e1-8d58-9d031f457c44 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=722300325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.722300325 |
| Directory | /workspace/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/35.uart_loopback.3611211673 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2789785271 ps |
| CPU time | 1.81 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:40:02 PM PDT 24 |
| Peak memory | 196116 kb |
| Host | smart-54b031d0-9151-45c3-80fb-94ec11bb0361 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611211673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3611211673 |
| Directory | /workspace/35.uart_loopback/latest |
| Test location | /workspace/coverage/default/35.uart_noise_filter.3028522038 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 162938979630 ps |
| CPU time | 113.33 seconds |
| Started | Jul 12 04:39:53 PM PDT 24 |
| Finished | Jul 12 04:41:50 PM PDT 24 |
| Peak memory | 200084 kb |
| Host | smart-647baf66-3de1-4e17-960d-71f8d96d036b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028522038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3028522038 |
| Directory | /workspace/35.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/35.uart_perf.149776269 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 17155369521 ps |
| CPU time | 634.28 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:50:28 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-0ef4933c-8dae-40dd-adb5-f5de042b5ff0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=149776269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.149776269 |
| Directory | /workspace/35.uart_perf/latest |
| Test location | /workspace/coverage/default/35.uart_rx_oversample.2821008649 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 5914969916 ps |
| CPU time | 53.36 seconds |
| Started | Jul 12 04:39:49 PM PDT 24 |
| Finished | Jul 12 04:40:47 PM PDT 24 |
| Peak memory | 198712 kb |
| Host | smart-3ae3721f-cfb6-4468-a08e-393e01da8583 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2821008649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2821008649 |
| Directory | /workspace/35.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/35.uart_rx_parity_err.817889052 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 91861326272 ps |
| CPU time | 119 seconds |
| Started | Jul 12 04:40:01 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199388 kb |
| Host | smart-6474d584-2639-4434-bfee-0061619baaea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817889052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.817889052 |
| Directory | /workspace/35.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/35.uart_rx_start_bit_filter.1787807284 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 4385701259 ps |
| CPU time | 4.1 seconds |
| Started | Jul 12 04:40:01 PM PDT 24 |
| Finished | Jul 12 04:40:09 PM PDT 24 |
| Peak memory | 196052 kb |
| Host | smart-046bb1b6-e34c-44a1-ac8d-9ed62f151b74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787807284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1787807284 |
| Directory | /workspace/35.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/35.uart_smoke.642660126 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 679338979 ps |
| CPU time | 2.36 seconds |
| Started | Jul 12 04:39:47 PM PDT 24 |
| Finished | Jul 12 04:39:54 PM PDT 24 |
| Peak memory | 198628 kb |
| Host | smart-be31c4df-8bcf-4131-ae58-2218cf222f5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642660126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.642660126 |
| Directory | /workspace/35.uart_smoke/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all.1025117552 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 13332635127 ps |
| CPU time | 9.49 seconds |
| Started | Jul 12 04:39:50 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-85721e16-63bb-4311-96df-ae36e56be076 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025117552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1025117552 |
| Directory | /workspace/35.uart_stress_all/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2636486614 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 28616146319 ps |
| CPU time | 264.54 seconds |
| Started | Jul 12 04:39:55 PM PDT 24 |
| Finished | Jul 12 04:44:23 PM PDT 24 |
| Peak memory | 215956 kb |
| Host | smart-ab390db0-e6f5-42fe-8447-3d3b16aabe0f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636486614 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2636486614 |
| Directory | /workspace/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.uart_tx_ovrd.1640523987 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 995888656 ps |
| CPU time | 3.37 seconds |
| Started | Jul 12 04:39:54 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 199468 kb |
| Host | smart-471dc479-7da7-4100-91ce-0a1ef0d92326 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640523987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1640523987 |
| Directory | /workspace/35.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/35.uart_tx_rx.3755923178 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 61322241335 ps |
| CPU time | 5.83 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 199520 kb |
| Host | smart-9f160969-be41-47e3-83f1-fe9b2095660d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755923178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3755923178 |
| Directory | /workspace/35.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/36.uart_alert_test.4163231405 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 42154303 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 195392 kb |
| Host | smart-a1ca942d-ca26-485f-97f2-2f00f85d8c98 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163231405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.4163231405 |
| Directory | /workspace/36.uart_alert_test/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_full.1154355561 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 67397697591 ps |
| CPU time | 23.25 seconds |
| Started | Jul 12 04:39:53 PM PDT 24 |
| Finished | Jul 12 04:40:20 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-65a00111-dcba-4477-9452-ac3ca79c0358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154355561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1154355561 |
| Directory | /workspace/36.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_overflow.1629205703 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 39109744804 ps |
| CPU time | 32.73 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:40:34 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-aba6db88-e91b-427d-893b-67ec17373088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629205703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1629205703 |
| Directory | /workspace/36.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_reset.1778434976 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 129778194218 ps |
| CPU time | 151.01 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:42:32 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-fe3b46d9-0815-49b2-bbbd-13074bc6da95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778434976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1778434976 |
| Directory | /workspace/36.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/36.uart_intr.3968419844 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 193446884267 ps |
| CPU time | 432.99 seconds |
| Started | Jul 12 04:39:54 PM PDT 24 |
| Finished | Jul 12 04:47:10 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-d5b88f68-fa00-4be5-9c3e-033b1cf6e0fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968419844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3968419844 |
| Directory | /workspace/36.uart_intr/latest |
| Test location | /workspace/coverage/default/36.uart_loopback.3718464750 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 11597654112 ps |
| CPU time | 6.95 seconds |
| Started | Jul 12 04:39:54 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-5a000b6e-487e-4477-b8e0-f822245b9687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718464750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3718464750 |
| Directory | /workspace/36.uart_loopback/latest |
| Test location | /workspace/coverage/default/36.uart_noise_filter.2354027763 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 60925936235 ps |
| CPU time | 23.56 seconds |
| Started | Jul 12 04:40:01 PM PDT 24 |
| Finished | Jul 12 04:40:29 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-afcdfe82-25a0-4969-a413-dca312b16959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354027763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2354027763 |
| Directory | /workspace/36.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/36.uart_perf.389594676 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 23052885715 ps |
| CPU time | 654.76 seconds |
| Started | Jul 12 04:39:54 PM PDT 24 |
| Finished | Jul 12 04:50:52 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-a13980b4-c7d7-4ee4-8d54-6101a50ba219 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=389594676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.389594676 |
| Directory | /workspace/36.uart_perf/latest |
| Test location | /workspace/coverage/default/36.uart_rx_oversample.1421873881 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 3702494304 ps |
| CPU time | 15.07 seconds |
| Started | Jul 12 04:39:55 PM PDT 24 |
| Finished | Jul 12 04:40:13 PM PDT 24 |
| Peak memory | 197980 kb |
| Host | smart-87b9ba18-64d7-4905-a91e-4bece05039d4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1421873881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1421873881 |
| Directory | /workspace/36.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/36.uart_rx_parity_err.3523642342 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 30500033169 ps |
| CPU time | 15.31 seconds |
| Started | Jul 12 04:39:55 PM PDT 24 |
| Finished | Jul 12 04:40:13 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-97dcabae-a033-4ac4-b542-47a450d5d60b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523642342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3523642342 |
| Directory | /workspace/36.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/36.uart_rx_start_bit_filter.3774342662 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3327760700 ps |
| CPU time | 1.85 seconds |
| Started | Jul 12 04:39:56 PM PDT 24 |
| Finished | Jul 12 04:40:01 PM PDT 24 |
| Peak memory | 196108 kb |
| Host | smart-246a1b85-d7fa-4a0c-a2cc-ac162536950c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774342662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3774342662 |
| Directory | /workspace/36.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/36.uart_smoke.4229364434 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 441230187 ps |
| CPU time | 1.4 seconds |
| Started | Jul 12 04:39:53 PM PDT 24 |
| Finished | Jul 12 04:39:58 PM PDT 24 |
| Peak memory | 198180 kb |
| Host | smart-4165b33c-88f3-463b-b499-b8bbbd1f7191 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229364434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4229364434 |
| Directory | /workspace/36.uart_smoke/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all.1920907625 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 126698857770 ps |
| CPU time | 546.83 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:49:09 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-4f967d78-64e8-45b9-a97b-c6664dbc8d55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920907625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1920907625 |
| Directory | /workspace/36.uart_stress_all/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1093481517 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 15519611467 ps |
| CPU time | 216.57 seconds |
| Started | Jul 12 04:40:00 PM PDT 24 |
| Finished | Jul 12 04:43:41 PM PDT 24 |
| Peak memory | 216348 kb |
| Host | smart-e680748f-b708-48c7-8e50-50f56b3bd945 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093481517 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1093481517 |
| Directory | /workspace/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.uart_tx_ovrd.985513486 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 7251588559 ps |
| CPU time | 21.79 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:40:23 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-b278024b-1568-40be-8d21-84852628ecc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985513486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.985513486 |
| Directory | /workspace/36.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/36.uart_tx_rx.4135281353 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 12612522637 ps |
| CPU time | 16.9 seconds |
| Started | Jul 12 04:39:54 PM PDT 24 |
| Finished | Jul 12 04:40:14 PM PDT 24 |
| Peak memory | 198276 kb |
| Host | smart-5d0142e2-01df-459b-8f75-c7e6a8188c74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135281353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4135281353 |
| Directory | /workspace/36.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/37.uart_alert_test.3045710320 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 21564365 ps |
| CPU time | 0.54 seconds |
| Started | Jul 12 04:40:06 PM PDT 24 |
| Finished | Jul 12 04:40:08 PM PDT 24 |
| Peak memory | 194660 kb |
| Host | smart-e33a1851-cd36-4084-a072-a900bbc28daa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045710320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3045710320 |
| Directory | /workspace/37.uart_alert_test/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_full.2560084622 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 72968062105 ps |
| CPU time | 33.73 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:40:36 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-3fb53cf8-788f-438b-ba76-16c08ebb8bc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560084622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2560084622 |
| Directory | /workspace/37.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_overflow.1770806328 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 138932566977 ps |
| CPU time | 274.29 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:44:38 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-a5dbd587-8a06-4b74-9c76-80a15c692310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770806328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1770806328 |
| Directory | /workspace/37.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/37.uart_intr.661956919 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 783565813 ps |
| CPU time | 0.84 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:40:02 PM PDT 24 |
| Peak memory | 195436 kb |
| Host | smart-897e29e5-597c-4d3b-b2b9-db6e69f5912e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661956919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.661956919 |
| Directory | /workspace/37.uart_intr/latest |
| Test location | /workspace/coverage/default/37.uart_long_xfer_wo_dly.859458766 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 115046126949 ps |
| CPU time | 493.32 seconds |
| Started | Jul 12 05:12:29 PM PDT 24 |
| Finished | Jul 12 05:20:45 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-8da5fc74-5716-4339-8d6a-bf5397d18c4b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=859458766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.859458766 |
| Directory | /workspace/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/37.uart_loopback.3385266129 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 9181962519 ps |
| CPU time | 14.37 seconds |
| Started | Jul 12 05:38:09 PM PDT 24 |
| Finished | Jul 12 05:38:42 PM PDT 24 |
| Peak memory | 198164 kb |
| Host | smart-ce51795a-ac3d-4b1b-aa26-96dcdf20b0ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3385266129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3385266129 |
| Directory | /workspace/37.uart_loopback/latest |
| Test location | /workspace/coverage/default/37.uart_noise_filter.3181891239 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 9307062102 ps |
| CPU time | 12.27 seconds |
| Started | Jul 12 04:45:01 PM PDT 24 |
| Finished | Jul 12 04:45:16 PM PDT 24 |
| Peak memory | 194380 kb |
| Host | smart-454cf99a-63e8-4ff8-889a-5178ea15c337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181891239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3181891239 |
| Directory | /workspace/37.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/37.uart_perf.396289205 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 11803864684 ps |
| CPU time | 583.77 seconds |
| Started | Jul 12 06:55:54 PM PDT 24 |
| Finished | Jul 12 07:05:40 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-3b7b6134-e443-441e-b4cb-f674f70fdc7a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=396289205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.396289205 |
| Directory | /workspace/37.uart_perf/latest |
| Test location | /workspace/coverage/default/37.uart_rx_oversample.190117944 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4645876459 ps |
| CPU time | 36.12 seconds |
| Started | Jul 12 04:40:09 PM PDT 24 |
| Finished | Jul 12 04:40:46 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-3d8c6cfc-f84e-42b8-8901-8295e7800469 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=190117944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.190117944 |
| Directory | /workspace/37.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/37.uart_rx_parity_err.3669784230 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 119179999557 ps |
| CPU time | 180.48 seconds |
| Started | Jul 12 06:03:00 PM PDT 24 |
| Finished | Jul 12 06:06:00 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-5ff4d281-2de3-44f7-af1c-6b72b6224db7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669784230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3669784230 |
| Directory | /workspace/37.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/37.uart_rx_start_bit_filter.4029073347 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 6770741010 ps |
| CPU time | 3.61 seconds |
| Started | Jul 12 06:09:49 PM PDT 24 |
| Finished | Jul 12 06:11:35 PM PDT 24 |
| Peak memory | 196332 kb |
| Host | smart-e7125ecb-5f68-4109-9d08-4e6e7e532a77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029073347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4029073347 |
| Directory | /workspace/37.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/37.uart_smoke.214354590 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 476464491 ps |
| CPU time | 1.34 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:05 PM PDT 24 |
| Peak memory | 198176 kb |
| Host | smart-b6a26bec-0b96-4a56-8aff-92d74f80f701 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214354590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.214354590 |
| Directory | /workspace/37.uart_smoke/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all.90841225 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 488270821770 ps |
| CPU time | 416.64 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:47:00 PM PDT 24 |
| Peak memory | 199688 kb |
| Host | smart-4d2adcf6-5243-4072-997e-9016e601641a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90841225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.90841225 |
| Directory | /workspace/37.uart_stress_all/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2117904415 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 24878955997 ps |
| CPU time | 476 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:47:59 PM PDT 24 |
| Peak memory | 216268 kb |
| Host | smart-67bbd9c4-76c6-4d08-81d8-176e66f921b7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117904415 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2117904415 |
| Directory | /workspace/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.uart_tx_ovrd.1125842156 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 922579169 ps |
| CPU time | 2.87 seconds |
| Started | Jul 12 05:52:09 PM PDT 24 |
| Finished | Jul 12 05:52:14 PM PDT 24 |
| Peak memory | 199560 kb |
| Host | smart-e39170d1-eb85-4342-a1bb-c21fc798b687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125842156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1125842156 |
| Directory | /workspace/37.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/37.uart_tx_rx.4283554922 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 53887264516 ps |
| CPU time | 42.38 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:46 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-ef32821d-977e-49ec-9eab-40346ae51e6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283554922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4283554922 |
| Directory | /workspace/37.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/38.uart_alert_test.1076283297 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 44168273 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 195216 kb |
| Host | smart-bcb3121b-8f63-4b5e-9990-7b528861e6f9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076283297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1076283297 |
| Directory | /workspace/38.uart_alert_test/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_full.2014285063 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 44938989877 ps |
| CPU time | 68.53 seconds |
| Started | Jul 12 04:40:02 PM PDT 24 |
| Finished | Jul 12 04:41:14 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-a80e62ad-9305-47a9-86d8-9d183f0512f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014285063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2014285063 |
| Directory | /workspace/38.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_overflow.3427593091 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 129386581935 ps |
| CPU time | 209.56 seconds |
| Started | Jul 12 04:40:06 PM PDT 24 |
| Finished | Jul 12 04:43:38 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-cfbb5390-e773-484c-b565-4c882ba2f0ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427593091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3427593091 |
| Directory | /workspace/38.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_reset.1800859932 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 140864573479 ps |
| CPU time | 37.27 seconds |
| Started | Jul 12 04:40:02 PM PDT 24 |
| Finished | Jul 12 04:40:43 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-e5b5e7f5-74a7-4c3d-9705-c2ce5947428d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800859932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1800859932 |
| Directory | /workspace/38.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/38.uart_intr.3982936603 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 46896289569 ps |
| CPU time | 5.61 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:40:12 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-584cf1d3-139d-443d-b5da-093dc47c2116 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982936603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3982936603 |
| Directory | /workspace/38.uart_intr/latest |
| Test location | /workspace/coverage/default/38.uart_long_xfer_wo_dly.2155745266 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 162641643832 ps |
| CPU time | 431.03 seconds |
| Started | Jul 12 04:40:05 PM PDT 24 |
| Finished | Jul 12 04:47:19 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-115e5841-88df-4b45-a0f3-1515db48f6cd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2155745266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2155745266 |
| Directory | /workspace/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/38.uart_loopback.318804417 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 11511831718 ps |
| CPU time | 2.8 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-4da48dc4-fced-4ae4-ac8b-8b82c36e8b25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=318804417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.318804417 |
| Directory | /workspace/38.uart_loopback/latest |
| Test location | /workspace/coverage/default/38.uart_noise_filter.42242898 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 83148992641 ps |
| CPU time | 57.48 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:41:05 PM PDT 24 |
| Peak memory | 208232 kb |
| Host | smart-8ff45006-0a15-4a7e-8dd6-705ab08123cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42242898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.42242898 |
| Directory | /workspace/38.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/38.uart_perf.3566568362 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 26134378716 ps |
| CPU time | 695.5 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:51:38 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-773107fa-a121-4c5c-8664-d050616e2761 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3566568362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3566568362 |
| Directory | /workspace/38.uart_perf/latest |
| Test location | /workspace/coverage/default/38.uart_rx_oversample.923654771 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 5552378897 ps |
| CPU time | 11.08 seconds |
| Started | Jul 12 04:39:57 PM PDT 24 |
| Finished | Jul 12 04:40:13 PM PDT 24 |
| Peak memory | 199192 kb |
| Host | smart-a70a508c-9b7a-40cd-8448-2b067507ab4e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=923654771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.923654771 |
| Directory | /workspace/38.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/38.uart_rx_parity_err.29604474 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 181793582357 ps |
| CPU time | 44.77 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:40:47 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-5b816265-dd53-4de6-95e0-2823f1730197 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29604474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.29604474 |
| Directory | /workspace/38.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/38.uart_rx_start_bit_filter.3428084201 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 545866493 ps |
| CPU time | 1.37 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:05 PM PDT 24 |
| Peak memory | 195388 kb |
| Host | smart-4444ecd2-3125-4479-bc56-1952c4aab3dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428084201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3428084201 |
| Directory | /workspace/38.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/38.uart_smoke.2145854656 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 271549316 ps |
| CPU time | 1.38 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:40:08 PM PDT 24 |
| Peak memory | 198564 kb |
| Host | smart-4514163c-8f66-4337-96df-e11066da9978 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145854656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2145854656 |
| Directory | /workspace/38.uart_smoke/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all.3804824030 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 583713619974 ps |
| CPU time | 1992.97 seconds |
| Started | Jul 12 04:40:03 PM PDT 24 |
| Finished | Jul 12 05:13:20 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-de4fa71e-06cd-4a80-8335-0048ae7a8f40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804824030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3804824030 |
| Directory | /workspace/38.uart_stress_all/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1477344081 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 82502338038 ps |
| CPU time | 1288.5 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 05:01:32 PM PDT 24 |
| Peak memory | 216424 kb |
| Host | smart-1a67e5cf-6576-4666-a43a-d920e01e5bdb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477344081 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1477344081 |
| Directory | /workspace/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.uart_tx_ovrd.943130182 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 1204922357 ps |
| CPU time | 3.59 seconds |
| Started | Jul 12 04:40:00 PM PDT 24 |
| Finished | Jul 12 04:40:08 PM PDT 24 |
| Peak memory | 198820 kb |
| Host | smart-855a697e-c6ff-450d-9d96-728afaf6dd89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943130182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.943130182 |
| Directory | /workspace/38.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/38.uart_tx_rx.1457952084 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 62299667335 ps |
| CPU time | 18.22 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:22 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-7bd06f39-78c9-4d69-b00a-d4a28e8b937d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457952084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1457952084 |
| Directory | /workspace/38.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/39.uart_alert_test.3175814177 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 42413881 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:40:04 PM PDT 24 |
| Peak memory | 195472 kb |
| Host | smart-5fed0941-4ec3-4a88-a9d3-b7b5e482744c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175814177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3175814177 |
| Directory | /workspace/39.uart_alert_test/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_full.2858814305 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 51969994964 ps |
| CPU time | 33.61 seconds |
| Started | Jul 12 04:40:03 PM PDT 24 |
| Finished | Jul 12 04:40:40 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-f62e3666-7365-4636-a1ef-46986db5a0b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858814305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2858814305 |
| Directory | /workspace/39.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_overflow.3314774885 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 78246517671 ps |
| CPU time | 135.66 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:42:19 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-243f81cb-b7a2-4278-a722-f095f81030c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3314774885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3314774885 |
| Directory | /workspace/39.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_reset.440309006 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 131629816118 ps |
| CPU time | 51.5 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:40:54 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-16f53ae5-82c8-4f21-8c0b-cf0e9254e31e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440309006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.440309006 |
| Directory | /workspace/39.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/39.uart_intr.3724555304 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 9066831896 ps |
| CPU time | 4.3 seconds |
| Started | Jul 12 04:40:03 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 198052 kb |
| Host | smart-ec4afb5d-2e02-4f38-8d8c-0f1a14372d6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724555304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3724555304 |
| Directory | /workspace/39.uart_intr/latest |
| Test location | /workspace/coverage/default/39.uart_long_xfer_wo_dly.45604311 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 61943459649 ps |
| CPU time | 312.39 seconds |
| Started | Jul 12 04:40:00 PM PDT 24 |
| Finished | Jul 12 04:45:17 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-72822f04-2715-484f-af7a-81d44265893d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=45604311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.45604311 |
| Directory | /workspace/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/39.uart_loopback.1321586165 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 8534669917 ps |
| CPU time | 21.03 seconds |
| Started | Jul 12 04:40:03 PM PDT 24 |
| Finished | Jul 12 04:40:27 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-bcc4cb6b-7616-4617-86e5-5b65db9b3e6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321586165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1321586165 |
| Directory | /workspace/39.uart_loopback/latest |
| Test location | /workspace/coverage/default/39.uart_noise_filter.223792078 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 66683302707 ps |
| CPU time | 55.97 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:59 PM PDT 24 |
| Peak memory | 198780 kb |
| Host | smart-e218452d-b45d-42ac-b6c1-30676e5e259d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223792078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.223792078 |
| Directory | /workspace/39.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/39.uart_perf.137780751 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 8752606994 ps |
| CPU time | 249.23 seconds |
| Started | Jul 12 04:40:01 PM PDT 24 |
| Finished | Jul 12 04:44:14 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-2c0c6ca2-d709-4439-8da0-690818834570 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=137780751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.137780751 |
| Directory | /workspace/39.uart_perf/latest |
| Test location | /workspace/coverage/default/39.uart_rx_oversample.1706717046 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 7706201708 ps |
| CPU time | 70.07 seconds |
| Started | Jul 12 04:39:58 PM PDT 24 |
| Finished | Jul 12 04:41:13 PM PDT 24 |
| Peak memory | 198064 kb |
| Host | smart-0e3af274-da71-45ba-a8e4-36386e72cd07 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1706717046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1706717046 |
| Directory | /workspace/39.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/39.uart_rx_parity_err.1210925789 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 116349191858 ps |
| CPU time | 129.27 seconds |
| Started | Jul 12 04:40:07 PM PDT 24 |
| Finished | Jul 12 04:42:18 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-f619fd87-0fd7-4aa8-b1df-7b3321bf620d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210925789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1210925789 |
| Directory | /workspace/39.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/39.uart_rx_start_bit_filter.240911246 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 43737989327 ps |
| CPU time | 16.15 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:40:23 PM PDT 24 |
| Peak memory | 196316 kb |
| Host | smart-0788b6fd-0c01-499b-aec6-1fc51370fadc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240911246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.240911246 |
| Directory | /workspace/39.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/39.uart_smoke.3904169559 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 736393889 ps |
| CPU time | 1.85 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:05 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-33b3c95f-3c29-43b4-a57b-9d23de655fde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904169559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3904169559 |
| Directory | /workspace/39.uart_smoke/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2752667758 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 54474946514 ps |
| CPU time | 778.9 seconds |
| Started | Jul 12 04:40:08 PM PDT 24 |
| Finished | Jul 12 04:53:08 PM PDT 24 |
| Peak memory | 216232 kb |
| Host | smart-6947555b-90aa-49c5-bfbd-ffe7722cdaeb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752667758 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2752667758 |
| Directory | /workspace/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.uart_tx_ovrd.1345990121 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 1684767099 ps |
| CPU time | 1.92 seconds |
| Started | Jul 12 04:40:05 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-9d644331-03d8-4f0e-88a0-4499c5e90c3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345990121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1345990121 |
| Directory | /workspace/39.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/39.uart_tx_rx.2903927289 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 48393412233 ps |
| CPU time | 35.13 seconds |
| Started | Jul 12 04:39:59 PM PDT 24 |
| Finished | Jul 12 04:40:39 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-3c5f6743-364b-441b-8691-c8e471235411 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903927289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2903927289 |
| Directory | /workspace/39.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.uart_alert_test.3414365186 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 39008198 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:38:38 PM PDT 24 |
| Finished | Jul 12 04:38:44 PM PDT 24 |
| Peak memory | 195488 kb |
| Host | smart-262a0aab-f6d3-4f9b-9d5c-7affd2b41cfc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414365186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3414365186 |
| Directory | /workspace/4.uart_alert_test/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_full.3987542590 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 113628344849 ps |
| CPU time | 82.16 seconds |
| Started | Jul 12 04:38:44 PM PDT 24 |
| Finished | Jul 12 04:40:10 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-55ac5c84-50f6-45cc-adfc-51dd1f45d958 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987542590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3987542590 |
| Directory | /workspace/4.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_overflow.835300301 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 32773413656 ps |
| CPU time | 30.22 seconds |
| Started | Jul 12 04:38:32 PM PDT 24 |
| Finished | Jul 12 04:39:08 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-77067803-ccd2-44f8-bf00-848d090fc33c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835300301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.835300301 |
| Directory | /workspace/4.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_reset.2509967405 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 12611884614 ps |
| CPU time | 12.76 seconds |
| Started | Jul 12 04:38:39 PM PDT 24 |
| Finished | Jul 12 04:38:57 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-736a1747-41bb-4871-af42-7fbcdd9cdc63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2509967405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2509967405 |
| Directory | /workspace/4.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/4.uart_intr.2149405466 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 5624965745 ps |
| CPU time | 8.53 seconds |
| Started | Jul 12 04:38:39 PM PDT 24 |
| Finished | Jul 12 04:38:53 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-3e61c6ac-18f7-4abd-aaab-140e3674ded6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149405466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2149405466 |
| Directory | /workspace/4.uart_intr/latest |
| Test location | /workspace/coverage/default/4.uart_long_xfer_wo_dly.1632588673 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 99280533031 ps |
| CPU time | 373.79 seconds |
| Started | Jul 12 04:38:46 PM PDT 24 |
| Finished | Jul 12 04:45:05 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-77630e4f-29d9-4416-b8db-ad3f95bd1baf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1632588673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1632588673 |
| Directory | /workspace/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/4.uart_loopback.2899959001 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 7091844226 ps |
| CPU time | 12.03 seconds |
| Started | Jul 12 04:38:48 PM PDT 24 |
| Finished | Jul 12 04:39:05 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-ae890be8-74ff-444d-be22-0837d92b4d11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899959001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2899959001 |
| Directory | /workspace/4.uart_loopback/latest |
| Test location | /workspace/coverage/default/4.uart_noise_filter.1635433560 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 84010846454 ps |
| CPU time | 152.86 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:41:25 PM PDT 24 |
| Peak memory | 208172 kb |
| Host | smart-ac85e9a5-8bb2-4a72-959d-8e028b52e32b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635433560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1635433560 |
| Directory | /workspace/4.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/4.uart_perf.3160325083 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 17799671513 ps |
| CPU time | 549.94 seconds |
| Started | Jul 12 04:38:40 PM PDT 24 |
| Finished | Jul 12 04:47:55 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-df544cfa-2b75-4b97-9421-51f8264d9416 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3160325083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3160325083 |
| Directory | /workspace/4.uart_perf/latest |
| Test location | /workspace/coverage/default/4.uart_rx_oversample.1720947808 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3459536631 ps |
| CPU time | 6.13 seconds |
| Started | Jul 12 04:38:38 PM PDT 24 |
| Finished | Jul 12 04:38:50 PM PDT 24 |
| Peak memory | 198468 kb |
| Host | smart-40456a1e-f589-4206-96a4-59c6e4e1c6b1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1720947808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1720947808 |
| Directory | /workspace/4.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/4.uart_rx_parity_err.2724399472 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 76512740870 ps |
| CPU time | 163.14 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:41:35 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-5d1c7ef2-a2b3-416c-87ef-c5aa2c4fa9e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724399472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2724399472 |
| Directory | /workspace/4.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/4.uart_rx_start_bit_filter.3225868027 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 492576892 ps |
| CPU time | 1.39 seconds |
| Started | Jul 12 04:38:38 PM PDT 24 |
| Finished | Jul 12 04:38:45 PM PDT 24 |
| Peak memory | 195288 kb |
| Host | smart-d7598b76-68a7-4fd2-b76f-1a73c7e1e6b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225868027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3225868027 |
| Directory | /workspace/4.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/4.uart_sec_cm.1006676715 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 380945361 ps |
| CPU time | 0.75 seconds |
| Started | Jul 12 04:38:32 PM PDT 24 |
| Finished | Jul 12 04:38:38 PM PDT 24 |
| Peak memory | 218060 kb |
| Host | smart-664d4a09-4721-42b6-9c4f-c9f70ab992f2 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006676715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1006676715 |
| Directory | /workspace/4.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/4.uart_smoke.802358562 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 6198986869 ps |
| CPU time | 16.43 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:39:09 PM PDT 24 |
| Peak memory | 199572 kb |
| Host | smart-e96ddeeb-abc4-4ea1-ad06-21d9b26dc2f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802358562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.802358562 |
| Directory | /workspace/4.uart_smoke/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all.1819752069 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 292520068038 ps |
| CPU time | 323.81 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:44:06 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-27cb79ee-758d-4eaa-8cb3-d5861d33fdaa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819752069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1819752069 |
| Directory | /workspace/4.uart_stress_all/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3509701510 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 31889171217 ps |
| CPU time | 415.06 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:45:47 PM PDT 24 |
| Peak memory | 215472 kb |
| Host | smart-d7c84e7e-300a-408a-97d7-869d788ec05b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509701510 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3509701510 |
| Directory | /workspace/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.uart_tx_ovrd.3250651413 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 10034691539 ps |
| CPU time | 7.19 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:38:48 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-d6e8d2b9-e0b1-4bb7-8085-68669d4ccd34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250651413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3250651413 |
| Directory | /workspace/4.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/4.uart_tx_rx.1265358372 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 8061211822 ps |
| CPU time | 11.55 seconds |
| Started | Jul 12 04:38:51 PM PDT 24 |
| Finished | Jul 12 04:39:08 PM PDT 24 |
| Peak memory | 197928 kb |
| Host | smart-c5433e3b-61f5-432a-99e4-52aefc3451ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265358372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1265358372 |
| Directory | /workspace/4.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/40.uart_alert_test.3121114926 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 23182296 ps |
| CPU time | 0.6 seconds |
| Started | Jul 12 04:40:07 PM PDT 24 |
| Finished | Jul 12 04:40:09 PM PDT 24 |
| Peak memory | 195100 kb |
| Host | smart-f45f3068-bdf4-4ba8-8887-9a3bcecb461d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121114926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3121114926 |
| Directory | /workspace/40.uart_alert_test/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_full.2759899306 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 52093691081 ps |
| CPU time | 41.59 seconds |
| Started | Jul 12 04:40:05 PM PDT 24 |
| Finished | Jul 12 04:40:49 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-282c1018-67a7-415b-9d0e-4eb862f9e91d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759899306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2759899306 |
| Directory | /workspace/40.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_overflow.1174267735 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 25289047344 ps |
| CPU time | 37.68 seconds |
| Started | Jul 12 04:40:03 PM PDT 24 |
| Finished | Jul 12 04:40:44 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-14eeee2d-8e6a-4045-833b-f8019895845d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174267735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1174267735 |
| Directory | /workspace/40.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_reset.1491649080 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 12822712013 ps |
| CPU time | 26.08 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:40:33 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-47c35bcc-f7dd-47dc-abeb-b088e08308e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491649080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1491649080 |
| Directory | /workspace/40.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/40.uart_intr.3595104718 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 8428677307 ps |
| CPU time | 2.82 seconds |
| Started | Jul 12 04:40:08 PM PDT 24 |
| Finished | Jul 12 04:40:12 PM PDT 24 |
| Peak memory | 196540 kb |
| Host | smart-8a2aae60-a63b-4821-978e-2c64fab75ac2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595104718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3595104718 |
| Directory | /workspace/40.uart_intr/latest |
| Test location | /workspace/coverage/default/40.uart_long_xfer_wo_dly.241579687 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 101054662341 ps |
| CPU time | 190.07 seconds |
| Started | Jul 12 04:40:03 PM PDT 24 |
| Finished | Jul 12 04:43:17 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-bb6035de-2903-4d89-98b4-4fee612e7f7b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=241579687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.241579687 |
| Directory | /workspace/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/40.uart_loopback.3836272098 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 8234087963 ps |
| CPU time | 3.75 seconds |
| Started | Jul 12 04:40:05 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 199496 kb |
| Host | smart-0463c479-abf6-47bc-8737-7210951b0eb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3836272098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3836272098 |
| Directory | /workspace/40.uart_loopback/latest |
| Test location | /workspace/coverage/default/40.uart_noise_filter.3350964785 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 98833444878 ps |
| CPU time | 110.29 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:41:58 PM PDT 24 |
| Peak memory | 199972 kb |
| Host | smart-ebee1e23-c623-4acc-89e4-def06e467364 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350964785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3350964785 |
| Directory | /workspace/40.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/40.uart_perf.3052114302 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 15513857518 ps |
| CPU time | 142.08 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:42:29 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-9d26bf6d-0592-4987-9a62-d01c32c5b278 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3052114302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3052114302 |
| Directory | /workspace/40.uart_perf/latest |
| Test location | /workspace/coverage/default/40.uart_rx_oversample.2087475954 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2020598373 ps |
| CPU time | 6.89 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:40:20 PM PDT 24 |
| Peak memory | 198228 kb |
| Host | smart-a6159f55-1bb1-42d0-a171-e436efdca111 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2087475954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2087475954 |
| Directory | /workspace/40.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/40.uart_rx_parity_err.2255675402 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 61901325353 ps |
| CPU time | 104.06 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:41:51 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-1eeff150-5f21-4d1f-88d1-f053c7af09a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255675402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2255675402 |
| Directory | /workspace/40.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/40.uart_rx_start_bit_filter.2711225679 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 45943532737 ps |
| CPU time | 21.24 seconds |
| Started | Jul 12 04:40:02 PM PDT 24 |
| Finished | Jul 12 04:40:27 PM PDT 24 |
| Peak memory | 195724 kb |
| Host | smart-829e12f1-c1ac-44aa-8f14-63ea3d1bb543 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711225679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2711225679 |
| Directory | /workspace/40.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/40.uart_smoke.3576111109 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 5576731010 ps |
| CPU time | 14.97 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:40:29 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-6e82db28-0d44-488a-bc36-54503338933d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3576111109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3576111109 |
| Directory | /workspace/40.uart_smoke/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all.1758186414 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 56604515317 ps |
| CPU time | 2229.97 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 05:17:17 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-fe9aeaa0-ee1c-42fc-9c81-2469cefebb5d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758186414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1758186414 |
| Directory | /workspace/40.uart_stress_all/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all_with_rand_reset.474912248 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 115356890571 ps |
| CPU time | 1140.75 seconds |
| Started | Jul 12 04:40:07 PM PDT 24 |
| Finished | Jul 12 04:59:09 PM PDT 24 |
| Peak memory | 216772 kb |
| Host | smart-927fb7c5-9eab-4c04-93d4-8e86b19d5f18 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474912248 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.474912248 |
| Directory | /workspace/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.uart_tx_ovrd.3805742666 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1855832524 ps |
| CPU time | 1.97 seconds |
| Started | Jul 12 04:40:08 PM PDT 24 |
| Finished | Jul 12 04:40:11 PM PDT 24 |
| Peak memory | 199060 kb |
| Host | smart-f8206447-2b18-4597-8b4e-f406aad0a694 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805742666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3805742666 |
| Directory | /workspace/40.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/40.uart_tx_rx.468124388 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 62880884105 ps |
| CPU time | 76.58 seconds |
| Started | Jul 12 04:40:04 PM PDT 24 |
| Finished | Jul 12 04:41:24 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-c6948f5c-933d-48cd-8bd1-b951cd83575d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468124388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.468124388 |
| Directory | /workspace/40.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/41.uart_alert_test.3298067488 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 14688146 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:40:15 PM PDT 24 |
| Peak memory | 195228 kb |
| Host | smart-1495a27b-6dae-4cbf-8c5e-702b01543487 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298067488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3298067488 |
| Directory | /workspace/41.uart_alert_test/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_full.3249597326 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 24998080621 ps |
| CPU time | 15.77 seconds |
| Started | Jul 12 04:40:09 PM PDT 24 |
| Finished | Jul 12 04:40:27 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-891ad678-6c67-46c2-84bc-13cd53dcc252 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249597326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3249597326 |
| Directory | /workspace/41.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_overflow.329654142 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 79168720165 ps |
| CPU time | 33.76 seconds |
| Started | Jul 12 04:40:03 PM PDT 24 |
| Finished | Jul 12 04:40:40 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-c4b331e7-a048-4ac1-b445-0e0833fbfba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329654142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.329654142 |
| Directory | /workspace/41.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_reset.2031514856 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 98334480268 ps |
| CPU time | 28.67 seconds |
| Started | Jul 12 04:40:08 PM PDT 24 |
| Finished | Jul 12 04:40:38 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-2bbe50ec-b817-4053-bf8d-cb4aa5954218 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031514856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2031514856 |
| Directory | /workspace/41.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/41.uart_intr.1074048799 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 45902484658 ps |
| CPU time | 44.88 seconds |
| Started | Jul 12 04:40:05 PM PDT 24 |
| Finished | Jul 12 04:40:52 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-a5eecfad-d64a-4122-9046-4528e0b8092f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074048799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1074048799 |
| Directory | /workspace/41.uart_intr/latest |
| Test location | /workspace/coverage/default/41.uart_long_xfer_wo_dly.562753398 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 98678919477 ps |
| CPU time | 369.53 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:46:22 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-499289df-96b2-41ce-a43a-710cf87d4a32 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=562753398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.562753398 |
| Directory | /workspace/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/41.uart_loopback.1967901300 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 10579272997 ps |
| CPU time | 18.61 seconds |
| Started | Jul 12 04:40:12 PM PDT 24 |
| Finished | Jul 12 04:40:34 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-427aee02-c1a2-4900-898e-e639b263c3be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967901300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1967901300 |
| Directory | /workspace/41.uart_loopback/latest |
| Test location | /workspace/coverage/default/41.uart_noise_filter.846551106 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 29642280828 ps |
| CPU time | 11.82 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:40:24 PM PDT 24 |
| Peak memory | 197432 kb |
| Host | smart-0717e364-898d-4c78-a1eb-4987694bfa10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846551106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.846551106 |
| Directory | /workspace/41.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/41.uart_perf.3746240206 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 16192789482 ps |
| CPU time | 569.15 seconds |
| Started | Jul 12 04:40:09 PM PDT 24 |
| Finished | Jul 12 04:49:40 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-b611f5f4-9729-458c-a539-473ef5a03bd0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3746240206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3746240206 |
| Directory | /workspace/41.uart_perf/latest |
| Test location | /workspace/coverage/default/41.uart_rx_oversample.3397335002 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3485049266 ps |
| CPU time | 7.43 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:40:20 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-d31f3b46-04a2-4f15-b2bf-344dfe0d36ce |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3397335002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3397335002 |
| Directory | /workspace/41.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/41.uart_rx_parity_err.1690032772 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 111672120804 ps |
| CPU time | 262.76 seconds |
| Started | Jul 12 04:40:14 PM PDT 24 |
| Finished | Jul 12 04:44:39 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-da666717-a14d-4d41-b409-75a1da8c32fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1690032772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1690032772 |
| Directory | /workspace/41.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/41.uart_rx_start_bit_filter.3149525984 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2418039977 ps |
| CPU time | 4.06 seconds |
| Started | Jul 12 04:40:06 PM PDT 24 |
| Finished | Jul 12 04:40:12 PM PDT 24 |
| Peak memory | 196164 kb |
| Host | smart-0d52f014-69a5-45c0-ae12-92dbfdb47d27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149525984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3149525984 |
| Directory | /workspace/41.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/41.uart_smoke.1538001407 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 109992493 ps |
| CPU time | 0.92 seconds |
| Started | Jul 12 04:40:06 PM PDT 24 |
| Finished | Jul 12 04:40:09 PM PDT 24 |
| Peak memory | 196828 kb |
| Host | smart-9c3b7f27-4807-4436-a376-9ec1d78d5301 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538001407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1538001407 |
| Directory | /workspace/41.uart_smoke/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all.3693336797 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 31211155620 ps |
| CPU time | 57.25 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:41:11 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-876864ed-670d-4ee3-843a-62232e8a17fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693336797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3693336797 |
| Directory | /workspace/41.uart_stress_all/latest |
| Test location | /workspace/coverage/default/41.uart_tx_ovrd.205634920 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 6788781771 ps |
| CPU time | 25.97 seconds |
| Started | Jul 12 04:40:09 PM PDT 24 |
| Finished | Jul 12 04:40:38 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-6cd2d6b7-c64b-4f00-bdf2-0bc5068580b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205634920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.205634920 |
| Directory | /workspace/41.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/41.uart_tx_rx.1313799397 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 16974914396 ps |
| CPU time | 13.86 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:40:28 PM PDT 24 |
| Peak memory | 197120 kb |
| Host | smart-6b4ac61f-4bbf-41ee-a913-3b1d446088ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313799397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1313799397 |
| Directory | /workspace/41.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/42.uart_alert_test.52891435 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 19335799 ps |
| CPU time | 0.53 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:40:14 PM PDT 24 |
| Peak memory | 195220 kb |
| Host | smart-231bdd70-34d5-4037-81a5-c0aefe5d5c68 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52891435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.52891435 |
| Directory | /workspace/42.uart_alert_test/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_full.923651325 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 34944685715 ps |
| CPU time | 28.21 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:40:41 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-4e48cc66-cebe-48ec-ac7b-3094a0676854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923651325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.923651325 |
| Directory | /workspace/42.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_overflow.315792557 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 33099365931 ps |
| CPU time | 27.23 seconds |
| Started | Jul 12 04:40:14 PM PDT 24 |
| Finished | Jul 12 04:40:43 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-81531232-1e84-468d-9a21-356a12016a86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315792557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.315792557 |
| Directory | /workspace/42.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_reset.3630105331 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 46388767551 ps |
| CPU time | 7.04 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:40:20 PM PDT 24 |
| Peak memory | 199004 kb |
| Host | smart-df96b6c6-b9c0-4cf0-a25d-22d59bd05770 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630105331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3630105331 |
| Directory | /workspace/42.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/42.uart_intr.3870955979 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 20036874224 ps |
| CPU time | 10.31 seconds |
| Started | Jul 12 04:40:09 PM PDT 24 |
| Finished | Jul 12 04:40:22 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-ff21ea4d-b840-4d0b-a260-c62b4bccadd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870955979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3870955979 |
| Directory | /workspace/42.uart_intr/latest |
| Test location | /workspace/coverage/default/42.uart_long_xfer_wo_dly.1037696401 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 106719097047 ps |
| CPU time | 374.52 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:46:29 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-80c95b90-6504-4e48-bb0a-f73237ee931d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1037696401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1037696401 |
| Directory | /workspace/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/42.uart_loopback.147510300 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 6358429143 ps |
| CPU time | 3.95 seconds |
| Started | Jul 12 04:40:12 PM PDT 24 |
| Finished | Jul 12 04:40:18 PM PDT 24 |
| Peak memory | 199368 kb |
| Host | smart-89aa2434-7e84-4904-ac80-a45f7d0f4f34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147510300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.147510300 |
| Directory | /workspace/42.uart_loopback/latest |
| Test location | /workspace/coverage/default/42.uart_noise_filter.2536742390 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 280082466247 ps |
| CPU time | 24.82 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:40:37 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-14b997a3-e9fc-4606-a116-e3fe48ca5432 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536742390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2536742390 |
| Directory | /workspace/42.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/42.uart_perf.2920390246 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 15734182685 ps |
| CPU time | 361.05 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:46:14 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-7e1d3561-1376-4e3c-b10e-c240e6ef657e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2920390246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2920390246 |
| Directory | /workspace/42.uart_perf/latest |
| Test location | /workspace/coverage/default/42.uart_rx_oversample.3956804267 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1801951822 ps |
| CPU time | 2.53 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:40:16 PM PDT 24 |
| Peak memory | 197704 kb |
| Host | smart-c5e6ff8a-4f20-4e25-81db-2f2b0c4ff499 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3956804267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3956804267 |
| Directory | /workspace/42.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/42.uart_rx_start_bit_filter.846881646 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 29808821154 ps |
| CPU time | 23.98 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:40:38 PM PDT 24 |
| Peak memory | 195928 kb |
| Host | smart-23b889fb-20f4-4066-9c4d-69c509ad4470 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846881646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.846881646 |
| Directory | /workspace/42.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/42.uart_smoke.1483585318 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 501214453 ps |
| CPU time | 1.78 seconds |
| Started | Jul 12 04:40:10 PM PDT 24 |
| Finished | Jul 12 04:40:15 PM PDT 24 |
| Peak memory | 198032 kb |
| Host | smart-5dab11a7-d3ae-418c-b0d1-63565293d1c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483585318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1483585318 |
| Directory | /workspace/42.uart_smoke/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all.2165385345 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 215962080988 ps |
| CPU time | 418.14 seconds |
| Started | Jul 12 04:40:14 PM PDT 24 |
| Finished | Jul 12 04:47:14 PM PDT 24 |
| Peak memory | 200036 kb |
| Host | smart-6cdfb34f-3238-4d51-8420-9c6f2181ef0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165385345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2165385345 |
| Directory | /workspace/42.uart_stress_all/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all_with_rand_reset.816655633 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 96229426082 ps |
| CPU time | 270.94 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:44:45 PM PDT 24 |
| Peak memory | 216552 kb |
| Host | smart-4af3fcc1-c0b7-42c3-9e8d-81cbfd4fe1b7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816655633 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.816655633 |
| Directory | /workspace/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.uart_tx_ovrd.1107056775 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 7589188505 ps |
| CPU time | 8.77 seconds |
| Started | Jul 12 04:40:13 PM PDT 24 |
| Finished | Jul 12 04:40:24 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-5593211e-5921-4d26-83e6-6b763e941293 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107056775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1107056775 |
| Directory | /workspace/42.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/42.uart_tx_rx.4192798674 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 29831730395 ps |
| CPU time | 16.17 seconds |
| Started | Jul 12 04:40:12 PM PDT 24 |
| Finished | Jul 12 04:40:31 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-952cb334-cae5-480f-bc1c-9de2750eb0a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192798674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4192798674 |
| Directory | /workspace/42.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/43.uart_alert_test.4194267384 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 73805206 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:40:16 PM PDT 24 |
| Finished | Jul 12 04:40:18 PM PDT 24 |
| Peak memory | 195220 kb |
| Host | smart-bf4531f0-90ec-43fb-a9a9-17d53d321d1f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194267384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.4194267384 |
| Directory | /workspace/43.uart_alert_test/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_overflow.1199144511 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 63953761158 ps |
| CPU time | 27.88 seconds |
| Started | Jul 12 04:40:12 PM PDT 24 |
| Finished | Jul 12 04:40:42 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-8abb8a9b-01ba-49da-a68a-aece45751f4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1199144511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1199144511 |
| Directory | /workspace/43.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_reset.2467613592 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 47361556834 ps |
| CPU time | 14.95 seconds |
| Started | Jul 12 04:40:14 PM PDT 24 |
| Finished | Jul 12 04:40:31 PM PDT 24 |
| Peak memory | 199540 kb |
| Host | smart-d690866a-1557-460a-a58e-e44e76e7006c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467613592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2467613592 |
| Directory | /workspace/43.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/43.uart_intr.1064049937 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 7851067697 ps |
| CPU time | 7.38 seconds |
| Started | Jul 12 04:40:15 PM PDT 24 |
| Finished | Jul 12 04:40:24 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-93c01715-ff47-4bc5-81f6-499aad2b52d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064049937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1064049937 |
| Directory | /workspace/43.uart_intr/latest |
| Test location | /workspace/coverage/default/43.uart_long_xfer_wo_dly.136579988 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 119800790281 ps |
| CPU time | 464.97 seconds |
| Started | Jul 12 04:40:16 PM PDT 24 |
| Finished | Jul 12 04:48:02 PM PDT 24 |
| Peak memory | 200100 kb |
| Host | smart-d45a9540-61f8-47e3-9f73-a0a8003bc658 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=136579988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.136579988 |
| Directory | /workspace/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/43.uart_loopback.109503854 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 5411126990 ps |
| CPU time | 3.87 seconds |
| Started | Jul 12 04:40:17 PM PDT 24 |
| Finished | Jul 12 04:40:22 PM PDT 24 |
| Peak memory | 198856 kb |
| Host | smart-6ee89a2d-b0bc-4112-bd66-fce60f87d0ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109503854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.109503854 |
| Directory | /workspace/43.uart_loopback/latest |
| Test location | /workspace/coverage/default/43.uart_noise_filter.4133819549 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 16796582419 ps |
| CPU time | 8.5 seconds |
| Started | Jul 12 04:40:11 PM PDT 24 |
| Finished | Jul 12 04:40:22 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-6410ec52-9094-4ce9-94f3-c0b892fd0494 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133819549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.4133819549 |
| Directory | /workspace/43.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/43.uart_perf.3984699127 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 14354127227 ps |
| CPU time | 156.47 seconds |
| Started | Jul 12 04:40:18 PM PDT 24 |
| Finished | Jul 12 04:42:56 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-d02292d9-5616-4700-8807-05a73ad4bef7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3984699127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3984699127 |
| Directory | /workspace/43.uart_perf/latest |
| Test location | /workspace/coverage/default/43.uart_rx_oversample.1178492980 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3885559496 ps |
| CPU time | 15.32 seconds |
| Started | Jul 12 04:40:12 PM PDT 24 |
| Finished | Jul 12 04:40:30 PM PDT 24 |
| Peak memory | 197952 kb |
| Host | smart-453178d6-3739-493d-8f97-2436214d57a9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1178492980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1178492980 |
| Directory | /workspace/43.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/43.uart_rx_parity_err.713329090 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 114571723519 ps |
| CPU time | 86.56 seconds |
| Started | Jul 12 04:40:19 PM PDT 24 |
| Finished | Jul 12 04:41:47 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-59885500-4ea3-4fd5-9fa9-292fe66d295e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713329090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.713329090 |
| Directory | /workspace/43.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/43.uart_rx_start_bit_filter.4011903630 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 2068692101 ps |
| CPU time | 1.37 seconds |
| Started | Jul 12 04:40:16 PM PDT 24 |
| Finished | Jul 12 04:40:19 PM PDT 24 |
| Peak memory | 195352 kb |
| Host | smart-fd0a0198-ad84-451e-b43c-3c4320ca3cf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011903630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4011903630 |
| Directory | /workspace/43.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/43.uart_smoke.4160530361 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 516125214 ps |
| CPU time | 1.44 seconds |
| Started | Jul 12 04:40:15 PM PDT 24 |
| Finished | Jul 12 04:40:18 PM PDT 24 |
| Peak memory | 198148 kb |
| Host | smart-dcae4f69-76c9-448f-8138-152022689955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160530361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.4160530361 |
| Directory | /workspace/43.uart_smoke/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all.1077417266 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 141691767169 ps |
| CPU time | 56.2 seconds |
| Started | Jul 12 04:40:17 PM PDT 24 |
| Finished | Jul 12 04:41:14 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-decdc0ce-7932-43c1-bcee-a3f32ea01cd1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077417266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1077417266 |
| Directory | /workspace/43.uart_stress_all/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3067640298 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 144406467860 ps |
| CPU time | 458.17 seconds |
| Started | Jul 12 04:40:20 PM PDT 24 |
| Finished | Jul 12 04:47:59 PM PDT 24 |
| Peak memory | 210388 kb |
| Host | smart-1cec6860-486e-47f0-b813-f7dc2dc037c4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067640298 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3067640298 |
| Directory | /workspace/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_tx_ovrd.392741872 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1441170534 ps |
| CPU time | 2.43 seconds |
| Started | Jul 12 04:40:15 PM PDT 24 |
| Finished | Jul 12 04:40:19 PM PDT 24 |
| Peak memory | 198760 kb |
| Host | smart-ef401833-4e4f-4a72-b831-d3b59c890594 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392741872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.392741872 |
| Directory | /workspace/43.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/43.uart_tx_rx.1029474207 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 136629520436 ps |
| CPU time | 40.93 seconds |
| Started | Jul 12 04:40:12 PM PDT 24 |
| Finished | Jul 12 04:40:56 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-4fc43d7e-69fd-4f22-b3f8-b1aca001f592 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1029474207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1029474207 |
| Directory | /workspace/43.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/44.uart_alert_test.3526315854 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11413785 ps |
| CPU time | 0.61 seconds |
| Started | Jul 12 04:40:19 PM PDT 24 |
| Finished | Jul 12 04:40:21 PM PDT 24 |
| Peak memory | 195140 kb |
| Host | smart-35b889fc-7191-480d-a98f-d6934d2f4cfa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526315854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3526315854 |
| Directory | /workspace/44.uart_alert_test/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_full.2708593939 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 48498729595 ps |
| CPU time | 70.87 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:41:33 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-1e5f60dc-5a40-4565-963f-68845d7c6588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708593939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2708593939 |
| Directory | /workspace/44.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_overflow.1265149999 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 36314521382 ps |
| CPU time | 19.08 seconds |
| Started | Jul 12 04:40:16 PM PDT 24 |
| Finished | Jul 12 04:40:37 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-4ef9dbbf-3d54-4a4b-9c02-3effe27ca4ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265149999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1265149999 |
| Directory | /workspace/44.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_reset.1787147213 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 105867847677 ps |
| CPU time | 178.3 seconds |
| Started | Jul 12 04:40:18 PM PDT 24 |
| Finished | Jul 12 04:43:17 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-9a55677e-9e20-402a-8d61-5a0a578b6871 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787147213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1787147213 |
| Directory | /workspace/44.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/44.uart_intr.1656863602 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 402500058459 ps |
| CPU time | 592.52 seconds |
| Started | Jul 12 04:40:20 PM PDT 24 |
| Finished | Jul 12 04:50:14 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-3d3b90d8-6035-4099-b287-022a2d331727 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656863602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1656863602 |
| Directory | /workspace/44.uart_intr/latest |
| Test location | /workspace/coverage/default/44.uart_long_xfer_wo_dly.1390222795 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 40549236331 ps |
| CPU time | 276.04 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:44:59 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-eb51c96b-f15a-4c0d-b440-22bc202538d2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1390222795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1390222795 |
| Directory | /workspace/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/44.uart_loopback.1806535106 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5298788421 ps |
| CPU time | 5.64 seconds |
| Started | Jul 12 04:40:21 PM PDT 24 |
| Finished | Jul 12 04:40:27 PM PDT 24 |
| Peak memory | 199600 kb |
| Host | smart-b9dcbc71-fcb1-448a-92bd-aaf5cc710dcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806535106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1806535106 |
| Directory | /workspace/44.uart_loopback/latest |
| Test location | /workspace/coverage/default/44.uart_perf.2154042669 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 4214089054 ps |
| CPU time | 65.13 seconds |
| Started | Jul 12 04:40:16 PM PDT 24 |
| Finished | Jul 12 04:41:22 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-30352a9a-e791-469d-8efc-b0bdf26a2e7c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2154042669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2154042669 |
| Directory | /workspace/44.uart_perf/latest |
| Test location | /workspace/coverage/default/44.uart_rx_oversample.828495491 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3384740281 ps |
| CPU time | 5.22 seconds |
| Started | Jul 12 04:40:19 PM PDT 24 |
| Finished | Jul 12 04:40:26 PM PDT 24 |
| Peak memory | 198396 kb |
| Host | smart-5cc41179-931c-4ede-a461-c63875ba4bb4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=828495491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.828495491 |
| Directory | /workspace/44.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/44.uart_rx_parity_err.3383112778 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 13088952166 ps |
| CPU time | 23.57 seconds |
| Started | Jul 12 04:40:18 PM PDT 24 |
| Finished | Jul 12 04:40:43 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-5ac9e454-75db-46d7-a509-6eabaa8b810b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383112778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3383112778 |
| Directory | /workspace/44.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/44.uart_rx_start_bit_filter.979005913 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 554643779 ps |
| CPU time | 1.12 seconds |
| Started | Jul 12 04:40:17 PM PDT 24 |
| Finished | Jul 12 04:40:19 PM PDT 24 |
| Peak memory | 195200 kb |
| Host | smart-b9e52e30-1095-4846-99a6-f5ad2e5cb489 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979005913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.979005913 |
| Directory | /workspace/44.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/44.uart_smoke.2048285789 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 709484587 ps |
| CPU time | 1.9 seconds |
| Started | Jul 12 04:40:18 PM PDT 24 |
| Finished | Jul 12 04:40:21 PM PDT 24 |
| Peak memory | 199396 kb |
| Host | smart-1d7d7df2-3d30-4eee-ab77-02673131ae29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048285789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2048285789 |
| Directory | /workspace/44.uart_smoke/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all.1974237162 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 210369491223 ps |
| CPU time | 827.75 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:54:12 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-1f823cdd-f22d-471d-bfd6-78b449e979e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974237162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1974237162 |
| Directory | /workspace/44.uart_stress_all/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3567152005 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 60876539746 ps |
| CPU time | 175.51 seconds |
| Started | Jul 12 04:40:19 PM PDT 24 |
| Finished | Jul 12 04:43:16 PM PDT 24 |
| Peak memory | 208184 kb |
| Host | smart-f5e24d3d-682d-4e0f-aff6-c4fc43691a9d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567152005 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3567152005 |
| Directory | /workspace/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.uart_tx_ovrd.1552757608 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 581912154 ps |
| CPU time | 2.12 seconds |
| Started | Jul 12 04:40:16 PM PDT 24 |
| Finished | Jul 12 04:40:19 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-19e6f224-8d77-406e-b054-195fd4222162 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552757608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1552757608 |
| Directory | /workspace/44.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/44.uart_tx_rx.4241770367 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 182343483051 ps |
| CPU time | 61.62 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:41:25 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-51b454aa-303b-4f66-b4dd-458424390d76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241770367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4241770367 |
| Directory | /workspace/44.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/45.uart_alert_test.628959855 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 14890814 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:40:27 PM PDT 24 |
| Finished | Jul 12 04:40:29 PM PDT 24 |
| Peak memory | 195168 kb |
| Host | smart-20192a20-59fe-4aca-badc-e98d00c59840 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628959855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.628959855 |
| Directory | /workspace/45.uart_alert_test/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_full.866183844 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 140438509860 ps |
| CPU time | 241.4 seconds |
| Started | Jul 12 04:40:18 PM PDT 24 |
| Finished | Jul 12 04:44:21 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-9ec9685d-fcc9-472c-8193-bdba7043f75e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866183844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.866183844 |
| Directory | /workspace/45.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_overflow.3749159648 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 38713959415 ps |
| CPU time | 66.12 seconds |
| Started | Jul 12 04:40:19 PM PDT 24 |
| Finished | Jul 12 04:41:27 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-d84233fc-7051-4605-b830-3d70b030442f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749159648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3749159648 |
| Directory | /workspace/45.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_reset.3702722280 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 26957698292 ps |
| CPU time | 42.64 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:41:05 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-4400c691-da6d-4cbe-8791-4caaf33d728c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3702722280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3702722280 |
| Directory | /workspace/45.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/45.uart_intr.3700813056 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 33966957208 ps |
| CPU time | 16.83 seconds |
| Started | Jul 12 04:40:23 PM PDT 24 |
| Finished | Jul 12 04:40:41 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-1ba7bbb8-dd1d-4c3f-baa0-f01938d2b90e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700813056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3700813056 |
| Directory | /workspace/45.uart_intr/latest |
| Test location | /workspace/coverage/default/45.uart_long_xfer_wo_dly.335592044 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 83876493081 ps |
| CPU time | 317.9 seconds |
| Started | Jul 12 04:40:24 PM PDT 24 |
| Finished | Jul 12 04:45:43 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-7b17f706-c7d1-4906-8331-aeb9798db81c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=335592044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.335592044 |
| Directory | /workspace/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/45.uart_loopback.3410893149 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1053005007 ps |
| CPU time | 1.04 seconds |
| Started | Jul 12 04:40:28 PM PDT 24 |
| Finished | Jul 12 04:40:30 PM PDT 24 |
| Peak memory | 195816 kb |
| Host | smart-2f12fad4-e061-4ae8-b883-a6e32fc4d1d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3410893149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3410893149 |
| Directory | /workspace/45.uart_loopback/latest |
| Test location | /workspace/coverage/default/45.uart_noise_filter.1370936001 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 31965458155 ps |
| CPU time | 51.08 seconds |
| Started | Jul 12 04:40:21 PM PDT 24 |
| Finished | Jul 12 04:41:13 PM PDT 24 |
| Peak memory | 200064 kb |
| Host | smart-dbafef75-411e-4ca1-b049-a5cd537727a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370936001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1370936001 |
| Directory | /workspace/45.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/45.uart_perf.647771239 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 7128016837 ps |
| CPU time | 97.71 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:42:01 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-cdec3905-1411-4b25-9432-01dff047281c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=647771239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.647771239 |
| Directory | /workspace/45.uart_perf/latest |
| Test location | /workspace/coverage/default/45.uart_rx_oversample.1356989528 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3687992042 ps |
| CPU time | 16.3 seconds |
| Started | Jul 12 04:40:24 PM PDT 24 |
| Finished | Jul 12 04:40:42 PM PDT 24 |
| Peak memory | 197776 kb |
| Host | smart-a25262b9-07f3-408c-adfd-2c50c3820758 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1356989528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1356989528 |
| Directory | /workspace/45.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/45.uart_rx_parity_err.1532676145 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 117156797036 ps |
| CPU time | 128.1 seconds |
| Started | Jul 12 04:40:24 PM PDT 24 |
| Finished | Jul 12 04:42:33 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-d830c23c-187d-40ea-b718-23193247cd53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532676145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1532676145 |
| Directory | /workspace/45.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/45.uart_rx_start_bit_filter.1155414580 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 5478929124 ps |
| CPU time | 2.71 seconds |
| Started | Jul 12 04:40:27 PM PDT 24 |
| Finished | Jul 12 04:40:31 PM PDT 24 |
| Peak memory | 196000 kb |
| Host | smart-b799d57c-0e39-4236-8a30-c5eeddd290ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155414580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1155414580 |
| Directory | /workspace/45.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/45.uart_smoke.3737896742 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 705618825 ps |
| CPU time | 2.1 seconds |
| Started | Jul 12 04:40:19 PM PDT 24 |
| Finished | Jul 12 04:40:22 PM PDT 24 |
| Peak memory | 198748 kb |
| Host | smart-170af701-b861-4fc3-a008-498bc5ffbd65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737896742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3737896742 |
| Directory | /workspace/45.uart_smoke/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2257090134 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 84517263437 ps |
| CPU time | 225.32 seconds |
| Started | Jul 12 04:40:26 PM PDT 24 |
| Finished | Jul 12 04:44:12 PM PDT 24 |
| Peak memory | 216624 kb |
| Host | smart-c75081c4-cacd-4bf5-b6c7-d235bb524cb5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257090134 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2257090134 |
| Directory | /workspace/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.uart_tx_ovrd.988018185 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 8275955678 ps |
| CPU time | 7.38 seconds |
| Started | Jul 12 04:40:23 PM PDT 24 |
| Finished | Jul 12 04:40:32 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-2d0965b4-98e0-492a-a08f-9ea072323387 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988018185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.988018185 |
| Directory | /workspace/45.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/45.uart_tx_rx.3148846499 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 8878301379 ps |
| CPU time | 9.37 seconds |
| Started | Jul 12 04:40:19 PM PDT 24 |
| Finished | Jul 12 04:40:29 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-0795bf2c-0ae1-4f1b-8928-0185b9dd3f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148846499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3148846499 |
| Directory | /workspace/45.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/46.uart_alert_test.854301874 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 15965916 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:40:39 PM PDT 24 |
| Peak memory | 194876 kb |
| Host | smart-56e34bc7-2077-4bc9-a771-a7d96c3411b4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854301874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.854301874 |
| Directory | /workspace/46.uart_alert_test/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_overflow.4185197196 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 103151037811 ps |
| CPU time | 161.17 seconds |
| Started | Jul 12 04:40:24 PM PDT 24 |
| Finished | Jul 12 04:43:07 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-c614bb30-aaab-40b4-a85b-401f2f5ce138 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4185197196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.4185197196 |
| Directory | /workspace/46.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_reset.3466677043 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 72189652926 ps |
| CPU time | 62.37 seconds |
| Started | Jul 12 04:40:27 PM PDT 24 |
| Finished | Jul 12 04:41:30 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-b7267998-f60f-493f-a69b-23826346cb59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466677043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3466677043 |
| Directory | /workspace/46.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/46.uart_intr.2158323483 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 67229908741 ps |
| CPU time | 103.46 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:42:07 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-d9e49a17-a108-4bf0-899c-c7d982d5dc27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158323483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2158323483 |
| Directory | /workspace/46.uart_intr/latest |
| Test location | /workspace/coverage/default/46.uart_long_xfer_wo_dly.4079742975 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 118065182361 ps |
| CPU time | 429.8 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:47:50 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-4ba7ddc8-2980-4186-8b85-53700f71a08e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4079742975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4079742975 |
| Directory | /workspace/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/46.uart_loopback.1405431781 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 109790129 ps |
| CPU time | 0.79 seconds |
| Started | Jul 12 04:40:24 PM PDT 24 |
| Finished | Jul 12 04:40:26 PM PDT 24 |
| Peak memory | 195584 kb |
| Host | smart-2837701f-eaae-4b40-822e-6ec6c111ae45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405431781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1405431781 |
| Directory | /workspace/46.uart_loopback/latest |
| Test location | /workspace/coverage/default/46.uart_noise_filter.3475851051 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 23764357081 ps |
| CPU time | 28.1 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:40:51 PM PDT 24 |
| Peak memory | 198848 kb |
| Host | smart-a39a2d49-d2fc-4732-b680-8b4f44f52c6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475851051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3475851051 |
| Directory | /workspace/46.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/46.uart_perf.942947008 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6474720362 ps |
| CPU time | 367.76 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:46:48 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-43cd5120-8467-4426-822e-e4ccdd90e148 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=942947008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.942947008 |
| Directory | /workspace/46.uart_perf/latest |
| Test location | /workspace/coverage/default/46.uart_rx_oversample.4020034132 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 5469067660 ps |
| CPU time | 14.32 seconds |
| Started | Jul 12 04:40:24 PM PDT 24 |
| Finished | Jul 12 04:40:39 PM PDT 24 |
| Peak memory | 199052 kb |
| Host | smart-3f8358b2-936f-445f-9bd9-089fa875d342 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4020034132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4020034132 |
| Directory | /workspace/46.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/46.uart_rx_parity_err.2128030287 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 124347960812 ps |
| CPU time | 188.7 seconds |
| Started | Jul 12 04:40:23 PM PDT 24 |
| Finished | Jul 12 04:43:33 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-99adbf0d-72e9-4349-81e0-46276476637f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128030287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2128030287 |
| Directory | /workspace/46.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/46.uart_rx_start_bit_filter.455419474 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 32655410177 ps |
| CPU time | 8.57 seconds |
| Started | Jul 12 04:40:22 PM PDT 24 |
| Finished | Jul 12 04:40:32 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-934c05ee-c51d-456e-9b36-e86e6d25a8a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455419474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.455419474 |
| Directory | /workspace/46.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/46.uart_smoke.2089369596 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 6332172084 ps |
| CPU time | 9.81 seconds |
| Started | Jul 12 04:40:39 PM PDT 24 |
| Finished | Jul 12 04:40:51 PM PDT 24 |
| Peak memory | 199204 kb |
| Host | smart-e10ffae1-98a3-410d-bed5-2a9e41531d80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089369596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2089369596 |
| Directory | /workspace/46.uart_smoke/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all.1287314723 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 77519154553 ps |
| CPU time | 120.14 seconds |
| Started | Jul 12 04:40:34 PM PDT 24 |
| Finished | Jul 12 04:42:36 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-75272faf-a858-4ad2-8fdc-ae36615f7ef9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287314723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1287314723 |
| Directory | /workspace/46.uart_stress_all/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3285785369 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 228676651657 ps |
| CPU time | 203.59 seconds |
| Started | Jul 12 04:40:33 PM PDT 24 |
| Finished | Jul 12 04:43:58 PM PDT 24 |
| Peak memory | 216480 kb |
| Host | smart-7904e662-73d6-4597-9224-8d8bf2e0d343 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285785369 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3285785369 |
| Directory | /workspace/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.uart_tx_ovrd.908133741 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 10353018612 ps |
| CPU time | 5.59 seconds |
| Started | Jul 12 04:40:27 PM PDT 24 |
| Finished | Jul 12 04:40:34 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-af51e01f-69c0-4d17-a23f-bfcf694050d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908133741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.908133741 |
| Directory | /workspace/46.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/46.uart_tx_rx.3412431223 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 43625672697 ps |
| CPU time | 37.5 seconds |
| Started | Jul 12 04:40:30 PM PDT 24 |
| Finished | Jul 12 04:41:08 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-45adee0c-48a9-4e11-a8e6-be53ae79dda7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412431223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3412431223 |
| Directory | /workspace/46.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/47.uart_alert_test.852979383 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 39378127 ps |
| CPU time | 0.62 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:40:38 PM PDT 24 |
| Peak memory | 195252 kb |
| Host | smart-27f9175b-e2e4-4797-8573-79cc85865ca4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852979383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.852979383 |
| Directory | /workspace/47.uart_alert_test/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_full.4027961589 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 37067608891 ps |
| CPU time | 60.22 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:41:40 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-2d8c4bcd-8d47-4f88-8bbe-db1b11e2d3fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027961589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4027961589 |
| Directory | /workspace/47.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_overflow.3473830232 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 113849770529 ps |
| CPU time | 84.11 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:42:05 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-eb50e573-1256-407c-bee5-3d484f2a8e9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473830232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3473830232 |
| Directory | /workspace/47.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_reset.964160029 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 160546075259 ps |
| CPU time | 99.8 seconds |
| Started | Jul 12 04:40:42 PM PDT 24 |
| Finished | Jul 12 04:42:24 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-49a93024-9c26-4acd-a15c-2da73388d59e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964160029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.964160029 |
| Directory | /workspace/47.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/47.uart_intr.1743814357 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 26527795123 ps |
| CPU time | 10.34 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:40:47 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-c16b9116-c592-4d96-a8b7-95c82007b71d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743814357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1743814357 |
| Directory | /workspace/47.uart_intr/latest |
| Test location | /workspace/coverage/default/47.uart_long_xfer_wo_dly.2842604133 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 139869165482 ps |
| CPU time | 1499.47 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 05:05:36 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-9319fe2a-0e5c-44c3-83d9-206d88cdabae |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2842604133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2842604133 |
| Directory | /workspace/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/47.uart_loopback.4150607704 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 738332688 ps |
| CPU time | 1.17 seconds |
| Started | Jul 12 04:40:31 PM PDT 24 |
| Finished | Jul 12 04:40:33 PM PDT 24 |
| Peak memory | 196020 kb |
| Host | smart-8a649e85-b055-4c50-af95-fbda51d342a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150607704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.4150607704 |
| Directory | /workspace/47.uart_loopback/latest |
| Test location | /workspace/coverage/default/47.uart_noise_filter.4129220802 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 59461071264 ps |
| CPU time | 119.9 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:42:39 PM PDT 24 |
| Peak memory | 208160 kb |
| Host | smart-10978a38-b3ee-4028-8f1b-c898a5441456 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129220802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.4129220802 |
| Directory | /workspace/47.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/47.uart_perf.997814004 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 17956732952 ps |
| CPU time | 248.85 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:44:48 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-1721b7ce-6066-4a5c-a35b-7cff236de68d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=997814004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.997814004 |
| Directory | /workspace/47.uart_perf/latest |
| Test location | /workspace/coverage/default/47.uart_rx_oversample.117499520 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2502890358 ps |
| CPU time | 6.82 seconds |
| Started | Jul 12 04:40:31 PM PDT 24 |
| Finished | Jul 12 04:40:38 PM PDT 24 |
| Peak memory | 198908 kb |
| Host | smart-3202a207-6975-41f1-a23a-740fd0fd755f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=117499520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.117499520 |
| Directory | /workspace/47.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/47.uart_rx_parity_err.837060873 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 119162827975 ps |
| CPU time | 93.57 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:42:13 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-8ba672fd-0c81-4a7d-bb45-4a8bc8b684dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837060873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.837060873 |
| Directory | /workspace/47.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/47.uart_rx_start_bit_filter.2745760066 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2727004476 ps |
| CPU time | 1.69 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:40:42 PM PDT 24 |
| Peak memory | 195820 kb |
| Host | smart-b345331d-b692-4dff-80fc-05159fe8a0db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745760066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2745760066 |
| Directory | /workspace/47.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/47.uart_smoke.3817915578 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 495292972 ps |
| CPU time | 1.96 seconds |
| Started | Jul 12 04:40:33 PM PDT 24 |
| Finished | Jul 12 04:40:36 PM PDT 24 |
| Peak memory | 198500 kb |
| Host | smart-02536f2b-e2b1-423b-9e6b-7a219b2e671d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817915578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3817915578 |
| Directory | /workspace/47.uart_smoke/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all.2144802874 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 418391846989 ps |
| CPU time | 1716.04 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 05:09:16 PM PDT 24 |
| Peak memory | 216120 kb |
| Host | smart-8b6e89de-052a-43f9-bc60-a7be19f78b9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144802874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2144802874 |
| Directory | /workspace/47.uart_stress_all/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all_with_rand_reset.560260550 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 267515548664 ps |
| CPU time | 818.16 seconds |
| Started | Jul 12 04:40:34 PM PDT 24 |
| Finished | Jul 12 04:54:14 PM PDT 24 |
| Peak memory | 216348 kb |
| Host | smart-a9c4928c-8b27-41f4-b0f9-92e32a652a7e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560260550 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.560260550 |
| Directory | /workspace/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.uart_tx_ovrd.3754178195 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1171798896 ps |
| CPU time | 1.92 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:40:47 PM PDT 24 |
| Peak memory | 200048 kb |
| Host | smart-f728f3b2-65d7-474f-90c9-d92a84f2a756 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754178195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3754178195 |
| Directory | /workspace/47.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/47.uart_tx_rx.488512007 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 39348660631 ps |
| CPU time | 38.07 seconds |
| Started | Jul 12 04:40:38 PM PDT 24 |
| Finished | Jul 12 04:41:19 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-a84a0e85-816f-4428-a739-b35bf005cce0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488512007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.488512007 |
| Directory | /workspace/47.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/48.uart_alert_test.3595977881 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 13515592 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:40:33 PM PDT 24 |
| Finished | Jul 12 04:40:35 PM PDT 24 |
| Peak memory | 195200 kb |
| Host | smart-5e062e9e-11e0-4757-b18e-8465a8390b5b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595977881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3595977881 |
| Directory | /workspace/48.uart_alert_test/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_full.3622062888 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 69341213939 ps |
| CPU time | 92.84 seconds |
| Started | Jul 12 04:40:41 PM PDT 24 |
| Finished | Jul 12 04:42:16 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-bf194de5-7e05-4df0-a44f-3528383dfaa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622062888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3622062888 |
| Directory | /workspace/48.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_overflow.975962822 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 240918899248 ps |
| CPU time | 175.57 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:43:35 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-1fd2e275-7ffd-4ee1-8608-19af31dbf69a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975962822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.975962822 |
| Directory | /workspace/48.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_reset.1379459689 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 127640130825 ps |
| CPU time | 100.99 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:42:20 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-35e635af-d8a9-4615-9cb8-0cda89cdd7d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379459689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1379459689 |
| Directory | /workspace/48.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/48.uart_intr.3254899596 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 147466468724 ps |
| CPU time | 42.24 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:41:21 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-fe8d342c-6883-4a0f-947c-25a764b9efe9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254899596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3254899596 |
| Directory | /workspace/48.uart_intr/latest |
| Test location | /workspace/coverage/default/48.uart_long_xfer_wo_dly.1902123209 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 32323427998 ps |
| CPU time | 101.39 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:42:20 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-20246ed5-3505-404a-8906-3986299f9159 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1902123209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1902123209 |
| Directory | /workspace/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/48.uart_loopback.589481080 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 11882821907 ps |
| CPU time | 8.75 seconds |
| Started | Jul 12 04:40:33 PM PDT 24 |
| Finished | Jul 12 04:40:42 PM PDT 24 |
| Peak memory | 199496 kb |
| Host | smart-c36a7486-05d4-4ef3-9e76-f96598298395 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589481080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.589481080 |
| Directory | /workspace/48.uart_loopback/latest |
| Test location | /workspace/coverage/default/48.uart_noise_filter.3685570678 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 11145945535 ps |
| CPU time | 18.34 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:40:59 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-bc2eadad-bd18-48c2-b908-2112ef43c86a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685570678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3685570678 |
| Directory | /workspace/48.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/48.uart_perf.2381222003 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 11441382218 ps |
| CPU time | 691.56 seconds |
| Started | Jul 12 04:40:32 PM PDT 24 |
| Finished | Jul 12 04:52:04 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-17346794-c76d-4af0-9c1f-cf0b46865fa6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2381222003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2381222003 |
| Directory | /workspace/48.uart_perf/latest |
| Test location | /workspace/coverage/default/48.uart_rx_oversample.2579300606 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3169822731 ps |
| CPU time | 4.79 seconds |
| Started | Jul 12 04:40:34 PM PDT 24 |
| Finished | Jul 12 04:40:40 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-3d916f23-bea0-4af3-b298-e91cf00f68d1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2579300606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2579300606 |
| Directory | /workspace/48.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/48.uart_rx_parity_err.535707036 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 37806084977 ps |
| CPU time | 41.77 seconds |
| Started | Jul 12 04:40:33 PM PDT 24 |
| Finished | Jul 12 04:41:16 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-3b7485aa-9821-41b0-8e7d-d616fbbf308e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535707036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.535707036 |
| Directory | /workspace/48.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/48.uart_rx_start_bit_filter.1707390073 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 687730645 ps |
| CPU time | 0.92 seconds |
| Started | Jul 12 04:40:32 PM PDT 24 |
| Finished | Jul 12 04:40:34 PM PDT 24 |
| Peak memory | 195256 kb |
| Host | smart-acc38def-c5e7-4791-b765-68d53179caf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707390073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1707390073 |
| Directory | /workspace/48.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/48.uart_smoke.1322454623 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 5552120729 ps |
| CPU time | 22.44 seconds |
| Started | Jul 12 04:40:33 PM PDT 24 |
| Finished | Jul 12 04:40:57 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-c3a903b1-65d5-4d66-8897-6df20b54e968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322454623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1322454623 |
| Directory | /workspace/48.uart_smoke/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all.1380375873 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 322978681828 ps |
| CPU time | 270.14 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:45:11 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-26e9d1a0-dc7e-4a89-bb72-50b8072adf17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380375873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1380375873 |
| Directory | /workspace/48.uart_stress_all/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2633302 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 139263352873 ps |
| CPU time | 1255.13 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 05:01:34 PM PDT 24 |
| Peak memory | 224748 kb |
| Host | smart-fd253915-a5e3-449b-b2e7-b853a0f419d6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2633302 |
| Directory | /workspace/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.uart_tx_ovrd.3986050563 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 1339206921 ps |
| CPU time | 2.66 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:40:41 PM PDT 24 |
| Peak memory | 199624 kb |
| Host | smart-0345a02e-074a-406e-a4bb-e94407ce0d4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986050563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3986050563 |
| Directory | /workspace/48.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/48.uart_tx_rx.1758153758 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 12406467525 ps |
| CPU time | 22.96 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:41:02 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-9fa24bf8-2eab-4d81-b284-c6e3fd9c2822 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758153758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1758153758 |
| Directory | /workspace/48.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/49.uart_alert_test.2413911868 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 35623112 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:40:39 PM PDT 24 |
| Peak memory | 195220 kb |
| Host | smart-62d9ea1a-00f1-404e-8865-263092b549cb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413911868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2413911868 |
| Directory | /workspace/49.uart_alert_test/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_full.4151179247 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 59760460617 ps |
| CPU time | 85.24 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-5782101d-4a13-4c4c-afb2-60ec4d0a683a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4151179247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4151179247 |
| Directory | /workspace/49.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_overflow.3915241907 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 18685158700 ps |
| CPU time | 32.71 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:41:13 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-a8d19ea5-2a4d-46ea-877f-4ac335839ba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915241907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3915241907 |
| Directory | /workspace/49.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_reset.696555238 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 48090004565 ps |
| CPU time | 24.1 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:41:04 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-c2fe23f9-6e2d-4519-ac43-900983587358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696555238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.696555238 |
| Directory | /workspace/49.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/49.uart_intr.918165273 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 261166021456 ps |
| CPU time | 201.97 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:44:01 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-f69f5a21-865a-4ced-8a21-a25b71fd5045 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918165273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.918165273 |
| Directory | /workspace/49.uart_intr/latest |
| Test location | /workspace/coverage/default/49.uart_long_xfer_wo_dly.3405575856 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 98514549422 ps |
| CPU time | 746.78 seconds |
| Started | Jul 12 04:40:39 PM PDT 24 |
| Finished | Jul 12 04:53:08 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-4f52fc8a-2fec-4db4-95d5-00e3944fcb8c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3405575856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3405575856 |
| Directory | /workspace/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/49.uart_loopback.1624006614 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 11354938965 ps |
| CPU time | 5.43 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:40:43 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-1f9ed99f-7e7b-48ec-a460-615c17bd96fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624006614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1624006614 |
| Directory | /workspace/49.uart_loopback/latest |
| Test location | /workspace/coverage/default/49.uart_noise_filter.2039123238 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 68403800186 ps |
| CPU time | 31.98 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:41:11 PM PDT 24 |
| Peak memory | 198772 kb |
| Host | smart-3a53d61c-492f-4f7b-bd74-1b1f30036685 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039123238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2039123238 |
| Directory | /workspace/49.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/49.uart_perf.44605591 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 6995463790 ps |
| CPU time | 183.38 seconds |
| Started | Jul 12 04:40:45 PM PDT 24 |
| Finished | Jul 12 04:43:49 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-d6fdff87-f0d1-41f5-bfc5-e0dab838f707 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=44605591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.44605591 |
| Directory | /workspace/49.uart_perf/latest |
| Test location | /workspace/coverage/default/49.uart_rx_oversample.670162739 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2244875547 ps |
| CPU time | 3.53 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:40:43 PM PDT 24 |
| Peak memory | 198004 kb |
| Host | smart-978d01d8-43e2-455b-ac0d-9026d0fbbcb2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=670162739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.670162739 |
| Directory | /workspace/49.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/49.uart_rx_parity_err.4096733897 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 17622918519 ps |
| CPU time | 27.46 seconds |
| Started | Jul 12 04:40:49 PM PDT 24 |
| Finished | Jul 12 04:41:18 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-e1c9fa2f-e48a-48f5-8cbf-f07ebd3e7c41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096733897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.4096733897 |
| Directory | /workspace/49.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/49.uart_rx_start_bit_filter.186879789 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3642290919 ps |
| CPU time | 5.62 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:40:42 PM PDT 24 |
| Peak memory | 196116 kb |
| Host | smart-488df51b-2d1c-4cff-85ea-adbb87bc2f83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186879789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.186879789 |
| Directory | /workspace/49.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/49.uart_smoke.2969332894 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 428515368 ps |
| CPU time | 2.09 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:40:42 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-1c4f6035-32a8-4e36-9466-a423c60babcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969332894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2969332894 |
| Directory | /workspace/49.uart_smoke/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all.2020198826 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 200220794586 ps |
| CPU time | 330.53 seconds |
| Started | Jul 12 04:40:35 PM PDT 24 |
| Finished | Jul 12 04:46:09 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-a489dda7-22ae-49a3-9fcf-209c421737b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020198826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2020198826 |
| Directory | /workspace/49.uart_stress_all/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3600836095 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 48036322475 ps |
| CPU time | 378.48 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:46:59 PM PDT 24 |
| Peak memory | 208240 kb |
| Host | smart-a6caa3b5-5954-4955-889d-39742087572c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600836095 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3600836095 |
| Directory | /workspace/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.uart_tx_ovrd.1242494773 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1492446339 ps |
| CPU time | 1.59 seconds |
| Started | Jul 12 04:49:42 PM PDT 24 |
| Finished | Jul 12 04:49:45 PM PDT 24 |
| Peak memory | 197868 kb |
| Host | smart-a1da1e19-f0b1-4f7d-abb3-654458abbaf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242494773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1242494773 |
| Directory | /workspace/49.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/49.uart_tx_rx.1171644294 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 38273953690 ps |
| CPU time | 17.68 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:40:58 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-1204ce32-387a-4d93-b964-7567fe933536 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171644294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1171644294 |
| Directory | /workspace/49.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/5.uart_alert_test.2269323412 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 36775368 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:38:48 PM PDT 24 |
| Finished | Jul 12 04:38:54 PM PDT 24 |
| Peak memory | 195192 kb |
| Host | smart-09005aa4-e20a-4961-a433-1cb6e4f050ee |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269323412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2269323412 |
| Directory | /workspace/5.uart_alert_test/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_full.650514168 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 28984689232 ps |
| CPU time | 55.67 seconds |
| Started | Jul 12 04:38:50 PM PDT 24 |
| Finished | Jul 12 04:39:51 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-338daaf5-9f7c-4172-9eb5-159e8ea0a392 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650514168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.650514168 |
| Directory | /workspace/5.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_overflow.2365727102 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 75872644537 ps |
| CPU time | 40.87 seconds |
| Started | Jul 12 04:38:37 PM PDT 24 |
| Finished | Jul 12 04:39:24 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-14d76b16-cc1f-455e-bbd6-7d8bfdcef481 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365727102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2365727102 |
| Directory | /workspace/5.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/5.uart_intr.1534620710 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 60416021580 ps |
| CPU time | 55.6 seconds |
| Started | Jul 12 04:38:37 PM PDT 24 |
| Finished | Jul 12 04:39:39 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-15fdf608-41fb-48e1-9e34-7d818a70da9e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534620710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1534620710 |
| Directory | /workspace/5.uart_intr/latest |
| Test location | /workspace/coverage/default/5.uart_long_xfer_wo_dly.1021743039 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 86819379880 ps |
| CPU time | 675.63 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:49:57 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-98dd2a1c-9ecb-4359-8ffd-161fb315eb4f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1021743039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1021743039 |
| Directory | /workspace/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/5.uart_loopback.4052314665 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 7386169496 ps |
| CPU time | 4.34 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:38:46 PM PDT 24 |
| Peak memory | 199208 kb |
| Host | smart-9cd5b918-a824-4d37-b664-0cb287d7607a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052314665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4052314665 |
| Directory | /workspace/5.uart_loopback/latest |
| Test location | /workspace/coverage/default/5.uart_noise_filter.2241962051 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 40718411648 ps |
| CPU time | 64.44 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:39:56 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-f1a04927-9472-4cb1-8ce0-d9976f2b7574 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241962051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2241962051 |
| Directory | /workspace/5.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/5.uart_perf.3139763524 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 14965989144 ps |
| CPU time | 402.04 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:45:35 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-f3691616-52ef-4a9c-9ae2-dbc1ed965d38 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3139763524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3139763524 |
| Directory | /workspace/5.uart_perf/latest |
| Test location | /workspace/coverage/default/5.uart_rx_oversample.1005573245 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3061037257 ps |
| CPU time | 19.08 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:39:11 PM PDT 24 |
| Peak memory | 198252 kb |
| Host | smart-302beace-d4b0-44ad-a111-9281b51157d7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1005573245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1005573245 |
| Directory | /workspace/5.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/5.uart_rx_parity_err.1140513481 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 202774132204 ps |
| CPU time | 131.77 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:40:54 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-20eaa343-595b-48a8-b1ea-5687ec2bc841 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140513481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1140513481 |
| Directory | /workspace/5.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/5.uart_rx_start_bit_filter.2259586923 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 3013656130 ps |
| CPU time | 1.82 seconds |
| Started | Jul 12 04:38:43 PM PDT 24 |
| Finished | Jul 12 04:38:49 PM PDT 24 |
| Peak memory | 196304 kb |
| Host | smart-0a39f672-9af3-407f-8852-508e2e1bae4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259586923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2259586923 |
| Directory | /workspace/5.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/5.uart_smoke.1258429733 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 653990008 ps |
| CPU time | 2.08 seconds |
| Started | Jul 12 04:38:35 PM PDT 24 |
| Finished | Jul 12 04:38:43 PM PDT 24 |
| Peak memory | 198804 kb |
| Host | smart-84946d70-7972-4d6c-9d4e-d4be64074ddf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258429733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1258429733 |
| Directory | /workspace/5.uart_smoke/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all.3028533687 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 515557202622 ps |
| CPU time | 2100.11 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 05:13:47 PM PDT 24 |
| Peak memory | 208280 kb |
| Host | smart-b41600d6-e667-47ba-9cf5-1fdc3b6f8dba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028533687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3028533687 |
| Directory | /workspace/5.uart_stress_all/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all_with_rand_reset.4112014909 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 34550704320 ps |
| CPU time | 411.86 seconds |
| Started | Jul 12 04:38:40 PM PDT 24 |
| Finished | Jul 12 04:45:37 PM PDT 24 |
| Peak memory | 216364 kb |
| Host | smart-c3cfc7d1-5c00-4836-8650-1a4fbf2de1c8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112014909 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.4112014909 |
| Directory | /workspace/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.uart_tx_ovrd.3681980370 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 555816310 ps |
| CPU time | 1.37 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:38:54 PM PDT 24 |
| Peak memory | 198116 kb |
| Host | smart-828bb0dc-88dc-45a4-8e63-cc9d40c1e9e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681980370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3681980370 |
| Directory | /workspace/5.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/5.uart_tx_rx.1071431657 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 156568034679 ps |
| CPU time | 77.73 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:40:00 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-f6df59be-3bc7-45ae-8c70-88f42b2007ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071431657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1071431657 |
| Directory | /workspace/5.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/50.uart_fifo_reset.2384039052 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 25519034262 ps |
| CPU time | 16.38 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:40:56 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-08bf1ff9-eb12-4776-b1a6-22b28bf46233 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384039052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2384039052 |
| Directory | /workspace/50.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1909719498 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 52186016099 ps |
| CPU time | 293.2 seconds |
| Started | Jul 12 04:40:34 PM PDT 24 |
| Finished | Jul 12 04:45:29 PM PDT 24 |
| Peak memory | 215772 kb |
| Host | smart-e06663c7-10d9-43a5-9cef-c500380d9315 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909719498 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1909719498 |
| Directory | /workspace/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/51.uart_fifo_reset.1535346498 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 19134876176 ps |
| CPU time | 18.38 seconds |
| Started | Jul 12 04:40:38 PM PDT 24 |
| Finished | Jul 12 04:40:59 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-d2827a0d-e191-41e4-9cd4-9d74ebe5b31f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535346498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1535346498 |
| Directory | /workspace/51.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/51.uart_stress_all_with_rand_reset.507452457 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 61450634140 ps |
| CPU time | 671.94 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:51:53 PM PDT 24 |
| Peak memory | 216292 kb |
| Host | smart-3a0c2dd4-0836-49f1-b379-d590e281cd0d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507452457 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.507452457 |
| Directory | /workspace/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/52.uart_fifo_reset.885281663 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 69812871073 ps |
| CPU time | 106.63 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:42:27 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-f6f2e47f-204b-4e31-87f1-7997f03ca942 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885281663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.885281663 |
| Directory | /workspace/52.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/53.uart_fifo_reset.688786693 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 135250025185 ps |
| CPU time | 53.49 seconds |
| Started | Jul 12 04:40:50 PM PDT 24 |
| Finished | Jul 12 04:41:45 PM PDT 24 |
| Peak memory | 199352 kb |
| Host | smart-89e06a46-cf8f-4231-89fc-e10ede33dc1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688786693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.688786693 |
| Directory | /workspace/53.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1770006461 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 53776884491 ps |
| CPU time | 647.21 seconds |
| Started | Jul 12 04:40:36 PM PDT 24 |
| Finished | Jul 12 04:51:26 PM PDT 24 |
| Peak memory | 224704 kb |
| Host | smart-52fff197-c0ae-40da-a016-706d7755ed2c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770006461 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1770006461 |
| Directory | /workspace/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/54.uart_fifo_reset.1473192052 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 187017241844 ps |
| CPU time | 36.15 seconds |
| Started | Jul 12 04:40:40 PM PDT 24 |
| Finished | Jul 12 04:41:18 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-d604308c-2a20-4797-aaf5-d9bed9e6e21d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473192052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1473192052 |
| Directory | /workspace/54.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/54.uart_stress_all_with_rand_reset.4122152496 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 351067387996 ps |
| CPU time | 351.35 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:46:44 PM PDT 24 |
| Peak memory | 224844 kb |
| Host | smart-c39aaeaf-5b89-4556-9832-478374577d99 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122152496 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.4122152496 |
| Directory | /workspace/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/55.uart_fifo_reset.2099817521 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 5136065335 ps |
| CPU time | 9 seconds |
| Started | Jul 12 04:40:37 PM PDT 24 |
| Finished | Jul 12 04:40:49 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-0fc99071-78d7-456c-9eaa-836ff2bc4919 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099817521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2099817521 |
| Directory | /workspace/55.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/55.uart_stress_all_with_rand_reset.570598815 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 134070918004 ps |
| CPU time | 286.49 seconds |
| Started | Jul 12 04:40:42 PM PDT 24 |
| Finished | Jul 12 04:45:31 PM PDT 24 |
| Peak memory | 216632 kb |
| Host | smart-4da1597f-ac6b-4049-9d88-50e80917c088 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570598815 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.570598815 |
| Directory | /workspace/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/56.uart_stress_all_with_rand_reset.601540131 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 96757456237 ps |
| CPU time | 284.27 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:45:37 PM PDT 24 |
| Peak memory | 216828 kb |
| Host | smart-666bbc1d-43f1-41b1-a0c3-c355c498a835 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601540131 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.601540131 |
| Directory | /workspace/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/57.uart_fifo_reset.1005883759 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 5662113096 ps |
| CPU time | 8.97 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:41:05 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-5900fabb-3525-4289-bf17-a47d5bae4176 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005883759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1005883759 |
| Directory | /workspace/57.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2563428658 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 49378409783 ps |
| CPU time | 496.86 seconds |
| Started | Jul 12 04:40:41 PM PDT 24 |
| Finished | Jul 12 04:48:59 PM PDT 24 |
| Peak memory | 224712 kb |
| Host | smart-e4395e14-2c77-4678-8f22-923d440166ab |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563428658 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2563428658 |
| Directory | /workspace/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/58.uart_fifo_reset.679432040 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 34580519461 ps |
| CPU time | 12.94 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:40:58 PM PDT 24 |
| Peak memory | 199556 kb |
| Host | smart-792fbb05-78fa-4207-9a72-dcc3fbcfa8e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679432040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.679432040 |
| Directory | /workspace/58.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2877218175 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 69999067603 ps |
| CPU time | 252.03 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:45:04 PM PDT 24 |
| Peak memory | 216404 kb |
| Host | smart-c6ff1597-8da8-47c3-a7ca-e039740e4130 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877218175 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2877218175 |
| Directory | /workspace/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/59.uart_fifo_reset.3003346157 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 54754946577 ps |
| CPU time | 79.2 seconds |
| Started | Jul 12 04:40:43 PM PDT 24 |
| Finished | Jul 12 04:42:04 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-61e672af-56cb-4ab5-bd77-40e21205ac4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003346157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3003346157 |
| Directory | /workspace/59.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1449923641 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 44266867753 ps |
| CPU time | 120.92 seconds |
| Started | Jul 12 04:40:42 PM PDT 24 |
| Finished | Jul 12 04:42:45 PM PDT 24 |
| Peak memory | 216328 kb |
| Host | smart-64e99b0e-6689-439b-8614-dff8ec494ff3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449923641 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1449923641 |
| Directory | /workspace/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_alert_test.27820845 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 35399271 ps |
| CPU time | 0.56 seconds |
| Started | Jul 12 04:38:54 PM PDT 24 |
| Finished | Jul 12 04:38:59 PM PDT 24 |
| Peak memory | 194672 kb |
| Host | smart-40359176-d896-45a7-bb6b-3709495a5c39 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27820845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.27820845 |
| Directory | /workspace/6.uart_alert_test/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_full.2933191103 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 161177698930 ps |
| CPU time | 133.96 seconds |
| Started | Jul 12 04:38:49 PM PDT 24 |
| Finished | Jul 12 04:41:08 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-9d835cc9-a9aa-4348-884e-c67f452d18d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933191103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2933191103 |
| Directory | /workspace/6.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_overflow.2633425683 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 54528103469 ps |
| CPU time | 133.51 seconds |
| Started | Jul 12 04:38:38 PM PDT 24 |
| Finished | Jul 12 04:40:57 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-ce53e3f0-df67-4ecc-ab40-f606f8672fe8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2633425683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2633425683 |
| Directory | /workspace/6.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_reset.3531910586 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 64217176232 ps |
| CPU time | 49.15 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:40:00 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-ae642536-b7e9-4725-8d5d-605cb3743064 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531910586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3531910586 |
| Directory | /workspace/6.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/6.uart_intr.1335727172 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 25971957416 ps |
| CPU time | 6.11 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:27 PM PDT 24 |
| Peak memory | 199516 kb |
| Host | smart-c41a0402-3356-4b2b-8f4e-326b9d9bda67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335727172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1335727172 |
| Directory | /workspace/6.uart_intr/latest |
| Test location | /workspace/coverage/default/6.uart_long_xfer_wo_dly.2057701163 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 82379392810 ps |
| CPU time | 229.12 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:42:35 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-63142fa7-b8c8-40df-9f06-b644da9bc58c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2057701163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2057701163 |
| Directory | /workspace/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/6.uart_loopback.4293026595 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2751435372 ps |
| CPU time | 3.01 seconds |
| Started | Jul 12 04:38:53 PM PDT 24 |
| Finished | Jul 12 04:39:01 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-cfbba96f-c381-4d0d-8b28-c300d162ec5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293026595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.4293026595 |
| Directory | /workspace/6.uart_loopback/latest |
| Test location | /workspace/coverage/default/6.uart_noise_filter.3658688796 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 139145869637 ps |
| CPU time | 58.04 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:40:12 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-4e5320fd-aaf1-4f8d-9573-3abb029639b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658688796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3658688796 |
| Directory | /workspace/6.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/6.uart_perf.3819031456 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 19191863453 ps |
| CPU time | 666.21 seconds |
| Started | Jul 12 04:38:57 PM PDT 24 |
| Finished | Jul 12 04:50:08 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-c96244dc-1fcd-41ba-9e39-d7761101c0c7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3819031456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3819031456 |
| Directory | /workspace/6.uart_perf/latest |
| Test location | /workspace/coverage/default/6.uart_rx_oversample.3835714704 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1879821687 ps |
| CPU time | 6.59 seconds |
| Started | Jul 12 04:38:50 PM PDT 24 |
| Finished | Jul 12 04:39:02 PM PDT 24 |
| Peak memory | 198892 kb |
| Host | smart-f8fe51c0-ef5f-47a6-b8df-20bd4e3d4e9b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3835714704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3835714704 |
| Directory | /workspace/6.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/6.uart_rx_parity_err.3595090672 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 83191222405 ps |
| CPU time | 40.26 seconds |
| Started | Jul 12 04:38:55 PM PDT 24 |
| Finished | Jul 12 04:39:40 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-078c2abe-4da0-43ef-b3b0-82f778d718bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595090672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3595090672 |
| Directory | /workspace/6.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/6.uart_rx_start_bit_filter.1418067584 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1942728476 ps |
| CPU time | 1.37 seconds |
| Started | Jul 12 04:38:38 PM PDT 24 |
| Finished | Jul 12 04:38:45 PM PDT 24 |
| Peak memory | 195404 kb |
| Host | smart-16d9bc97-b6ff-4f60-8358-ce1d3c89dcaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418067584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1418067584 |
| Directory | /workspace/6.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/6.uart_smoke.2880160054 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 5858322752 ps |
| CPU time | 16.19 seconds |
| Started | Jul 12 04:38:50 PM PDT 24 |
| Finished | Jul 12 04:39:12 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-388f67a9-4705-4aa7-8273-41d2e25bd8b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880160054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2880160054 |
| Directory | /workspace/6.uart_smoke/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all.3831984160 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 127478983321 ps |
| CPU time | 457.93 seconds |
| Started | Jul 12 04:38:49 PM PDT 24 |
| Finished | Jul 12 04:46:33 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-ef6b208b-7629-4a16-8031-e00fc950a9ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831984160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3831984160 |
| Directory | /workspace/6.uart_stress_all/latest |
| Test location | /workspace/coverage/default/6.uart_tx_ovrd.110395579 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 8313282871 ps |
| CPU time | 10.04 seconds |
| Started | Jul 12 04:38:51 PM PDT 24 |
| Finished | Jul 12 04:39:07 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-21dc1b27-9f0c-4b78-8c55-f811ef5f43ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110395579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.110395579 |
| Directory | /workspace/6.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/6.uart_tx_rx.3750846912 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 181616172214 ps |
| CPU time | 21.1 seconds |
| Started | Jul 12 04:38:42 PM PDT 24 |
| Finished | Jul 12 04:39:08 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-cf3d58f2-b246-489b-96ce-e363e505b04d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750846912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3750846912 |
| Directory | /workspace/6.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/60.uart_fifo_reset.3467610096 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 161090567210 ps |
| CPU time | 136.5 seconds |
| Started | Jul 12 04:40:52 PM PDT 24 |
| Finished | Jul 12 04:43:12 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-501212dc-aee4-497b-81c3-242adfaa1111 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467610096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3467610096 |
| Directory | /workspace/60.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3855318498 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 74060019309 ps |
| CPU time | 858.64 seconds |
| Started | Jul 12 04:40:39 PM PDT 24 |
| Finished | Jul 12 04:55:00 PM PDT 24 |
| Peak memory | 224788 kb |
| Host | smart-85e541a8-309a-4da6-b458-262113ec71bc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855318498 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3855318498 |
| Directory | /workspace/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/61.uart_fifo_reset.1729165837 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 32832078182 ps |
| CPU time | 15.41 seconds |
| Started | Jul 12 04:40:46 PM PDT 24 |
| Finished | Jul 12 04:41:02 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-6fce9f2e-efee-4a87-96e2-e1cb5f707c27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729165837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1729165837 |
| Directory | /workspace/61.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3307155375 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 841966451299 ps |
| CPU time | 1141.39 seconds |
| Started | Jul 12 04:40:45 PM PDT 24 |
| Finished | Jul 12 04:59:47 PM PDT 24 |
| Peak memory | 227692 kb |
| Host | smart-914a68ec-5bb9-418b-8fe5-b4aa6574c283 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307155375 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3307155375 |
| Directory | /workspace/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/62.uart_fifo_reset.1657072258 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 88282059964 ps |
| CPU time | 131.78 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:43:08 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-364860a5-9071-4ae7-b1c1-284982d32d8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657072258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1657072258 |
| Directory | /workspace/62.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1740375943 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 128117479018 ps |
| CPU time | 1015.7 seconds |
| Started | Jul 12 04:40:41 PM PDT 24 |
| Finished | Jul 12 04:57:38 PM PDT 24 |
| Peak memory | 217900 kb |
| Host | smart-80b99dcb-8182-4026-87fe-db91c3c429cc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740375943 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1740375943 |
| Directory | /workspace/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/63.uart_fifo_reset.470515665 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 102191109080 ps |
| CPU time | 45.72 seconds |
| Started | Jul 12 04:40:46 PM PDT 24 |
| Finished | Jul 12 04:41:33 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-3a829e48-abc6-4a1e-8fa6-e83085b108ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470515665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.470515665 |
| Directory | /workspace/63.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1196264192 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 83409333865 ps |
| CPU time | 943.06 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:56:29 PM PDT 24 |
| Peak memory | 216380 kb |
| Host | smart-5dff0da3-6084-4a61-8aef-c0172274099c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196264192 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1196264192 |
| Directory | /workspace/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/64.uart_fifo_reset.2340555070 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 86920628230 ps |
| CPU time | 108.47 seconds |
| Started | Jul 12 04:40:48 PM PDT 24 |
| Finished | Jul 12 04:42:38 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-3e63865e-33e1-4356-82b6-d7d30df65e42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340555070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2340555070 |
| Directory | /workspace/64.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1704209486 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 11044349556 ps |
| CPU time | 84.14 seconds |
| Started | Jul 12 04:40:45 PM PDT 24 |
| Finished | Jul 12 04:42:10 PM PDT 24 |
| Peak memory | 209460 kb |
| Host | smart-07bc5382-f024-44f8-8059-199f92b5ff95 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704209486 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1704209486 |
| Directory | /workspace/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/65.uart_fifo_reset.3735081348 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 108936331427 ps |
| CPU time | 56.94 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:41:42 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-61872c2b-2bed-402d-b87f-307356d9a023 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735081348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3735081348 |
| Directory | /workspace/65.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/65.uart_stress_all_with_rand_reset.248733820 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 138207792086 ps |
| CPU time | 350.86 seconds |
| Started | Jul 12 04:40:50 PM PDT 24 |
| Finished | Jul 12 04:46:41 PM PDT 24 |
| Peak memory | 215732 kb |
| Host | smart-9096d3b7-e218-4ab1-b8d8-378b1cb691dc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248733820 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.248733820 |
| Directory | /workspace/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/66.uart_fifo_reset.394135860 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 119778825116 ps |
| CPU time | 95.43 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:42:21 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-8c82f9df-cce2-4a27-8b42-d38facff546f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394135860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.394135860 |
| Directory | /workspace/66.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/66.uart_stress_all_with_rand_reset.45582520 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 31497228456 ps |
| CPU time | 236.28 seconds |
| Started | Jul 12 04:40:43 PM PDT 24 |
| Finished | Jul 12 04:44:41 PM PDT 24 |
| Peak memory | 216432 kb |
| Host | smart-ae8de1d5-ea13-4859-983d-5afb448a2b6c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45582520 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.45582520 |
| Directory | /workspace/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/67.uart_fifo_reset.2089538703 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 18279831004 ps |
| CPU time | 26.15 seconds |
| Started | Jul 12 04:40:49 PM PDT 24 |
| Finished | Jul 12 04:41:16 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-71651c36-da11-40f5-a3bc-e7d03f9245eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089538703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2089538703 |
| Directory | /workspace/67.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2736873138 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 25973451848 ps |
| CPU time | 205.81 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:44:11 PM PDT 24 |
| Peak memory | 216272 kb |
| Host | smart-03f0424c-fe91-40c3-aa03-40e5f1328826 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736873138 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2736873138 |
| Directory | /workspace/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/68.uart_fifo_reset.2582211099 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 101806022756 ps |
| CPU time | 45.55 seconds |
| Started | Jul 12 04:40:40 PM PDT 24 |
| Finished | Jul 12 04:41:27 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-2abbbe6c-c731-4429-8ecb-007f825c1381 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582211099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2582211099 |
| Directory | /workspace/68.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4153522679 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 137019222783 ps |
| CPU time | 414.14 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:47:52 PM PDT 24 |
| Peak memory | 216596 kb |
| Host | smart-613eff08-e2e7-4b47-a895-0b3edf33edea |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153522679 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4153522679 |
| Directory | /workspace/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/69.uart_fifo_reset.3418984682 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 52208350795 ps |
| CPU time | 38.77 seconds |
| Started | Jul 12 04:40:42 PM PDT 24 |
| Finished | Jul 12 04:41:23 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-9e1b585e-35bf-4ddc-aba2-43a100252173 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418984682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3418984682 |
| Directory | /workspace/69.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1191814246 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 37882350517 ps |
| CPU time | 213.07 seconds |
| Started | Jul 12 04:40:43 PM PDT 24 |
| Finished | Jul 12 04:44:18 PM PDT 24 |
| Peak memory | 215452 kb |
| Host | smart-05435817-282a-4c41-86f5-5e82af36d462 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191814246 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1191814246 |
| Directory | /workspace/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_alert_test.108876826 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 13382998 ps |
| CPU time | 0.57 seconds |
| Started | Jul 12 04:38:56 PM PDT 24 |
| Finished | Jul 12 04:39:01 PM PDT 24 |
| Peak memory | 194076 kb |
| Host | smart-bbc5349f-5fc5-4c23-b004-fdbae220593d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108876826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.108876826 |
| Directory | /workspace/7.uart_alert_test/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_full.583447370 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 44195910930 ps |
| CPU time | 20.35 seconds |
| Started | Jul 12 04:38:52 PM PDT 24 |
| Finished | Jul 12 04:39:18 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-29e75432-b7d5-45f8-b7ea-482845be76cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583447370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.583447370 |
| Directory | /workspace/7.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_overflow.638302040 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 141197593373 ps |
| CPU time | 241.57 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:42:48 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-38766a03-c9b1-47c7-9e46-817645c9a179 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638302040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.638302040 |
| Directory | /workspace/7.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_reset.1582468448 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 92908774212 ps |
| CPU time | 36.72 seconds |
| Started | Jul 12 04:38:59 PM PDT 24 |
| Finished | Jul 12 04:39:39 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-17c500f9-59c7-4da5-8018-ebe97dca996c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582468448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1582468448 |
| Directory | /workspace/7.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/7.uart_intr.2353370827 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 35798560454 ps |
| CPU time | 33.13 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:43 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-bf355172-7233-4f55-aa63-3c43beea4343 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353370827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2353370827 |
| Directory | /workspace/7.uart_intr/latest |
| Test location | /workspace/coverage/default/7.uart_long_xfer_wo_dly.918719762 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 178869444691 ps |
| CPU time | 305.71 seconds |
| Started | Jul 12 04:38:49 PM PDT 24 |
| Finished | Jul 12 04:44:00 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-a5eea430-1f89-4785-bb0c-0a871dce8917 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=918719762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.918719762 |
| Directory | /workspace/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/7.uart_loopback.879237625 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 7800153188 ps |
| CPU time | 8.74 seconds |
| Started | Jul 12 04:39:00 PM PDT 24 |
| Finished | Jul 12 04:39:12 PM PDT 24 |
| Peak memory | 199368 kb |
| Host | smart-17aef5d2-f4ee-4154-8fb9-5ce41efd2b66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879237625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.879237625 |
| Directory | /workspace/7.uart_loopback/latest |
| Test location | /workspace/coverage/default/7.uart_noise_filter.3252015035 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 75908275385 ps |
| CPU time | 61.34 seconds |
| Started | Jul 12 04:39:12 PM PDT 24 |
| Finished | Jul 12 04:40:21 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-26ef0dd3-a2a9-426f-b582-65d1d1d21fe9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252015035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3252015035 |
| Directory | /workspace/7.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/7.uart_perf.2289623742 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 16276028921 ps |
| CPU time | 101.12 seconds |
| Started | Jul 12 04:39:17 PM PDT 24 |
| Finished | Jul 12 04:41:04 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-770b7295-89d1-4600-8971-c3d56730fb0e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2289623742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2289623742 |
| Directory | /workspace/7.uart_perf/latest |
| Test location | /workspace/coverage/default/7.uart_rx_oversample.2835703338 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3830124776 ps |
| CPU time | 7.96 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:14 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-e03be56f-8f4b-43fd-a23d-ab7bfac86438 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2835703338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2835703338 |
| Directory | /workspace/7.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/7.uart_rx_parity_err.3968807439 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 32456810494 ps |
| CPU time | 21.9 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:32 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-6ce7c217-e8c4-4856-85cc-31f278a8837a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968807439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3968807439 |
| Directory | /workspace/7.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/7.uart_rx_start_bit_filter.3463100631 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4164383348 ps |
| CPU time | 2.54 seconds |
| Started | Jul 12 04:38:48 PM PDT 24 |
| Finished | Jul 12 04:38:56 PM PDT 24 |
| Peak memory | 196648 kb |
| Host | smart-e51b829e-d850-4434-a01e-e26c1721921f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3463100631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3463100631 |
| Directory | /workspace/7.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/7.uart_smoke.2060397259 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 457324041 ps |
| CPU time | 1.3 seconds |
| Started | Jul 12 04:38:49 PM PDT 24 |
| Finished | Jul 12 04:38:56 PM PDT 24 |
| Peak memory | 198360 kb |
| Host | smart-f325953c-2dd5-411f-9048-46ff56f268ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060397259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2060397259 |
| Directory | /workspace/7.uart_smoke/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all.1315984084 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 244373427072 ps |
| CPU time | 1188.18 seconds |
| Started | Jul 12 04:38:53 PM PDT 24 |
| Finished | Jul 12 04:58:46 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-563ff6ad-50ae-4415-8b83-f65ac7af3ab6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315984084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1315984084 |
| Directory | /workspace/7.uart_stress_all/latest |
| Test location | /workspace/coverage/default/7.uart_tx_ovrd.3231415206 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 691110206 ps |
| CPU time | 2.5 seconds |
| Started | Jul 12 04:38:58 PM PDT 24 |
| Finished | Jul 12 04:39:04 PM PDT 24 |
| Peak memory | 198704 kb |
| Host | smart-d1d8e322-c1d8-4c2d-bdcd-1ff824e0dd66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231415206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3231415206 |
| Directory | /workspace/7.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/7.uart_tx_rx.2400374840 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 103924035851 ps |
| CPU time | 98.91 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:40:53 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-11f532d8-838c-4289-8b71-0e82dbd915be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400374840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2400374840 |
| Directory | /workspace/7.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/70.uart_fifo_reset.133613089 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 171199848568 ps |
| CPU time | 11.91 seconds |
| Started | Jul 12 04:40:43 PM PDT 24 |
| Finished | Jul 12 04:40:57 PM PDT 24 |
| Peak memory | 198344 kb |
| Host | smart-a1e4486c-5d40-4569-b41d-23dea581c6ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133613089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.133613089 |
| Directory | /workspace/70.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1999455903 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 80130502605 ps |
| CPU time | 481.51 seconds |
| Started | Jul 12 04:40:45 PM PDT 24 |
| Finished | Jul 12 04:48:48 PM PDT 24 |
| Peak memory | 212396 kb |
| Host | smart-b5268e59-f3fc-4b0b-964f-011d317e3577 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999455903 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1999455903 |
| Directory | /workspace/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/71.uart_fifo_reset.2347001672 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 60632323684 ps |
| CPU time | 105.71 seconds |
| Started | Jul 12 04:40:40 PM PDT 24 |
| Finished | Jul 12 04:42:28 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-c5b13a39-1464-4d1b-b821-630dff5ce04f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347001672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2347001672 |
| Directory | /workspace/71.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/71.uart_stress_all_with_rand_reset.4053766756 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 27505204131 ps |
| CPU time | 745.6 seconds |
| Started | Jul 12 04:40:43 PM PDT 24 |
| Finished | Jul 12 04:53:10 PM PDT 24 |
| Peak memory | 216560 kb |
| Host | smart-667ec342-23dc-4950-944d-41ccfa05c7ca |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053766756 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.4053766756 |
| Directory | /workspace/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/72.uart_fifo_reset.1536111143 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 12082824724 ps |
| CPU time | 20.7 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:41:14 PM PDT 24 |
| Peak memory | 199688 kb |
| Host | smart-340f9016-029e-4633-b9a8-6533dae845d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536111143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1536111143 |
| Directory | /workspace/72.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1386585320 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 87223585075 ps |
| CPU time | 228.57 seconds |
| Started | Jul 12 04:40:48 PM PDT 24 |
| Finished | Jul 12 04:44:38 PM PDT 24 |
| Peak memory | 216580 kb |
| Host | smart-d5ee56d1-5d6a-4c9d-a6a0-e231ea04c95d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386585320 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1386585320 |
| Directory | /workspace/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/73.uart_fifo_reset.1467545649 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 30035644585 ps |
| CPU time | 23.45 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:41:09 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-b32f4fce-bceb-47ca-ad85-5b6342e49954 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467545649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1467545649 |
| Directory | /workspace/73.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/74.uart_fifo_reset.2377699560 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 137880805052 ps |
| CPU time | 19.93 seconds |
| Started | Jul 12 04:40:48 PM PDT 24 |
| Finished | Jul 12 04:41:09 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-60c8d3f6-104a-439c-a0c5-e9467f4d1776 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377699560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2377699560 |
| Directory | /workspace/74.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3322449968 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 53541583769 ps |
| CPU time | 545.85 seconds |
| Started | Jul 12 04:40:42 PM PDT 24 |
| Finished | Jul 12 04:49:50 PM PDT 24 |
| Peak memory | 216240 kb |
| Host | smart-d3c896fe-a66a-424a-b5a1-bda6bf664498 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322449968 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3322449968 |
| Directory | /workspace/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/75.uart_fifo_reset.284146313 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 97556387549 ps |
| CPU time | 145.79 seconds |
| Started | Jul 12 04:40:44 PM PDT 24 |
| Finished | Jul 12 04:43:12 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-3e0d8cd9-7a32-495a-8908-9e16651074fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284146313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.284146313 |
| Directory | /workspace/75.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2361178665 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 563275923990 ps |
| CPU time | 809.79 seconds |
| Started | Jul 12 04:40:48 PM PDT 24 |
| Finished | Jul 12 04:54:19 PM PDT 24 |
| Peak memory | 216420 kb |
| Host | smart-ebc4e249-a678-4a95-a829-c1dc9254f3d7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361178665 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2361178665 |
| Directory | /workspace/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/76.uart_fifo_reset.675802475 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 7698718342 ps |
| CPU time | 11.73 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:41:06 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-5b6a4fa1-fbc7-403d-a88d-06892f3cb4fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675802475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.675802475 |
| Directory | /workspace/76.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4274824505 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 37580146035 ps |
| CPU time | 138.75 seconds |
| Started | Jul 12 04:40:52 PM PDT 24 |
| Finished | Jul 12 04:43:14 PM PDT 24 |
| Peak memory | 215604 kb |
| Host | smart-a23fe791-5d58-4e89-9048-47666ddda72b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274824505 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4274824505 |
| Directory | /workspace/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/77.uart_fifo_reset.3289479422 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 224607925627 ps |
| CPU time | 169.85 seconds |
| Started | Jul 12 04:40:54 PM PDT 24 |
| Finished | Jul 12 04:43:49 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-73bd6a94-6bdc-4d90-897b-cc70731e4e90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3289479422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3289479422 |
| Directory | /workspace/77.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1744871132 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 75679392377 ps |
| CPU time | 366.95 seconds |
| Started | Jul 12 04:40:52 PM PDT 24 |
| Finished | Jul 12 04:47:02 PM PDT 24 |
| Peak memory | 215680 kb |
| Host | smart-d774b837-162a-418b-8de4-74936ebdc98c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744871132 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1744871132 |
| Directory | /workspace/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/78.uart_fifo_reset.1422577775 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 31098456658 ps |
| CPU time | 37.51 seconds |
| Started | Jul 12 04:40:57 PM PDT 24 |
| Finished | Jul 12 04:41:39 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-ad880cdd-2140-4ea1-a9e6-5bbb4b888969 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422577775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1422577775 |
| Directory | /workspace/78.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/79.uart_fifo_reset.1207053743 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 47813560997 ps |
| CPU time | 262.06 seconds |
| Started | Jul 12 04:40:50 PM PDT 24 |
| Finished | Jul 12 04:45:13 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-1ece49ed-68b6-4f02-b6a7-8021b5a0c577 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207053743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1207053743 |
| Directory | /workspace/79.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/79.uart_stress_all_with_rand_reset.654731129 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 49583364150 ps |
| CPU time | 422.56 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:48:01 PM PDT 24 |
| Peak memory | 208328 kb |
| Host | smart-43050daa-731f-490a-a623-82a60770f94c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654731129 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.654731129 |
| Directory | /workspace/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_alert_test.4027663949 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 31536658 ps |
| CPU time | 0.59 seconds |
| Started | Jul 12 04:38:40 PM PDT 24 |
| Finished | Jul 12 04:38:45 PM PDT 24 |
| Peak memory | 195372 kb |
| Host | smart-669b6347-5ae5-45f7-9310-7a8b452fdee8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027663949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4027663949 |
| Directory | /workspace/8.uart_alert_test/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_full.3483240938 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 195817579191 ps |
| CPU time | 50.39 seconds |
| Started | Jul 12 04:38:43 PM PDT 24 |
| Finished | Jul 12 04:39:38 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-8255e874-fa4b-46c5-925e-c844c0919b5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483240938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3483240938 |
| Directory | /workspace/8.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_overflow.1318667959 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 47435533072 ps |
| CPU time | 39.52 seconds |
| Started | Jul 12 04:38:57 PM PDT 24 |
| Finished | Jul 12 04:39:41 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-54a933fa-5e99-4591-a7ee-8f5b23d50b1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1318667959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1318667959 |
| Directory | /workspace/8.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_reset.4134257929 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 177378391019 ps |
| CPU time | 276.97 seconds |
| Started | Jul 12 04:38:36 PM PDT 24 |
| Finished | Jul 12 04:43:19 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-dac29746-9e94-445e-9902-995549b751ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134257929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.4134257929 |
| Directory | /workspace/8.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/8.uart_intr.2432364159 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 26040826105 ps |
| CPU time | 41.85 seconds |
| Started | Jul 12 04:38:41 PM PDT 24 |
| Finished | Jul 12 04:39:28 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-ab51efd6-0918-4f5b-881d-95ad7b5a9f4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432364159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2432364159 |
| Directory | /workspace/8.uart_intr/latest |
| Test location | /workspace/coverage/default/8.uart_long_xfer_wo_dly.1912295940 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 37969334416 ps |
| CPU time | 316.33 seconds |
| Started | Jul 12 04:38:51 PM PDT 24 |
| Finished | Jul 12 04:44:12 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-0446f657-e5d7-4834-89d8-fc921d374345 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1912295940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1912295940 |
| Directory | /workspace/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/8.uart_loopback.983471471 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2687862189 ps |
| CPU time | 5.24 seconds |
| Started | Jul 12 04:38:39 PM PDT 24 |
| Finished | Jul 12 04:38:50 PM PDT 24 |
| Peak memory | 197320 kb |
| Host | smart-f236b40b-4d91-44b8-880f-d54bc43571b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983471471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.983471471 |
| Directory | /workspace/8.uart_loopback/latest |
| Test location | /workspace/coverage/default/8.uart_noise_filter.1336227023 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 283272505 ps |
| CPU time | 0.9 seconds |
| Started | Jul 12 04:39:02 PM PDT 24 |
| Finished | Jul 12 04:39:07 PM PDT 24 |
| Peak memory | 194368 kb |
| Host | smart-830e9bef-b256-4cff-ac8e-5ac906073ba4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336227023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1336227023 |
| Directory | /workspace/8.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/8.uart_perf.1385411069 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 11945097581 ps |
| CPU time | 743.45 seconds |
| Started | Jul 12 04:38:47 PM PDT 24 |
| Finished | Jul 12 04:51:16 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-5afe8b38-5904-4d59-b8ff-4f817523810e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1385411069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1385411069 |
| Directory | /workspace/8.uart_perf/latest |
| Test location | /workspace/coverage/default/8.uart_rx_oversample.771109656 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 3775168202 ps |
| CPU time | 27.91 seconds |
| Started | Jul 12 04:38:40 PM PDT 24 |
| Finished | Jul 12 04:39:13 PM PDT 24 |
| Peak memory | 198808 kb |
| Host | smart-e481595d-45c3-48b7-a7b5-8b9fb1a25910 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=771109656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.771109656 |
| Directory | /workspace/8.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/8.uart_rx_parity_err.3574418833 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 52987964312 ps |
| CPU time | 19.92 seconds |
| Started | Jul 12 04:38:44 PM PDT 24 |
| Finished | Jul 12 04:39:09 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-e94c5830-630e-4ab9-923c-405c15799d8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574418833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3574418833 |
| Directory | /workspace/8.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/8.uart_rx_start_bit_filter.1467579759 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3327775766 ps |
| CPU time | 2.76 seconds |
| Started | Jul 12 04:38:58 PM PDT 24 |
| Finished | Jul 12 04:39:05 PM PDT 24 |
| Peak memory | 195860 kb |
| Host | smart-0d92da57-8ff1-4e05-aea5-6cb9e584f4a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467579759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1467579759 |
| Directory | /workspace/8.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/8.uart_smoke.2557194319 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 5295300202 ps |
| CPU time | 16.9 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:26 PM PDT 24 |
| Peak memory | 199336 kb |
| Host | smart-eb6ca1b2-8a5d-4b30-9e12-f18a3f9d5e57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557194319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2557194319 |
| Directory | /workspace/8.uart_smoke/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all.1071576804 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 175645061611 ps |
| CPU time | 296.55 seconds |
| Started | Jul 12 04:38:54 PM PDT 24 |
| Finished | Jul 12 04:43:56 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-53a26a93-13fb-4b56-8a74-14353c7b9a92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071576804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1071576804 |
| Directory | /workspace/8.uart_stress_all/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3377868462 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 61483510861 ps |
| CPU time | 137.63 seconds |
| Started | Jul 12 04:38:45 PM PDT 24 |
| Finished | Jul 12 04:41:08 PM PDT 24 |
| Peak memory | 208104 kb |
| Host | smart-0f1ff20d-e908-43e7-9d8e-defbc1afc25b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377868462 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3377868462 |
| Directory | /workspace/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_tx_ovrd.3145627719 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 1512065736 ps |
| CPU time | 1.84 seconds |
| Started | Jul 12 04:39:08 PM PDT 24 |
| Finished | Jul 12 04:39:18 PM PDT 24 |
| Peak memory | 199444 kb |
| Host | smart-2b7c3043-67ad-443e-baa8-6e0d8a5ce2aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145627719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3145627719 |
| Directory | /workspace/8.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/8.uart_tx_rx.454592778 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 99562106598 ps |
| CPU time | 179.35 seconds |
| Started | Jul 12 04:39:00 PM PDT 24 |
| Finished | Jul 12 04:42:03 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-38c41979-91e5-414a-88be-84d64f12b1d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454592778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.454592778 |
| Directory | /workspace/8.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/80.uart_fifo_reset.543611101 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 248851547216 ps |
| CPU time | 42.85 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:41:37 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-cb394a98-cae7-43de-9be2-f232cc9d5819 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543611101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.543611101 |
| Directory | /workspace/80.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3669202608 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 42664663140 ps |
| CPU time | 856.8 seconds |
| Started | Jul 12 04:40:52 PM PDT 24 |
| Finished | Jul 12 04:55:12 PM PDT 24 |
| Peak memory | 216412 kb |
| Host | smart-8a321583-8149-4d75-bb83-cbba83b05246 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669202608 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3669202608 |
| Directory | /workspace/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/81.uart_fifo_reset.3465395508 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 37928117132 ps |
| CPU time | 68.13 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:42:06 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-7b57eb09-685e-43d5-b6aa-efa3882e1468 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465395508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3465395508 |
| Directory | /workspace/81.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1425359063 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 24653719024 ps |
| CPU time | 262.45 seconds |
| Started | Jul 12 04:40:47 PM PDT 24 |
| Finished | Jul 12 04:45:11 PM PDT 24 |
| Peak memory | 215908 kb |
| Host | smart-28205cd9-e33a-4983-91b2-41fd89bd5699 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425359063 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1425359063 |
| Directory | /workspace/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/82.uart_fifo_reset.2357196026 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 54401682439 ps |
| CPU time | 18.64 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:41:11 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-3d6527f7-1441-4f43-b5e8-0ba1749846c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357196026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2357196026 |
| Directory | /workspace/82.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3668610044 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 39156476369 ps |
| CPU time | 518.49 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:49:36 PM PDT 24 |
| Peak memory | 216380 kb |
| Host | smart-daf0de5b-5fb7-41bf-b4ca-18988d9f71a9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668610044 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3668610044 |
| Directory | /workspace/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4261603170 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 400976915156 ps |
| CPU time | 747.54 seconds |
| Started | Jul 12 04:40:47 PM PDT 24 |
| Finished | Jul 12 04:53:16 PM PDT 24 |
| Peak memory | 224736 kb |
| Host | smart-47a20545-d582-4d61-b4be-efeca8689804 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261603170 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4261603170 |
| Directory | /workspace/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/84.uart_fifo_reset.11539249 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 12471085019 ps |
| CPU time | 10.76 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:41:07 PM PDT 24 |
| Peak memory | 199500 kb |
| Host | smart-41e35651-bdfa-4118-9d2f-6c696004877f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11539249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.11539249 |
| Directory | /workspace/84.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/84.uart_stress_all_with_rand_reset.122680386 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 53680347853 ps |
| CPU time | 297.46 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:45:55 PM PDT 24 |
| Peak memory | 208192 kb |
| Host | smart-7077d0a1-08f8-4396-9a71-e104f7c2b7db |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122680386 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.122680386 |
| Directory | /workspace/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/85.uart_fifo_reset.4287048183 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 19410640404 ps |
| CPU time | 16.88 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:41:11 PM PDT 24 |
| Peak memory | 199604 kb |
| Host | smart-e565dc85-24f5-4e17-b934-85fd88a0e109 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287048183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.4287048183 |
| Directory | /workspace/85.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/85.uart_stress_all_with_rand_reset.271643519 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 31761314291 ps |
| CPU time | 357.42 seconds |
| Started | Jul 12 04:40:55 PM PDT 24 |
| Finished | Jul 12 04:46:58 PM PDT 24 |
| Peak memory | 216412 kb |
| Host | smart-8311dcb7-cd68-4535-aaf6-820120ea5047 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271643519 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.271643519 |
| Directory | /workspace/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/86.uart_fifo_reset.3699585493 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 17172554870 ps |
| CPU time | 23.73 seconds |
| Started | Jul 12 04:40:49 PM PDT 24 |
| Finished | Jul 12 04:41:14 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-1aac9023-0b11-4dea-b585-e2c9c0b89524 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699585493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3699585493 |
| Directory | /workspace/86.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/87.uart_fifo_reset.4127954682 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 155131483607 ps |
| CPU time | 137.93 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:43:10 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-cfeeaa2e-606c-4ba9-b9f7-f7610a2d8de0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127954682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4127954682 |
| Directory | /workspace/87.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3793094469 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 191155494815 ps |
| CPU time | 435.43 seconds |
| Started | Jul 12 04:40:49 PM PDT 24 |
| Finished | Jul 12 04:48:06 PM PDT 24 |
| Peak memory | 215224 kb |
| Host | smart-deba1f3f-f9ce-4aca-ab08-2f42554ef594 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793094469 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3793094469 |
| Directory | /workspace/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/88.uart_fifo_reset.971891382 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 102056008551 ps |
| CPU time | 153.11 seconds |
| Started | Jul 12 04:40:48 PM PDT 24 |
| Finished | Jul 12 04:43:22 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-94c23224-13f6-476a-b95d-546794cb2aad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=971891382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.971891382 |
| Directory | /workspace/88.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/88.uart_stress_all_with_rand_reset.807006256 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 133458514167 ps |
| CPU time | 892 seconds |
| Started | Jul 12 04:40:52 PM PDT 24 |
| Finished | Jul 12 04:55:47 PM PDT 24 |
| Peak memory | 224816 kb |
| Host | smart-acf3e2dc-f280-444f-aab9-167454cee261 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807006256 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.807006256 |
| Directory | /workspace/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/89.uart_fifo_reset.2282055125 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 69587539811 ps |
| CPU time | 27.58 seconds |
| Started | Jul 12 04:40:48 PM PDT 24 |
| Finished | Jul 12 04:41:17 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-93668852-8a07-46eb-b8b9-7d6dbc76a223 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282055125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2282055125 |
| Directory | /workspace/89.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1597003198 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 133477453364 ps |
| CPU time | 764.2 seconds |
| Started | Jul 12 04:40:48 PM PDT 24 |
| Finished | Jul 12 04:53:33 PM PDT 24 |
| Peak memory | 216396 kb |
| Host | smart-386b87ee-ab2d-43da-a543-9b3f0bea36b0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597003198 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1597003198 |
| Directory | /workspace/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_alert_test.3257564169 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 19891633 ps |
| CPU time | 0.55 seconds |
| Started | Jul 12 04:38:45 PM PDT 24 |
| Finished | Jul 12 04:38:50 PM PDT 24 |
| Peak memory | 195120 kb |
| Host | smart-89c5254c-6309-4890-8248-0b7ab51026c4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257564169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3257564169 |
| Directory | /workspace/9.uart_alert_test/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_full.1671576906 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 113520324398 ps |
| CPU time | 41.95 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:39:53 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-6ab6d8b0-9da6-4412-b662-3dac25460792 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671576906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1671576906 |
| Directory | /workspace/9.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_overflow.3922208255 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 33272439226 ps |
| CPU time | 49.07 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:39:58 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-3702d43a-f471-47ef-962d-79bbc90eac7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922208255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3922208255 |
| Directory | /workspace/9.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_reset.1078905347 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 51726297652 ps |
| CPU time | 116.4 seconds |
| Started | Jul 12 04:39:04 PM PDT 24 |
| Finished | Jul 12 04:41:07 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-4f964974-38b4-49ee-bb26-044f9a13f0fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078905347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1078905347 |
| Directory | /workspace/9.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/9.uart_intr.2404584412 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 25905391204 ps |
| CPU time | 5.06 seconds |
| Started | Jul 12 04:39:07 PM PDT 24 |
| Finished | Jul 12 04:39:20 PM PDT 24 |
| Peak memory | 197552 kb |
| Host | smart-3e4660df-f476-4d65-8c3f-960e83f5ba15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404584412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2404584412 |
| Directory | /workspace/9.uart_intr/latest |
| Test location | /workspace/coverage/default/9.uart_long_xfer_wo_dly.797775125 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 68830381772 ps |
| CPU time | 117.22 seconds |
| Started | Jul 12 04:38:57 PM PDT 24 |
| Finished | Jul 12 04:40:58 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-7a44501d-dcf7-4a33-878c-7aed52339bac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=797775125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.797775125 |
| Directory | /workspace/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/9.uart_loopback.3842726468 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 9383077391 ps |
| CPU time | 11.48 seconds |
| Started | Jul 12 04:39:06 PM PDT 24 |
| Finished | Jul 12 04:39:25 PM PDT 24 |
| Peak memory | 199308 kb |
| Host | smart-5315ba35-fd3f-45c0-b3ee-0b9dfaec1f64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842726468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3842726468 |
| Directory | /workspace/9.uart_loopback/latest |
| Test location | /workspace/coverage/default/9.uart_noise_filter.1360401378 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 11733226574 ps |
| CPU time | 7.79 seconds |
| Started | Jul 12 04:38:49 PM PDT 24 |
| Finished | Jul 12 04:39:02 PM PDT 24 |
| Peak memory | 198232 kb |
| Host | smart-e89624f6-fd3a-4d06-bdab-246eb8544eef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360401378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1360401378 |
| Directory | /workspace/9.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/9.uart_perf.439402865 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 17638688544 ps |
| CPU time | 536.19 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:48:06 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-23f22f7e-e975-4e40-99b8-b13b3610f7e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=439402865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.439402865 |
| Directory | /workspace/9.uart_perf/latest |
| Test location | /workspace/coverage/default/9.uart_rx_oversample.4143159665 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4122021008 ps |
| CPU time | 12.24 seconds |
| Started | Jul 12 04:39:11 PM PDT 24 |
| Finished | Jul 12 04:39:31 PM PDT 24 |
| Peak memory | 198824 kb |
| Host | smart-af014ada-8579-45c3-b9f8-f0c294c3e595 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4143159665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4143159665 |
| Directory | /workspace/9.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/9.uart_rx_parity_err.338877071 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 58317442069 ps |
| CPU time | 41.54 seconds |
| Started | Jul 12 04:38:46 PM PDT 24 |
| Finished | Jul 12 04:39:32 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-993d4f91-47ec-4bf2-a8fe-ca6623a47fcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338877071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.338877071 |
| Directory | /workspace/9.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/9.uart_rx_start_bit_filter.2826893029 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 1771030082 ps |
| CPU time | 1.4 seconds |
| Started | Jul 12 04:38:50 PM PDT 24 |
| Finished | Jul 12 04:38:57 PM PDT 24 |
| Peak memory | 195224 kb |
| Host | smart-4a50b38a-88a4-46ae-b36a-73655da8532f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826893029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2826893029 |
| Directory | /workspace/9.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/9.uart_smoke.1222306934 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 515232330 ps |
| CPU time | 2.08 seconds |
| Started | Jul 12 04:38:52 PM PDT 24 |
| Finished | Jul 12 04:38:59 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-8298cd20-6cc0-42dc-b7fe-b14197ed04f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222306934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1222306934 |
| Directory | /workspace/9.uart_smoke/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all.1632649885 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 136323197751 ps |
| CPU time | 193.26 seconds |
| Started | Jul 12 04:39:03 PM PDT 24 |
| Finished | Jul 12 04:42:29 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-24f3e343-af65-4068-988b-6c5ea340494c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632649885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1632649885 |
| Directory | /workspace/9.uart_stress_all/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3936478656 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 203044315676 ps |
| CPU time | 988.87 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:55:34 PM PDT 24 |
| Peak memory | 216408 kb |
| Host | smart-2a616ab5-1906-42b8-9b9a-b0de625a7286 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936478656 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3936478656 |
| Directory | /workspace/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_tx_ovrd.2944031631 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 672073333 ps |
| CPU time | 2.47 seconds |
| Started | Jul 12 04:38:58 PM PDT 24 |
| Finished | Jul 12 04:39:04 PM PDT 24 |
| Peak memory | 198564 kb |
| Host | smart-58e7e711-c8f3-489a-b285-99167cb9d50a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944031631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2944031631 |
| Directory | /workspace/9.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/9.uart_tx_rx.562066134 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 38811136350 ps |
| CPU time | 38.07 seconds |
| Started | Jul 12 04:39:01 PM PDT 24 |
| Finished | Jul 12 04:39:42 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-267dd19b-6a3e-47a6-9d05-ebc84e851540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562066134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.562066134 |
| Directory | /workspace/9.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/90.uart_fifo_reset.730415867 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 45341105366 ps |
| CPU time | 79.99 seconds |
| Started | Jul 12 04:40:57 PM PDT 24 |
| Finished | Jul 12 04:42:21 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-8def53f4-49ce-469b-bb50-f9147fc7be38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730415867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.730415867 |
| Directory | /workspace/90.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3888685383 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1052525880458 ps |
| CPU time | 935.52 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:56:33 PM PDT 24 |
| Peak memory | 225920 kb |
| Host | smart-47a511f7-45e2-4b73-8fd4-9f8f3999e309 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888685383 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3888685383 |
| Directory | /workspace/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/91.uart_fifo_reset.3844487334 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 26601571942 ps |
| CPU time | 44.47 seconds |
| Started | Jul 12 04:40:49 PM PDT 24 |
| Finished | Jul 12 04:41:35 PM PDT 24 |
| Peak memory | 199696 kb |
| Host | smart-95cdfa48-47a3-4e78-9e2d-c526f334aee6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844487334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3844487334 |
| Directory | /workspace/91.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/91.uart_stress_all_with_rand_reset.882555616 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 96320313189 ps |
| CPU time | 310.85 seconds |
| Started | Jul 12 04:40:47 PM PDT 24 |
| Finished | Jul 12 04:45:59 PM PDT 24 |
| Peak memory | 216400 kb |
| Host | smart-f22eded6-67fd-4b56-8613-ad6990ad9c7f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882555616 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.882555616 |
| Directory | /workspace/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/92.uart_fifo_reset.2547043418 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 16959599976 ps |
| CPU time | 27.57 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:41:21 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-6c9649f2-8fff-4982-93a6-8b12ed0e482f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547043418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2547043418 |
| Directory | /workspace/92.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/93.uart_fifo_reset.879429497 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 44264570765 ps |
| CPU time | 78.82 seconds |
| Started | Jul 12 04:40:49 PM PDT 24 |
| Finished | Jul 12 04:42:09 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-2bb1df23-511e-475f-b7fd-8204ebf20e68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879429497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.879429497 |
| Directory | /workspace/93.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3877100917 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 532444773827 ps |
| CPU time | 909.51 seconds |
| Started | Jul 12 04:40:49 PM PDT 24 |
| Finished | Jul 12 04:56:00 PM PDT 24 |
| Peak memory | 216428 kb |
| Host | smart-9270d6c5-892a-4e7b-9b66-075c4aaba687 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877100917 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3877100917 |
| Directory | /workspace/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/94.uart_fifo_reset.1250133317 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 150709931718 ps |
| CPU time | 419.85 seconds |
| Started | Jul 12 04:40:51 PM PDT 24 |
| Finished | Jul 12 04:47:52 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-b0c41435-60b4-4e0e-99ac-59631752473a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250133317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1250133317 |
| Directory | /workspace/94.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/94.uart_stress_all_with_rand_reset.795195282 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 473099211737 ps |
| CPU time | 854.83 seconds |
| Started | Jul 12 04:40:52 PM PDT 24 |
| Finished | Jul 12 04:55:10 PM PDT 24 |
| Peak memory | 232036 kb |
| Host | smart-6fbb132c-67ae-4804-b438-ec38c135c598 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795195282 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.795195282 |
| Directory | /workspace/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/95.uart_fifo_reset.3843582248 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 118706732908 ps |
| CPU time | 660.76 seconds |
| Started | Jul 12 04:40:50 PM PDT 24 |
| Finished | Jul 12 04:51:52 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-651d1fed-cdc6-4e9d-a9e5-09ab13f91f5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843582248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3843582248 |
| Directory | /workspace/95.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/95.uart_stress_all_with_rand_reset.308088195 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 67848897110 ps |
| CPU time | 786.57 seconds |
| Started | Jul 12 04:40:46 PM PDT 24 |
| Finished | Jul 12 04:53:54 PM PDT 24 |
| Peak memory | 226264 kb |
| Host | smart-52850b16-5ea9-4e1d-b3f1-74c0d992c729 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308088195 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.308088195 |
| Directory | /workspace/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/96.uart_fifo_reset.4218797658 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 68138364730 ps |
| CPU time | 302.91 seconds |
| Started | Jul 12 04:40:52 PM PDT 24 |
| Finished | Jul 12 04:45:59 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-fbe47d13-8d83-4bad-a252-75e21325c337 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4218797658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.4218797658 |
| Directory | /workspace/96.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3255321461 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 57423080314 ps |
| CPU time | 307.69 seconds |
| Started | Jul 12 04:40:53 PM PDT 24 |
| Finished | Jul 12 04:46:06 PM PDT 24 |
| Peak memory | 216180 kb |
| Host | smart-cb2fbe57-7321-4675-8a27-cfaa589513bc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255321461 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3255321461 |
| Directory | /workspace/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/97.uart_fifo_reset.2092280195 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 70040381482 ps |
| CPU time | 24 seconds |
| Started | Jul 12 04:40:56 PM PDT 24 |
| Finished | Jul 12 04:41:25 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-95037968-d341-4399-ba7a-1ac87a8c4ebc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092280195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2092280195 |
| Directory | /workspace/97.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1678873368 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 33232004023 ps |
| CPU time | 424.81 seconds |
| Started | Jul 12 04:40:54 PM PDT 24 |
| Finished | Jul 12 04:48:04 PM PDT 24 |
| Peak memory | 216372 kb |
| Host | smart-f1e3845a-f7b0-453c-a116-941f34ac95e0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678873368 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1678873368 |
| Directory | /workspace/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/99.uart_fifo_reset.13109312 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 43487086558 ps |
| CPU time | 18.88 seconds |
| Started | Jul 12 04:40:56 PM PDT 24 |
| Finished | Jul 12 04:41:20 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-e8486af3-70f4-4f9f-8bad-b22acaea6d27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13109312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.13109312 |
| Directory | /workspace/99.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1743699114 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 36841717258 ps |
| CPU time | 658.74 seconds |
| Started | Jul 12 04:40:54 PM PDT 24 |
| Finished | Jul 12 04:51:58 PM PDT 24 |
| Peak memory | 216540 kb |
| Host | smart-6358005d-002c-4e04-b909-5cd88d855167 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743699114 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1743699114 |
| Directory | /workspace/99.uart_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |