Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 36 0 36 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 9 0 9 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 36 0 36 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 9 0 9 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 109116 1 T1 499 T2 22 T3 10
all_values[1] 109116 1 T1 499 T2 22 T3 10
all_values[2] 109116 1 T1 499 T2 22 T3 10
all_values[3] 109116 1 T1 499 T2 22 T3 10
all_values[4] 109116 1 T1 499 T2 22 T3 10
all_values[5] 109116 1 T1 499 T2 22 T3 10
all_values[6] 109116 1 T1 499 T2 22 T3 10
all_values[7] 109116 1 T1 499 T2 22 T3 10
all_values[8] 109116 1 T1 499 T2 22 T3 10



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 510083 1 T1 1781 T2 107 T3 46
auto[1] 471961 1 T1 2710 T2 91 T3 44



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 889647 1 T1 4246 T2 174 T3 76
auto[1] 92397 1 T1 245 T2 24 T3 14



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 36 0 36 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 31537 1 T1 222 T2 14 T3 1
all_values[0] auto[0] auto[1] 24218 1 T1 241 T2 7 T3 9
all_values[0] auto[1] auto[0] 31734 1 T1 36 T7 4 T20 23
all_values[0] auto[1] auto[1] 21627 1 T2 1 T4 4 T10 3
all_values[1] auto[0] auto[0] 52650 1 T1 440 T2 4 T3 9
all_values[1] auto[0] auto[1] 1720 1 T2 2 T11 1 T12 8
all_values[1] auto[1] auto[0] 53175 1 T1 59 T2 16 T3 1
all_values[1] auto[1] auto[1] 1571 1 T4 2 T12 2 T73 4
all_values[2] auto[0] auto[0] 54689 1 T1 104 T2 16 T3 1
all_values[2] auto[0] auto[1] 2763 1 T1 1 T2 2 T3 1
all_values[2] auto[1] auto[0] 49243 1 T1 392 T2 1 T3 6
all_values[2] auto[1] auto[1] 2421 1 T1 2 T2 3 T3 2
all_values[3] auto[0] auto[0] 55422 1 T1 163 T2 3 T3 8
all_values[3] auto[0] auto[1] 278 1 T12 2 T14 2 T17 5
all_values[3] auto[1] auto[0] 53108 1 T1 336 T2 18 T3 2
all_values[3] auto[1] auto[1] 308 1 T2 1 T13 3 T14 3
all_values[4] auto[0] auto[0] 57440 1 T1 103 T2 19 T3 3
all_values[4] auto[0] auto[1] 433 1 T12 17 T13 2 T14 3
all_values[4] auto[1] auto[0] 50813 1 T1 396 T2 3 T3 7
all_values[4] auto[1] auto[1] 430 1 T13 5 T14 3 T17 9
all_values[5] auto[0] auto[0] 58804 1 T1 101 T2 1 T3 9
all_values[5] auto[0] auto[1] 184 1 T14 2 T19 3 T27 3
all_values[5] auto[1] auto[0] 49944 1 T1 398 T2 21 T3 1
all_values[5] auto[1] auto[1] 184 1 T14 3 T17 1 T19 2
all_values[6] auto[0] auto[0] 55506 1 T1 312 T2 19 T3 3
all_values[6] auto[0] auto[1] 175 1 T14 2 T19 3 T27 1
all_values[6] auto[1] auto[0] 53263 1 T1 187 T2 3 T3 7
all_values[6] auto[1] auto[1] 172 1 T14 1 T17 1 T19 3
all_values[7] auto[0] auto[0] 53398 1 T1 63 T2 4 T3 1
all_values[7] auto[0] auto[1] 310 1 T15 1 T16 3 T14 1
all_values[7] auto[1] auto[0] 55141 1 T1 436 T2 18 T3 9
all_values[7] auto[1] auto[1] 267 1 T12 6 T16 9 T13 1
all_values[8] auto[0] auto[0] 40963 1 T1 31 T2 12 T3 1
all_values[8] auto[0] auto[1] 19593 1 T2 4 T4 22 T5 2
all_values[8] auto[1] auto[0] 32817 1 T1 467 T2 2 T3 7
all_values[8] auto[1] auto[1] 15743 1 T1 1 T2 4 T3 2

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