Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2361	1			T4	1		T7	1		T10	1
auto[BaudRate115200]	1995	1			T1	2		T2	1		T3	1
auto[BaudRate230400]	2019	1			T1	1		T2	1		T3	1
auto[BaudRate128Kbps]	2051	1			T1	2		T2	1		T3	1
auto[BaudRate256Kbps]	2233	1			T3	1		T4	2		T6	1
auto[BaudRate1Mbps]	1866	1			T1	2		T2	3		T3	1
auto[BaudRate1p5Mbps]	1476	1			T1	2		T3	2		T20	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1515	1			T5	2		T11	7		T17	30
freqs[25]	1128	1			T40	5		T316	1		T36	8
freqs[48]	644	1			T122	7		T117	7		T137	10
freqs[50]	937	1			T2	6		T20	7		T16	9
freqs[100]	1099	1			T279	1		T13	2		T249	8

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	282	1			T11	1		T17	4		T89	3
auto[BaudRate9600]	freqs[25]	129	1			T165	2		T19	23		T132	1
auto[BaudRate9600]	freqs[48]	124	1			T117	1		T102	10		T320	1
auto[BaudRate9600]	freqs[50]	126	1			T16	2		T26	4		T321	3
auto[BaudRate9600]	freqs[100]	213	1			T249	3		T138	2		T129	2
auto[BaudRate115200]	freqs[24]	224	1			T5	1		T11	1		T17	1
auto[BaudRate115200]	freqs[25]	175	1			T165	1		T19	20		T87	1
auto[BaudRate115200]	freqs[48]	94	1			T122	1		T137	2		T102	4
auto[BaudRate115200]	freqs[50]	120	1			T2	1		T20	2		T293	1
auto[BaudRate115200]	freqs[100]	121	1			T249	2		T129	1		T268	3
auto[BaudRate230400]	freqs[24]	235	1			T17	4		T89	2		T92	2
auto[BaudRate230400]	freqs[25]	165	1			T36	2		T19	12		T99	2
auto[BaudRate230400]	freqs[48]	78	1			T117	1		T137	1		T102	2
auto[BaudRate230400]	freqs[50]	137	1			T2	1		T20	1		T16	2
auto[BaudRate230400]	freqs[100]	137	1			T13	1		T249	2		T138	2
auto[BaudRate128Kbps]	freqs[24]	200	1			T5	1		T11	3		T17	3
auto[BaudRate128Kbps]	freqs[25]	188	1			T36	3		T165	1		T19	16
auto[BaudRate128Kbps]	freqs[48]	95	1			T122	1		T117	2		T137	3
auto[BaudRate128Kbps]	freqs[50]	136	1			T2	1		T20	2		T16	3
auto[BaudRate128Kbps]	freqs[100]	152	1			T279	1		T13	1		T138	1
auto[BaudRate256Kbps]	freqs[24]	230	1			T11	1		T17	11		T89	1
auto[BaudRate256Kbps]	freqs[25]	180	1			T40	2		T36	1		T165	4
auto[BaudRate256Kbps]	freqs[48]	78	1			T122	3		T117	2		T137	3
auto[BaudRate256Kbps]	freqs[50]	117	1			T293	1		T26	7		T239	1
auto[BaudRate256Kbps]	freqs[100]	160	1			T138	1		T268	1		T271	2
auto[BaudRate1Mbps]	freqs[24]	214	1			T11	1		T17	5		T251	3
auto[BaudRate1Mbps]	freqs[25]	203	1			T40	1		T36	1		T19	13
auto[BaudRate1Mbps]	freqs[48]	72	1			T122	2		T117	1		T307	3
auto[BaudRate1Mbps]	freqs[50]	158	1			T2	3		T16	2		T26	13
auto[BaudRate1Mbps]	freqs[100]	155	1			T129	3		T88	2		T268	1
auto[BaudRate1p5Mbps]	freqs[25]	88	1			T40	2		T316	1		T36	1
auto[BaudRate1p5Mbps]	freqs[48]	103	1			T137	1		T307	1		T102	13
auto[BaudRate1p5Mbps]	freqs[50]	143	1			T20	2		T26	20		T239	3
auto[BaudRate1p5Mbps]	freqs[100]	161	1			T249	1		T138	3		T268	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded