Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	30870538	1			T1	225200		T2	26		T3	25
all_levels[1]	195755	1			T1	88		T3	2		T4	6
all_levels[2]	2345	1			T4	6		T15	7		T111	3
all_levels[3]	1063	1			T4	8		T111	2		T73	1
all_levels[4]	642	1			T4	9		T11	1		T111	2
all_levels[5]	484	1			T3	1		T111	2		T38	1
all_levels[6]	433	1			T3	1		T4	8		T111	2
all_levels[7]	359	1			T3	2		T4	2		T11	1
all_levels[8]	287	1			T4	1		T111	2		T73	1
all_levels[9]	241	1			T111	1		T16	1		T14	1
all_levels[10]	205	1			T4	2		T11	1		T16	1
all_levels[11]	193	1			T4	1		T111	2		T73	1
all_levels[12]	184	1			T16	1		T32	1		T98	2
all_levels[13]	165	1			T111	1		T73	1		T16	1
all_levels[14]	139	1			T3	1		T32	1		T34	1
all_levels[15]	112	1			T11	1		T112	1		T113	2
all_levels[16]	120	1			T16	2		T36	1		T18	1
all_levels[17]	80	1			T3	1		T111	1		T19	1
all_levels[18]	98	1			T11	1		T111	1		T114	1
all_levels[19]	98	1			T11	1		T73	2		T19	1
all_levels[20]	65	1			T99	1		T28	1		T90	1
all_levels[21]	59	1			T15	1		T73	1		T27	1
all_levels[22]	81	1			T10	2		T11	1		T16	1
all_levels[23]	62	1			T16	1		T87	1		T115	1
all_levels[24]	70	1			T16	1		T116	1		T101	3
all_levels[25]	55	1			T16	1		T99	1		T29	1
all_levels[26]	48	1			T28	1		T117	4		T100	2
all_levels[27]	41	1			T16	1		T32	1		T27	1
all_levels[28]	46	1			T73	1		T16	2		T34	1
all_levels[29]	26	1			T73	1		T34	1		T95	1
all_levels[30]	43	1			T73	1		T34	1		T118	1
all_levels[31]	37	1			T87	1		T115	1		T119	1
all_levels[32]	40	1			T120	1		T18	1		T99	1
all_levels[33]	28	1			T16	1		T119	2		T121	1
all_levels[34]	31	1			T16	3		T87	1		T31	1
all_levels[35]	25	1			T122	1		T104	1		T95	1
all_levels[36]	16	1			T104	1		T123	1		T124	1
all_levels[37]	20	1			T3	1		T113	1		T125	1
all_levels[38]	32	1			T11	1		T126	1		T104	1
all_levels[39]	19	1			T99	1		T89	1		T117	1
all_levels[40]	17	1			T18	1		T127	1		T128	1
all_levels[41]	17	1			T129	1		T130	1		T131	1
all_levels[42]	20	1			T120	1		T99	1		T132	1
all_levels[43]	18	1			T99	1		T133	1		T134	1
all_levels[44]	24	1			T116	1		T132	3		T135	1
all_levels[45]	15	1			T16	1		T136	1		T100	1
all_levels[46]	18	1			T73	1		T16	1		T137	2
all_levels[47]	18	1			T138	1		T105	1		T139	1
all_levels[48]	14	1			T101	1		T89	1		T140	2
all_levels[49]	8	1			T135	1		T125	1		T95	1
all_levels[50]	12	1			T42	1		T141	1		T142	1
all_levels[51]	14	1			T101	1		T143	1		T144	2
all_levels[52]	15	1			T18	1		T89	5		T143	2
all_levels[53]	12	1			T135	2		T145	1		T146	2
all_levels[54]	11	1			T133	2		T141	1		T147	1
all_levels[55]	6	1			T148	1		T149	1		T150	1
all_levels[56]	10	1			T145	1		T151	1		T152	1
all_levels[57]	8	1			T107	1		T153	1		T154	1
all_levels[58]	9	1			T155	1		T144	1		T156	1
all_levels[59]	6	1			T117	2		T134	1		T157	1
all_levels[60]	11	1			T2	1		T100	1		T158	2
all_levels[61]	7	1			T90	1		T159	1		T160	1
all_levels[62]	3	1			T161	2		T162	1		-	-
all_levels[63]	7	1			T90	1		T163	1		T164	2
all_levels[64]	97	1			T2	2		T18	2		T122	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31069919

1

T1

225288

T2

23

T3

30

auto[1]

4863

1

T2

6

T3

4

T4

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[49] , all_levels[50]]	[auto[1]]	--	--	2
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[58] , all_levels[59]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	30866087	1			T1	225200		T2	21		T3	22
all_levels[0]	auto[1]	4451	1			T2	5		T3	3		T4	3
all_levels[1]	auto[0]	195707	1			T1	88		T3	2		T4	6
all_levels[1]	auto[1]	48	1			T165	1		T122	1		T98	1
all_levels[2]	auto[0]	2333	1			T4	6		T15	7		T111	3
all_levels[2]	auto[1]	12	1			T166	1		T119	1		T167	1
all_levels[3]	auto[0]	1043	1			T4	8		T111	2		T73	1
all_levels[3]	auto[1]	20	1			T89	1		T92	1		T168	1
all_levels[4]	auto[0]	618	1			T4	9		T11	1		T111	2
all_levels[4]	auto[1]	24	1			T169	1		T170	1		T146	2
all_levels[5]	auto[0]	473	1			T3	1		T111	2		T38	1
all_levels[5]	auto[1]	11	1			T27	1		T148	1		T171	1
all_levels[6]	auto[0]	416	1			T3	1		T4	5		T111	2
all_levels[6]	auto[1]	17	1			T4	3		T114	2		T91	1
all_levels[7]	auto[0]	333	1			T3	1		T4	2		T11	1
all_levels[7]	auto[1]	26	1			T3	1		T28	1		T113	1
all_levels[8]	auto[0]	271	1			T4	1		T111	2		T73	1
all_levels[8]	auto[1]	16	1			T172	1		T137	1		T139	1
all_levels[9]	auto[0]	229	1			T111	1		T16	1		T14	1
all_levels[9]	auto[1]	12	1			T173	1		T174	1		T164	2
all_levels[10]	auto[0]	195	1			T4	2		T11	1		T16	1
all_levels[10]	auto[1]	10	1			T118	2		T133	2		T175	1
all_levels[11]	auto[0]	181	1			T4	1		T111	2		T73	1
all_levels[11]	auto[1]	12	1			T176	1		T164	1		T177	1
all_levels[12]	auto[0]	169	1			T16	1		T32	1		T98	1
all_levels[12]	auto[1]	15	1			T98	1		T90	1		T178	1
all_levels[13]	auto[0]	156	1			T111	1		T73	1		T16	1
all_levels[13]	auto[1]	9	1			T98	1		T179	1		T180	2
all_levels[14]	auto[0]	133	1			T3	1		T32	1		T34	1
all_levels[14]	auto[1]	6	1			T181	1		T182	1		T183	2
all_levels[15]	auto[0]	106	1			T11	1		T112	1		T113	2
all_levels[15]	auto[1]	6	1			T184	2		T185	1		T186	1
all_levels[16]	auto[0]	108	1			T16	2		T36	1		T18	1
all_levels[16]	auto[1]	12	1			T101	1		T113	1		T164	1
all_levels[17]	auto[0]	74	1			T3	1		T111	1		T19	1
all_levels[17]	auto[1]	6	1			T187	1		T188	3		T189	1
all_levels[18]	auto[0]	91	1			T11	1		T111	1		T114	1
all_levels[18]	auto[1]	7	1			T101	2		T190	2		T191	2
all_levels[19]	auto[0]	93	1			T11	1		T73	2		T19	1
all_levels[19]	auto[1]	5	1			T181	1		T192	1		T162	1
all_levels[20]	auto[0]	63	1			T99	1		T28	1		T90	1
all_levels[20]	auto[1]	2	1			T193	1		T183	1		-	-
all_levels[21]	auto[0]	55	1			T15	1		T73	1		T27	1
all_levels[21]	auto[1]	4	1			T194	1		T192	1		T195	1
all_levels[22]	auto[0]	71	1			T10	1		T11	1		T16	1
all_levels[22]	auto[1]	10	1			T10	1		T135	1		T196	1
all_levels[23]	auto[0]	53	1			T16	1		T87	1		T115	1
all_levels[23]	auto[1]	9	1			T197	3		T198	1		T199	2
all_levels[24]	auto[0]	61	1			T16	1		T116	1		T101	1
all_levels[24]	auto[1]	9	1			T101	2		T200	1		T158	1
all_levels[25]	auto[0]	50	1			T16	1		T99	1		T29	1
all_levels[25]	auto[1]	5	1			T201	2		T202	3		-	-
all_levels[26]	auto[0]	40	1			T28	1		T117	1		T100	2
all_levels[26]	auto[1]	8	1			T117	3		T203	1		T204	3
all_levels[27]	auto[0]	39	1			T16	1		T32	1		T27	1
all_levels[27]	auto[1]	2	1			T205	2		-	-		-	-
all_levels[28]	auto[0]	41	1			T73	1		T16	2		T34	1
all_levels[28]	auto[1]	5	1			T206	3		T207	2		-	-
all_levels[29]	auto[0]	25	1			T73	1		T34	1		T95	1
all_levels[29]	auto[1]	1	1			T208	1		-	-		-	-
all_levels[30]	auto[0]	36	1			T73	1		T34	1		T118	1
all_levels[30]	auto[1]	7	1			T105	1		T209	1		T182	1
all_levels[31]	auto[0]	32	1			T87	1		T115	1		T119	1
all_levels[31]	auto[1]	5	1			T210	1		T211	1		T185	2
all_levels[32]	auto[0]	37	1			T120	1		T18	1		T99	1
all_levels[32]	auto[1]	3	1			T139	1		T212	1		T213	1
all_levels[33]	auto[0]	26	1			T16	1		T119	1		T121	1
all_levels[33]	auto[1]	2	1			T119	1		T214	1		-	-
all_levels[34]	auto[0]	28	1			T16	3		T87	1		T31	1
all_levels[34]	auto[1]	3	1			T215	1		T216	1		T217	1
all_levels[35]	auto[0]	25	1			T122	1		T104	1		T95	1
all_levels[36]	auto[0]	15	1			T104	1		T123	1		T124	1
all_levels[36]	auto[1]	1	1			T218	1		-	-		-	-
all_levels[37]	auto[0]	20	1			T3	1		T113	1		T125	1
all_levels[38]	auto[0]	26	1			T11	1		T126	1		T104	1
all_levels[38]	auto[1]	6	1			T219	2		T220	1		T221	3
all_levels[39]	auto[0]	17	1			T99	1		T89	1		T117	1
all_levels[39]	auto[1]	2	1			T151	2		-	-		-	-
all_levels[40]	auto[0]	17	1			T18	1		T127	1		T128	1
all_levels[41]	auto[0]	14	1			T129	1		T130	1		T131	1
all_levels[41]	auto[1]	3	1			T222	1		T223	2		-	-
all_levels[42]	auto[0]	18	1			T120	1		T99	1		T132	1
all_levels[42]	auto[1]	2	1			T224	2		-	-		-	-
all_levels[43]	auto[0]	17	1			T99	1		T133	1		T134	1
all_levels[43]	auto[1]	1	1			T225	1		-	-		-	-
all_levels[44]	auto[0]	18	1			T116	1		T132	1		T135	1
all_levels[44]	auto[1]	6	1			T132	2		T226	1		T227	3
all_levels[45]	auto[0]	13	1			T16	1		T136	1		T100	1
all_levels[45]	auto[1]	2	1			T228	2		-	-		-	-
all_levels[46]	auto[0]	16	1			T73	1		T16	1		T137	1
all_levels[46]	auto[1]	2	1			T137	1		T229	1		-	-
all_levels[47]	auto[0]	16	1			T138	1		T105	1		T139	1
all_levels[47]	auto[1]	2	1			T230	2		-	-		-	-
all_levels[48]	auto[0]	11	1			T101	1		T89	1		T140	1
all_levels[48]	auto[1]	3	1			T140	1		T231	2		-	-
all_levels[49]	auto[0]	8	1			T135	1		T125	1		T95	1
all_levels[50]	auto[0]	12	1			T42	1		T141	1		T142	1
all_levels[51]	auto[0]	12	1			T101	1		T143	1		T144	1
all_levels[51]	auto[1]	2	1			T144	1		T216	1		-	-
all_levels[52]	auto[0]	10	1			T18	1		T89	2		T143	1
all_levels[52]	auto[1]	5	1			T89	3		T143	1		T203	1
all_levels[53]	auto[0]	8	1			T135	1		T145	1		T146	1
all_levels[53]	auto[1]	4	1			T135	1		T146	1		T203	2
all_levels[54]	auto[0]	9	1			T133	1		T141	1		T147	1
all_levels[54]	auto[1]	2	1			T133	1		T232	1		-	-
all_levels[55]	auto[0]	6	1			T148	1		T149	1		T150	1
all_levels[56]	auto[0]	8	1			T145	1		T151	1		T152	1
all_levels[56]	auto[1]	2	1			T233	2		-	-		-	-
all_levels[57]	auto[0]	7	1			T107	1		T153	1		T154	1
all_levels[57]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[58]	auto[0]	9	1			T155	1		T144	1		T156	1
all_levels[59]	auto[0]	6	1			T117	2		T134	1		T157	1
all_levels[60]	auto[0]	9	1			T2	1		T100	1		T158	1
all_levels[60]	auto[1]	2	1			T158	1		T235	1		-	-
all_levels[61]	auto[0]	6	1			T90	1		T159	1		T160	1
all_levels[61]	auto[1]	1	1			T203	1		-	-		-	-
all_levels[62]	auto[0]	2	1			T161	1		T162	1		-	-
all_levels[62]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[63]	auto[0]	6	1			T90	1		T163	1		T164	1
all_levels[63]	auto[1]	1	1			T164	1		-	-		-	-
all_levels[64]	auto[0]	85	1			T2	1		T18	2		T122	1
all_levels[64]	auto[1]	12	1			T2	1		T122	1		T194	2