Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	109116	1			T1	499		T2	22		T3	10
all_pins[1]	109116	1			T1	499		T2	22		T3	10
all_pins[2]	109116	1			T1	499		T2	22		T3	10
all_pins[3]	109116	1			T1	499		T2	22		T3	10
all_pins[4]	109116	1			T1	499		T2	22		T3	10
all_pins[5]	109116	1			T1	499		T2	22		T3	10
all_pins[6]	109116	1			T1	499		T2	22		T3	10
all_pins[7]	109116	1			T1	499		T2	22		T3	10
all_pins[8]	109116	1			T1	499		T2	22		T3	10

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	938455	1			T1	4488		T2	189		T3	86
values[0x1]	43589	1			T1	3		T2	9		T3	4
transitions[0x0=>0x1]	34264	1			T1	3		T2	8		T3	4
transitions[0x1=>0x0]	34045	1			T1	3		T2	9		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	87420	1			T1	499		T2	21		T3	10
all_pins[0]	values[0x1]	21696	1			T2	1		T4	4		T10	3
all_pins[0]	transitions[0x0=>0x1]	21049	1			T2	1		T4	4		T10	3
all_pins[0]	transitions[0x1=>0x0]	922	1			T4	2		T73	4		T13	5
all_pins[1]	values[0x0]	107547	1			T1	499		T2	22		T3	10
all_pins[1]	values[0x1]	1569	1			T4	2		T12	2		T73	4
all_pins[1]	transitions[0x0=>0x1]	1434	1			T4	2		T12	2		T73	4
all_pins[1]	transitions[0x1=>0x0]	2337	1			T1	2		T2	3		T3	2
all_pins[2]	values[0x0]	106644	1			T1	497		T2	19		T3	8
all_pins[2]	values[0x1]	2472	1			T1	2		T2	3		T3	2
all_pins[2]	transitions[0x0=>0x1]	2408	1			T1	2		T2	3		T3	2
all_pins[2]	transitions[0x1=>0x0]	244	1			T2	1		T13	3		T14	2
all_pins[3]	values[0x0]	108808	1			T1	499		T2	21		T3	10
all_pins[3]	values[0x1]	308	1			T2	1		T13	3		T14	3
all_pins[3]	transitions[0x0=>0x1]	266	1			T2	1		T13	3		T14	2
all_pins[3]	transitions[0x1=>0x0]	388	1			T13	5		T14	2		T17	9
all_pins[4]	values[0x0]	108686	1			T1	499		T2	22		T3	10
all_pins[4]	values[0x1]	430	1			T13	5		T14	3		T17	9
all_pins[4]	transitions[0x0=>0x1]	364	1			T13	4		T14	3		T17	8
all_pins[4]	transitions[0x1=>0x0]	160	1			T14	3		T17	1		T19	2
all_pins[5]	values[0x0]	108890	1			T1	499		T2	22		T3	10
all_pins[5]	values[0x1]	226	1			T13	1		T14	3		T17	2
all_pins[5]	transitions[0x0=>0x1]	169	1			T13	1		T14	3		T17	1
all_pins[5]	transitions[0x1=>0x0]	752	1			T4	4		T7	2		T11	6
all_pins[6]	values[0x0]	108307	1			T1	499		T2	22		T3	10
all_pins[6]	values[0x1]	809	1			T4	4		T7	2		T11	6
all_pins[6]	transitions[0x0=>0x1]	774	1			T4	4		T7	2		T11	6
all_pins[6]	transitions[0x1=>0x0]	232	1			T12	6		T16	9		T13	1
all_pins[7]	values[0x0]	108849	1			T1	499		T2	22		T3	10
all_pins[7]	values[0x1]	267	1			T12	6		T16	9		T13	1
all_pins[7]	transitions[0x0=>0x1]	153	1			T12	6		T16	8		T17	6
all_pins[7]	transitions[0x1=>0x0]	15698	1			T1	1		T2	4		T3	2
all_pins[8]	values[0x0]	93304	1			T1	498		T2	18		T3	8
all_pins[8]	values[0x1]	15812	1			T1	1		T2	4		T3	2
all_pins[8]	transitions[0x0=>0x1]	7647	1			T1	1		T2	3		T3	2
all_pins[8]	transitions[0x1=>0x0]	13312	1			T2	1		T4	4		T10	2