Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8373470	1			T1	415		T2	7		T3	5
all_levels[1]	1306638	1			T1	419		T2	3		T3	1
all_levels[2]	637588	1			T1	112089		T2	3		T20	5087
all_levels[3]	272769	1			T1	416		T4	2		T11	2
all_levels[4]	466340	1			T1	405		T4	3		T20	5061
all_levels[5]	217863	1			T1	415		T20	5087		T15	1
all_levels[6]	213618	1			T1	416		T4	3		T20	5086
all_levels[7]	225332	1			T1	415		T20	5091		T111	1
all_levels[8]	315084	1			T1	415		T20	5082		T15	2
all_levels[9]	211628	1			T1	415		T3	1		T20	5053
all_levels[10]	312123	1			T1	416		T4	1		T20	5082
all_levels[11]	339504	1			T1	415		T2	2		T4	1
all_levels[12]	276483	1			T1	416		T4	2		T20	3025
all_levels[13]	199445	1			T1	415		T3	15		T20	3019
all_levels[14]	196757	1			T1	416		T20	3015		T15	1
all_levels[15]	205117	1			T1	403		T20	3041		T40	1
all_levels[16]	238598	1			T1	415		T4	1		T20	3043
all_levels[17]	181767	1			T1	415		T2	1		T20	3027
all_levels[18]	291224	1			T1	414		T20	13315		T111	2
all_levels[19]	193930	1			T1	416		T20	3030		T16	18
all_levels[20]	186902	1			T1	415		T20	3032		T111	1
all_levels[21]	229568	1			T1	412		T3	4		T20	3036
all_levels[22]	378856	1			T1	406		T2	1		T4	1
all_levels[23]	205028	1			T1	414		T4	2		T20	3011
all_levels[24]	245002	1			T1	416		T20	3036		T15	2
all_levels[25]	180376	1			T1	415		T4	2		T20	3024
all_levels[26]	173538	1			T1	416		T20	3022		T111	1
all_levels[27]	235964	1			T1	415		T4	1		T20	3048
all_levels[28]	159046	1			T1	416		T2	1		T3	3
all_levels[29]	242330	1			T1	415		T3	5		T4	1
all_levels[30]	284334	1			T1	21775		T3	1		T20	3007
all_levels[31]	470200	1			T1	480		T2	2		T20	3299
all_levels[32]	13407925	1			T1	78933		T2	8		T7	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31069919

1

T1

225288

T2

23

T3

30

auto[1]

4428

1

T1

1

T2

5

T3

5

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8370787	1			T1	415		T2	5		T3	4
all_levels[0]	auto[1]	2683	1			T2	2		T3	1		T4	2
all_levels[1]	auto[0]	1306364	1			T1	419		T2	2		T3	1
all_levels[1]	auto[1]	274	1			T2	1		T10	3		T41	2
all_levels[2]	auto[0]	637539	1			T1	112088		T2	2		T20	5087
all_levels[2]	auto[1]	49	1			T1	1		T2	1		T138	2
all_levels[3]	auto[0]	272642	1			T1	416		T4	2		T11	2
all_levels[3]	auto[1]	127	1			T98	1		T27	11		T245	7
all_levels[4]	auto[0]	466303	1			T1	405		T4	3		T20	5061
all_levels[4]	auto[1]	37	1			T120	1		T32	2		T106	1
all_levels[5]	auto[0]	217831	1			T1	415		T20	5087		T15	1
all_levels[5]	auto[1]	32	1			T316	1		T32	1		T98	2
all_levels[6]	auto[0]	213596	1			T1	416		T4	3		T20	5086
all_levels[6]	auto[1]	22	1			T112	1		T92	3		T181	1
all_levels[7]	auto[0]	225277	1			T1	415		T20	5091		T111	1
all_levels[7]	auto[1]	55	1			T279	1		T19	2		T323	1
all_levels[8]	auto[0]	315037	1			T1	415		T20	5082		T15	2
all_levels[8]	auto[1]	47	1			T98	1		T90	1		T283	2
all_levels[9]	auto[0]	211582	1			T1	415		T3	1		T20	5053
all_levels[9]	auto[1]	46	1			T89	1		T113	1		T169	2
all_levels[10]	auto[0]	312095	1			T1	416		T4	1		T20	5082
all_levels[10]	auto[1]	28	1			T73	1		T98	1		T146	2
all_levels[11]	auto[0]	339473	1			T1	415		T2	2		T4	1
all_levels[11]	auto[1]	31	1			T28	2		T102	1		T184	1
all_levels[12]	auto[0]	276441	1			T1	416		T4	2		T20	3025
all_levels[12]	auto[1]	42	1			T165	4		T101	1		T28	1
all_levels[13]	auto[0]	199418	1			T1	415		T3	14		T20	3019
all_levels[13]	auto[1]	27	1			T3	1		T170	1		T174	1
all_levels[14]	auto[0]	196734	1			T1	416		T20	3015		T15	1
all_levels[14]	auto[1]	23	1			T136	1		T31	2		T148	3
all_levels[15]	auto[0]	205055	1			T1	403		T20	3041		T40	1
all_levels[15]	auto[1]	62	1			T122	3		T317	15		T107	1
all_levels[16]	auto[0]	238571	1			T1	415		T4	1		T20	3043
all_levels[16]	auto[1]	27	1			T41	4		T324	2		T178	1
all_levels[17]	auto[0]	181748	1			T1	415		T2	1		T20	3027
all_levels[17]	auto[1]	19	1			T89	2		T170	1		T105	2
all_levels[18]	auto[0]	291205	1			T1	414		T20	13314		T111	2
all_levels[18]	auto[1]	19	1			T20	1		T209	3		T325	1
all_levels[19]	auto[0]	193915	1			T1	416		T20	3030		T16	18
all_levels[19]	auto[1]	15	1			T97	1		T326	1		T140	1
all_levels[20]	auto[0]	186879	1			T1	415		T20	3032		T111	1
all_levels[20]	auto[1]	23	1			T129	1		T270	2		T327	1
all_levels[21]	auto[0]	229541	1			T1	412		T3	3		T20	3036
all_levels[21]	auto[1]	27	1			T3	1		T101	1		T107	1
all_levels[22]	auto[0]	378835	1			T1	406		T2	1		T4	1
all_levels[22]	auto[1]	21	1			T165	3		T102	1		T294	1
all_levels[23]	auto[0]	205007	1			T1	414		T4	2		T20	3011
all_levels[23]	auto[1]	21	1			T87	1		T117	2		T328	1
all_levels[24]	auto[0]	244966	1			T1	416		T20	3036		T15	2
all_levels[24]	auto[1]	36	1			T224	3		T97	19		T329	1
all_levels[25]	auto[0]	180362	1			T1	415		T4	2		T20	3024
all_levels[25]	auto[1]	14	1			T32	1		T118	1		T246	1
all_levels[26]	auto[0]	173520	1			T1	416		T20	3022		T111	1
all_levels[26]	auto[1]	18	1			T90	1		T166	1		T139	1
all_levels[27]	auto[0]	235947	1			T1	415		T4	1		T20	3048
all_levels[27]	auto[1]	17	1			T90	1		T132	1		T146	1
all_levels[28]	auto[0]	159031	1			T1	416		T2	1		T3	3
all_levels[28]	auto[1]	15	1			T117	1		T285	1		T276	1
all_levels[29]	auto[0]	242311	1			T1	415		T3	3		T4	1
all_levels[29]	auto[1]	19	1			T3	2		T105	1		T330	1
all_levels[30]	auto[0]	284323	1			T1	21775		T3	1		T20	3007
all_levels[30]	auto[1]	11	1			T172	1		T256	1		T247	1
all_levels[31]	auto[0]	470174	1			T1	480		T2	2		T20	3299
all_levels[31]	auto[1]	26	1			T248	1		T331	1		T177	1
all_levels[32]	auto[0]	13407410	1			T1	78933		T2	7		T7	1
all_levels[32]	auto[1]	515	1			T2	1		T7	1		T10	1