Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	724	1			T14	7		T17	4		T19	15
all_values[1]	724	1			T14	7		T17	4		T19	15
all_values[2]	724	1			T14	7		T17	4		T19	15
all_values[3]	724	1			T14	7		T17	4		T19	15
all_values[4]	724	1			T14	7		T17	4		T19	15
all_values[5]	724	1			T14	7		T17	4		T19	15
all_values[6]	724	1			T14	7		T17	4		T19	15
all_values[7]	724	1			T14	7		T17	4		T19	15
all_values[8]	724	1			T14	7		T17	4		T19	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3569

1

T14

29

T17

19

T19

88

auto[1]

2947

1

T14

34

T17

17

T19

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2142

1

T14

15

T17

7

T19

38

auto[1]

4374

1

T14

48

T17

29

T19

97

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3839

1

T14

31

T17

19

T19

75

auto[1]

2677

1

T14

32

T17

17

T19

60

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	226	1			T14	2		T17	2		T19	4
all_values[0]	auto[0]	auto[1]	auto[1]	211	1			T14	2		T19	5		T27	1
all_values[0]	auto[1]	auto[0]	auto[1]	156	1			T14	1		T17	1		T19	4
all_values[0]	auto[1]	auto[1]	auto[1]	131	1			T14	2		T17	1		T19	2
all_values[1]	auto[0]	auto[0]	auto[0]	219	1			T14	1		T17	2		T19	4
all_values[1]	auto[0]	auto[1]	auto[0]	188	1			T14	2		T17	1		T19	2
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T14	1		T17	1		T19	6
all_values[1]	auto[1]	auto[1]	auto[1]	137	1			T14	3		T19	3		T93	2
all_values[2]	auto[0]	auto[0]	auto[0]	171	1			T14	3		T19	5		T27	2
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T17	3		T19	3		T102	1
all_values[2]	auto[0]	auto[1]	auto[0]	152	1			T19	1		T102	1		T105	2
all_values[2]	auto[0]	auto[1]	auto[1]	56	1			T14	1		T93	1		T102	1
all_values[2]	auto[1]	auto[0]	auto[1]	148	1			T14	2		T17	1		T19	4
all_values[2]	auto[1]	auto[1]	auto[1]	117	1			T14	1		T19	2		T27	2
all_values[3]	auto[0]	auto[0]	auto[0]	170	1			T19	6		T27	1		T100	1
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T14	1		T17	2		T19	2
all_values[3]	auto[0]	auto[1]	auto[0]	107	1			T14	1		T19	1		T27	1
all_values[3]	auto[0]	auto[1]	auto[1]	76	1			T19	1		T27	2		T93	1
all_values[3]	auto[1]	auto[0]	auto[1]	171	1			T14	2		T17	1		T19	4
all_values[3]	auto[1]	auto[1]	auto[1]	125	1			T14	3		T17	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T19	5		T100	1		T106	2
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T14	1		T19	1		T27	3
all_values[4]	auto[0]	auto[1]	auto[0]	132	1			T14	1		T19	2		T27	2
all_values[4]	auto[0]	auto[1]	auto[1]	58	1			T17	1		T102	3		T107	1
all_values[4]	auto[1]	auto[0]	auto[1]	165	1			T14	4		T17	2		T19	5
all_values[4]	auto[1]	auto[1]	auto[1]	127	1			T14	1		T17	1		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	128	1			T14	1		T19	2		T27	3
all_values[5]	auto[0]	auto[0]	auto[1]	73	1			T19	2		T27	1		T102	2
all_values[5]	auto[0]	auto[1]	auto[0]	124	1			T17	2		T19	3		T93	1
all_values[5]	auto[0]	auto[1]	auto[1]	79	1			T14	1		T19	1		T100	2
all_values[5]	auto[1]	auto[0]	auto[1]	178	1			T14	2		T19	5		T27	3
all_values[5]	auto[1]	auto[1]	auto[1]	142	1			T14	3		T17	2		T19	2
all_values[6]	auto[0]	auto[0]	auto[0]	167	1			T14	1		T17	1		T19	3
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T14	1		T19	2		T93	2
all_values[6]	auto[0]	auto[1]	auto[0]	117	1			T14	1		T17	1		T19	2
all_values[6]	auto[0]	auto[1]	auto[1]	72	1			T19	1		T100	2		T102	1
all_values[6]	auto[1]	auto[0]	auto[1]	166	1			T14	2		T19	2		T27	2
all_values[6]	auto[1]	auto[1]	auto[1]	132	1			T14	2		T17	2		T19	5
all_values[7]	auto[0]	auto[0]	auto[0]	163	1			T19	2		T100	1		T108	2
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T19	3		T27	1		T100	1
all_values[7]	auto[0]	auto[1]	auto[0]	131	1			T14	4		T27	3		T93	2
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T14	2		T17	2		T19	3
all_values[7]	auto[1]	auto[0]	auto[1]	151	1			T14	1		T19	4		T27	1
all_values[7]	auto[1]	auto[1]	auto[1]	131	1			T17	2		T19	3		T27	2
all_values[8]	auto[0]	auto[0]	auto[1]	209	1			T14	1		T17	1		T19	4
all_values[8]	auto[0]	auto[1]	auto[1]	195	1			T14	4		T17	1		T19	5
all_values[8]	auto[1]	auto[0]	auto[1]	190	1			T14	2		T17	2		T19	6
all_values[8]	auto[1]	auto[1]	auto[1]	130	1			T27	2		T93	2		T108	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal