| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.12 | 99.10 | 97.65 | 100.00 | 98.38 | 100.00 | 99.59 |
| T1256 | /workspace/coverage/cover_reg_top/10.uart_tl_errors.3747536834 | Jul 13 04:38:37 PM PDT 24 | Jul 13 04:38:40 PM PDT 24 | 65292942 ps | ||
| T1257 | /workspace/coverage/cover_reg_top/39.uart_intr_test.1921326876 | Jul 13 04:38:51 PM PDT 24 | Jul 13 04:38:53 PM PDT 24 | 16187064 ps | ||
| T1258 | /workspace/coverage/cover_reg_top/6.uart_tl_errors.2454164741 | Jul 13 04:38:41 PM PDT 24 | Jul 13 04:38:44 PM PDT 24 | 75110004 ps | ||
| T1259 | /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.899869330 | Jul 13 04:38:51 PM PDT 24 | Jul 13 04:38:58 PM PDT 24 | 33076953 ps | ||
| T109 | /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2791806717 | Jul 13 04:38:48 PM PDT 24 | Jul 13 04:38:50 PM PDT 24 | 322003619 ps | ||
| T1260 | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.829724836 | Jul 13 04:38:34 PM PDT 24 | Jul 13 04:38:37 PM PDT 24 | 53756329 ps | ||
| T1261 | /workspace/coverage/cover_reg_top/3.uart_intr_test.503185172 | Jul 13 04:38:39 PM PDT 24 | Jul 13 04:38:40 PM PDT 24 | 29217735 ps | ||
| T1262 | /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.647622081 | Jul 13 04:38:36 PM PDT 24 | Jul 13 04:38:43 PM PDT 24 | 75967347 ps | ||
| T1263 | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2728799607 | Jul 13 04:38:30 PM PDT 24 | Jul 13 04:38:33 PM PDT 24 | 39809254 ps | ||
| T1264 | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1304081525 | Jul 13 04:38:29 PM PDT 24 | Jul 13 04:38:32 PM PDT 24 | 64832580 ps | ||
| T1265 | /workspace/coverage/cover_reg_top/1.uart_intr_test.3216931606 | Jul 13 04:38:23 PM PDT 24 | Jul 13 04:38:26 PM PDT 24 | 46873890 ps | ||
| T1266 | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3545548909 | Jul 13 04:38:49 PM PDT 24 | Jul 13 04:38:50 PM PDT 24 | 59075895 ps | ||
| T1267 | /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1180238467 | Jul 13 04:38:33 PM PDT 24 | Jul 13 04:38:35 PM PDT 24 | 100346055 ps | ||
| T1268 | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3714733937 | Jul 13 04:38:49 PM PDT 24 | Jul 13 04:38:52 PM PDT 24 | 45226490 ps | ||
| T1269 | /workspace/coverage/cover_reg_top/5.uart_tl_errors.448059159 | Jul 13 04:38:35 PM PDT 24 | Jul 13 04:38:39 PM PDT 24 | 144600628 ps | ||
| T1270 | /workspace/coverage/cover_reg_top/18.uart_tl_errors.3315131018 | Jul 13 04:38:55 PM PDT 24 | Jul 13 04:38:58 PM PDT 24 | 73588476 ps | ||
| T1271 | /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.541593999 | Jul 13 04:39:10 PM PDT 24 | Jul 13 04:39:11 PM PDT 24 | 26516134 ps | ||
| T1272 | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.714749443 | Jul 13 04:38:41 PM PDT 24 | Jul 13 04:38:44 PM PDT 24 | 901688928 ps | ||
| T57 | /workspace/coverage/cover_reg_top/14.uart_csr_rw.3982870983 | Jul 13 04:38:50 PM PDT 24 | Jul 13 04:38:52 PM PDT 24 | 21224425 ps | ||
| T1273 | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.546392319 | Jul 13 04:38:47 PM PDT 24 | Jul 13 04:38:51 PM PDT 24 | 179072207 ps | ||
| T1274 | /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1799587638 | Jul 13 04:38:53 PM PDT 24 | Jul 13 04:38:56 PM PDT 24 | 83440564 ps | ||
| T1275 | /workspace/coverage/cover_reg_top/18.uart_intr_test.755608399 | Jul 13 04:39:02 PM PDT 24 | Jul 13 04:39:03 PM PDT 24 | 14090053 ps | ||
| T1276 | /workspace/coverage/cover_reg_top/4.uart_intr_test.3782999555 | Jul 13 04:38:44 PM PDT 24 | Jul 13 04:38:45 PM PDT 24 | 75169680 ps | ||
| T1277 | /workspace/coverage/cover_reg_top/34.uart_intr_test.2793183931 | Jul 13 04:38:56 PM PDT 24 | Jul 13 04:38:58 PM PDT 24 | 22610263 ps | ||
| T1278 | /workspace/coverage/cover_reg_top/13.uart_intr_test.813535896 | Jul 13 04:38:51 PM PDT 24 | Jul 13 04:38:53 PM PDT 24 | 52336721 ps | ||
| T1279 | /workspace/coverage/cover_reg_top/0.uart_tl_errors.2947172194 | Jul 13 04:38:32 PM PDT 24 | Jul 13 04:38:35 PM PDT 24 | 42306944 ps | ||
| T1280 | /workspace/coverage/cover_reg_top/15.uart_tl_errors.2696457912 | Jul 13 04:38:37 PM PDT 24 | Jul 13 04:38:41 PM PDT 24 | 30998077 ps | ||
| T1281 | /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3047323143 | Jul 13 04:38:29 PM PDT 24 | Jul 13 04:38:32 PM PDT 24 | 18454124 ps | ||
| T1282 | /workspace/coverage/cover_reg_top/46.uart_intr_test.4063386456 | Jul 13 04:39:07 PM PDT 24 | Jul 13 04:39:08 PM PDT 24 | 13344340 ps | ||
| T1283 | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.344578675 | Jul 13 04:38:38 PM PDT 24 | Jul 13 04:38:40 PM PDT 24 | 37323506 ps | ||
| T1284 | /workspace/coverage/cover_reg_top/42.uart_intr_test.823300859 | Jul 13 04:38:56 PM PDT 24 | Jul 13 04:38:58 PM PDT 24 | 13487034 ps | ||
| T1285 | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1881180662 | Jul 13 04:38:36 PM PDT 24 | Jul 13 04:38:39 PM PDT 24 | 255406721 ps | ||
| T1286 | /workspace/coverage/cover_reg_top/45.uart_intr_test.1727317511 | Jul 13 04:39:04 PM PDT 24 | Jul 13 04:39:05 PM PDT 24 | 30403997 ps | ||
| T1287 | /workspace/coverage/cover_reg_top/22.uart_intr_test.52294678 | Jul 13 04:38:58 PM PDT 24 | Jul 13 04:38:59 PM PDT 24 | 24923929 ps | ||
| T1288 | /workspace/coverage/cover_reg_top/2.uart_tl_errors.2144847997 | Jul 13 04:38:47 PM PDT 24 | Jul 13 04:38:49 PM PDT 24 | 283504017 ps | ||
| T1289 | /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.540290350 | Jul 13 04:38:49 PM PDT 24 | Jul 13 04:38:51 PM PDT 24 | 19333867 ps | ||
| T83 | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2949683899 | Jul 13 04:38:43 PM PDT 24 | Jul 13 04:38:45 PM PDT 24 | 307650243 ps | ||
| T1290 | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1890026052 | Jul 13 04:38:48 PM PDT 24 | Jul 13 04:38:50 PM PDT 24 | 58983794 ps | ||
| T1291 | /workspace/coverage/cover_reg_top/36.uart_intr_test.679223403 | Jul 13 04:39:12 PM PDT 24 | Jul 13 04:39:14 PM PDT 24 | 38467703 ps | ||
| T1292 | /workspace/coverage/cover_reg_top/0.uart_intr_test.3619860974 | Jul 13 04:38:43 PM PDT 24 | Jul 13 04:38:45 PM PDT 24 | 46063008 ps | ||
| T1293 | /workspace/coverage/cover_reg_top/15.uart_intr_test.4239822445 | Jul 13 04:38:47 PM PDT 24 | Jul 13 04:38:55 PM PDT 24 | 13300874 ps | ||
| T1294 | /workspace/coverage/cover_reg_top/37.uart_intr_test.3300866722 | Jul 13 04:38:48 PM PDT 24 | Jul 13 04:38:50 PM PDT 24 | 14577459 ps | ||
| T1295 | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.14361020 | Jul 13 04:38:45 PM PDT 24 | Jul 13 04:38:47 PM PDT 24 | 56437998 ps | ||
| T1296 | /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4206620779 | Jul 13 04:38:34 PM PDT 24 | Jul 13 04:38:37 PM PDT 24 | 93854988 ps | ||
| T1297 | /workspace/coverage/cover_reg_top/48.uart_intr_test.2023647909 | Jul 13 04:39:24 PM PDT 24 | Jul 13 04:39:26 PM PDT 24 | 38261650 ps | ||
| T1298 | /workspace/coverage/cover_reg_top/38.uart_intr_test.2690721216 | Jul 13 04:39:08 PM PDT 24 | Jul 13 04:39:09 PM PDT 24 | 14532180 ps | ||
| T1299 | /workspace/coverage/cover_reg_top/9.uart_tl_errors.1126898266 | Jul 13 04:38:49 PM PDT 24 | Jul 13 04:38:51 PM PDT 24 | 188027346 ps | ||
| T1300 | /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.540824343 | Jul 13 04:38:26 PM PDT 24 | Jul 13 04:38:31 PM PDT 24 | 260708180 ps | ||
| T58 | /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2723126188 | Jul 13 04:38:25 PM PDT 24 | Jul 13 04:38:29 PM PDT 24 | 94061486 ps | ||
| T1301 | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1717160233 | Jul 13 04:38:31 PM PDT 24 | Jul 13 04:38:34 PM PDT 24 | 21918426 ps | ||
| T1302 | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2103216345 | Jul 13 04:38:39 PM PDT 24 | Jul 13 04:38:42 PM PDT 24 | 83371573 ps | ||
| T1303 | /workspace/coverage/cover_reg_top/7.uart_intr_test.1308774810 | Jul 13 04:38:47 PM PDT 24 | Jul 13 04:38:49 PM PDT 24 | 40364709 ps | ||
| T110 | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1464814103 | Jul 13 04:38:41 PM PDT 24 | Jul 13 04:38:43 PM PDT 24 | 213360275 ps | ||
| T1304 | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4123832585 | Jul 13 04:38:34 PM PDT 24 | Jul 13 04:38:36 PM PDT 24 | 73952389 ps | ||
| T1305 | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1620584946 | Jul 13 04:38:51 PM PDT 24 | Jul 13 04:38:54 PM PDT 24 | 164821742 ps | ||
| T1306 | /workspace/coverage/cover_reg_top/33.uart_intr_test.2620196372 | Jul 13 04:38:49 PM PDT 24 | Jul 13 04:38:51 PM PDT 24 | 36432032 ps | ||
| T1307 | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.961100554 | Jul 13 04:38:36 PM PDT 24 | Jul 13 04:38:39 PM PDT 24 | 88935896 ps | ||
| T1308 | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1003005801 | Jul 13 04:38:51 PM PDT 24 | Jul 13 04:38:53 PM PDT 24 | 91357873 ps | ||
| T1309 | /workspace/coverage/cover_reg_top/6.uart_intr_test.4159299377 | Jul 13 04:38:36 PM PDT 24 | Jul 13 04:38:38 PM PDT 24 | 18285018 ps | ||
| T1310 | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.968727724 | Jul 13 04:38:53 PM PDT 24 | Jul 13 04:38:56 PM PDT 24 | 49985098 ps | ||
| T1311 | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1358443501 | Jul 13 04:38:43 PM PDT 24 | Jul 13 04:38:45 PM PDT 24 | 57928458 ps | ||
| T1312 | /workspace/coverage/cover_reg_top/2.uart_intr_test.2440674062 | Jul 13 04:38:32 PM PDT 24 | Jul 13 04:38:35 PM PDT 24 | 80886000 ps | ||
| T1313 | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4079903148 | Jul 13 04:38:56 PM PDT 24 | Jul 13 04:38:58 PM PDT 24 | 18338207 ps |
| Test location | /workspace/coverage/default/26.uart_fifo_reset.447134232 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 123977603658 ps |
| CPU time | 39.17 seconds |
| Started | Jul 13 06:00:21 PM PDT 24 |
| Finished | Jul 13 06:01:01 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-4cc60bc9-0c64-4277-95a3-df960d161fa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447134232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.447134232 |
| Directory | /workspace/26.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1703396369 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 190351410994 ps |
| CPU time | 618.13 seconds |
| Started | Jul 13 06:03:23 PM PDT 24 |
| Finished | Jul 13 06:13:43 PM PDT 24 |
| Peak memory | 216592 kb |
| Host | smart-f56ccd62-f116-4d99-aae9-aa77bbc3bddc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703396369 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1703396369 |
| Directory | /workspace/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/274.uart_fifo_reset.1563097568 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28856836833 ps |
| CPU time | 16.11 seconds |
| Started | Jul 13 06:04:41 PM PDT 24 |
| Finished | Jul 13 06:04:58 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-dec2889e-c1fd-4cca-b4a9-c856fbbdc0b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563097568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1563097568 |
| Directory | /workspace/274.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2705198162 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 326593126670 ps |
| CPU time | 1293 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:24:25 PM PDT 24 |
| Peak memory | 226580 kb |
| Host | smart-8547fe71-0967-46db-8a24-c658ff783b41 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705198162 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2705198162 |
| Directory | /workspace/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all.528749702 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 356626760371 ps |
| CPU time | 553 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 06:08:39 PM PDT 24 |
| Peak memory | 208072 kb |
| Host | smart-fd0afc26-2ee9-4d3c-9a2e-d00340c1108e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528749702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.528749702 |
| Directory | /workspace/15.uart_stress_all/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1077464565 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 330526743727 ps |
| CPU time | 940.84 seconds |
| Started | Jul 13 05:59:28 PM PDT 24 |
| Finished | Jul 13 06:15:09 PM PDT 24 |
| Peak memory | 224776 kb |
| Host | smart-8d600699-46ed-490f-8abb-10323cedb047 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077464565 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1077464565 |
| Directory | /workspace/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2880409542 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 69831907172 ps |
| CPU time | 1159.01 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:22:45 PM PDT 24 |
| Peak memory | 224720 kb |
| Host | smart-4f1e87dd-f010-460f-901f-88fcf82602a6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880409542 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2880409542 |
| Directory | /workspace/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3005582094 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 135028130324 ps |
| CPU time | 681.79 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 06:10:15 PM PDT 24 |
| Peak memory | 216480 kb |
| Host | smart-7af8b310-27b1-40de-8557-b2182dd4ecd8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005582094 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3005582094 |
| Directory | /workspace/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/70.uart_stress_all_with_rand_reset.635185543 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 127083332807 ps |
| CPU time | 703.45 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:14:49 PM PDT 24 |
| Peak memory | 224872 kb |
| Host | smart-3bf6b611-fca2-4d6f-858a-e14c45dedea4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635185543 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.635185543 |
| Directory | /workspace/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.uart_sec_cm.3137133827 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 227354343 ps |
| CPU time | 0.78 seconds |
| Started | Jul 13 05:58:44 PM PDT 24 |
| Finished | Jul 13 05:58:45 PM PDT 24 |
| Peak memory | 218276 kb |
| Host | smart-a3f297d2-c228-45b9-a4d3-dafcdda61431 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137133827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3137133827 |
| Directory | /workspace/1.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all.1782316025 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 278323289281 ps |
| CPU time | 300.51 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 06:04:20 PM PDT 24 |
| Peak memory | 216436 kb |
| Host | smart-64b9b73c-d0f5-4647-b2ec-674ef42ef7d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782316025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1782316025 |
| Directory | /workspace/11.uart_stress_all/latest |
| Test location | /workspace/coverage/default/51.uart_stress_all_with_rand_reset.976706911 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 103974904415 ps |
| CPU time | 559.74 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:12:12 PM PDT 24 |
| Peak memory | 216404 kb |
| Host | smart-ac36d23c-950d-4425-bec9-55d846c6dcb6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976706911 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.976706911 |
| Directory | /workspace/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/94.uart_stress_all_with_rand_reset.4130929833 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 220078084770 ps |
| CPU time | 1551.69 seconds |
| Started | Jul 13 06:03:29 PM PDT 24 |
| Finished | Jul 13 06:29:22 PM PDT 24 |
| Peak memory | 230652 kb |
| Host | smart-a008bfe0-df01-4199-9d4a-bd99d263acbb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130929833 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4130929833 |
| Directory | /workspace/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1852310461 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 104303605695 ps |
| CPU time | 431.26 seconds |
| Started | Jul 13 06:00:16 PM PDT 24 |
| Finished | Jul 13 06:07:28 PM PDT 24 |
| Peak memory | 216596 kb |
| Host | smart-0b5cc406-c26d-419e-9a21-5e9fe0bc0a39 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852310461 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1852310461 |
| Directory | /workspace/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all_with_rand_reset.4113965085 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 829092207515 ps |
| CPU time | 671.73 seconds |
| Started | Jul 13 05:59:26 PM PDT 24 |
| Finished | Jul 13 06:10:39 PM PDT 24 |
| Peak memory | 229980 kb |
| Host | smart-5f61ee48-d996-49f1-ba16-f4d1f8d2c170 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113965085 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.4113965085 |
| Directory | /workspace/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2791806717 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 322003619 ps |
| CPU time | 1.33 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:50 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-f277b9fb-a8d6-458e-bb56-f92a859848d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791806717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2791806717 |
| Directory | /workspace/1.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4025879263 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 100836300568 ps |
| CPU time | 728.34 seconds |
| Started | Jul 13 05:58:41 PM PDT 24 |
| Finished | Jul 13 06:10:50 PM PDT 24 |
| Peak memory | 224840 kb |
| Host | smart-198a2f1a-82e4-4e08-9ceb-b48ea1809aae |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025879263 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4025879263 |
| Directory | /workspace/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all.600932095 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 276825594382 ps |
| CPU time | 303.69 seconds |
| Started | Jul 13 05:59:44 PM PDT 24 |
| Finished | Jul 13 06:04:48 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-a52b30e0-c93d-4c70-b058-35c55a8fd1c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600932095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.600932095 |
| Directory | /workspace/17.uart_stress_all/latest |
| Test location | /workspace/coverage/default/53.uart_fifo_reset.1777471944 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 97447370208 ps |
| CPU time | 40.15 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:03:30 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-a6efdb6d-cbbc-484a-aeac-05d68055385d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777471944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1777471944 |
| Directory | /workspace/53.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_alert_test.4114467785 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 72722772 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 05:59:24 PM PDT 24 |
| Finished | Jul 13 05:59:25 PM PDT 24 |
| Peak memory | 195236 kb |
| Host | smart-b8de18a4-b723-462b-b022-25bf4d80168a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114467785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.4114467785 |
| Directory | /workspace/13.uart_alert_test/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2284550600 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 153370090654 ps |
| CPU time | 1418.21 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:23:31 PM PDT 24 |
| Peak memory | 224632 kb |
| Host | smart-c08ea0f2-d126-48ad-b452-30dd233f676d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284550600 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2284550600 |
| Directory | /workspace/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all.1512250953 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 293444350770 ps |
| CPU time | 540.63 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:09:16 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-32f15052-6c98-4172-8d8a-2d95b937ce18 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512250953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1512250953 |
| Directory | /workspace/25.uart_stress_all/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all.2273432974 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 277474078465 ps |
| CPU time | 125.21 seconds |
| Started | Jul 13 06:00:30 PM PDT 24 |
| Finished | Jul 13 06:02:36 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-2d36bc98-e06f-4125-908c-7010d30eafda |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273432974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2273432974 |
| Directory | /workspace/27.uart_stress_all/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all.3916850736 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 115065162806 ps |
| CPU time | 113.95 seconds |
| Started | Jul 13 06:00:46 PM PDT 24 |
| Finished | Jul 13 06:02:41 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-ece34f4c-6f42-4ee8-98b0-4502c5ade9c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916850736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3916850736 |
| Directory | /workspace/30.uart_stress_all/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_reset.1813514997 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 66364139565 ps |
| CPU time | 32.71 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:59:18 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-18644940-7b8e-4fa8-a869-64e4ff49a602 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813514997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1813514997 |
| Directory | /workspace/2.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_rw.2354330339 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 54030416 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:38:27 PM PDT 24 |
| Finished | Jul 13 04:38:30 PM PDT 24 |
| Peak memory | 196240 kb |
| Host | smart-b6096830-3578-44ae-98b4-e955f624a7d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354330339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2354330339 |
| Directory | /workspace/0.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_rw.2775723114 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 55882645 ps |
| CPU time | 0.6 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 196156 kb |
| Host | smart-07004781-5d56-4fc1-af4d-5458e2d1b111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775723114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2775723114 |
| Directory | /workspace/10.uart_csr_rw/latest |
| Test location | /workspace/coverage/default/223.uart_fifo_reset.791046876 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 24089849214 ps |
| CPU time | 36.32 seconds |
| Started | Jul 13 06:04:19 PM PDT 24 |
| Finished | Jul 13 06:04:57 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-a48c20e2-9093-497c-aaf3-fdffe797c071 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791046876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.791046876 |
| Directory | /workspace/223.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/289.uart_fifo_reset.1856946693 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 34598862873 ps |
| CPU time | 21.85 seconds |
| Started | Jul 13 06:04:51 PM PDT 24 |
| Finished | Jul 13 06:05:13 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-652a6bb0-0f09-4c0b-b914-ec60f7470805 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856946693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1856946693 |
| Directory | /workspace/289.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_reset.2082116987 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 100763877058 ps |
| CPU time | 250.42 seconds |
| Started | Jul 13 06:02:09 PM PDT 24 |
| Finished | Jul 13 06:06:20 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-4ea1d85a-6c25-458b-a690-7ea6133bd0b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082116987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2082116987 |
| Directory | /workspace/45.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/43.uart_rx_parity_err.3070363442 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 210133658202 ps |
| CPU time | 81.8 seconds |
| Started | Jul 13 06:02:07 PM PDT 24 |
| Finished | Jul 13 06:03:29 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-949d0af8-e77d-45d1-b809-3682882d0d55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070363442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3070363442 |
| Directory | /workspace/43.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/124.uart_fifo_reset.4166015100 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 38116279818 ps |
| CPU time | 31.58 seconds |
| Started | Jul 13 06:03:33 PM PDT 24 |
| Finished | Jul 13 06:04:06 PM PDT 24 |
| Peak memory | 199652 kb |
| Host | smart-6422180f-bc61-4e94-9da1-05a0f1f1ca35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166015100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4166015100 |
| Directory | /workspace/124.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3046712766 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 144691326099 ps |
| CPU time | 449.4 seconds |
| Started | Jul 13 06:03:07 PM PDT 24 |
| Finished | Jul 13 06:10:38 PM PDT 24 |
| Peak memory | 216376 kb |
| Host | smart-45b8de8e-e252-4921-bfb9-7045a4c3f924 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046712766 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3046712766 |
| Directory | /workspace/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/213.uart_fifo_reset.3091120896 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 198055459096 ps |
| CPU time | 372.96 seconds |
| Started | Jul 13 06:04:19 PM PDT 24 |
| Finished | Jul 13 06:10:33 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-fe5be0b5-2751-4756-83ff-33d9845076a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091120896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3091120896 |
| Directory | /workspace/213.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2949683899 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 307650243 ps |
| CPU time | 1.32 seconds |
| Started | Jul 13 04:38:43 PM PDT 24 |
| Finished | Jul 13 04:38:45 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-b7d5fc0d-7732-4560-8afb-c1ee8bda9a3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949683899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2949683899 |
| Directory | /workspace/17.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/107.uart_fifo_reset.4061647791 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 34300749807 ps |
| CPU time | 28.59 seconds |
| Started | Jul 13 06:03:23 PM PDT 24 |
| Finished | Jul 13 06:03:54 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-40ea79ac-ab21-4779-916a-c39bf3a76ef0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061647791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.4061647791 |
| Directory | /workspace/107.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/121.uart_fifo_reset.165172236 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 107404754206 ps |
| CPU time | 30.58 seconds |
| Started | Jul 13 06:03:34 PM PDT 24 |
| Finished | Jul 13 06:04:05 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-6646464b-fcbc-40b4-b8e2-8ba08fdb2a6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165172236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.165172236 |
| Directory | /workspace/121.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all.944191849 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 243987656309 ps |
| CPU time | 461.02 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:10:22 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-8c936bdb-b3f2-4451-a034-697150012e6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944191849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.944191849 |
| Directory | /workspace/48.uart_stress_all/latest |
| Test location | /workspace/coverage/default/149.uart_fifo_reset.2704418459 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 196814492875 ps |
| CPU time | 334.77 seconds |
| Started | Jul 13 06:03:52 PM PDT 24 |
| Finished | Jul 13 06:09:27 PM PDT 24 |
| Peak memory | 199452 kb |
| Host | smart-7586425d-d66b-49bc-beb3-baa3483aec7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704418459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2704418459 |
| Directory | /workspace/149.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/110.uart_fifo_reset.4217382511 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 35773140934 ps |
| CPU time | 55.61 seconds |
| Started | Jul 13 06:03:22 PM PDT 24 |
| Finished | Jul 13 06:04:19 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-2b03e564-4f22-4deb-a44e-a4abad9b3e76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217382511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4217382511 |
| Directory | /workspace/110.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/150.uart_fifo_reset.3570302880 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 264853490097 ps |
| CPU time | 98.9 seconds |
| Started | Jul 13 06:03:50 PM PDT 24 |
| Finished | Jul 13 06:05:30 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-17682893-6f34-4577-ab4f-1e5f0df5dcf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570302880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3570302880 |
| Directory | /workspace/150.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/157.uart_fifo_reset.4086497566 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 133149520503 ps |
| CPU time | 246.74 seconds |
| Started | Jul 13 06:03:50 PM PDT 24 |
| Finished | Jul 13 06:07:58 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-b6d7cb42-bf43-47a6-be47-5930171ce0a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086497566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4086497566 |
| Directory | /workspace/157.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/233.uart_fifo_reset.3332370008 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 71519691884 ps |
| CPU time | 32.56 seconds |
| Started | Jul 13 06:04:26 PM PDT 24 |
| Finished | Jul 13 06:04:59 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-81aaa4f9-2d05-48da-b384-a363d483768b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332370008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3332370008 |
| Directory | /workspace/233.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_reset.4014871362 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 183607905626 ps |
| CPU time | 126.05 seconds |
| Started | Jul 13 06:02:14 PM PDT 24 |
| Finished | Jul 13 06:04:20 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-76cb3ae1-671d-418b-b254-8fe4887fad97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014871362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4014871362 |
| Directory | /workspace/46.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1375451041 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 215183592255 ps |
| CPU time | 606.04 seconds |
| Started | Jul 13 06:03:13 PM PDT 24 |
| Finished | Jul 13 06:13:20 PM PDT 24 |
| Peak memory | 224832 kb |
| Host | smart-767a6dd2-25ad-4178-b842-778064624435 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375451041 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1375451041 |
| Directory | /workspace/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/111.uart_fifo_reset.2887627936 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 43384286877 ps |
| CPU time | 63 seconds |
| Started | Jul 13 06:03:23 PM PDT 24 |
| Finished | Jul 13 06:04:28 PM PDT 24 |
| Peak memory | 199636 kb |
| Host | smart-068b9cee-7023-4d57-9b2f-8f75f6e7e374 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2887627936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2887627936 |
| Directory | /workspace/111.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/175.uart_fifo_reset.3975677348 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 24912263654 ps |
| CPU time | 7.99 seconds |
| Started | Jul 13 06:04:01 PM PDT 24 |
| Finished | Jul 13 06:04:10 PM PDT 24 |
| Peak memory | 199668 kb |
| Host | smart-e500cde7-8cfa-4f91-b13c-4a2b2d347011 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975677348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3975677348 |
| Directory | /workspace/175.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/186.uart_fifo_reset.1321886267 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 120846985796 ps |
| CPU time | 42.96 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:04:53 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-1d967bdd-3b7a-40aa-9592-910bf3234013 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321886267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1321886267 |
| Directory | /workspace/186.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/204.uart_fifo_reset.1691659996 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 119667750092 ps |
| CPU time | 119.88 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:06:12 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-af934dda-2fdc-4431-9cd2-c1250a2d6c25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1691659996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1691659996 |
| Directory | /workspace/204.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/214.uart_fifo_reset.1104089383 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 88782964252 ps |
| CPU time | 256.06 seconds |
| Started | Jul 13 06:04:17 PM PDT 24 |
| Finished | Jul 13 06:08:33 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-13d3d703-c054-4c10-aa6d-2ffb12ee4f8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104089383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1104089383 |
| Directory | /workspace/214.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/282.uart_fifo_reset.2302703697 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 15820739304 ps |
| CPU time | 26.46 seconds |
| Started | Jul 13 06:04:46 PM PDT 24 |
| Finished | Jul 13 06:05:13 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-48489297-7624-4051-88f7-c0747ef8ff65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302703697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2302703697 |
| Directory | /workspace/282.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1074911028 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 121395168938 ps |
| CPU time | 203.93 seconds |
| Started | Jul 13 06:02:52 PM PDT 24 |
| Finished | Jul 13 06:06:16 PM PDT 24 |
| Peak memory | 213368 kb |
| Host | smart-f89d3971-1700-4768-8d47-f2ff06778c1c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074911028 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1074911028 |
| Directory | /workspace/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/101.uart_fifo_reset.3678362905 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 283242512305 ps |
| CPU time | 120.33 seconds |
| Started | Jul 13 06:03:22 PM PDT 24 |
| Finished | Jul 13 06:05:25 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-a962ca22-69ee-4c55-9803-59c46a0c65a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678362905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3678362905 |
| Directory | /workspace/101.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/105.uart_fifo_reset.1558157827 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 158093944760 ps |
| CPU time | 58.84 seconds |
| Started | Jul 13 06:03:23 PM PDT 24 |
| Finished | Jul 13 06:04:24 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-a64b1cb7-f8a0-4788-9a48-1fb0f8577225 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1558157827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1558157827 |
| Directory | /workspace/105.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/114.uart_fifo_reset.2470215312 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 78630298969 ps |
| CPU time | 70.38 seconds |
| Started | Jul 13 06:03:34 PM PDT 24 |
| Finished | Jul 13 06:04:45 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-acf5f1e1-a8ff-4312-8074-8b1dc9462226 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470215312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2470215312 |
| Directory | /workspace/114.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/115.uart_fifo_reset.159446604 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 31586762404 ps |
| CPU time | 41.95 seconds |
| Started | Jul 13 06:03:33 PM PDT 24 |
| Finished | Jul 13 06:04:16 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-70423cdf-af65-4977-b9e1-87f109aec686 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159446604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.159446604 |
| Directory | /workspace/115.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/148.uart_fifo_reset.1376277577 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 91363572876 ps |
| CPU time | 15.71 seconds |
| Started | Jul 13 06:03:39 PM PDT 24 |
| Finished | Jul 13 06:03:55 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-a20e4ee5-44ff-4861-858a-c394288a3369 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376277577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1376277577 |
| Directory | /workspace/148.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/160.uart_fifo_reset.819973589 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 69599192899 ps |
| CPU time | 28.71 seconds |
| Started | Jul 13 06:04:00 PM PDT 24 |
| Finished | Jul 13 06:04:29 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-8f4a9a44-6a28-4526-b55b-57188fa07326 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819973589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.819973589 |
| Directory | /workspace/160.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/174.uart_fifo_reset.1412896339 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 13073318260 ps |
| CPU time | 21.72 seconds |
| Started | Jul 13 06:04:02 PM PDT 24 |
| Finished | Jul 13 06:04:25 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-45ac67ce-1bb9-47db-902f-36cfce677ce7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412896339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1412896339 |
| Directory | /workspace/174.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/178.uart_fifo_reset.3521695015 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 12302602043 ps |
| CPU time | 10.07 seconds |
| Started | Jul 13 06:04:02 PM PDT 24 |
| Finished | Jul 13 06:04:13 PM PDT 24 |
| Peak memory | 199560 kb |
| Host | smart-c77f4d8b-cafa-4a1f-a90c-13b5742e8a10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521695015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3521695015 |
| Directory | /workspace/178.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/188.uart_fifo_reset.3437712691 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 32230801906 ps |
| CPU time | 42.34 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:04:54 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-bf6a8c61-190f-480c-a262-7a2c0f3f6c7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437712691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3437712691 |
| Directory | /workspace/188.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_reset.1749369037 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 77139101915 ps |
| CPU time | 51.37 seconds |
| Started | Jul 13 05:59:53 PM PDT 24 |
| Finished | Jul 13 06:00:45 PM PDT 24 |
| Peak memory | 199960 kb |
| Host | smart-dfa4b2b3-d542-46bf-a28f-3a9b3a3d6fd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749369037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1749369037 |
| Directory | /workspace/20.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/206.uart_fifo_reset.3904564195 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 76043447357 ps |
| CPU time | 32.86 seconds |
| Started | Jul 13 06:04:14 PM PDT 24 |
| Finished | Jul 13 06:04:48 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-85e0ec5c-1420-4720-91fd-069aab8ddccb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904564195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3904564195 |
| Directory | /workspace/206.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/229.uart_fifo_reset.1438140211 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 80580596032 ps |
| CPU time | 36.45 seconds |
| Started | Jul 13 06:04:17 PM PDT 24 |
| Finished | Jul 13 06:04:55 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-56a33965-42e3-4a83-9c25-8535389c3e77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438140211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1438140211 |
| Directory | /workspace/229.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/251.uart_fifo_reset.416893895 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 23386121755 ps |
| CPU time | 7.22 seconds |
| Started | Jul 13 06:04:35 PM PDT 24 |
| Finished | Jul 13 06:04:43 PM PDT 24 |
| Peak memory | 199668 kb |
| Host | smart-34979c95-db9c-4942-8742-bf5f702ee28b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416893895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.416893895 |
| Directory | /workspace/251.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/268.uart_fifo_reset.231121460 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 21448572344 ps |
| CPU time | 35.23 seconds |
| Started | Jul 13 06:04:39 PM PDT 24 |
| Finished | Jul 13 06:05:15 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-231db726-88e1-4fbf-8798-991ad7a76b49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231121460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.231121460 |
| Directory | /workspace/268.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/278.uart_fifo_reset.1659463426 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 13526150074 ps |
| CPU time | 12.96 seconds |
| Started | Jul 13 06:04:45 PM PDT 24 |
| Finished | Jul 13 06:04:59 PM PDT 24 |
| Peak memory | 200200 kb |
| Host | smart-abbd96f9-f49b-47d7-ac61-69c5ebe2be19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659463426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1659463426 |
| Directory | /workspace/278.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/284.uart_fifo_reset.1385324270 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 36391997076 ps |
| CPU time | 15.62 seconds |
| Started | Jul 13 06:04:44 PM PDT 24 |
| Finished | Jul 13 06:05:01 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-fad1fa0e-8784-4865-81b9-a34e47feb0c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385324270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1385324270 |
| Directory | /workspace/284.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3916998482 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 62190982068 ps |
| CPU time | 183.4 seconds |
| Started | Jul 13 06:00:46 PM PDT 24 |
| Finished | Jul 13 06:03:50 PM PDT 24 |
| Peak memory | 216384 kb |
| Host | smart-9147c64b-86b3-4476-a3ad-cef074f32098 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916998482 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3916998482 |
| Directory | /workspace/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/295.uart_fifo_reset.1245858939 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 75333626693 ps |
| CPU time | 15.98 seconds |
| Started | Jul 13 06:04:51 PM PDT 24 |
| Finished | Jul 13 06:05:07 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-2ee918c9-e72d-4e4a-a7f6-6be8e2bb052f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245858939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1245858939 |
| Directory | /workspace/295.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/297.uart_fifo_reset.880801158 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 55148787512 ps |
| CPU time | 96.21 seconds |
| Started | Jul 13 06:04:52 PM PDT 24 |
| Finished | Jul 13 06:06:29 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-c94901d9-f3c9-4fa2-bcee-0fd8c3212ff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=880801158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.880801158 |
| Directory | /workspace/297.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_reset.963010665 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 151352874960 ps |
| CPU time | 65.18 seconds |
| Started | Jul 13 05:58:44 PM PDT 24 |
| Finished | Jul 13 05:59:51 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-b293cfc7-606c-43f7-9694-f8f6488c0402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963010665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.963010665 |
| Directory | /workspace/3.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_reset.2496768675 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 34643323145 ps |
| CPU time | 56.69 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:02:59 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-f2746d94-ee2b-4cb3-adc9-910e2bfc81bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2496768675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2496768675 |
| Directory | /workspace/43.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/63.uart_fifo_reset.810127727 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 115710548782 ps |
| CPU time | 39.31 seconds |
| Started | Jul 13 06:03:07 PM PDT 24 |
| Finished | Jul 13 06:03:47 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-23e5794d-e1f9-42b6-a248-e3759cf73222 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810127727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.810127727 |
| Directory | /workspace/63.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/78.uart_fifo_reset.3098142622 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 50601007426 ps |
| CPU time | 42.2 seconds |
| Started | Jul 13 06:03:12 PM PDT 24 |
| Finished | Jul 13 06:03:55 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-dc6faf15-1574-4138-b211-e89ad466185a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098142622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3098142622 |
| Directory | /workspace/78.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.220259896 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 30620663 ps |
| CPU time | 0.82 seconds |
| Started | Jul 13 04:38:40 PM PDT 24 |
| Finished | Jul 13 04:38:41 PM PDT 24 |
| Peak memory | 196732 kb |
| Host | smart-70212b92-3c72-4709-bfb8-32b5c965223c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220259896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.220259896 |
| Directory | /workspace/0.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.714749443 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 901688928 ps |
| CPU time | 2.55 seconds |
| Started | Jul 13 04:38:41 PM PDT 24 |
| Finished | Jul 13 04:38:44 PM PDT 24 |
| Peak memory | 198656 kb |
| Host | smart-c7d7e72f-6dae-4c6d-a049-4ff92e68e5d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714749443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.714749443 |
| Directory | /workspace/0.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.344578675 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 37323506 ps |
| CPU time | 0.7 seconds |
| Started | Jul 13 04:38:38 PM PDT 24 |
| Finished | Jul 13 04:38:40 PM PDT 24 |
| Peak memory | 196100 kb |
| Host | smart-9c67b945-ba92-4791-8f97-fe849cc75c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344578675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.344578675 |
| Directory | /workspace/0.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1786996570 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 46660776 ps |
| CPU time | 0.63 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:52 PM PDT 24 |
| Peak memory | 198332 kb |
| Host | smart-985246f7-2e81-4bd0-afa4-559334fc8353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786996570 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1786996570 |
| Directory | /workspace/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_intr_test.3619860974 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 46063008 ps |
| CPU time | 0.61 seconds |
| Started | Jul 13 04:38:43 PM PDT 24 |
| Finished | Jul 13 04:38:45 PM PDT 24 |
| Peak memory | 195060 kb |
| Host | smart-15dc64b4-2f88-4037-82b8-b6fb9e9592da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619860974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3619860974 |
| Directory | /workspace/0.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1717160233 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 21918426 ps |
| CPU time | 0.64 seconds |
| Started | Jul 13 04:38:31 PM PDT 24 |
| Finished | Jul 13 04:38:34 PM PDT 24 |
| Peak memory | 195376 kb |
| Host | smart-dcd662c2-98bd-4efd-b6ae-0ebac30219e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717160233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.1717160233 |
| Directory | /workspace/0.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_errors.2947172194 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 42306944 ps |
| CPU time | 1.12 seconds |
| Started | Jul 13 04:38:32 PM PDT 24 |
| Finished | Jul 13 04:38:35 PM PDT 24 |
| Peak memory | 200428 kb |
| Host | smart-57fb4d4c-66a0-4154-9d9b-834e85d97449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947172194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2947172194 |
| Directory | /workspace/0.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1961383792 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 311452346 ps |
| CPU time | 1.33 seconds |
| Started | Jul 13 04:38:28 PM PDT 24 |
| Finished | Jul 13 04:38:31 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-9ff29822-f6e2-47eb-bda0-68bdbff0e082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961383792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1961383792 |
| Directory | /workspace/0.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1504453675 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 57479482 ps |
| CPU time | 0.72 seconds |
| Started | Jul 13 04:38:30 PM PDT 24 |
| Finished | Jul 13 04:38:33 PM PDT 24 |
| Peak memory | 196936 kb |
| Host | smart-ee3f4dcc-8329-4ae3-841b-09e1bfc77e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504453675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1504453675 |
| Directory | /workspace/1.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.540824343 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 260708180 ps |
| CPU time | 2.47 seconds |
| Started | Jul 13 04:38:26 PM PDT 24 |
| Finished | Jul 13 04:38:31 PM PDT 24 |
| Peak memory | 197828 kb |
| Host | smart-5cff43ce-3aec-46e1-bdec-e6230088d0f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540824343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.540824343 |
| Directory | /workspace/1.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1551809101 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 53948025 ps |
| CPU time | 0.64 seconds |
| Started | Jul 13 04:38:31 PM PDT 24 |
| Finished | Jul 13 04:38:33 PM PDT 24 |
| Peak memory | 196060 kb |
| Host | smart-4d1d168b-5d3b-4f21-984c-7385b027937f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551809101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1551809101 |
| Directory | /workspace/1.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.90208953 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 48265628 ps |
| CPU time | 1.33 seconds |
| Started | Jul 13 04:38:31 PM PDT 24 |
| Finished | Jul 13 04:38:34 PM PDT 24 |
| Peak memory | 200612 kb |
| Host | smart-928ab9cd-4849-4f2b-90a2-325233855052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90208953 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.90208953 |
| Directory | /workspace/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_rw.1932272904 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 13037216 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 04:38:36 PM PDT 24 |
| Finished | Jul 13 04:38:39 PM PDT 24 |
| Peak memory | 196060 kb |
| Host | smart-db9f05b6-1dcc-49cb-a584-bda26c9e966b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932272904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1932272904 |
| Directory | /workspace/1.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_intr_test.3216931606 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 46873890 ps |
| CPU time | 0.6 seconds |
| Started | Jul 13 04:38:23 PM PDT 24 |
| Finished | Jul 13 04:38:26 PM PDT 24 |
| Peak memory | 194912 kb |
| Host | smart-d12bab67-96c6-49fd-987e-219c0166f750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216931606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3216931606 |
| Directory | /workspace/1.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2009218973 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 130351593 ps |
| CPU time | 0.8 seconds |
| Started | Jul 13 04:38:41 PM PDT 24 |
| Finished | Jul 13 04:38:43 PM PDT 24 |
| Peak memory | 197796 kb |
| Host | smart-4fa1efbe-d11b-4edd-abdb-0f59c0590d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009218973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.2009218973 |
| Directory | /workspace/1.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_errors.3649705235 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 42163450 ps |
| CPU time | 1.02 seconds |
| Started | Jul 13 04:38:28 PM PDT 24 |
| Finished | Jul 13 04:38:31 PM PDT 24 |
| Peak memory | 200340 kb |
| Host | smart-302aeb47-93d5-415a-bc26-b1911147806f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649705235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3649705235 |
| Directory | /workspace/1.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.829724836 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 53756329 ps |
| CPU time | 0.65 seconds |
| Started | Jul 13 04:38:34 PM PDT 24 |
| Finished | Jul 13 04:38:37 PM PDT 24 |
| Peak memory | 198560 kb |
| Host | smart-ff1e8559-25a0-488c-bcee-3edc589c1f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829724836 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.829724836 |
| Directory | /workspace/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_intr_test.2280090015 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 12755232 ps |
| CPU time | 0.64 seconds |
| Started | Jul 13 04:39:20 PM PDT 24 |
| Finished | Jul 13 04:39:23 PM PDT 24 |
| Peak memory | 195052 kb |
| Host | smart-c046e52b-80c5-4a2a-81b4-c58df37334b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280090015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2280090015 |
| Directory | /workspace/10.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.739064658 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 122140200 ps |
| CPU time | 0.8 seconds |
| Started | Jul 13 04:38:52 PM PDT 24 |
| Finished | Jul 13 04:38:55 PM PDT 24 |
| Peak memory | 196772 kb |
| Host | smart-5da68e8b-0a6e-4dce-bd1d-a770d2f13afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739064658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr _outstanding.739064658 |
| Directory | /workspace/10.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_errors.3747536834 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 65292942 ps |
| CPU time | 1.04 seconds |
| Started | Jul 13 04:38:37 PM PDT 24 |
| Finished | Jul 13 04:38:40 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-583879cd-954f-49cb-ae2a-3879a8a1fa8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747536834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3747536834 |
| Directory | /workspace/10.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1890026052 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 58983794 ps |
| CPU time | 0.87 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:50 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-eb0c982a-3a27-4631-bbe5-afacd401583f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890026052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1890026052 |
| Directory | /workspace/10.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4123832585 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 73952389 ps |
| CPU time | 0.65 seconds |
| Started | Jul 13 04:38:34 PM PDT 24 |
| Finished | Jul 13 04:38:36 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-25fcdfa5-48d5-4c3e-b90d-1e49ed5bcc2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123832585 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4123832585 |
| Directory | /workspace/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_rw.697390548 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 85477806 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:42 PM PDT 24 |
| Peak memory | 196220 kb |
| Host | smart-6ca7362c-6007-419f-af8e-0b638c87d9b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697390548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.697390548 |
| Directory | /workspace/11.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_intr_test.1664506254 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 35976694 ps |
| CPU time | 0.63 seconds |
| Started | Jul 13 04:38:37 PM PDT 24 |
| Finished | Jul 13 04:38:40 PM PDT 24 |
| Peak memory | 195072 kb |
| Host | smart-ae602593-559b-4030-8a1c-3a9d53ec89d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664506254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1664506254 |
| Directory | /workspace/11.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3611632682 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 22638956 ps |
| CPU time | 0.64 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:42 PM PDT 24 |
| Peak memory | 196472 kb |
| Host | smart-6b051ebb-0344-43d3-a65d-0af2a173db19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611632682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.3611632682 |
| Directory | /workspace/11.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_errors.668883210 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 23330768 ps |
| CPU time | 1.2 seconds |
| Started | Jul 13 04:38:41 PM PDT 24 |
| Finished | Jul 13 04:38:48 PM PDT 24 |
| Peak memory | 200680 kb |
| Host | smart-aa3b5245-2e77-4508-a31c-688aef93d824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668883210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.668883210 |
| Directory | /workspace/11.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1660671940 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 75341274 ps |
| CPU time | 0.91 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:37 PM PDT 24 |
| Peak memory | 199340 kb |
| Host | smart-6909cece-6a24-41fc-8b07-cf294c31ae94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660671940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1660671940 |
| Directory | /workspace/11.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3313323904 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 21596927 ps |
| CPU time | 0.66 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 198436 kb |
| Host | smart-cc9d640f-4bfa-466f-83d3-90eb70e08b83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313323904 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3313323904 |
| Directory | /workspace/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_rw.1394466955 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 14306345 ps |
| CPU time | 0.6 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:37 PM PDT 24 |
| Peak memory | 196076 kb |
| Host | smart-a6fc271e-d36c-4b5d-b24a-0cf83be09303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394466955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1394466955 |
| Directory | /workspace/12.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_intr_test.2609273393 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 39133688 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:38 PM PDT 24 |
| Peak memory | 195044 kb |
| Host | smart-684b747e-beef-4213-b6f6-9f4f1266f775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609273393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2609273393 |
| Directory | /workspace/12.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.899869330 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 33076953 ps |
| CPU time | 0.73 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:58 PM PDT 24 |
| Peak memory | 198168 kb |
| Host | smart-c8a023a8-e60d-4588-8a77-d9e2dcf90146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899869330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr _outstanding.899869330 |
| Directory | /workspace/12.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_errors.1700572544 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 372926997 ps |
| CPU time | 1.74 seconds |
| Started | Jul 13 04:38:37 PM PDT 24 |
| Finished | Jul 13 04:38:40 PM PDT 24 |
| Peak memory | 200728 kb |
| Host | smart-d29f82b8-c4ee-4044-bb25-845f8919ad15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700572544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1700572544 |
| Directory | /workspace/12.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.647622081 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 75967347 ps |
| CPU time | 0.9 seconds |
| Started | Jul 13 04:38:36 PM PDT 24 |
| Finished | Jul 13 04:38:43 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-e395bc7e-40f2-4272-81b5-f198a249323c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647622081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.647622081 |
| Directory | /workspace/12.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3636686443 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 15942255 ps |
| CPU time | 0.76 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:37 PM PDT 24 |
| Peak memory | 199564 kb |
| Host | smart-5263216c-d42f-4494-825b-31fa7a523a64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636686443 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3636686443 |
| Directory | /workspace/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_rw.2235332752 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 32995914 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 04:39:31 PM PDT 24 |
| Finished | Jul 13 04:39:34 PM PDT 24 |
| Peak memory | 196072 kb |
| Host | smart-bd11457c-4c85-4591-895f-82df359d5ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235332752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2235332752 |
| Directory | /workspace/13.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_intr_test.813535896 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 52336721 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:53 PM PDT 24 |
| Peak memory | 195052 kb |
| Host | smart-73f16d23-b8ac-449b-aa61-1b51adfa42ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813535896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.813535896 |
| Directory | /workspace/13.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4052049187 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 72070316 ps |
| CPU time | 0.66 seconds |
| Started | Jul 13 04:38:50 PM PDT 24 |
| Finished | Jul 13 04:38:52 PM PDT 24 |
| Peak memory | 197108 kb |
| Host | smart-f8dc8741-6f17-48be-842e-a7685a2eec64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052049187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.4052049187 |
| Directory | /workspace/13.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_errors.3121617538 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 331913966 ps |
| CPU time | 1.56 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:38 PM PDT 24 |
| Peak memory | 200636 kb |
| Host | smart-4c9ed005-3a11-4acc-a80f-467b90fb9f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121617538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3121617538 |
| Directory | /workspace/13.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1881180662 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 255406721 ps |
| CPU time | 1.28 seconds |
| Started | Jul 13 04:38:36 PM PDT 24 |
| Finished | Jul 13 04:38:39 PM PDT 24 |
| Peak memory | 200056 kb |
| Host | smart-5de8e133-a5fe-49e5-abe4-ff0ebd484096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881180662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1881180662 |
| Directory | /workspace/13.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3975329289 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 25896847 ps |
| CPU time | 0.74 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 199988 kb |
| Host | smart-6aeb2a6c-cd9b-42f0-a870-fb6671bb08bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975329289 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3975329289 |
| Directory | /workspace/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_rw.3982870983 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 21224425 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 04:38:50 PM PDT 24 |
| Finished | Jul 13 04:38:52 PM PDT 24 |
| Peak memory | 196168 kb |
| Host | smart-556a622a-0bc9-4895-9814-f8b24dc3aa4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982870983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3982870983 |
| Directory | /workspace/14.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_intr_test.3721573038 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 99805881 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:38 PM PDT 24 |
| Finished | Jul 13 04:38:40 PM PDT 24 |
| Peak memory | 195032 kb |
| Host | smart-c6921588-1ce3-4b93-a432-50c95b38173a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721573038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3721573038 |
| Directory | /workspace/14.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.402680702 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 57227683 ps |
| CPU time | 0.77 seconds |
| Started | Jul 13 04:38:52 PM PDT 24 |
| Finished | Jul 13 04:39:04 PM PDT 24 |
| Peak memory | 196720 kb |
| Host | smart-cfcc8c17-d30b-4460-832e-bcb882b65812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402680702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr _outstanding.402680702 |
| Directory | /workspace/14.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_errors.3100655184 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 103575076 ps |
| CPU time | 0.98 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:56 PM PDT 24 |
| Peak memory | 200500 kb |
| Host | smart-c696bef4-59ca-43b8-9cdc-73682f4d7af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100655184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3100655184 |
| Directory | /workspace/14.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2103216345 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 83371573 ps |
| CPU time | 1.18 seconds |
| Started | Jul 13 04:38:39 PM PDT 24 |
| Finished | Jul 13 04:38:42 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-e12b3a8c-78b8-45b5-89c1-d8c8a6623d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103216345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2103216345 |
| Directory | /workspace/14.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3340972529 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 101309983 ps |
| CPU time | 0.92 seconds |
| Started | Jul 13 04:38:36 PM PDT 24 |
| Finished | Jul 13 04:38:38 PM PDT 24 |
| Peak memory | 200492 kb |
| Host | smart-87ab269c-885b-49c7-b66e-3d1063ff83d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340972529 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3340972529 |
| Directory | /workspace/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_rw.1436497603 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 12474449 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:37 PM PDT 24 |
| Finished | Jul 13 04:38:39 PM PDT 24 |
| Peak memory | 196076 kb |
| Host | smart-c3845d64-c7b3-419b-af42-87d4e76b9625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436497603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1436497603 |
| Directory | /workspace/15.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_intr_test.4239822445 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 13300874 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 04:38:47 PM PDT 24 |
| Finished | Jul 13 04:38:55 PM PDT 24 |
| Peak memory | 195312 kb |
| Host | smart-f3e8a3e2-d555-4124-a969-b05a1325df3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239822445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.4239822445 |
| Directory | /workspace/15.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1358443501 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 57928458 ps |
| CPU time | 0.76 seconds |
| Started | Jul 13 04:38:43 PM PDT 24 |
| Finished | Jul 13 04:38:45 PM PDT 24 |
| Peak memory | 197628 kb |
| Host | smart-a99800e1-d03d-4043-a201-c476716b8ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358443501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.1358443501 |
| Directory | /workspace/15.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_errors.2696457912 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 30998077 ps |
| CPU time | 1.57 seconds |
| Started | Jul 13 04:38:37 PM PDT 24 |
| Finished | Jul 13 04:38:41 PM PDT 24 |
| Peak memory | 200660 kb |
| Host | smart-39b27103-0797-460e-8d23-78663ddb5633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696457912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2696457912 |
| Directory | /workspace/15.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2637120623 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 143313405 ps |
| CPU time | 0.95 seconds |
| Started | Jul 13 04:39:26 PM PDT 24 |
| Finished | Jul 13 04:39:30 PM PDT 24 |
| Peak memory | 199404 kb |
| Host | smart-a6c2ea9b-f08e-4ebc-9c82-a497f6fe5fa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637120623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2637120623 |
| Directory | /workspace/15.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2593769189 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 95265387 ps |
| CPU time | 1.05 seconds |
| Started | Jul 13 04:38:52 PM PDT 24 |
| Finished | Jul 13 04:38:55 PM PDT 24 |
| Peak memory | 200696 kb |
| Host | smart-a5e1c4d7-ded1-4729-abac-9df1fe53393f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593769189 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2593769189 |
| Directory | /workspace/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_rw.860241932 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 42378981 ps |
| CPU time | 0.63 seconds |
| Started | Jul 13 04:39:26 PM PDT 24 |
| Finished | Jul 13 04:39:30 PM PDT 24 |
| Peak memory | 196072 kb |
| Host | smart-240650e9-3951-433a-8f9b-5d072edeac14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860241932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.860241932 |
| Directory | /workspace/16.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_intr_test.4086156506 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 13101250 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:38:47 PM PDT 24 |
| Finished | Jul 13 04:38:48 PM PDT 24 |
| Peak memory | 195056 kb |
| Host | smart-353d0ec6-64d4-4186-bb9f-5a4f447246da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086156506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4086156506 |
| Directory | /workspace/16.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.860739350 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 32512343 ps |
| CPU time | 0.65 seconds |
| Started | Jul 13 04:38:37 PM PDT 24 |
| Finished | Jul 13 04:38:39 PM PDT 24 |
| Peak memory | 196560 kb |
| Host | smart-0c277613-f3d8-4dea-bd00-1fd30c001609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860739350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr _outstanding.860739350 |
| Directory | /workspace/16.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_errors.2558027303 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 81551648 ps |
| CPU time | 2.13 seconds |
| Started | Jul 13 04:38:57 PM PDT 24 |
| Finished | Jul 13 04:39:01 PM PDT 24 |
| Peak memory | 200716 kb |
| Host | smart-0971f633-f9ca-4448-bc6e-3b5064276416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558027303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2558027303 |
| Directory | /workspace/16.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.968727724 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 49985098 ps |
| CPU time | 0.98 seconds |
| Started | Jul 13 04:38:53 PM PDT 24 |
| Finished | Jul 13 04:38:56 PM PDT 24 |
| Peak memory | 199588 kb |
| Host | smart-3f8802d9-6889-4af3-bc3f-76f77e60b6d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968727724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.968727724 |
| Directory | /workspace/16.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4288167613 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 20165146 ps |
| CPU time | 0.92 seconds |
| Started | Jul 13 04:39:11 PM PDT 24 |
| Finished | Jul 13 04:39:12 PM PDT 24 |
| Peak memory | 200480 kb |
| Host | smart-04039611-7b23-4950-bd98-00def7222f02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288167613 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4288167613 |
| Directory | /workspace/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_rw.108508687 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 29313343 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:38:52 PM PDT 24 |
| Finished | Jul 13 04:38:55 PM PDT 24 |
| Peak memory | 196636 kb |
| Host | smart-abd2b912-6b3f-4c4d-a9f0-808eb7310cf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108508687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.108508687 |
| Directory | /workspace/17.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_intr_test.1036209256 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 12691772 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:37 PM PDT 24 |
| Finished | Jul 13 04:38:39 PM PDT 24 |
| Peak memory | 195076 kb |
| Host | smart-3853151d-5f9f-4648-9eb9-ee0f260b799e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036209256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1036209256 |
| Directory | /workspace/17.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.541593999 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 26516134 ps |
| CPU time | 0.79 seconds |
| Started | Jul 13 04:39:10 PM PDT 24 |
| Finished | Jul 13 04:39:11 PM PDT 24 |
| Peak memory | 197720 kb |
| Host | smart-1104ce4f-529f-4f47-bfa8-12c9083d278a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541593999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr _outstanding.541593999 |
| Directory | /workspace/17.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_errors.3463050156 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 379445274 ps |
| CPU time | 1.75 seconds |
| Started | Jul 13 04:38:38 PM PDT 24 |
| Finished | Jul 13 04:38:41 PM PDT 24 |
| Peak memory | 200704 kb |
| Host | smart-04ae502b-03c2-4620-8dee-f5ea993e16ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463050156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3463050156 |
| Directory | /workspace/17.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1126942195 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 29421714 ps |
| CPU time | 0.82 seconds |
| Started | Jul 13 04:38:54 PM PDT 24 |
| Finished | Jul 13 04:38:57 PM PDT 24 |
| Peak memory | 200488 kb |
| Host | smart-d7dfc9a7-2cd7-43ab-b449-8fe055db2280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126942195 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1126942195 |
| Directory | /workspace/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_rw.2324147382 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 71778507 ps |
| CPU time | 0.63 seconds |
| Started | Jul 13 04:39:02 PM PDT 24 |
| Finished | Jul 13 04:39:04 PM PDT 24 |
| Peak memory | 196088 kb |
| Host | smart-2f5abf69-9449-49ca-8c2d-1177f0c7240c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324147382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2324147382 |
| Directory | /workspace/18.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_intr_test.755608399 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 14090053 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 04:39:02 PM PDT 24 |
| Finished | Jul 13 04:39:03 PM PDT 24 |
| Peak memory | 194988 kb |
| Host | smart-43bcf0bd-44d6-440b-9986-4ea153ca920a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755608399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.755608399 |
| Directory | /workspace/18.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3714733937 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 45226490 ps |
| CPU time | 0.64 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:52 PM PDT 24 |
| Peak memory | 196272 kb |
| Host | smart-5c41f27c-72fd-4135-a99e-e6fdb86481bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714733937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.3714733937 |
| Directory | /workspace/18.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_errors.3315131018 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 73588476 ps |
| CPU time | 1.87 seconds |
| Started | Jul 13 04:38:55 PM PDT 24 |
| Finished | Jul 13 04:38:58 PM PDT 24 |
| Peak memory | 200664 kb |
| Host | smart-1f7b858c-2e0b-42a5-9036-05601d2b02e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315131018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3315131018 |
| Directory | /workspace/18.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1799587638 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 83440564 ps |
| CPU time | 1.33 seconds |
| Started | Jul 13 04:38:53 PM PDT 24 |
| Finished | Jul 13 04:38:56 PM PDT 24 |
| Peak memory | 200496 kb |
| Host | smart-a504f13f-39f2-4293-9a35-44fe5ec61704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799587638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1799587638 |
| Directory | /workspace/18.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4079903148 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 18338207 ps |
| CPU time | 0.72 seconds |
| Started | Jul 13 04:38:56 PM PDT 24 |
| Finished | Jul 13 04:38:58 PM PDT 24 |
| Peak memory | 199368 kb |
| Host | smart-18d1cc28-b2c8-4d37-8400-218b1ca83e28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079903148 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4079903148 |
| Directory | /workspace/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_rw.2851334988 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 27875435 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:38:53 PM PDT 24 |
| Finished | Jul 13 04:38:56 PM PDT 24 |
| Peak memory | 196032 kb |
| Host | smart-69e7a114-fb59-4f3b-bf0e-0f9df06a1b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851334988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2851334988 |
| Directory | /workspace/19.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_intr_test.3473089309 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 27134833 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:53 PM PDT 24 |
| Peak memory | 195036 kb |
| Host | smart-eefbd11c-2d99-44c2-8919-10636be2a929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473089309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3473089309 |
| Directory | /workspace/19.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1552691446 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 63868444 ps |
| CPU time | 0.65 seconds |
| Started | Jul 13 04:38:47 PM PDT 24 |
| Finished | Jul 13 04:38:55 PM PDT 24 |
| Peak memory | 196340 kb |
| Host | smart-fefd0efd-7623-4f7c-b496-7a47de6ffb5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552691446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.1552691446 |
| Directory | /workspace/19.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_errors.2818184886 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 663139807 ps |
| CPU time | 1.64 seconds |
| Started | Jul 13 04:38:54 PM PDT 24 |
| Finished | Jul 13 04:38:57 PM PDT 24 |
| Peak memory | 200668 kb |
| Host | smart-a844b1a4-234f-46dc-b51f-40202be8e29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818184886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2818184886 |
| Directory | /workspace/19.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1620584946 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 164821742 ps |
| CPU time | 1.28 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:54 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-500f6570-64b9-4873-9d93-cfe3be75ace3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620584946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1620584946 |
| Directory | /workspace/19.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.520595773 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 12856122 ps |
| CPU time | 0.66 seconds |
| Started | Jul 13 04:38:31 PM PDT 24 |
| Finished | Jul 13 04:38:33 PM PDT 24 |
| Peak memory | 195516 kb |
| Host | smart-cca3bb08-9cef-428f-aaff-4b520072b278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520595773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.520595773 |
| Directory | /workspace/2.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2723126188 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 94061486 ps |
| CPU time | 1.48 seconds |
| Started | Jul 13 04:38:25 PM PDT 24 |
| Finished | Jul 13 04:38:29 PM PDT 24 |
| Peak memory | 198364 kb |
| Host | smart-1e8d7737-33ff-405f-bbed-e1c2c5656d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723126188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2723126188 |
| Directory | /workspace/2.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3895720673 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 60067480 ps |
| CPU time | 0.61 seconds |
| Started | Jul 13 04:38:34 PM PDT 24 |
| Finished | Jul 13 04:38:36 PM PDT 24 |
| Peak memory | 196068 kb |
| Host | smart-e9af1c15-470e-486f-bc5a-bff934b7124d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895720673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3895720673 |
| Directory | /workspace/2.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.117188742 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 43444296 ps |
| CPU time | 0.68 seconds |
| Started | Jul 13 04:38:27 PM PDT 24 |
| Finished | Jul 13 04:38:30 PM PDT 24 |
| Peak memory | 198852 kb |
| Host | smart-36110b71-e0c0-48c2-abab-4b814b87cd13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117188742 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.117188742 |
| Directory | /workspace/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_rw.1253753662 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 64839887 ps |
| CPU time | 0.65 seconds |
| Started | Jul 13 04:38:32 PM PDT 24 |
| Finished | Jul 13 04:38:35 PM PDT 24 |
| Peak memory | 196076 kb |
| Host | smart-597e11c8-58de-4ad8-88c4-1bad26cf7aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253753662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1253753662 |
| Directory | /workspace/2.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_intr_test.2440674062 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 80886000 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 04:38:32 PM PDT 24 |
| Finished | Jul 13 04:38:35 PM PDT 24 |
| Peak memory | 195044 kb |
| Host | smart-3e52420a-9acb-439d-9cf4-2b579fcc7e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440674062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2440674062 |
| Directory | /workspace/2.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.912456893 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 23352089 ps |
| CPU time | 0.65 seconds |
| Started | Jul 13 04:38:38 PM PDT 24 |
| Finished | Jul 13 04:38:40 PM PDT 24 |
| Peak memory | 196356 kb |
| Host | smart-82a4d6ff-773b-47d0-be29-8c4525baca76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912456893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_ outstanding.912456893 |
| Directory | /workspace/2.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_errors.2144847997 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 283504017 ps |
| CPU time | 1.53 seconds |
| Started | Jul 13 04:38:47 PM PDT 24 |
| Finished | Jul 13 04:38:49 PM PDT 24 |
| Peak memory | 200672 kb |
| Host | smart-ccc2b561-30c4-42bf-8c67-df6e8fe12444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144847997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2144847997 |
| Directory | /workspace/2.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3344164506 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 98239232 ps |
| CPU time | 1.29 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:54 PM PDT 24 |
| Peak memory | 200080 kb |
| Host | smart-17196f57-daa5-4be2-a31a-2ad2efd8f184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344164506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3344164506 |
| Directory | /workspace/2.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.uart_intr_test.2587696788 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 12270740 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:39:07 PM PDT 24 |
| Finished | Jul 13 04:39:08 PM PDT 24 |
| Peak memory | 195048 kb |
| Host | smart-ee6a0158-b82e-471b-9aa4-8b73f21eb3a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587696788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2587696788 |
| Directory | /workspace/20.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.uart_intr_test.3434025480 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 28012708 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:54 PM PDT 24 |
| Finished | Jul 13 04:38:57 PM PDT 24 |
| Peak memory | 194932 kb |
| Host | smart-d057e268-b535-412f-9b38-cdeac7a988eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434025480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3434025480 |
| Directory | /workspace/21.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.uart_intr_test.52294678 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 24923929 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:38:58 PM PDT 24 |
| Finished | Jul 13 04:38:59 PM PDT 24 |
| Peak memory | 195060 kb |
| Host | smart-d0a4f071-b1fe-4413-b102-73991a45ca49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52294678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.52294678 |
| Directory | /workspace/22.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.uart_intr_test.1278339663 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 46146529 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:52 PM PDT 24 |
| Peak memory | 195028 kb |
| Host | smart-d481f49c-3212-45e2-99b9-969513ceb1bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278339663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1278339663 |
| Directory | /workspace/23.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.uart_intr_test.1010540615 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 23779053 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:43 PM PDT 24 |
| Finished | Jul 13 04:38:45 PM PDT 24 |
| Peak memory | 195068 kb |
| Host | smart-a96d544d-74f0-4d8e-b162-e783decfeaea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010540615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1010540615 |
| Directory | /workspace/24.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.uart_intr_test.440699399 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 12842650 ps |
| CPU time | 0.6 seconds |
| Started | Jul 13 04:39:03 PM PDT 24 |
| Finished | Jul 13 04:39:05 PM PDT 24 |
| Peak memory | 195120 kb |
| Host | smart-07c2f251-e553-4d4f-90cf-ec94ab481d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440699399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.440699399 |
| Directory | /workspace/25.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.uart_intr_test.3194666536 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 12476667 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:53 PM PDT 24 |
| Finished | Jul 13 04:38:56 PM PDT 24 |
| Peak memory | 195072 kb |
| Host | smart-52c2ea9e-4449-40da-84e5-da285a348d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194666536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3194666536 |
| Directory | /workspace/26.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.uart_intr_test.2733865729 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 39402762 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 04:39:01 PM PDT 24 |
| Finished | Jul 13 04:39:03 PM PDT 24 |
| Peak memory | 195040 kb |
| Host | smart-b788c0e7-87eb-4672-8b1e-3c33d8f70379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733865729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2733865729 |
| Directory | /workspace/27.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.uart_intr_test.2822579145 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 79448000 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:52 PM PDT 24 |
| Finished | Jul 13 04:38:59 PM PDT 24 |
| Peak memory | 195000 kb |
| Host | smart-28645107-364b-4f02-8c07-7b55657b8aee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822579145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2822579145 |
| Directory | /workspace/28.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.uart_intr_test.2524808327 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 20391989 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:38:55 PM PDT 24 |
| Finished | Jul 13 04:38:57 PM PDT 24 |
| Peak memory | 195092 kb |
| Host | smart-5d42110e-fb96-4e4a-b648-38d4cc3a92d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524808327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2524808327 |
| Directory | /workspace/29.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3047323143 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 18454124 ps |
| CPU time | 0.65 seconds |
| Started | Jul 13 04:38:29 PM PDT 24 |
| Finished | Jul 13 04:38:32 PM PDT 24 |
| Peak memory | 195404 kb |
| Host | smart-33be7183-63df-4b76-ab21-7b9892398e14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047323143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3047323143 |
| Directory | /workspace/3.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.383228571 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 63292623 ps |
| CPU time | 2.23 seconds |
| Started | Jul 13 04:38:27 PM PDT 24 |
| Finished | Jul 13 04:38:32 PM PDT 24 |
| Peak memory | 198636 kb |
| Host | smart-7f74f680-d394-44a3-9b25-67998b8ddfe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383228571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.383228571 |
| Directory | /workspace/3.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2896604856 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 17496090 ps |
| CPU time | 0.61 seconds |
| Started | Jul 13 04:38:39 PM PDT 24 |
| Finished | Jul 13 04:38:41 PM PDT 24 |
| Peak memory | 196056 kb |
| Host | smart-968ac6e9-be56-446e-a37d-5bd3361b9784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896604856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2896604856 |
| Directory | /workspace/3.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3068470752 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 28735651 ps |
| CPU time | 1.08 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:50 PM PDT 24 |
| Peak memory | 201032 kb |
| Host | smart-1167b406-2d04-4324-b379-df859bcd00e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068470752 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3068470752 |
| Directory | /workspace/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_rw.3866641904 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 41332662 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:26 PM PDT 24 |
| Finished | Jul 13 04:38:29 PM PDT 24 |
| Peak memory | 195996 kb |
| Host | smart-4c0f5760-983f-4b5c-9da4-a194167196a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866641904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3866641904 |
| Directory | /workspace/3.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_intr_test.503185172 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 29217735 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:39 PM PDT 24 |
| Finished | Jul 13 04:38:40 PM PDT 24 |
| Peak memory | 194992 kb |
| Host | smart-947b4ae1-3599-45fc-8f3b-4c108cf755ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503185172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.503185172 |
| Directory | /workspace/3.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.540290350 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 19333867 ps |
| CPU time | 0.74 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 197696 kb |
| Host | smart-9f71cf79-3bc1-4f4a-8a83-45b925a4f3a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540290350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_ outstanding.540290350 |
| Directory | /workspace/3.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_errors.472239928 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 27833284 ps |
| CPU time | 1.48 seconds |
| Started | Jul 13 04:38:43 PM PDT 24 |
| Finished | Jul 13 04:38:46 PM PDT 24 |
| Peak memory | 200692 kb |
| Host | smart-ecdf387c-6e78-49b9-b7e2-930a3104c9ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472239928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.472239928 |
| Directory | /workspace/3.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.252782181 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 228060596 ps |
| CPU time | 1.29 seconds |
| Started | Jul 13 04:38:29 PM PDT 24 |
| Finished | Jul 13 04:38:32 PM PDT 24 |
| Peak memory | 199960 kb |
| Host | smart-01cc7176-54e0-477f-b1fd-bfb7a1081463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252782181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.252782181 |
| Directory | /workspace/3.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.uart_intr_test.1387131084 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 35599069 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:54 PM PDT 24 |
| Finished | Jul 13 04:38:57 PM PDT 24 |
| Peak memory | 194984 kb |
| Host | smart-ba69ded5-0f49-4644-8051-7b8580fdc2fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387131084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1387131084 |
| Directory | /workspace/30.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.uart_intr_test.4249805489 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 13268226 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:39:02 PM PDT 24 |
| Finished | Jul 13 04:39:04 PM PDT 24 |
| Peak memory | 195016 kb |
| Host | smart-01e67ce5-9b52-4a12-886f-557ef2ca4584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249805489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4249805489 |
| Directory | /workspace/31.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.uart_intr_test.3676378412 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 16133703 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:54 PM PDT 24 |
| Peak memory | 195008 kb |
| Host | smart-d9bb3889-faf7-4717-9959-0f5699f62e47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676378412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3676378412 |
| Directory | /workspace/32.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.uart_intr_test.2620196372 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 36432032 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 194984 kb |
| Host | smart-4b9fb045-02ff-409d-bb94-9adee5dfab43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620196372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2620196372 |
| Directory | /workspace/33.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.uart_intr_test.2793183931 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 22610263 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:56 PM PDT 24 |
| Finished | Jul 13 04:38:58 PM PDT 24 |
| Peak memory | 195060 kb |
| Host | smart-d3a6481f-5251-47d1-a299-3dcd33ddeb28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793183931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2793183931 |
| Directory | /workspace/34.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.uart_intr_test.594049228 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 11167095 ps |
| CPU time | 0.6 seconds |
| Started | Jul 13 04:39:09 PM PDT 24 |
| Finished | Jul 13 04:39:10 PM PDT 24 |
| Peak memory | 195088 kb |
| Host | smart-8bea80ce-e37f-4676-8902-d790b43c6e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594049228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.594049228 |
| Directory | /workspace/35.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.uart_intr_test.679223403 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 38467703 ps |
| CPU time | 0.61 seconds |
| Started | Jul 13 04:39:12 PM PDT 24 |
| Finished | Jul 13 04:39:14 PM PDT 24 |
| Peak memory | 195060 kb |
| Host | smart-4c2f09ea-7095-48a6-a1a1-5061a79d8039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679223403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.679223403 |
| Directory | /workspace/36.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.uart_intr_test.3300866722 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 14577459 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:50 PM PDT 24 |
| Peak memory | 195048 kb |
| Host | smart-69c65b65-e175-4ad5-adb4-690496cf23fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300866722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3300866722 |
| Directory | /workspace/37.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.uart_intr_test.2690721216 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 14532180 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 04:39:08 PM PDT 24 |
| Finished | Jul 13 04:39:09 PM PDT 24 |
| Peak memory | 195060 kb |
| Host | smart-89dbb5b7-2026-4830-b5a3-9d0525d8360d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690721216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2690721216 |
| Directory | /workspace/38.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.uart_intr_test.1921326876 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 16187064 ps |
| CPU time | 0.61 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:53 PM PDT 24 |
| Peak memory | 195056 kb |
| Host | smart-bc7d0ba9-18db-4983-a8e9-2cf81d1195c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921326876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1921326876 |
| Directory | /workspace/39.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1937319269 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 17660053 ps |
| CPU time | 0.77 seconds |
| Started | Jul 13 04:38:39 PM PDT 24 |
| Finished | Jul 13 04:38:41 PM PDT 24 |
| Peak memory | 197084 kb |
| Host | smart-ba5ca2a6-77e6-4e5f-9936-0a49e291ea69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937319269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1937319269 |
| Directory | /workspace/4.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.546392319 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 179072207 ps |
| CPU time | 2.35 seconds |
| Started | Jul 13 04:38:47 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 197900 kb |
| Host | smart-00b8ca6b-c692-4a98-8d84-531168d3e415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546392319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.546392319 |
| Directory | /workspace/4.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1284629954 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 21590975 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:38:45 PM PDT 24 |
| Finished | Jul 13 04:38:46 PM PDT 24 |
| Peak memory | 196092 kb |
| Host | smart-4584f91f-4cee-47dc-b4f6-e475bfbc8bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284629954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1284629954 |
| Directory | /workspace/4.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3545548909 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 59075895 ps |
| CPU time | 0.67 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:50 PM PDT 24 |
| Peak memory | 198768 kb |
| Host | smart-a2cf57d6-379b-48a3-b727-659043d36b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545548909 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3545548909 |
| Directory | /workspace/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_rw.919984471 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 15271130 ps |
| CPU time | 0.63 seconds |
| Started | Jul 13 04:38:33 PM PDT 24 |
| Finished | Jul 13 04:38:35 PM PDT 24 |
| Peak memory | 196132 kb |
| Host | smart-0291ff3a-fc8d-4a6c-83de-b40a45175daa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919984471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.919984471 |
| Directory | /workspace/4.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_intr_test.3782999555 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 75169680 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:44 PM PDT 24 |
| Finished | Jul 13 04:38:45 PM PDT 24 |
| Peak memory | 194952 kb |
| Host | smart-f3f0ac56-4277-45c0-b40e-f298c6cf8f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782999555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3782999555 |
| Directory | /workspace/4.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1180238467 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 100346055 ps |
| CPU time | 0.74 seconds |
| Started | Jul 13 04:38:33 PM PDT 24 |
| Finished | Jul 13 04:38:35 PM PDT 24 |
| Peak memory | 198576 kb |
| Host | smart-efb71b1d-811d-48a0-8412-e0a6aa5436c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180238467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.1180238467 |
| Directory | /workspace/4.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_errors.1045260220 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 86702141 ps |
| CPU time | 1.7 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 201076 kb |
| Host | smart-27c1277b-4da6-44d9-81fc-5d9140cd2153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045260220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1045260220 |
| Directory | /workspace/4.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4206620779 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 93854988 ps |
| CPU time | 1.31 seconds |
| Started | Jul 13 04:38:34 PM PDT 24 |
| Finished | Jul 13 04:38:37 PM PDT 24 |
| Peak memory | 199980 kb |
| Host | smart-a4623076-f382-4454-af4d-65db7eceb5e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206620779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4206620779 |
| Directory | /workspace/4.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.uart_intr_test.1553500012 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 33118136 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:54 PM PDT 24 |
| Peak memory | 194948 kb |
| Host | smart-cbbc2ca6-53d0-46e7-aef0-b54cc3a1359f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553500012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1553500012 |
| Directory | /workspace/40.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.uart_intr_test.1835524237 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 30798190 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:53 PM PDT 24 |
| Peak memory | 195056 kb |
| Host | smart-0c07b273-6b41-4e7c-b679-a4a522682a3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835524237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1835524237 |
| Directory | /workspace/41.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.uart_intr_test.823300859 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 13487034 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:38:56 PM PDT 24 |
| Finished | Jul 13 04:38:58 PM PDT 24 |
| Peak memory | 195084 kb |
| Host | smart-fcb17b65-e39c-433e-bc3c-67b6d17600dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823300859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.823300859 |
| Directory | /workspace/42.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.uart_intr_test.2614637060 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 18132922 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:50 PM PDT 24 |
| Finished | Jul 13 04:38:53 PM PDT 24 |
| Peak memory | 195044 kb |
| Host | smart-9beab2b8-c261-48f5-8080-50c97da37ba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614637060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2614637060 |
| Directory | /workspace/43.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.uart_intr_test.4211383052 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 33042641 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:39:02 PM PDT 24 |
| Finished | Jul 13 04:39:04 PM PDT 24 |
| Peak memory | 195060 kb |
| Host | smart-9eddaf03-cf55-411b-949d-ff36c233e0d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211383052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.4211383052 |
| Directory | /workspace/44.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.uart_intr_test.1727317511 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 30403997 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:39:04 PM PDT 24 |
| Finished | Jul 13 04:39:05 PM PDT 24 |
| Peak memory | 195100 kb |
| Host | smart-c1414309-29c0-49cd-b3ce-d14d9194e4a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727317511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1727317511 |
| Directory | /workspace/45.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.uart_intr_test.4063386456 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 13344340 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 04:39:07 PM PDT 24 |
| Finished | Jul 13 04:39:08 PM PDT 24 |
| Peak memory | 195068 kb |
| Host | smart-32b86b11-b365-4d92-b9fb-d42365c14612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063386456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4063386456 |
| Directory | /workspace/46.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.uart_intr_test.2569891977 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 14201153 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:39:31 PM PDT 24 |
| Finished | Jul 13 04:39:34 PM PDT 24 |
| Peak memory | 195036 kb |
| Host | smart-a9b731d4-1c63-4cc9-8ea2-a75073221f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569891977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2569891977 |
| Directory | /workspace/47.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.uart_intr_test.2023647909 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 38261650 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:39:24 PM PDT 24 |
| Finished | Jul 13 04:39:26 PM PDT 24 |
| Peak memory | 195072 kb |
| Host | smart-88b53927-7522-4c96-92cc-5d5c708b8146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023647909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2023647909 |
| Directory | /workspace/48.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.uart_intr_test.2494225963 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 15008604 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:54 PM PDT 24 |
| Peak memory | 195012 kb |
| Host | smart-5ff689c0-c985-46eb-ae18-bf86cc8e4395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494225963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2494225963 |
| Directory | /workspace/49.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.274807168 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 77190953 ps |
| CPU time | 0.81 seconds |
| Started | Jul 13 04:38:33 PM PDT 24 |
| Finished | Jul 13 04:38:35 PM PDT 24 |
| Peak memory | 200472 kb |
| Host | smart-286d3a7a-4014-4dff-8c91-741025a4d470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274807168 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.274807168 |
| Directory | /workspace/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_rw.527971232 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 14151299 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:38:34 PM PDT 24 |
| Finished | Jul 13 04:38:36 PM PDT 24 |
| Peak memory | 196308 kb |
| Host | smart-1f16558e-7fea-459a-bfce-fd3dc6476280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527971232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.527971232 |
| Directory | /workspace/5.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_intr_test.4079017420 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 21959503 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:53 PM PDT 24 |
| Peak memory | 195016 kb |
| Host | smart-caa99cb5-6d08-49dc-9952-d7d112db0f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079017420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4079017420 |
| Directory | /workspace/5.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.14361020 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 56437998 ps |
| CPU time | 0.79 seconds |
| Started | Jul 13 04:38:45 PM PDT 24 |
| Finished | Jul 13 04:38:47 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-c735693e-1fa7-4e36-9aea-02685fec5671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14361020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_o utstanding.14361020 |
| Directory | /workspace/5.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_errors.448059159 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 144600628 ps |
| CPU time | 2.38 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:39 PM PDT 24 |
| Peak memory | 200732 kb |
| Host | smart-78eca63b-9ede-4672-8d7b-0236357c5fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448059159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.448059159 |
| Directory | /workspace/5.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.961100554 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 88935896 ps |
| CPU time | 1.31 seconds |
| Started | Jul 13 04:38:36 PM PDT 24 |
| Finished | Jul 13 04:38:39 PM PDT 24 |
| Peak memory | 200044 kb |
| Host | smart-668e20ce-f6fd-4b9e-9bd2-081f43c59c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961100554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.961100554 |
| Directory | /workspace/5.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2728799607 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 39809254 ps |
| CPU time | 1.07 seconds |
| Started | Jul 13 04:38:30 PM PDT 24 |
| Finished | Jul 13 04:38:33 PM PDT 24 |
| Peak memory | 200428 kb |
| Host | smart-6697ba36-13ba-45c1-afdd-a6eeacae1b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728799607 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2728799607 |
| Directory | /workspace/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_rw.2439786334 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26380582 ps |
| CPU time | 0.61 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:50 PM PDT 24 |
| Peak memory | 196076 kb |
| Host | smart-42d62b04-35ff-4b50-a0e0-77daac874729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439786334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2439786334 |
| Directory | /workspace/6.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_intr_test.4159299377 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 18285018 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:38:36 PM PDT 24 |
| Finished | Jul 13 04:38:38 PM PDT 24 |
| Peak memory | 195092 kb |
| Host | smart-4273ffcb-3854-49f1-8f49-a563759ad6d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159299377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4159299377 |
| Directory | /workspace/6.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1003005801 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 91357873 ps |
| CPU time | 0.8 seconds |
| Started | Jul 13 04:38:51 PM PDT 24 |
| Finished | Jul 13 04:38:53 PM PDT 24 |
| Peak memory | 197740 kb |
| Host | smart-4bb8c993-0dbe-4b81-97b3-7c14547bb007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003005801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.1003005801 |
| Directory | /workspace/6.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_errors.2454164741 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 75110004 ps |
| CPU time | 1.51 seconds |
| Started | Jul 13 04:38:41 PM PDT 24 |
| Finished | Jul 13 04:38:44 PM PDT 24 |
| Peak memory | 200736 kb |
| Host | smart-3e9ea884-64a8-42c9-8285-d7653e5781ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454164741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2454164741 |
| Directory | /workspace/6.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3102744885 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 70019764 ps |
| CPU time | 1.3 seconds |
| Started | Jul 13 04:38:31 PM PDT 24 |
| Finished | Jul 13 04:38:34 PM PDT 24 |
| Peak memory | 199992 kb |
| Host | smart-7cb18553-4716-4e23-bfc7-17580f960389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102744885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3102744885 |
| Directory | /workspace/6.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1909011925 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 62796101 ps |
| CPU time | 0.82 seconds |
| Started | Jul 13 04:38:30 PM PDT 24 |
| Finished | Jul 13 04:38:33 PM PDT 24 |
| Peak memory | 200484 kb |
| Host | smart-3f66f24e-b159-42c3-8644-43dedeaf5cf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909011925 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1909011925 |
| Directory | /workspace/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_rw.2249295539 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 15446711 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:46 PM PDT 24 |
| Finished | Jul 13 04:38:47 PM PDT 24 |
| Peak memory | 196088 kb |
| Host | smart-42c3b15d-6a9e-4574-a0c9-b38029963a0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249295539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2249295539 |
| Directory | /workspace/7.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_intr_test.1308774810 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 40364709 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 04:38:47 PM PDT 24 |
| Finished | Jul 13 04:38:49 PM PDT 24 |
| Peak memory | 195048 kb |
| Host | smart-f51fae04-d1ca-43c3-b577-70dd3b074089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308774810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1308774810 |
| Directory | /workspace/7.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2142082461 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 81074111 ps |
| CPU time | 0.64 seconds |
| Started | Jul 13 04:38:53 PM PDT 24 |
| Finished | Jul 13 04:38:56 PM PDT 24 |
| Peak memory | 196592 kb |
| Host | smart-5f3bde20-c954-42f4-afd9-7596513f660b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142082461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.2142082461 |
| Directory | /workspace/7.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_errors.118915584 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 793849821 ps |
| CPU time | 1.35 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 200748 kb |
| Host | smart-7d7dd90c-d524-4162-b5bc-d45992d0fcff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118915584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.118915584 |
| Directory | /workspace/7.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1367768565 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 542123900 ps |
| CPU time | 1.04 seconds |
| Started | Jul 13 04:38:46 PM PDT 24 |
| Finished | Jul 13 04:38:48 PM PDT 24 |
| Peak memory | 199540 kb |
| Host | smart-ccbf74a8-2a84-415a-bd02-903ab3d640b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367768565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1367768565 |
| Directory | /workspace/7.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1304081525 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 64832580 ps |
| CPU time | 0.87 seconds |
| Started | Jul 13 04:38:29 PM PDT 24 |
| Finished | Jul 13 04:38:32 PM PDT 24 |
| Peak memory | 200252 kb |
| Host | smart-36257296-ea90-4038-b5a9-4f6928339a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304081525 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1304081525 |
| Directory | /workspace/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_rw.1053039187 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 17303458 ps |
| CPU time | 0.64 seconds |
| Started | Jul 13 04:38:48 PM PDT 24 |
| Finished | Jul 13 04:38:50 PM PDT 24 |
| Peak memory | 196076 kb |
| Host | smart-2ee73c7d-5039-4a19-8913-87e32d126b1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053039187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1053039187 |
| Directory | /workspace/8.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_intr_test.4002460421 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 11040778 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 04:38:47 PM PDT 24 |
| Finished | Jul 13 04:38:48 PM PDT 24 |
| Peak memory | 194924 kb |
| Host | smart-3a94c002-ad69-46cb-bb22-b10117d86cd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002460421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4002460421 |
| Directory | /workspace/8.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2862181651 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 13847892 ps |
| CPU time | 0.63 seconds |
| Started | Jul 13 04:38:46 PM PDT 24 |
| Finished | Jul 13 04:38:48 PM PDT 24 |
| Peak memory | 196240 kb |
| Host | smart-affb4b9c-9670-40e5-adaf-452d6bd116bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862181651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.2862181651 |
| Directory | /workspace/8.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_errors.1583440660 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 51900650 ps |
| CPU time | 1.5 seconds |
| Started | Jul 13 04:38:35 PM PDT 24 |
| Finished | Jul 13 04:38:38 PM PDT 24 |
| Peak memory | 201020 kb |
| Host | smart-64386c86-bb20-43c6-9e0f-030d5b3b1c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583440660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1583440660 |
| Directory | /workspace/8.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1464814103 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 213360275 ps |
| CPU time | 1.37 seconds |
| Started | Jul 13 04:38:41 PM PDT 24 |
| Finished | Jul 13 04:38:43 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-da41a9e4-e925-46cc-9e08-92ccfdf819a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464814103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1464814103 |
| Directory | /workspace/8.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2020515412 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 70347791 ps |
| CPU time | 1.01 seconds |
| Started | Jul 13 04:38:41 PM PDT 24 |
| Finished | Jul 13 04:38:43 PM PDT 24 |
| Peak memory | 200448 kb |
| Host | smart-ea182986-704a-4cf1-8a35-6a357e5d91a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020515412 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2020515412 |
| Directory | /workspace/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_rw.2518492550 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 14249488 ps |
| CPU time | 0.62 seconds |
| Started | Jul 13 04:38:44 PM PDT 24 |
| Finished | Jul 13 04:38:46 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-dcf29e38-bbf3-4fa7-a04b-5013f8bebe48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518492550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2518492550 |
| Directory | /workspace/9.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_intr_test.1196868465 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 85426516 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 04:38:34 PM PDT 24 |
| Finished | Jul 13 04:38:36 PM PDT 24 |
| Peak memory | 195080 kb |
| Host | smart-f5115515-6e2e-486a-8874-0c78667cddef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196868465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1196868465 |
| Directory | /workspace/9.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2648759080 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 92764142 ps |
| CPU time | 0.79 seconds |
| Started | Jul 13 04:38:45 PM PDT 24 |
| Finished | Jul 13 04:38:46 PM PDT 24 |
| Peak memory | 197868 kb |
| Host | smart-a66de4fc-fd80-4592-bdfa-2155946f4e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648759080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.2648759080 |
| Directory | /workspace/9.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_errors.1126898266 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 188027346 ps |
| CPU time | 1.06 seconds |
| Started | Jul 13 04:38:49 PM PDT 24 |
| Finished | Jul 13 04:38:51 PM PDT 24 |
| Peak memory | 200496 kb |
| Host | smart-d72b9cb9-422e-4310-8709-75b4a3814b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126898266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1126898266 |
| Directory | /workspace/9.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1676033194 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 163202625 ps |
| CPU time | 1.27 seconds |
| Started | Jul 13 04:38:32 PM PDT 24 |
| Finished | Jul 13 04:38:35 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-5d0cdb32-9cf7-410f-bf04-e53f4088a6e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676033194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1676033194 |
| Directory | /workspace/9.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_alert_test.4218097498 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 44854884 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 05:58:37 PM PDT 24 |
| Finished | Jul 13 05:58:38 PM PDT 24 |
| Peak memory | 195472 kb |
| Host | smart-e1afae73-c256-4936-9341-003d4db44aa2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218097498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.4218097498 |
| Directory | /workspace/0.uart_alert_test/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_full.1564983957 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 97049904179 ps |
| CPU time | 29.23 seconds |
| Started | Jul 13 05:58:39 PM PDT 24 |
| Finished | Jul 13 05:59:09 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-703c57c6-8c59-4e0f-a743-f104e10d0b0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564983957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1564983957 |
| Directory | /workspace/0.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_overflow.3433564042 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 48791252419 ps |
| CPU time | 34.81 seconds |
| Started | Jul 13 05:58:40 PM PDT 24 |
| Finished | Jul 13 05:59:15 PM PDT 24 |
| Peak memory | 200156 kb |
| Host | smart-3f78b886-c484-41b0-b7bd-a33c48a80eb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433564042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3433564042 |
| Directory | /workspace/0.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_reset.197820719 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 35252423010 ps |
| CPU time | 20.64 seconds |
| Started | Jul 13 05:58:36 PM PDT 24 |
| Finished | Jul 13 05:58:57 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-79555479-c9aa-48fe-892d-3a27672e5485 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=197820719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.197820719 |
| Directory | /workspace/0.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/0.uart_intr.3715025424 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 20818007826 ps |
| CPU time | 7.88 seconds |
| Started | Jul 13 05:58:38 PM PDT 24 |
| Finished | Jul 13 05:58:46 PM PDT 24 |
| Peak memory | 196800 kb |
| Host | smart-86652613-6368-4b32-8383-b8e6563ac1a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715025424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3715025424 |
| Directory | /workspace/0.uart_intr/latest |
| Test location | /workspace/coverage/default/0.uart_long_xfer_wo_dly.1825954809 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 55975139093 ps |
| CPU time | 317.07 seconds |
| Started | Jul 13 05:58:41 PM PDT 24 |
| Finished | Jul 13 06:03:58 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-fd47a030-313d-41cf-8d8e-f3d410849ead |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1825954809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1825954809 |
| Directory | /workspace/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/0.uart_loopback.1163201200 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 4011626732 ps |
| CPU time | 7.92 seconds |
| Started | Jul 13 05:58:38 PM PDT 24 |
| Finished | Jul 13 05:58:46 PM PDT 24 |
| Peak memory | 199160 kb |
| Host | smart-0c16c464-eeee-41b1-be0d-5881cdaccd11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163201200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1163201200 |
| Directory | /workspace/0.uart_loopback/latest |
| Test location | /workspace/coverage/default/0.uart_noise_filter.2788271673 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 54138939457 ps |
| CPU time | 85.96 seconds |
| Started | Jul 13 05:58:38 PM PDT 24 |
| Finished | Jul 13 06:00:04 PM PDT 24 |
| Peak memory | 199376 kb |
| Host | smart-9a609eb9-9618-4790-8a21-1a67492ca14d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2788271673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2788271673 |
| Directory | /workspace/0.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/0.uart_perf.3630951692 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 16974934591 ps |
| CPU time | 425.53 seconds |
| Started | Jul 13 05:58:38 PM PDT 24 |
| Finished | Jul 13 06:05:44 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-1ea17040-c07f-4bc7-83b3-357e32baf9ae |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3630951692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3630951692 |
| Directory | /workspace/0.uart_perf/latest |
| Test location | /workspace/coverage/default/0.uart_rx_oversample.3454086035 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 3261198198 ps |
| CPU time | 10.08 seconds |
| Started | Jul 13 05:58:37 PM PDT 24 |
| Finished | Jul 13 05:58:47 PM PDT 24 |
| Peak memory | 198076 kb |
| Host | smart-77a030be-98d3-4efb-9f4a-d2a5324acbf4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3454086035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3454086035 |
| Directory | /workspace/0.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/0.uart_rx_parity_err.2876288484 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 11794374212 ps |
| CPU time | 20.92 seconds |
| Started | Jul 13 05:58:39 PM PDT 24 |
| Finished | Jul 13 05:59:01 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-58a84941-9b41-4ead-9429-7b816a65a3c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2876288484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2876288484 |
| Directory | /workspace/0.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/0.uart_rx_start_bit_filter.1382338463 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3467236980 ps |
| CPU time | 3.36 seconds |
| Started | Jul 13 05:58:37 PM PDT 24 |
| Finished | Jul 13 05:58:41 PM PDT 24 |
| Peak memory | 195964 kb |
| Host | smart-d80a9f4a-22c2-484e-aede-7e1b74f8d435 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382338463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1382338463 |
| Directory | /workspace/0.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/0.uart_sec_cm.2725107326 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 125747999 ps |
| CPU time | 0.79 seconds |
| Started | Jul 13 05:58:41 PM PDT 24 |
| Finished | Jul 13 05:58:43 PM PDT 24 |
| Peak memory | 218304 kb |
| Host | smart-8bfde175-787a-4d5d-9b15-2df64b8e2874 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725107326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2725107326 |
| Directory | /workspace/0.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/0.uart_smoke.3001214749 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 622773988 ps |
| CPU time | 1.72 seconds |
| Started | Jul 13 05:58:38 PM PDT 24 |
| Finished | Jul 13 05:58:40 PM PDT 24 |
| Peak memory | 198896 kb |
| Host | smart-c0c9edd5-ff8b-46d3-b894-d77710a5e947 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001214749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3001214749 |
| Directory | /workspace/0.uart_smoke/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all.1668168024 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 75934674301 ps |
| CPU time | 467.51 seconds |
| Started | Jul 13 05:58:37 PM PDT 24 |
| Finished | Jul 13 06:06:25 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-fd2b7a57-c124-4d50-976e-15c2fc7a9296 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668168024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1668168024 |
| Directory | /workspace/0.uart_stress_all/latest |
| Test location | /workspace/coverage/default/0.uart_tx_ovrd.3382857590 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1189794972 ps |
| CPU time | 1.81 seconds |
| Started | Jul 13 05:58:37 PM PDT 24 |
| Finished | Jul 13 05:58:39 PM PDT 24 |
| Peak memory | 198696 kb |
| Host | smart-785e939e-2515-4695-b491-872dc6996d8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3382857590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3382857590 |
| Directory | /workspace/0.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/0.uart_tx_rx.3250724146 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 75438585768 ps |
| CPU time | 183.31 seconds |
| Started | Jul 13 05:58:41 PM PDT 24 |
| Finished | Jul 13 06:01:45 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-e1a2220b-09eb-4dad-93af-d33c9163131c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250724146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3250724146 |
| Directory | /workspace/0.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.uart_alert_test.1068843894 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 12740363 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 05:58:44 PM PDT 24 |
| Finished | Jul 13 05:58:45 PM PDT 24 |
| Peak memory | 195204 kb |
| Host | smart-8dcbfd3a-0f4c-4f81-b729-01ab78967967 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068843894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1068843894 |
| Directory | /workspace/1.uart_alert_test/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_full.1664571936 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 31028118617 ps |
| CPU time | 12.67 seconds |
| Started | Jul 13 05:58:48 PM PDT 24 |
| Finished | Jul 13 05:59:01 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-811fb9ff-17f6-4ff3-bd28-b11ba769aa5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664571936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1664571936 |
| Directory | /workspace/1.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_overflow.2599930930 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 24456836070 ps |
| CPU time | 40.44 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:59:26 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-7a950976-bd11-4014-85a5-9d09d65cd028 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599930930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2599930930 |
| Directory | /workspace/1.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_reset.1712460181 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 51951753960 ps |
| CPU time | 35.69 seconds |
| Started | Jul 13 05:58:53 PM PDT 24 |
| Finished | Jul 13 05:59:30 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-18c36471-8b8e-4469-8f31-5d4ab970d6ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712460181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1712460181 |
| Directory | /workspace/1.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_intr.754170859 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 16373157223 ps |
| CPU time | 11.35 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 05:58:59 PM PDT 24 |
| Peak memory | 197168 kb |
| Host | smart-2334e9ca-3d4a-4acb-96fb-530585e64cbc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754170859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.754170859 |
| Directory | /workspace/1.uart_intr/latest |
| Test location | /workspace/coverage/default/1.uart_long_xfer_wo_dly.2082688768 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 94605802451 ps |
| CPU time | 714.51 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 06:10:48 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-82606fa3-6c01-4e2f-b03c-cba7cb1a6761 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2082688768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2082688768 |
| Directory | /workspace/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/1.uart_loopback.1097700114 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 7361536126 ps |
| CPU time | 12.88 seconds |
| Started | Jul 13 05:58:48 PM PDT 24 |
| Finished | Jul 13 05:59:01 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-115c7561-b9a0-45cc-b328-4839c723e0d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097700114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1097700114 |
| Directory | /workspace/1.uart_loopback/latest |
| Test location | /workspace/coverage/default/1.uart_noise_filter.2285040606 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 12649478858 ps |
| CPU time | 5.25 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:58:51 PM PDT 24 |
| Peak memory | 194480 kb |
| Host | smart-aefd3777-a82b-43e2-bd9c-4e305c87a87d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285040606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2285040606 |
| Directory | /workspace/1.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/1.uart_perf.3954607507 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 14950415057 ps |
| CPU time | 52.6 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 05:59:45 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-546b83bd-b161-4d73-9fed-c329512a6d1a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3954607507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3954607507 |
| Directory | /workspace/1.uart_perf/latest |
| Test location | /workspace/coverage/default/1.uart_rx_oversample.2467527848 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5364317989 ps |
| CPU time | 12.14 seconds |
| Started | Jul 13 05:58:48 PM PDT 24 |
| Finished | Jul 13 05:59:01 PM PDT 24 |
| Peak memory | 199000 kb |
| Host | smart-8a9ceca4-f4fd-49e4-8e83-a7f2ab99a198 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2467527848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2467527848 |
| Directory | /workspace/1.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/1.uart_rx_parity_err.2510636503 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 17719748026 ps |
| CPU time | 7.96 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 05:58:55 PM PDT 24 |
| Peak memory | 199124 kb |
| Host | smart-0cc355f7-6738-4c7c-a7ee-5ceec4176168 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510636503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2510636503 |
| Directory | /workspace/1.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/1.uart_rx_start_bit_filter.2950662519 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 39129296796 ps |
| CPU time | 51.77 seconds |
| Started | Jul 13 05:58:44 PM PDT 24 |
| Finished | Jul 13 05:59:37 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-7ed45b9c-91c2-4693-af93-46b92ed833b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950662519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2950662519 |
| Directory | /workspace/1.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/1.uart_smoke.576219789 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 634460249 ps |
| CPU time | 1.55 seconds |
| Started | Jul 13 05:58:41 PM PDT 24 |
| Finished | Jul 13 05:58:43 PM PDT 24 |
| Peak memory | 198192 kb |
| Host | smart-3b63bd11-2376-4c3b-9a00-f8c3bf6748ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576219789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.576219789 |
| Directory | /workspace/1.uart_smoke/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all.1349852870 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 195612059337 ps |
| CPU time | 902.03 seconds |
| Started | Jul 13 05:58:51 PM PDT 24 |
| Finished | Jul 13 06:13:53 PM PDT 24 |
| Peak memory | 200148 kb |
| Host | smart-ebb9f834-c71a-4bdd-b8e2-eb29a66d2e1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349852870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1349852870 |
| Directory | /workspace/1.uart_stress_all/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3793712198 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 122565202119 ps |
| CPU time | 707.55 seconds |
| Started | Jul 13 05:58:50 PM PDT 24 |
| Finished | Jul 13 06:10:38 PM PDT 24 |
| Peak memory | 216364 kb |
| Host | smart-2adff438-0110-44ca-bae8-cb287391a914 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793712198 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3793712198 |
| Directory | /workspace/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.uart_tx_ovrd.3500903196 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1253294215 ps |
| CPU time | 2.01 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:58:48 PM PDT 24 |
| Peak memory | 199540 kb |
| Host | smart-c36f6122-20c7-41d3-bb2a-4100856de5c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500903196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3500903196 |
| Directory | /workspace/1.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/1.uart_tx_rx.1787661842 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 6542972726 ps |
| CPU time | 8.88 seconds |
| Started | Jul 13 05:58:53 PM PDT 24 |
| Finished | Jul 13 05:59:03 PM PDT 24 |
| Peak memory | 196976 kb |
| Host | smart-56500c18-f179-495d-b1ac-0e38d23b8509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787661842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1787661842 |
| Directory | /workspace/1.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/10.uart_alert_test.620589528 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 19499217 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 05:59:14 PM PDT 24 |
| Finished | Jul 13 05:59:15 PM PDT 24 |
| Peak memory | 195168 kb |
| Host | smart-28af0bac-4b38-4ed8-aacb-f7802e817480 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620589528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.620589528 |
| Directory | /workspace/10.uart_alert_test/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_full.2367788776 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 37128033199 ps |
| CPU time | 60.89 seconds |
| Started | Jul 13 05:59:11 PM PDT 24 |
| Finished | Jul 13 06:00:13 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-015ac29c-ffea-435e-b9ae-491f251d87e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367788776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2367788776 |
| Directory | /workspace/10.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_overflow.3990755959 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 104537747656 ps |
| CPU time | 73.93 seconds |
| Started | Jul 13 05:59:08 PM PDT 24 |
| Finished | Jul 13 06:00:23 PM PDT 24 |
| Peak memory | 199968 kb |
| Host | smart-62fd4520-6901-4b64-95e6-6263dea4990d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990755959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3990755959 |
| Directory | /workspace/10.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_reset.4164734914 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 96503626150 ps |
| CPU time | 138.81 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 06:01:30 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-2c2667a9-c1a8-469c-aa83-8d5224ccbe9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164734914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.4164734914 |
| Directory | /workspace/10.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/10.uart_intr.240221417 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 57304788535 ps |
| CPU time | 88.73 seconds |
| Started | Jul 13 05:59:11 PM PDT 24 |
| Finished | Jul 13 06:00:41 PM PDT 24 |
| Peak memory | 197844 kb |
| Host | smart-c9ad43a8-cc86-491d-97b6-e45a6c8a6474 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240221417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.240221417 |
| Directory | /workspace/10.uart_intr/latest |
| Test location | /workspace/coverage/default/10.uart_long_xfer_wo_dly.3092806597 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 96195048010 ps |
| CPU time | 518.5 seconds |
| Started | Jul 13 05:59:12 PM PDT 24 |
| Finished | Jul 13 06:07:51 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-adbf2bf6-8a19-4409-856b-2de88434768f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3092806597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3092806597 |
| Directory | /workspace/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/10.uart_loopback.1628232497 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 4625325588 ps |
| CPU time | 9.63 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 05:59:19 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-f085fea4-26d6-4e25-8ada-697954aebafd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628232497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1628232497 |
| Directory | /workspace/10.uart_loopback/latest |
| Test location | /workspace/coverage/default/10.uart_noise_filter.2315361121 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 113172033987 ps |
| CPU time | 45.24 seconds |
| Started | Jul 13 05:59:11 PM PDT 24 |
| Finished | Jul 13 05:59:57 PM PDT 24 |
| Peak memory | 208312 kb |
| Host | smart-dfb900a9-2a97-49a9-abdb-594f1a21abcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315361121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2315361121 |
| Directory | /workspace/10.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/10.uart_perf.4079750692 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 23521656775 ps |
| CPU time | 305.71 seconds |
| Started | Jul 13 05:59:14 PM PDT 24 |
| Finished | Jul 13 06:04:20 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-ecb3b4b5-e48e-495c-b84c-8254b7702697 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4079750692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4079750692 |
| Directory | /workspace/10.uart_perf/latest |
| Test location | /workspace/coverage/default/10.uart_rx_oversample.2751276582 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4330113569 ps |
| CPU time | 10.21 seconds |
| Started | Jul 13 05:59:11 PM PDT 24 |
| Finished | Jul 13 05:59:22 PM PDT 24 |
| Peak memory | 198720 kb |
| Host | smart-edcd8aa1-d692-4344-8a55-30ccbeadf0c4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2751276582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2751276582 |
| Directory | /workspace/10.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/10.uart_rx_parity_err.909098631 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 23011288705 ps |
| CPU time | 12.18 seconds |
| Started | Jul 13 05:59:14 PM PDT 24 |
| Finished | Jul 13 05:59:26 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-2ee40329-00a4-48f9-bd83-f1d81f8b164b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909098631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.909098631 |
| Directory | /workspace/10.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/10.uart_rx_start_bit_filter.1465568428 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 34154725178 ps |
| CPU time | 25.89 seconds |
| Started | Jul 13 05:59:12 PM PDT 24 |
| Finished | Jul 13 05:59:39 PM PDT 24 |
| Peak memory | 196652 kb |
| Host | smart-d544b9ef-7042-4f1c-87e3-fd281a1f7891 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465568428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1465568428 |
| Directory | /workspace/10.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/10.uart_smoke.3470817747 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5822018597 ps |
| CPU time | 22.42 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 05:59:33 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-cdcdd6f8-ab3a-41d6-80a7-28c359713aaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470817747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3470817747 |
| Directory | /workspace/10.uart_smoke/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all.3258187709 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 49886083376 ps |
| CPU time | 89.42 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 06:00:39 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-cd5ae18b-39b8-429c-bc67-231bdb6683ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258187709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3258187709 |
| Directory | /workspace/10.uart_stress_all/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2950554239 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 110151891981 ps |
| CPU time | 491.82 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 06:07:23 PM PDT 24 |
| Peak memory | 224868 kb |
| Host | smart-03b9f0c2-017d-4feb-a7e2-ca151afae21f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950554239 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2950554239 |
| Directory | /workspace/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.uart_tx_ovrd.4027956435 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 546130350 ps |
| CPU time | 2.06 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 05:59:13 PM PDT 24 |
| Peak memory | 199548 kb |
| Host | smart-9ae8f226-e32b-4582-b187-60d04ea7c9e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027956435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4027956435 |
| Directory | /workspace/10.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/10.uart_tx_rx.4191411888 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 52676335788 ps |
| CPU time | 22.32 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 05:59:32 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-dcd46748-19c1-4063-ba00-fe8c03d61c95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4191411888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.4191411888 |
| Directory | /workspace/10.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/100.uart_fifo_reset.1160882316 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 14619492115 ps |
| CPU time | 28.22 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:03:54 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-f7dcfbe3-7faf-4242-89d1-2563f78086e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160882316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1160882316 |
| Directory | /workspace/100.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/102.uart_fifo_reset.259455516 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 68997996354 ps |
| CPU time | 99.5 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:05:05 PM PDT 24 |
| Peak memory | 199572 kb |
| Host | smart-e30e2c7c-329c-405c-85d5-e4556bb9063b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259455516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.259455516 |
| Directory | /workspace/102.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/103.uart_fifo_reset.2138264870 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 11128073521 ps |
| CPU time | 19.46 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:03:45 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-463a59da-091c-46d0-a962-7f9d4023002a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138264870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2138264870 |
| Directory | /workspace/103.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/104.uart_fifo_reset.2416462393 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 29210661054 ps |
| CPU time | 45.19 seconds |
| Started | Jul 13 06:03:28 PM PDT 24 |
| Finished | Jul 13 06:04:14 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-1d4e89c7-7fad-42a4-85cc-78deb1dda57a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416462393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2416462393 |
| Directory | /workspace/104.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/106.uart_fifo_reset.3591699481 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 73514557291 ps |
| CPU time | 32.08 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:03:58 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-903a3396-964c-4b3d-8404-f07367910faa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3591699481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3591699481 |
| Directory | /workspace/106.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/108.uart_fifo_reset.3464475609 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 155069088976 ps |
| CPU time | 26.44 seconds |
| Started | Jul 13 06:03:22 PM PDT 24 |
| Finished | Jul 13 06:03:50 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-49e6d521-cae0-415d-9bf8-828422de6125 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3464475609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3464475609 |
| Directory | /workspace/108.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/109.uart_fifo_reset.1649719620 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 27869569890 ps |
| CPU time | 57.24 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:04:23 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-5bb8c9fd-36c8-4ad8-a60e-ea725961c980 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649719620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1649719620 |
| Directory | /workspace/109.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_alert_test.2695442328 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 35210254 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 05:59:23 PM PDT 24 |
| Finished | Jul 13 05:59:24 PM PDT 24 |
| Peak memory | 195564 kb |
| Host | smart-23e3da2d-3928-42c7-bc75-5e343d612fb5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695442328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2695442328 |
| Directory | /workspace/11.uart_alert_test/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_full.3295659842 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 13000445211 ps |
| CPU time | 7.94 seconds |
| Started | Jul 13 05:59:11 PM PDT 24 |
| Finished | Jul 13 05:59:20 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-33fe2a0c-2f65-4da9-9c96-30e7f90ec86f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3295659842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3295659842 |
| Directory | /workspace/11.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_overflow.1980656628 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 214104095355 ps |
| CPU time | 45.89 seconds |
| Started | Jul 13 05:59:11 PM PDT 24 |
| Finished | Jul 13 05:59:58 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-08fd09bb-fd8c-415d-b8fd-5384424a6691 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980656628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1980656628 |
| Directory | /workspace/11.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_reset.2532120671 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 61188645442 ps |
| CPU time | 49.77 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 06:00:01 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-adb7f8de-4df2-48aa-ab5e-bb15c3fa0ae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532120671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2532120671 |
| Directory | /workspace/11.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_intr.2738754551 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 92920080973 ps |
| CPU time | 63.13 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 06:00:12 PM PDT 24 |
| Peak memory | 197948 kb |
| Host | smart-e3481e75-42b4-459f-8a02-03193dffb17a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738754551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2738754551 |
| Directory | /workspace/11.uart_intr/latest |
| Test location | /workspace/coverage/default/11.uart_long_xfer_wo_dly.1045762446 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 100856845501 ps |
| CPU time | 788.62 seconds |
| Started | Jul 13 05:59:21 PM PDT 24 |
| Finished | Jul 13 06:12:31 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-8ddcdfb7-e75f-4125-8dd1-d73807c34937 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1045762446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1045762446 |
| Directory | /workspace/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/11.uart_loopback.1772693151 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2559701325 ps |
| CPU time | 5.45 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 05:59:17 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-260014a0-652e-4670-86dd-462e976cf3c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772693151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1772693151 |
| Directory | /workspace/11.uart_loopback/latest |
| Test location | /workspace/coverage/default/11.uart_noise_filter.3464209308 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 103817143760 ps |
| CPU time | 196.78 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 06:02:28 PM PDT 24 |
| Peak memory | 200040 kb |
| Host | smart-cdbc0388-7c97-41be-ad46-23d8ec090283 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3464209308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3464209308 |
| Directory | /workspace/11.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/11.uart_perf.3611581245 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 17038423649 ps |
| CPU time | 418.33 seconds |
| Started | Jul 13 05:59:12 PM PDT 24 |
| Finished | Jul 13 06:06:11 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-c4939604-d764-43d1-80f9-a881cbc5ad22 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3611581245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3611581245 |
| Directory | /workspace/11.uart_perf/latest |
| Test location | /workspace/coverage/default/11.uart_rx_oversample.2956652446 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 6038156679 ps |
| CPU time | 48.91 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 06:00:00 PM PDT 24 |
| Peak memory | 198000 kb |
| Host | smart-5153f694-32d9-434c-b1d0-437437058e5c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2956652446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2956652446 |
| Directory | /workspace/11.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/11.uart_rx_parity_err.4021585504 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 101065497160 ps |
| CPU time | 40.43 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 05:59:52 PM PDT 24 |
| Peak memory | 199624 kb |
| Host | smart-fc17de5a-1224-4efb-9aa2-43c4a5c42e9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021585504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4021585504 |
| Directory | /workspace/11.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/11.uart_rx_start_bit_filter.3056003235 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 3871582622 ps |
| CPU time | 6.09 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 05:59:18 PM PDT 24 |
| Peak memory | 196384 kb |
| Host | smart-462d4ce0-9731-4543-9448-54d1bcbc1f3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3056003235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3056003235 |
| Directory | /workspace/11.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/11.uart_smoke.2902927427 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 116713902 ps |
| CPU time | 0.74 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 05:59:12 PM PDT 24 |
| Peak memory | 196764 kb |
| Host | smart-4ddbd8d3-4f83-4106-8727-8edb907e7ee7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902927427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2902927427 |
| Directory | /workspace/11.uart_smoke/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all_with_rand_reset.84801533 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 167939918431 ps |
| CPU time | 259.82 seconds |
| Started | Jul 13 05:59:17 PM PDT 24 |
| Finished | Jul 13 06:03:38 PM PDT 24 |
| Peak memory | 215840 kb |
| Host | smart-d72e84e1-e3ca-4b1b-b9c4-f2897caf9b53 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84801533 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.84801533 |
| Directory | /workspace/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.uart_tx_ovrd.932411768 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 6964327215 ps |
| CPU time | 18.44 seconds |
| Started | Jul 13 05:59:12 PM PDT 24 |
| Finished | Jul 13 05:59:31 PM PDT 24 |
| Peak memory | 199344 kb |
| Host | smart-32a2278e-2992-4feb-bfb7-292aa62a5560 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932411768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.932411768 |
| Directory | /workspace/11.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/11.uart_tx_rx.2606594343 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 95683353586 ps |
| CPU time | 269.14 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 06:03:40 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-f8656f10-cc78-4619-936b-ef4adb25d915 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606594343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2606594343 |
| Directory | /workspace/11.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/112.uart_fifo_reset.3681190606 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 113950613832 ps |
| CPU time | 121.02 seconds |
| Started | Jul 13 06:03:23 PM PDT 24 |
| Finished | Jul 13 06:05:26 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-7550d89e-00f1-4fa9-90cd-1df2f494ee14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681190606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3681190606 |
| Directory | /workspace/112.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/113.uart_fifo_reset.4255779144 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 97339714446 ps |
| CPU time | 151.87 seconds |
| Started | Jul 13 06:03:25 PM PDT 24 |
| Finished | Jul 13 06:05:58 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-60680938-7f1a-40ef-bbbe-7cea6f446c51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255779144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4255779144 |
| Directory | /workspace/113.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/116.uart_fifo_reset.951825011 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 66542972470 ps |
| CPU time | 32.68 seconds |
| Started | Jul 13 06:03:31 PM PDT 24 |
| Finished | Jul 13 06:04:04 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-9e95fd56-f3f0-4cf1-9c6f-6dd3a833b1e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951825011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.951825011 |
| Directory | /workspace/116.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/117.uart_fifo_reset.2524004600 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 312308767379 ps |
| CPU time | 49.09 seconds |
| Started | Jul 13 06:03:33 PM PDT 24 |
| Finished | Jul 13 06:04:23 PM PDT 24 |
| Peak memory | 199664 kb |
| Host | smart-235d0008-09b1-48b0-b7ab-d78a114e8e07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524004600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2524004600 |
| Directory | /workspace/117.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/118.uart_fifo_reset.2734121505 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 28658561479 ps |
| CPU time | 11.37 seconds |
| Started | Jul 13 06:03:32 PM PDT 24 |
| Finished | Jul 13 06:03:44 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-aea95a08-8c01-46f8-96ff-a5b66c98efaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734121505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2734121505 |
| Directory | /workspace/118.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/119.uart_fifo_reset.62270213 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 69460419485 ps |
| CPU time | 102.58 seconds |
| Started | Jul 13 06:03:33 PM PDT 24 |
| Finished | Jul 13 06:05:16 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-22c5c51f-a356-43c4-af48-bb180c74529b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62270213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.62270213 |
| Directory | /workspace/119.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_alert_test.2737691841 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 19890486 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 05:59:21 PM PDT 24 |
| Peak memory | 194624 kb |
| Host | smart-76cb16d9-d065-4d0a-91e3-f16da00ac708 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737691841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2737691841 |
| Directory | /workspace/12.uart_alert_test/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_full.1074455747 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 70766777626 ps |
| CPU time | 29.2 seconds |
| Started | Jul 13 05:59:20 PM PDT 24 |
| Finished | Jul 13 05:59:50 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-75cdcac7-a488-4737-a69f-c62f3247eeae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074455747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1074455747 |
| Directory | /workspace/12.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_overflow.3752104621 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 198152471592 ps |
| CPU time | 89.59 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 06:00:49 PM PDT 24 |
| Peak memory | 200216 kb |
| Host | smart-9cb4c9c4-fbf2-42ca-a81d-92ed7351e9d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752104621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3752104621 |
| Directory | /workspace/12.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_reset.900163363 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 30754621332 ps |
| CPU time | 57.88 seconds |
| Started | Jul 13 05:59:17 PM PDT 24 |
| Finished | Jul 13 06:00:16 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-746da573-8771-4802-a7db-955217491f37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900163363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.900163363 |
| Directory | /workspace/12.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_intr.2953725528 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 470941496450 ps |
| CPU time | 643.82 seconds |
| Started | Jul 13 05:59:17 PM PDT 24 |
| Finished | Jul 13 06:10:02 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-15981f4e-2d0d-488f-aa28-867470a8a0d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953725528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2953725528 |
| Directory | /workspace/12.uart_intr/latest |
| Test location | /workspace/coverage/default/12.uart_long_xfer_wo_dly.1788871277 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 34775158194 ps |
| CPU time | 158.53 seconds |
| Started | Jul 13 05:59:16 PM PDT 24 |
| Finished | Jul 13 06:01:55 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-ea6db9c1-eb26-473f-828a-1c6ce31bb080 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1788871277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1788871277 |
| Directory | /workspace/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/12.uart_loopback.2968483324 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1803782933 ps |
| CPU time | 3.36 seconds |
| Started | Jul 13 05:59:17 PM PDT 24 |
| Finished | Jul 13 05:59:21 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-0564d150-82b4-49ba-b962-8836519b42ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968483324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2968483324 |
| Directory | /workspace/12.uart_loopback/latest |
| Test location | /workspace/coverage/default/12.uart_noise_filter.2760600759 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 123116114037 ps |
| CPU time | 55.64 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 06:00:15 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-742259f3-2c53-460f-9f63-6a6267d5a78a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760600759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2760600759 |
| Directory | /workspace/12.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/12.uart_perf.1766249817 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 13244220791 ps |
| CPU time | 127.59 seconds |
| Started | Jul 13 05:59:15 PM PDT 24 |
| Finished | Jul 13 06:01:23 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-77db6e60-9496-4aa9-a098-5fbe964f00b8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1766249817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1766249817 |
| Directory | /workspace/12.uart_perf/latest |
| Test location | /workspace/coverage/default/12.uart_rx_oversample.348441532 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3295368231 ps |
| CPU time | 11.59 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 05:59:31 PM PDT 24 |
| Peak memory | 198044 kb |
| Host | smart-458a7a5a-99ce-4ba9-bffb-9e716b2c066e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=348441532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.348441532 |
| Directory | /workspace/12.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/12.uart_rx_parity_err.920520097 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 39410028992 ps |
| CPU time | 16.46 seconds |
| Started | Jul 13 05:59:15 PM PDT 24 |
| Finished | Jul 13 05:59:32 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-aa5fbf20-44b6-43f4-86cd-0efe3ccea3f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920520097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.920520097 |
| Directory | /workspace/12.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/12.uart_rx_start_bit_filter.1397167534 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2945254144 ps |
| CPU time | 1.88 seconds |
| Started | Jul 13 05:59:17 PM PDT 24 |
| Finished | Jul 13 05:59:19 PM PDT 24 |
| Peak memory | 195912 kb |
| Host | smart-aebffbe4-0335-4216-85cc-f10fdf7b49b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397167534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1397167534 |
| Directory | /workspace/12.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/12.uart_smoke.4090530595 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 5381373291 ps |
| CPU time | 9.24 seconds |
| Started | Jul 13 05:59:15 PM PDT 24 |
| Finished | Jul 13 05:59:25 PM PDT 24 |
| Peak memory | 199192 kb |
| Host | smart-eeb77006-b04c-4fbf-860a-49775e695b22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090530595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4090530595 |
| Directory | /workspace/12.uart_smoke/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all.2596179417 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 153198207037 ps |
| CPU time | 254 seconds |
| Started | Jul 13 05:59:21 PM PDT 24 |
| Finished | Jul 13 06:03:36 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-99a89f27-0e02-46ee-a398-4be40e4d57db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596179417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2596179417 |
| Directory | /workspace/12.uart_stress_all/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3325513064 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 232565799336 ps |
| CPU time | 735.34 seconds |
| Started | Jul 13 05:59:16 PM PDT 24 |
| Finished | Jul 13 06:11:32 PM PDT 24 |
| Peak memory | 216332 kb |
| Host | smart-b52c38ef-9c3a-4605-8b65-88464723348f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325513064 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3325513064 |
| Directory | /workspace/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.uart_tx_ovrd.346097551 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 804784151 ps |
| CPU time | 2.6 seconds |
| Started | Jul 13 05:59:17 PM PDT 24 |
| Finished | Jul 13 05:59:21 PM PDT 24 |
| Peak memory | 198228 kb |
| Host | smart-de3a58a4-4a09-45fc-ab4d-81b3f463d0e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346097551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.346097551 |
| Directory | /workspace/12.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/12.uart_tx_rx.964237360 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 110210984605 ps |
| CPU time | 118.29 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 06:01:19 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-c3c583af-e4ee-4084-a682-4ad36f4a7e01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964237360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.964237360 |
| Directory | /workspace/12.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/120.uart_fifo_reset.1417725182 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 101647310504 ps |
| CPU time | 189.21 seconds |
| Started | Jul 13 06:03:32 PM PDT 24 |
| Finished | Jul 13 06:06:42 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-b19a1a9e-eb34-40af-b3b0-0d296d775806 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417725182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1417725182 |
| Directory | /workspace/120.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/122.uart_fifo_reset.2248108444 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 31025529819 ps |
| CPU time | 44.73 seconds |
| Started | Jul 13 06:03:34 PM PDT 24 |
| Finished | Jul 13 06:04:19 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-c6e3d852-ac85-42ff-a240-fef93a432bed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248108444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2248108444 |
| Directory | /workspace/122.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/123.uart_fifo_reset.2469053381 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9210270436 ps |
| CPU time | 16.73 seconds |
| Started | Jul 13 06:03:32 PM PDT 24 |
| Finished | Jul 13 06:03:50 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-af27ba21-ded3-4d51-ae21-dec3f50e027d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469053381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2469053381 |
| Directory | /workspace/123.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/125.uart_fifo_reset.2112639359 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 75976994695 ps |
| CPU time | 11.04 seconds |
| Started | Jul 13 06:03:32 PM PDT 24 |
| Finished | Jul 13 06:03:44 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-6857b2e1-ffe9-4162-853c-27d7321eb1b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2112639359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2112639359 |
| Directory | /workspace/125.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/126.uart_fifo_reset.2344845259 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 144968470460 ps |
| CPU time | 114.85 seconds |
| Started | Jul 13 06:03:34 PM PDT 24 |
| Finished | Jul 13 06:05:29 PM PDT 24 |
| Peak memory | 199572 kb |
| Host | smart-8549e4f2-17f9-431a-9ea7-a4279910af51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344845259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2344845259 |
| Directory | /workspace/126.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/127.uart_fifo_reset.1492756392 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 19527533829 ps |
| CPU time | 26.9 seconds |
| Started | Jul 13 06:03:30 PM PDT 24 |
| Finished | Jul 13 06:03:58 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-4af5c0fc-bfde-40d0-83d8-313f368587cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492756392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1492756392 |
| Directory | /workspace/127.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/128.uart_fifo_reset.3335129368 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 174160525608 ps |
| CPU time | 484.72 seconds |
| Started | Jul 13 06:03:33 PM PDT 24 |
| Finished | Jul 13 06:11:38 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-a9c4b098-17bd-482c-8b6d-2801b85303c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335129368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3335129368 |
| Directory | /workspace/128.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/129.uart_fifo_reset.292430744 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 73346339728 ps |
| CPU time | 7.59 seconds |
| Started | Jul 13 06:03:34 PM PDT 24 |
| Finished | Jul 13 06:03:42 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-c6da3e76-5345-4bd2-a08a-38db79c753f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292430744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.292430744 |
| Directory | /workspace/129.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_full.4165105760 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 113525304180 ps |
| CPU time | 200.92 seconds |
| Started | Jul 13 05:59:18 PM PDT 24 |
| Finished | Jul 13 06:02:39 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-43aad50d-b94f-430a-bfc8-ae72795f50f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165105760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.4165105760 |
| Directory | /workspace/13.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_overflow.2104087515 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 70108145779 ps |
| CPU time | 25.87 seconds |
| Started | Jul 13 05:59:16 PM PDT 24 |
| Finished | Jul 13 05:59:42 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-b0d0ffc4-a358-4fa5-a584-638dc3dad6ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104087515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2104087515 |
| Directory | /workspace/13.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_reset.2367428872 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 18411220930 ps |
| CPU time | 26.73 seconds |
| Started | Jul 13 05:59:16 PM PDT 24 |
| Finished | Jul 13 05:59:43 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-92a6147b-09cd-44c9-a7ce-2af969394dd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367428872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2367428872 |
| Directory | /workspace/13.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_intr.2187399870 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 490436396522 ps |
| CPU time | 624.41 seconds |
| Started | Jul 13 05:59:21 PM PDT 24 |
| Finished | Jul 13 06:09:46 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-61cd2297-faed-4c0e-8582-6e212961d606 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187399870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2187399870 |
| Directory | /workspace/13.uart_intr/latest |
| Test location | /workspace/coverage/default/13.uart_long_xfer_wo_dly.2919488758 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 181579404929 ps |
| CPU time | 495.53 seconds |
| Started | Jul 13 05:59:16 PM PDT 24 |
| Finished | Jul 13 06:07:33 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-55eb385a-d414-4392-867d-098c4b8423e3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2919488758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2919488758 |
| Directory | /workspace/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/13.uart_loopback.3162940545 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1353231787 ps |
| CPU time | 1.09 seconds |
| Started | Jul 13 05:59:18 PM PDT 24 |
| Finished | Jul 13 05:59:19 PM PDT 24 |
| Peak memory | 195996 kb |
| Host | smart-53edccbb-44d9-4eb8-8ec5-a177a6b3614d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162940545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3162940545 |
| Directory | /workspace/13.uart_loopback/latest |
| Test location | /workspace/coverage/default/13.uart_noise_filter.3468509787 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3808523919 ps |
| CPU time | 7.24 seconds |
| Started | Jul 13 05:59:20 PM PDT 24 |
| Finished | Jul 13 05:59:28 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-d5b4c8f9-8461-4d02-b897-bae6f2e0713c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468509787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3468509787 |
| Directory | /workspace/13.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/13.uart_perf.3196092476 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 8944473962 ps |
| CPU time | 127.71 seconds |
| Started | Jul 13 05:59:20 PM PDT 24 |
| Finished | Jul 13 06:01:29 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-2e3edd25-171f-4461-94e6-fe672dcd76b8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3196092476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3196092476 |
| Directory | /workspace/13.uart_perf/latest |
| Test location | /workspace/coverage/default/13.uart_rx_oversample.3078634226 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 5113766219 ps |
| CPU time | 13.05 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 05:59:33 PM PDT 24 |
| Peak memory | 199172 kb |
| Host | smart-e6a2c78c-2b2c-43d8-a538-f6d7bca7150d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3078634226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3078634226 |
| Directory | /workspace/13.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/13.uart_rx_parity_err.222069408 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 49730650531 ps |
| CPU time | 29.21 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 05:59:49 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-cd6010aa-e3dd-44a8-8c9d-d0c0cfd683c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=222069408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.222069408 |
| Directory | /workspace/13.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/13.uart_rx_start_bit_filter.3944890289 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 6174254964 ps |
| CPU time | 2.98 seconds |
| Started | Jul 13 05:59:20 PM PDT 24 |
| Finished | Jul 13 05:59:24 PM PDT 24 |
| Peak memory | 196348 kb |
| Host | smart-9afe752e-980a-4a9a-a1ca-6703dd0ddd5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944890289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3944890289 |
| Directory | /workspace/13.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/13.uart_smoke.4131366439 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 6022857578 ps |
| CPU time | 43.55 seconds |
| Started | Jul 13 05:59:16 PM PDT 24 |
| Finished | Jul 13 05:59:59 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-1fc5ccc6-0720-412b-aba8-1721aef2b047 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131366439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4131366439 |
| Directory | /workspace/13.uart_smoke/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all.2532664087 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 281974186856 ps |
| CPU time | 85.52 seconds |
| Started | Jul 13 05:59:20 PM PDT 24 |
| Finished | Jul 13 06:00:46 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-47a516cb-fa7d-4c72-9b07-9e8bc09f0b42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532664087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2532664087 |
| Directory | /workspace/13.uart_stress_all/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all_with_rand_reset.499190970 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 130132709605 ps |
| CPU time | 329.14 seconds |
| Started | Jul 13 05:59:21 PM PDT 24 |
| Finished | Jul 13 06:04:51 PM PDT 24 |
| Peak memory | 215192 kb |
| Host | smart-6de8a4f0-295e-47b2-a1de-10a34c3c846d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499190970 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.499190970 |
| Directory | /workspace/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.uart_tx_ovrd.54297507 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1173259924 ps |
| CPU time | 1.77 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 05:59:22 PM PDT 24 |
| Peak memory | 198664 kb |
| Host | smart-0e571c88-74e9-4360-91f7-9ba846473ef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54297507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.54297507 |
| Directory | /workspace/13.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/13.uart_tx_rx.3472358244 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 87715618101 ps |
| CPU time | 11.82 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 05:59:32 PM PDT 24 |
| Peak memory | 199660 kb |
| Host | smart-82c971fb-a086-4fae-b154-9f58417ec142 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472358244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3472358244 |
| Directory | /workspace/13.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/130.uart_fifo_reset.3934018504 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 8169594544 ps |
| CPU time | 5.05 seconds |
| Started | Jul 13 06:03:33 PM PDT 24 |
| Finished | Jul 13 06:03:39 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-a8b18055-f845-49ee-b4ea-26d018eb336d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934018504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3934018504 |
| Directory | /workspace/130.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/131.uart_fifo_reset.1665651218 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 64328430713 ps |
| CPU time | 11.15 seconds |
| Started | Jul 13 06:03:32 PM PDT 24 |
| Finished | Jul 13 06:03:44 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-45eede5f-1bdd-46f4-9a58-fdf26d159fa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1665651218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1665651218 |
| Directory | /workspace/131.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/132.uart_fifo_reset.3316305912 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 46354724370 ps |
| CPU time | 18.47 seconds |
| Started | Jul 13 06:03:32 PM PDT 24 |
| Finished | Jul 13 06:03:52 PM PDT 24 |
| Peak memory | 199492 kb |
| Host | smart-792fb97b-9c77-4bd9-a29a-4de9b18f13dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3316305912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3316305912 |
| Directory | /workspace/132.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/133.uart_fifo_reset.3290890859 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 137609729010 ps |
| CPU time | 96.69 seconds |
| Started | Jul 13 06:03:35 PM PDT 24 |
| Finished | Jul 13 06:05:12 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-01b640f7-b666-4b27-b8b3-5951d08f30ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290890859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3290890859 |
| Directory | /workspace/133.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/134.uart_fifo_reset.3876326153 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 129994399357 ps |
| CPU time | 476.98 seconds |
| Started | Jul 13 06:03:40 PM PDT 24 |
| Finished | Jul 13 06:11:37 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-019a2ffd-d0da-4bf4-a4de-f136f7756171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876326153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3876326153 |
| Directory | /workspace/134.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/135.uart_fifo_reset.144552547 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 175461242525 ps |
| CPU time | 288.58 seconds |
| Started | Jul 13 06:03:40 PM PDT 24 |
| Finished | Jul 13 06:08:29 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-38e2e7e1-cd9b-4af1-b338-60b41cf24ede |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=144552547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.144552547 |
| Directory | /workspace/135.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/136.uart_fifo_reset.1587324007 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 64737343170 ps |
| CPU time | 86.49 seconds |
| Started | Jul 13 06:03:40 PM PDT 24 |
| Finished | Jul 13 06:05:07 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-769a53cd-3f36-45a2-92be-68563573c868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587324007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1587324007 |
| Directory | /workspace/136.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/137.uart_fifo_reset.3784834615 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 146034525167 ps |
| CPU time | 68.15 seconds |
| Started | Jul 13 06:03:42 PM PDT 24 |
| Finished | Jul 13 06:04:50 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-67377b82-8438-4052-82bc-a77ebb3d6d74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3784834615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3784834615 |
| Directory | /workspace/137.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/138.uart_fifo_reset.2310117397 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 22554601236 ps |
| CPU time | 22.46 seconds |
| Started | Jul 13 06:03:41 PM PDT 24 |
| Finished | Jul 13 06:04:04 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-3dcaad0e-5323-4349-954a-08d5a5fee0fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310117397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2310117397 |
| Directory | /workspace/138.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/139.uart_fifo_reset.2567771738 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 72915520083 ps |
| CPU time | 108.21 seconds |
| Started | Jul 13 06:03:42 PM PDT 24 |
| Finished | Jul 13 06:05:31 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-77fe5e72-dbd7-4d40-bc1d-08b46991ba53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567771738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2567771738 |
| Directory | /workspace/139.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_alert_test.1386760295 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 13921189 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 05:59:28 PM PDT 24 |
| Finished | Jul 13 05:59:30 PM PDT 24 |
| Peak memory | 195204 kb |
| Host | smart-08c924fc-210a-4d2c-89d0-c28f75b3597d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386760295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1386760295 |
| Directory | /workspace/14.uart_alert_test/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_full.549102200 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 16293663058 ps |
| CPU time | 11.92 seconds |
| Started | Jul 13 05:59:19 PM PDT 24 |
| Finished | Jul 13 05:59:31 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-6280b768-a562-4e68-aa60-01a61ef5a3c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=549102200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.549102200 |
| Directory | /workspace/14.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_overflow.3571830194 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 120480349982 ps |
| CPU time | 190.59 seconds |
| Started | Jul 13 05:59:21 PM PDT 24 |
| Finished | Jul 13 06:02:32 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-d571bd1a-a5b6-495d-82ec-c5d5b4cf5422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3571830194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3571830194 |
| Directory | /workspace/14.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_reset.1855729707 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 34408994090 ps |
| CPU time | 43.59 seconds |
| Started | Jul 13 05:59:17 PM PDT 24 |
| Finished | Jul 13 06:00:02 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-6168eda1-37c3-4c5c-a90a-5f7954c14a7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1855729707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1855729707 |
| Directory | /workspace/14.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_intr.1703845507 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 29320713025 ps |
| CPU time | 40.88 seconds |
| Started | Jul 13 05:59:15 PM PDT 24 |
| Finished | Jul 13 05:59:56 PM PDT 24 |
| Peak memory | 198072 kb |
| Host | smart-03f85ab7-14de-4297-ba11-79c0aaa8e3e8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703845507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1703845507 |
| Directory | /workspace/14.uart_intr/latest |
| Test location | /workspace/coverage/default/14.uart_long_xfer_wo_dly.248113046 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 117984608457 ps |
| CPU time | 161.52 seconds |
| Started | Jul 13 05:59:27 PM PDT 24 |
| Finished | Jul 13 06:02:09 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-ff737768-ed01-48da-bcd5-e7f2f84661e1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=248113046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.248113046 |
| Directory | /workspace/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/14.uart_loopback.3229197731 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8599962593 ps |
| CPU time | 20.05 seconds |
| Started | Jul 13 05:59:27 PM PDT 24 |
| Finished | Jul 13 05:59:47 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-365b5ea7-9d0b-49ca-9081-72196823f23a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229197731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3229197731 |
| Directory | /workspace/14.uart_loopback/latest |
| Test location | /workspace/coverage/default/14.uart_noise_filter.4106361558 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 61348058394 ps |
| CPU time | 123.15 seconds |
| Started | Jul 13 05:59:20 PM PDT 24 |
| Finished | Jul 13 06:01:24 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-b09b076c-e186-4014-974e-34719d7fd79c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106361558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.4106361558 |
| Directory | /workspace/14.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/14.uart_perf.1900128342 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 8643195418 ps |
| CPU time | 430.53 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 06:06:36 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-c0b571dc-30f0-4b58-8860-c15388e7e8e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1900128342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1900128342 |
| Directory | /workspace/14.uart_perf/latest |
| Test location | /workspace/coverage/default/14.uart_rx_oversample.3929295604 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 1888785936 ps |
| CPU time | 10.71 seconds |
| Started | Jul 13 05:59:23 PM PDT 24 |
| Finished | Jul 13 05:59:35 PM PDT 24 |
| Peak memory | 198060 kb |
| Host | smart-52ab275a-1a48-4de1-a9eb-29a1a5b63670 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3929295604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3929295604 |
| Directory | /workspace/14.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/14.uart_rx_parity_err.1784188105 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 33463437896 ps |
| CPU time | 15.93 seconds |
| Started | Jul 13 05:59:14 PM PDT 24 |
| Finished | Jul 13 05:59:31 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-3a02270a-b576-496e-b970-df9d2c5d44ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784188105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1784188105 |
| Directory | /workspace/14.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/14.uart_rx_start_bit_filter.2011811996 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4055588935 ps |
| CPU time | 7.08 seconds |
| Started | Jul 13 05:59:20 PM PDT 24 |
| Finished | Jul 13 05:59:28 PM PDT 24 |
| Peak memory | 196700 kb |
| Host | smart-e44764a0-6ce0-41bd-b489-e4fe808a1410 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011811996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2011811996 |
| Directory | /workspace/14.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/14.uart_smoke.2225782433 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5472709325 ps |
| CPU time | 20.54 seconds |
| Started | Jul 13 05:59:16 PM PDT 24 |
| Finished | Jul 13 05:59:38 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-e41ca3a4-1277-4bbd-b8f8-a5558b672786 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225782433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2225782433 |
| Directory | /workspace/14.uart_smoke/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all.2203972 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 254909292773 ps |
| CPU time | 112.32 seconds |
| Started | Jul 13 05:59:24 PM PDT 24 |
| Finished | Jul 13 06:01:17 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-45da537f-1601-417d-a6ad-28b44b99ce5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2203972 |
| Directory | /workspace/14.uart_stress_all/latest |
| Test location | /workspace/coverage/default/14.uart_tx_ovrd.759546067 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 6752622854 ps |
| CPU time | 14.47 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 05:59:40 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-1ca6d047-358d-4f59-bb42-1c20be84e8d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759546067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.759546067 |
| Directory | /workspace/14.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/14.uart_tx_rx.3514365141 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 54675583609 ps |
| CPU time | 91.61 seconds |
| Started | Jul 13 05:59:23 PM PDT 24 |
| Finished | Jul 13 06:00:56 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-92ca1446-9149-4ec0-8790-fd28dadb3b96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514365141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3514365141 |
| Directory | /workspace/14.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/140.uart_fifo_reset.3598447097 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 256090687652 ps |
| CPU time | 156.89 seconds |
| Started | Jul 13 06:03:41 PM PDT 24 |
| Finished | Jul 13 06:06:19 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-c85607a6-993d-4428-9e97-8525b3883bf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598447097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3598447097 |
| Directory | /workspace/140.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/141.uart_fifo_reset.145408772 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 127855419706 ps |
| CPU time | 109.19 seconds |
| Started | Jul 13 06:03:42 PM PDT 24 |
| Finished | Jul 13 06:05:32 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-d7eddaef-9a28-48d5-8079-25ea2236eb95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145408772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.145408772 |
| Directory | /workspace/141.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/142.uart_fifo_reset.2858910402 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 6359448302 ps |
| CPU time | 12.25 seconds |
| Started | Jul 13 06:03:41 PM PDT 24 |
| Finished | Jul 13 06:03:53 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-145ab4f2-a28d-484f-bbdd-95c15ebc90d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858910402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2858910402 |
| Directory | /workspace/142.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/143.uart_fifo_reset.4189265007 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 305862982653 ps |
| CPU time | 26.47 seconds |
| Started | Jul 13 06:03:41 PM PDT 24 |
| Finished | Jul 13 06:04:08 PM PDT 24 |
| Peak memory | 199632 kb |
| Host | smart-d980abf4-0cbc-45dc-abc0-56c764b0f48e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4189265007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4189265007 |
| Directory | /workspace/143.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/144.uart_fifo_reset.3167410243 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 38153696015 ps |
| CPU time | 14.21 seconds |
| Started | Jul 13 06:03:40 PM PDT 24 |
| Finished | Jul 13 06:03:54 PM PDT 24 |
| Peak memory | 198184 kb |
| Host | smart-d98540ae-2294-4e11-9a24-4fe41d8a13f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3167410243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3167410243 |
| Directory | /workspace/144.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/145.uart_fifo_reset.501763750 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 81763589956 ps |
| CPU time | 35.01 seconds |
| Started | Jul 13 06:03:41 PM PDT 24 |
| Finished | Jul 13 06:04:16 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-c1761317-a070-4e99-9aef-21493df0d53f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501763750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.501763750 |
| Directory | /workspace/145.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/146.uart_fifo_reset.140477874 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 156219622990 ps |
| CPU time | 237.88 seconds |
| Started | Jul 13 06:03:42 PM PDT 24 |
| Finished | Jul 13 06:07:41 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-416e328c-e02b-486b-b8ff-645adf4e8bdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140477874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.140477874 |
| Directory | /workspace/146.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/147.uart_fifo_reset.1604910669 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 119856635306 ps |
| CPU time | 71.04 seconds |
| Started | Jul 13 06:03:40 PM PDT 24 |
| Finished | Jul 13 06:04:52 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-6b2b0c89-963e-46b5-8d7f-57d9ff8bad5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604910669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1604910669 |
| Directory | /workspace/147.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_alert_test.2461250723 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 53397573 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 05:59:28 PM PDT 24 |
| Finished | Jul 13 05:59:29 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-b1838a1b-548e-4bd3-beb3-ff49052c9f60 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461250723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2461250723 |
| Directory | /workspace/15.uart_alert_test/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_full.1402034838 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 30249797381 ps |
| CPU time | 23.51 seconds |
| Started | Jul 13 05:59:28 PM PDT 24 |
| Finished | Jul 13 05:59:52 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-1dc798db-3750-4cd5-98d1-8c47074be7e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1402034838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1402034838 |
| Directory | /workspace/15.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_overflow.2175004946 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 41567301113 ps |
| CPU time | 16.12 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 05:59:42 PM PDT 24 |
| Peak memory | 199528 kb |
| Host | smart-0a76594e-3781-4a3f-a15a-6fc223ce0375 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175004946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2175004946 |
| Directory | /workspace/15.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_reset.1681380115 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 51152300137 ps |
| CPU time | 83.6 seconds |
| Started | Jul 13 05:59:24 PM PDT 24 |
| Finished | Jul 13 06:00:49 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-b1b27d06-25c5-469d-a0df-bdecd08030a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681380115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1681380115 |
| Directory | /workspace/15.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_intr.4042794726 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 24588041992 ps |
| CPU time | 5.69 seconds |
| Started | Jul 13 05:59:26 PM PDT 24 |
| Finished | Jul 13 05:59:33 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-ad60ad43-1439-45f0-9054-bc599854b9ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042794726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4042794726 |
| Directory | /workspace/15.uart_intr/latest |
| Test location | /workspace/coverage/default/15.uart_long_xfer_wo_dly.3707634502 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 61485783828 ps |
| CPU time | 353.42 seconds |
| Started | Jul 13 05:59:28 PM PDT 24 |
| Finished | Jul 13 06:05:22 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-fe978ac6-838e-444e-9023-7c4d52529451 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3707634502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3707634502 |
| Directory | /workspace/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/15.uart_loopback.585058167 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 6807162036 ps |
| CPU time | 7.29 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 05:59:33 PM PDT 24 |
| Peak memory | 196364 kb |
| Host | smart-174e9278-24ec-4aa2-b020-dba9ab292725 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585058167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.585058167 |
| Directory | /workspace/15.uart_loopback/latest |
| Test location | /workspace/coverage/default/15.uart_noise_filter.3365557456 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 12851618569 ps |
| CPU time | 18 seconds |
| Started | Jul 13 05:59:28 PM PDT 24 |
| Finished | Jul 13 05:59:47 PM PDT 24 |
| Peak memory | 196248 kb |
| Host | smart-aff2244c-3189-49bf-8f76-0615adf4e340 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365557456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3365557456 |
| Directory | /workspace/15.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/15.uart_perf.3126973169 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 18705097853 ps |
| CPU time | 1123.39 seconds |
| Started | Jul 13 05:59:24 PM PDT 24 |
| Finished | Jul 13 06:18:09 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-2fea9373-6209-432d-91bc-b5b254a98a01 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3126973169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3126973169 |
| Directory | /workspace/15.uart_perf/latest |
| Test location | /workspace/coverage/default/15.uart_rx_oversample.1311898484 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3921184457 ps |
| CPU time | 6.38 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 05:59:32 PM PDT 24 |
| Peak memory | 197952 kb |
| Host | smart-35bbdfd0-ad74-40c2-82c2-b5d147d8bc12 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1311898484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1311898484 |
| Directory | /workspace/15.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/15.uart_rx_parity_err.3614743164 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 193182251366 ps |
| CPU time | 83.33 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 06:00:49 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-0db29524-ab0e-4dfb-9dda-e64edfed3ec6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614743164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3614743164 |
| Directory | /workspace/15.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/15.uart_rx_start_bit_filter.3081747237 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 4977324308 ps |
| CPU time | 4.43 seconds |
| Started | Jul 13 05:59:26 PM PDT 24 |
| Finished | Jul 13 05:59:31 PM PDT 24 |
| Peak memory | 196192 kb |
| Host | smart-f09d2bd2-429b-4532-bd16-464da4e0d94f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081747237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3081747237 |
| Directory | /workspace/15.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/15.uart_smoke.4270443932 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 519979649 ps |
| CPU time | 2.01 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 05:59:28 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-6b810e42-cddc-4cfa-9a78-0e6103eae04a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4270443932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.4270443932 |
| Directory | /workspace/15.uart_smoke/latest |
| Test location | /workspace/coverage/default/15.uart_tx_ovrd.563443577 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1456376469 ps |
| CPU time | 1.67 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 05:59:28 PM PDT 24 |
| Peak memory | 198504 kb |
| Host | smart-839b5cb2-69a7-4234-b295-4cec2a01708e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=563443577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.563443577 |
| Directory | /workspace/15.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/15.uart_tx_rx.3541881243 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 64748811351 ps |
| CPU time | 132.36 seconds |
| Started | Jul 13 05:59:24 PM PDT 24 |
| Finished | Jul 13 06:01:37 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-070cafee-4bed-441f-81cb-f34c75a46083 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541881243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3541881243 |
| Directory | /workspace/15.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/151.uart_fifo_reset.3857534236 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 86870755995 ps |
| CPU time | 89.07 seconds |
| Started | Jul 13 06:03:50 PM PDT 24 |
| Finished | Jul 13 06:05:19 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-eac5eead-81cf-4e30-997a-be2d01e7032c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857534236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3857534236 |
| Directory | /workspace/151.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/152.uart_fifo_reset.2207215081 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 48618780952 ps |
| CPU time | 164.46 seconds |
| Started | Jul 13 06:03:49 PM PDT 24 |
| Finished | Jul 13 06:06:34 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-b6b25eb7-aa40-40ac-9a09-aca630690cfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207215081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2207215081 |
| Directory | /workspace/152.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/153.uart_fifo_reset.2821817804 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 276536592032 ps |
| CPU time | 66.43 seconds |
| Started | Jul 13 06:03:52 PM PDT 24 |
| Finished | Jul 13 06:04:59 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-2206e51b-bb38-4223-8af3-d24952f040f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2821817804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2821817804 |
| Directory | /workspace/153.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/154.uart_fifo_reset.369368646 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 47087999995 ps |
| CPU time | 31.06 seconds |
| Started | Jul 13 06:03:49 PM PDT 24 |
| Finished | Jul 13 06:04:21 PM PDT 24 |
| Peak memory | 199632 kb |
| Host | smart-01e40728-241f-440a-88fc-d09f735b49c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369368646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.369368646 |
| Directory | /workspace/154.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/155.uart_fifo_reset.1144764438 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 11597238444 ps |
| CPU time | 18.04 seconds |
| Started | Jul 13 06:04:00 PM PDT 24 |
| Finished | Jul 13 06:04:18 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-163e4399-aa1e-4673-8d3b-28ec5e4a3120 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144764438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1144764438 |
| Directory | /workspace/155.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/156.uart_fifo_reset.2182976616 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 51356880046 ps |
| CPU time | 22.45 seconds |
| Started | Jul 13 06:03:49 PM PDT 24 |
| Finished | Jul 13 06:04:13 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-665fb3ea-52ce-4d6a-a713-9a37d3cc7119 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182976616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2182976616 |
| Directory | /workspace/156.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/158.uart_fifo_reset.1858286587 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 68312086339 ps |
| CPU time | 45.9 seconds |
| Started | Jul 13 06:04:00 PM PDT 24 |
| Finished | Jul 13 06:04:47 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-3e93f506-2d07-4d80-acd8-416df10d23a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858286587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1858286587 |
| Directory | /workspace/158.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/159.uart_fifo_reset.2773098470 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 11899917537 ps |
| CPU time | 7.28 seconds |
| Started | Jul 13 06:03:51 PM PDT 24 |
| Finished | Jul 13 06:03:59 PM PDT 24 |
| Peak memory | 199440 kb |
| Host | smart-59143b25-dbd4-4857-9faa-e313c82560bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773098470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2773098470 |
| Directory | /workspace/159.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_alert_test.3621061297 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 167094090 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 05:59:32 PM PDT 24 |
| Finished | Jul 13 05:59:34 PM PDT 24 |
| Peak memory | 195240 kb |
| Host | smart-71638f69-ce84-4e9f-ba25-07da1292f1b6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621061297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3621061297 |
| Directory | /workspace/16.uart_alert_test/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_full.4228456614 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 24847282971 ps |
| CPU time | 39.59 seconds |
| Started | Jul 13 05:59:24 PM PDT 24 |
| Finished | Jul 13 06:00:04 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-d5c40a3e-965b-453c-8e60-702d55ad3466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228456614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4228456614 |
| Directory | /workspace/16.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_overflow.4120178605 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 81954852505 ps |
| CPU time | 30.6 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 05:59:56 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-a0566587-a2f3-4887-858a-6dff96d4d982 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120178605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4120178605 |
| Directory | /workspace/16.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_reset.124949612 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7870575740 ps |
| CPU time | 13.74 seconds |
| Started | Jul 13 05:59:24 PM PDT 24 |
| Finished | Jul 13 05:59:38 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-add6d9ec-068b-4063-8107-42396dd29a7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124949612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.124949612 |
| Directory | /workspace/16.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_intr.869122472 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 30795270341 ps |
| CPU time | 46.51 seconds |
| Started | Jul 13 05:59:28 PM PDT 24 |
| Finished | Jul 13 06:00:16 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-bb9d44b8-c4b3-4596-8510-0e429917a748 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869122472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.869122472 |
| Directory | /workspace/16.uart_intr/latest |
| Test location | /workspace/coverage/default/16.uart_long_xfer_wo_dly.4131982085 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 70276895319 ps |
| CPU time | 198.98 seconds |
| Started | Jul 13 05:59:31 PM PDT 24 |
| Finished | Jul 13 06:02:51 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-cec85801-cdac-4338-a579-609d12c0f215 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4131982085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.4131982085 |
| Directory | /workspace/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/16.uart_loopback.2546650876 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1389913888 ps |
| CPU time | 2.5 seconds |
| Started | Jul 13 05:59:26 PM PDT 24 |
| Finished | Jul 13 05:59:29 PM PDT 24 |
| Peak memory | 198312 kb |
| Host | smart-e58ec563-220e-43d0-95c8-c365ac81f0f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546650876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2546650876 |
| Directory | /workspace/16.uart_loopback/latest |
| Test location | /workspace/coverage/default/16.uart_perf.3217222234 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 8977869273 ps |
| CPU time | 209.35 seconds |
| Started | Jul 13 05:59:29 PM PDT 24 |
| Finished | Jul 13 06:02:59 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-993aed49-a0f6-4d2e-915e-8832fe8cbb51 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3217222234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3217222234 |
| Directory | /workspace/16.uart_perf/latest |
| Test location | /workspace/coverage/default/16.uart_rx_oversample.235476679 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 7014436733 ps |
| CPU time | 65.22 seconds |
| Started | Jul 13 05:59:27 PM PDT 24 |
| Finished | Jul 13 06:00:33 PM PDT 24 |
| Peak memory | 198088 kb |
| Host | smart-90c846b9-2aef-4fdf-a198-f2dee8671b25 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=235476679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.235476679 |
| Directory | /workspace/16.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/16.uart_rx_parity_err.1564452684 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 110016769292 ps |
| CPU time | 46.72 seconds |
| Started | Jul 13 05:59:26 PM PDT 24 |
| Finished | Jul 13 06:00:14 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-02e74296-a4eb-4e1f-96a8-82dd5e88a388 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564452684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1564452684 |
| Directory | /workspace/16.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/16.uart_rx_start_bit_filter.1044645274 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 71679787545 ps |
| CPU time | 110.82 seconds |
| Started | Jul 13 05:59:26 PM PDT 24 |
| Finished | Jul 13 06:01:18 PM PDT 24 |
| Peak memory | 195716 kb |
| Host | smart-e757fb3d-585b-4c55-8113-9c5b9c552a0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044645274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1044645274 |
| Directory | /workspace/16.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/16.uart_smoke.2824372521 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 844980262 ps |
| CPU time | 3.59 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 05:59:30 PM PDT 24 |
| Peak memory | 199584 kb |
| Host | smart-741d1679-7188-4842-9ca2-d8a5631fb1d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824372521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2824372521 |
| Directory | /workspace/16.uart_smoke/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all.3777175804 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 153258393519 ps |
| CPU time | 236.1 seconds |
| Started | Jul 13 05:59:34 PM PDT 24 |
| Finished | Jul 13 06:03:31 PM PDT 24 |
| Peak memory | 200104 kb |
| Host | smart-7049eae4-596e-41fe-b077-a5e8e338d955 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777175804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3777175804 |
| Directory | /workspace/16.uart_stress_all/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all_with_rand_reset.615572736 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 70405583912 ps |
| CPU time | 959.48 seconds |
| Started | Jul 13 05:59:31 PM PDT 24 |
| Finished | Jul 13 06:15:31 PM PDT 24 |
| Peak memory | 216660 kb |
| Host | smart-9e6385b9-f32b-46ff-9c74-8f6335e5c654 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615572736 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.615572736 |
| Directory | /workspace/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.uart_tx_ovrd.2144686690 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1341383750 ps |
| CPU time | 1.94 seconds |
| Started | Jul 13 05:59:27 PM PDT 24 |
| Finished | Jul 13 05:59:30 PM PDT 24 |
| Peak memory | 198820 kb |
| Host | smart-7b8c1e20-dece-4d25-b922-8d34170303fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144686690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2144686690 |
| Directory | /workspace/16.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/16.uart_tx_rx.1039295142 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 38764928300 ps |
| CPU time | 54.75 seconds |
| Started | Jul 13 05:59:25 PM PDT 24 |
| Finished | Jul 13 06:00:21 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-f8d32246-1a5d-4faa-80a7-21c4a95aeec4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039295142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1039295142 |
| Directory | /workspace/16.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/161.uart_fifo_reset.2708742374 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 13967741661 ps |
| CPU time | 22.25 seconds |
| Started | Jul 13 06:04:00 PM PDT 24 |
| Finished | Jul 13 06:04:23 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-e1bc18e7-93f1-4ce4-85ed-e9e7f056c492 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708742374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2708742374 |
| Directory | /workspace/161.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/162.uart_fifo_reset.1550181 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 85981860114 ps |
| CPU time | 133.94 seconds |
| Started | Jul 13 06:03:48 PM PDT 24 |
| Finished | Jul 13 06:06:03 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-6b595c88-55a1-4a1e-9d0c-4270d96c4370 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1550181 |
| Directory | /workspace/162.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/163.uart_fifo_reset.2748247162 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 201187148732 ps |
| CPU time | 541.6 seconds |
| Started | Jul 13 06:04:01 PM PDT 24 |
| Finished | Jul 13 06:13:04 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-153f6688-fb8a-46f6-b4c2-0948f1a40476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748247162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2748247162 |
| Directory | /workspace/163.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/164.uart_fifo_reset.4158176142 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 24901169637 ps |
| CPU time | 11.77 seconds |
| Started | Jul 13 06:03:50 PM PDT 24 |
| Finished | Jul 13 06:04:02 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-a592fdd8-814b-4bc3-bb2b-b240016928bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158176142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4158176142 |
| Directory | /workspace/164.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/165.uart_fifo_reset.3589983936 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 112454891403 ps |
| CPU time | 20.09 seconds |
| Started | Jul 13 06:03:50 PM PDT 24 |
| Finished | Jul 13 06:04:11 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-acd3e784-7b53-4fe1-8976-93625c631bfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589983936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3589983936 |
| Directory | /workspace/165.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/166.uart_fifo_reset.3126739797 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 12165420547 ps |
| CPU time | 23.77 seconds |
| Started | Jul 13 06:04:01 PM PDT 24 |
| Finished | Jul 13 06:04:26 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-a6ac8eb1-6584-4b43-a60b-b2070da8ddc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126739797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3126739797 |
| Directory | /workspace/166.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/167.uart_fifo_reset.2441721942 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 135005504382 ps |
| CPU time | 213.61 seconds |
| Started | Jul 13 06:03:53 PM PDT 24 |
| Finished | Jul 13 06:07:27 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-e2b09b83-1e6b-4643-bc30-8721c56838ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2441721942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2441721942 |
| Directory | /workspace/167.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/168.uart_fifo_reset.100739379 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 36711344731 ps |
| CPU time | 58.05 seconds |
| Started | Jul 13 06:03:50 PM PDT 24 |
| Finished | Jul 13 06:04:49 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-71e81e9c-4d14-4701-b7cd-9661228aa8a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100739379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.100739379 |
| Directory | /workspace/168.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/169.uart_fifo_reset.2092648561 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 62719420348 ps |
| CPU time | 117.37 seconds |
| Started | Jul 13 06:03:50 PM PDT 24 |
| Finished | Jul 13 06:05:48 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-4802ea4f-6471-48b5-a0e5-c9d92d3931a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092648561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2092648561 |
| Directory | /workspace/169.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_alert_test.3227937218 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 112652462 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 05:59:43 PM PDT 24 |
| Peak memory | 195536 kb |
| Host | smart-9341c167-6504-43ab-95f4-744a7865f928 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227937218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3227937218 |
| Directory | /workspace/17.uart_alert_test/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_full.602209845 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 63174473444 ps |
| CPU time | 46.22 seconds |
| Started | Jul 13 05:59:32 PM PDT 24 |
| Finished | Jul 13 06:00:19 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-bb96b7e7-96ba-4057-bdd9-5c00c466b78f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=602209845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.602209845 |
| Directory | /workspace/17.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_overflow.1323592887 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 16592633278 ps |
| CPU time | 30.03 seconds |
| Started | Jul 13 05:59:34 PM PDT 24 |
| Finished | Jul 13 06:00:04 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-f69fd226-b9d1-4a28-9475-9531004b95fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323592887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1323592887 |
| Directory | /workspace/17.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_reset.217721303 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 11210635793 ps |
| CPU time | 19.64 seconds |
| Started | Jul 13 05:59:32 PM PDT 24 |
| Finished | Jul 13 05:59:52 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-c3212b9a-5df6-40ab-94d5-0ae52fcd4743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217721303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.217721303 |
| Directory | /workspace/17.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_intr.265171366 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 68442051059 ps |
| CPU time | 54.16 seconds |
| Started | Jul 13 05:59:32 PM PDT 24 |
| Finished | Jul 13 06:00:27 PM PDT 24 |
| Peak memory | 198828 kb |
| Host | smart-9bcff0ef-cd82-4d6f-9122-fe48a665fa8d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265171366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.265171366 |
| Directory | /workspace/17.uart_intr/latest |
| Test location | /workspace/coverage/default/17.uart_long_xfer_wo_dly.3996303021 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 114767848503 ps |
| CPU time | 176.8 seconds |
| Started | Jul 13 05:59:45 PM PDT 24 |
| Finished | Jul 13 06:02:42 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-c2649685-4934-4d3a-953a-a1a4ba05440b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3996303021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3996303021 |
| Directory | /workspace/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/17.uart_loopback.891555643 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5737523919 ps |
| CPU time | 6.56 seconds |
| Started | Jul 13 05:59:33 PM PDT 24 |
| Finished | Jul 13 05:59:40 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-59690434-da46-493b-8910-de41ebe1bf9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891555643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.891555643 |
| Directory | /workspace/17.uart_loopback/latest |
| Test location | /workspace/coverage/default/17.uart_noise_filter.1809402584 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 66630375080 ps |
| CPU time | 143.86 seconds |
| Started | Jul 13 05:59:32 PM PDT 24 |
| Finished | Jul 13 06:01:57 PM PDT 24 |
| Peak memory | 199480 kb |
| Host | smart-3524a151-b407-475f-9d85-c33c269bfc9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809402584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1809402584 |
| Directory | /workspace/17.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/17.uart_perf.3127368794 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 18765533873 ps |
| CPU time | 241.53 seconds |
| Started | Jul 13 05:59:44 PM PDT 24 |
| Finished | Jul 13 06:03:46 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-4c463521-ffe3-4948-9d47-e2307ae62a84 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3127368794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3127368794 |
| Directory | /workspace/17.uart_perf/latest |
| Test location | /workspace/coverage/default/17.uart_rx_oversample.2732170580 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 7272021075 ps |
| CPU time | 68.3 seconds |
| Started | Jul 13 05:59:30 PM PDT 24 |
| Finished | Jul 13 06:00:39 PM PDT 24 |
| Peak memory | 198080 kb |
| Host | smart-8b956d07-a25b-424c-8ec8-b17abd057faa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2732170580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2732170580 |
| Directory | /workspace/17.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/17.uart_rx_parity_err.4031580532 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 91918169078 ps |
| CPU time | 141.29 seconds |
| Started | Jul 13 05:59:32 PM PDT 24 |
| Finished | Jul 13 06:01:54 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-8913e579-cef0-4e9d-ba90-1cf0c7f4bc8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031580532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4031580532 |
| Directory | /workspace/17.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/17.uart_rx_start_bit_filter.3855323119 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 5655208343 ps |
| CPU time | 3.13 seconds |
| Started | Jul 13 05:59:35 PM PDT 24 |
| Finished | Jul 13 05:59:39 PM PDT 24 |
| Peak memory | 196044 kb |
| Host | smart-14bba09f-6b3f-49de-be59-06e16b6a334e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855323119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3855323119 |
| Directory | /workspace/17.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/17.uart_smoke.346213359 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 6072107964 ps |
| CPU time | 24.34 seconds |
| Started | Jul 13 05:59:35 PM PDT 24 |
| Finished | Jul 13 06:00:00 PM PDT 24 |
| Peak memory | 199300 kb |
| Host | smart-1683c34c-c5c2-4d8c-82d1-d66ecd029453 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346213359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.346213359 |
| Directory | /workspace/17.uart_smoke/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all_with_rand_reset.652475453 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 75633331103 ps |
| CPU time | 231.74 seconds |
| Started | Jul 13 05:59:44 PM PDT 24 |
| Finished | Jul 13 06:03:37 PM PDT 24 |
| Peak memory | 215504 kb |
| Host | smart-b8ed592e-fd05-4ad4-82ff-834c4c5a310b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652475453 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.652475453 |
| Directory | /workspace/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.uart_tx_ovrd.3794373709 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 6876320830 ps |
| CPU time | 17.2 seconds |
| Started | Jul 13 05:59:35 PM PDT 24 |
| Finished | Jul 13 05:59:53 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-0e6c6540-38d0-429c-8588-3255d79c5ff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794373709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3794373709 |
| Directory | /workspace/17.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/17.uart_tx_rx.2369231416 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 60387865018 ps |
| CPU time | 15.04 seconds |
| Started | Jul 13 05:59:31 PM PDT 24 |
| Finished | Jul 13 05:59:46 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-f8a74bdb-009a-409a-b91f-e68a2e5aba59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369231416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2369231416 |
| Directory | /workspace/17.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/170.uart_fifo_reset.3296058737 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 27547724510 ps |
| CPU time | 39.15 seconds |
| Started | Jul 13 06:03:49 PM PDT 24 |
| Finished | Jul 13 06:04:29 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-48d9a44e-a075-4a30-aad0-82206dfab98c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296058737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3296058737 |
| Directory | /workspace/170.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/171.uart_fifo_reset.1129321674 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 14733898095 ps |
| CPU time | 21.06 seconds |
| Started | Jul 13 06:04:00 PM PDT 24 |
| Finished | Jul 13 06:04:22 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-ea2ccad1-570b-4a0a-a511-7af1ffe635f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129321674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1129321674 |
| Directory | /workspace/171.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/172.uart_fifo_reset.3869273933 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 109463757751 ps |
| CPU time | 195.51 seconds |
| Started | Jul 13 06:04:01 PM PDT 24 |
| Finished | Jul 13 06:07:18 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-8efdcc74-e324-4d05-9cd3-1a9a121c3b58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869273933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3869273933 |
| Directory | /workspace/172.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/173.uart_fifo_reset.1629831609 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 203997327553 ps |
| CPU time | 26.38 seconds |
| Started | Jul 13 06:04:02 PM PDT 24 |
| Finished | Jul 13 06:04:29 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-e1e85180-9068-4cf0-a2da-64e18d348106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629831609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1629831609 |
| Directory | /workspace/173.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/176.uart_fifo_reset.2463558942 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 17955792007 ps |
| CPU time | 17.5 seconds |
| Started | Jul 13 06:04:03 PM PDT 24 |
| Finished | Jul 13 06:04:21 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-45a11b0f-e363-4f90-b609-a6d681779bd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463558942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2463558942 |
| Directory | /workspace/176.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/177.uart_fifo_reset.3942447688 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 73976448776 ps |
| CPU time | 127.05 seconds |
| Started | Jul 13 06:04:01 PM PDT 24 |
| Finished | Jul 13 06:06:09 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-fd1ebedc-996e-4f4e-aebb-796eb96736d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942447688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3942447688 |
| Directory | /workspace/177.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/179.uart_fifo_reset.3932065508 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 120588450282 ps |
| CPU time | 57.55 seconds |
| Started | Jul 13 06:04:00 PM PDT 24 |
| Finished | Jul 13 06:04:58 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-8e17093a-8cf4-4f97-a251-630265dcb5bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932065508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3932065508 |
| Directory | /workspace/179.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_alert_test.694929620 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 20974907 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 05:59:53 PM PDT 24 |
| Finished | Jul 13 05:59:55 PM PDT 24 |
| Peak memory | 195568 kb |
| Host | smart-2051672a-809a-44ae-b246-83e212965e6d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694929620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.694929620 |
| Directory | /workspace/18.uart_alert_test/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_full.1918893031 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 85783427006 ps |
| CPU time | 41.92 seconds |
| Started | Jul 13 05:59:44 PM PDT 24 |
| Finished | Jul 13 06:00:27 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-83834d8e-e3ed-40e8-89b4-37d3ada41e5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918893031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1918893031 |
| Directory | /workspace/18.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_overflow.1352250256 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 80287341386 ps |
| CPU time | 29.29 seconds |
| Started | Jul 13 05:59:45 PM PDT 24 |
| Finished | Jul 13 06:00:15 PM PDT 24 |
| Peak memory | 200104 kb |
| Host | smart-8329b8c7-c0ea-4907-b095-d72404ca6e56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352250256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1352250256 |
| Directory | /workspace/18.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_reset.3049809753 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 38718618561 ps |
| CPU time | 20.61 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 06:00:04 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-ee4d5401-5c9c-45a0-933e-94585c9fbc5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049809753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3049809753 |
| Directory | /workspace/18.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_intr.4056769628 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 267264439914 ps |
| CPU time | 103.67 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 06:01:28 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-792148bc-61ac-436e-9421-efd71125cbf0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056769628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4056769628 |
| Directory | /workspace/18.uart_intr/latest |
| Test location | /workspace/coverage/default/18.uart_long_xfer_wo_dly.2959371489 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 108479320989 ps |
| CPU time | 207.16 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 06:03:10 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-91756134-5bcd-4972-bcc3-044ce9d280fd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2959371489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2959371489 |
| Directory | /workspace/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/18.uart_loopback.3775549843 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1127935842 ps |
| CPU time | 4.06 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 05:59:47 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-5ddfd66f-7096-4c87-8e33-5537e75f0371 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775549843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3775549843 |
| Directory | /workspace/18.uart_loopback/latest |
| Test location | /workspace/coverage/default/18.uart_noise_filter.2538569840 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 109790430239 ps |
| CPU time | 49.81 seconds |
| Started | Jul 13 05:59:45 PM PDT 24 |
| Finished | Jul 13 06:00:35 PM PDT 24 |
| Peak memory | 199992 kb |
| Host | smart-3c3cf151-f44f-448a-8dc3-02b82477ac86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538569840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2538569840 |
| Directory | /workspace/18.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/18.uart_perf.3304513587 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 12998602765 ps |
| CPU time | 570.1 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 06:09:14 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-3fa56abb-69c8-4a4a-b87b-f0945e00574e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3304513587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3304513587 |
| Directory | /workspace/18.uart_perf/latest |
| Test location | /workspace/coverage/default/18.uart_rx_oversample.365238657 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5591131702 ps |
| CPU time | 58.56 seconds |
| Started | Jul 13 05:59:44 PM PDT 24 |
| Finished | Jul 13 06:00:43 PM PDT 24 |
| Peak memory | 199396 kb |
| Host | smart-31a117b4-3dee-4965-a059-045f82794f1b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=365238657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.365238657 |
| Directory | /workspace/18.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/18.uart_rx_parity_err.3985291265 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 91945901813 ps |
| CPU time | 35.24 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 06:00:19 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-c7448012-b7f1-4374-8181-e6d7e970cd01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3985291265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3985291265 |
| Directory | /workspace/18.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/18.uart_rx_start_bit_filter.256516223 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 34180087410 ps |
| CPU time | 5.63 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 05:59:49 PM PDT 24 |
| Peak memory | 196664 kb |
| Host | smart-1a597a0d-327f-410a-94aa-73e0dd3ce59b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=256516223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.256516223 |
| Directory | /workspace/18.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/18.uart_smoke.3014173155 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 460043609 ps |
| CPU time | 2.06 seconds |
| Started | Jul 13 05:59:44 PM PDT 24 |
| Finished | Jul 13 05:59:47 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-6a047e5a-13f6-4558-af73-8bc66934f106 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014173155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3014173155 |
| Directory | /workspace/18.uart_smoke/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all.216791792 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 273854878145 ps |
| CPU time | 263.33 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:04:16 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-39948de6-2ed1-4b4c-8fe2-09d2ac02716d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216791792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.216791792 |
| Directory | /workspace/18.uart_stress_all/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3192255321 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 70698571479 ps |
| CPU time | 884.04 seconds |
| Started | Jul 13 05:59:44 PM PDT 24 |
| Finished | Jul 13 06:14:29 PM PDT 24 |
| Peak memory | 230220 kb |
| Host | smart-0b10c380-68ae-4bf8-90eb-0fb3ef42202b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192255321 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3192255321 |
| Directory | /workspace/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.uart_tx_ovrd.30707522 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1201308138 ps |
| CPU time | 1.3 seconds |
| Started | Jul 13 05:59:43 PM PDT 24 |
| Finished | Jul 13 05:59:45 PM PDT 24 |
| Peak memory | 197988 kb |
| Host | smart-12a4b7fc-69d9-43ff-b655-f9606e084d9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30707522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.30707522 |
| Directory | /workspace/18.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/18.uart_tx_rx.437869334 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 25277943317 ps |
| CPU time | 47.88 seconds |
| Started | Jul 13 05:59:44 PM PDT 24 |
| Finished | Jul 13 06:00:33 PM PDT 24 |
| Peak memory | 199608 kb |
| Host | smart-1ba1d288-2bf5-4c22-8b44-d5a600548224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437869334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.437869334 |
| Directory | /workspace/18.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/180.uart_fifo_reset.3114833711 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 116541975385 ps |
| CPU time | 66.3 seconds |
| Started | Jul 13 06:04:01 PM PDT 24 |
| Finished | Jul 13 06:05:08 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-5beda35a-ff85-493c-b8b4-934ff3ce2bba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114833711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3114833711 |
| Directory | /workspace/180.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/181.uart_fifo_reset.514964928 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 132610242758 ps |
| CPU time | 227.51 seconds |
| Started | Jul 13 06:04:01 PM PDT 24 |
| Finished | Jul 13 06:07:50 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-91cf8dca-cbc8-4117-b998-e28fb567cc9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514964928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.514964928 |
| Directory | /workspace/181.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/182.uart_fifo_reset.1646183986 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 115617967717 ps |
| CPU time | 182.57 seconds |
| Started | Jul 13 06:04:01 PM PDT 24 |
| Finished | Jul 13 06:07:05 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-c70b4f84-dba7-4671-bfeb-924e0a6bb897 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646183986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1646183986 |
| Directory | /workspace/182.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/183.uart_fifo_reset.2302077058 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 45505069747 ps |
| CPU time | 17.2 seconds |
| Started | Jul 13 06:04:00 PM PDT 24 |
| Finished | Jul 13 06:04:18 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-c2446630-9cce-4f19-b1b7-77a9755a270a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302077058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2302077058 |
| Directory | /workspace/183.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/184.uart_fifo_reset.3747436280 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 74177388496 ps |
| CPU time | 26.16 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:04:36 PM PDT 24 |
| Peak memory | 199164 kb |
| Host | smart-a7c3693f-537f-4314-9193-3dd606eb5cb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747436280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3747436280 |
| Directory | /workspace/184.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/185.uart_fifo_reset.3663618459 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 14898084013 ps |
| CPU time | 28.08 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:04:39 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-3756d593-7280-46b8-b315-2d0591e1a309 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3663618459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3663618459 |
| Directory | /workspace/185.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/187.uart_fifo_reset.3963735495 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 50069803830 ps |
| CPU time | 78.07 seconds |
| Started | Jul 13 06:04:09 PM PDT 24 |
| Finished | Jul 13 06:05:27 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-197f7b65-bdb9-4a0c-bb0d-7af445fe6922 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963735495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3963735495 |
| Directory | /workspace/187.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/189.uart_fifo_reset.1251837670 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 79364822397 ps |
| CPU time | 13.22 seconds |
| Started | Jul 13 06:04:09 PM PDT 24 |
| Finished | Jul 13 06:04:23 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-e9700b98-ad26-49b7-9b4a-5f8027f74859 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1251837670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1251837670 |
| Directory | /workspace/189.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_alert_test.286711721 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 11470244 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 05:59:51 PM PDT 24 |
| Finished | Jul 13 05:59:52 PM PDT 24 |
| Peak memory | 194144 kb |
| Host | smart-90c562ac-a824-4c28-80fe-021619604802 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286711721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.286711721 |
| Directory | /workspace/19.uart_alert_test/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_full.4082678082 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 113359179378 ps |
| CPU time | 44.31 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:00:38 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-9025a05d-7076-445b-a03b-2161f14fe433 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082678082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4082678082 |
| Directory | /workspace/19.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_overflow.1029926688 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5805537402 ps |
| CPU time | 2.69 seconds |
| Started | Jul 13 05:59:51 PM PDT 24 |
| Finished | Jul 13 05:59:54 PM PDT 24 |
| Peak memory | 198196 kb |
| Host | smart-dc50a3b8-ba54-45f0-b652-b313dc97b3d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1029926688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1029926688 |
| Directory | /workspace/19.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_reset.782796866 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 18565506618 ps |
| CPU time | 46.43 seconds |
| Started | Jul 13 05:59:51 PM PDT 24 |
| Finished | Jul 13 06:00:37 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-1c2e8fc3-ceaf-493b-9604-270a745d35dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782796866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.782796866 |
| Directory | /workspace/19.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_intr.2148198636 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 27442652714 ps |
| CPU time | 21.91 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:00:15 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-1ea0d368-9ee9-4640-b8cb-d86a87a9bec2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148198636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2148198636 |
| Directory | /workspace/19.uart_intr/latest |
| Test location | /workspace/coverage/default/19.uart_long_xfer_wo_dly.2223795373 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 101979274051 ps |
| CPU time | 699.86 seconds |
| Started | Jul 13 05:59:54 PM PDT 24 |
| Finished | Jul 13 06:11:35 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-7033caad-84f3-45c1-9b39-0dd2a4e44734 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2223795373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2223795373 |
| Directory | /workspace/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/19.uart_loopback.3415906104 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1488751839 ps |
| CPU time | 1.37 seconds |
| Started | Jul 13 05:59:51 PM PDT 24 |
| Finished | Jul 13 05:59:53 PM PDT 24 |
| Peak memory | 195988 kb |
| Host | smart-ca4fe839-acbb-42b9-9d2b-7af03211a000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415906104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3415906104 |
| Directory | /workspace/19.uart_loopback/latest |
| Test location | /workspace/coverage/default/19.uart_noise_filter.2951868833 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 440838314248 ps |
| CPU time | 47.72 seconds |
| Started | Jul 13 05:59:55 PM PDT 24 |
| Finished | Jul 13 06:00:43 PM PDT 24 |
| Peak memory | 208116 kb |
| Host | smart-6cb1372b-bc30-4dad-8017-0a457242c310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951868833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2951868833 |
| Directory | /workspace/19.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/19.uart_perf.3256414004 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 28591069830 ps |
| CPU time | 339.03 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:05:31 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-bb4f6a72-e0b6-4ae7-949d-c15158abffa6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3256414004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3256414004 |
| Directory | /workspace/19.uart_perf/latest |
| Test location | /workspace/coverage/default/19.uart_rx_oversample.4120348782 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3720054240 ps |
| CPU time | 30.35 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:00:24 PM PDT 24 |
| Peak memory | 198060 kb |
| Host | smart-0c45b0c0-a891-46ac-adf7-5699854a29c0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4120348782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.4120348782 |
| Directory | /workspace/19.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/19.uart_rx_parity_err.1870680514 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 50524778657 ps |
| CPU time | 22.22 seconds |
| Started | Jul 13 05:59:53 PM PDT 24 |
| Finished | Jul 13 06:00:16 PM PDT 24 |
| Peak memory | 199436 kb |
| Host | smart-12c56ece-fe1f-4bdf-82cc-f5f0d937e04a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870680514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1870680514 |
| Directory | /workspace/19.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/19.uart_rx_start_bit_filter.3226519246 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2858809037 ps |
| CPU time | 1.72 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 05:59:55 PM PDT 24 |
| Peak memory | 196432 kb |
| Host | smart-9ae26423-2659-487d-bee9-97b14a3dda13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226519246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3226519246 |
| Directory | /workspace/19.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/19.uart_smoke.461297233 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 6292329317 ps |
| CPU time | 26.54 seconds |
| Started | Jul 13 05:59:53 PM PDT 24 |
| Finished | Jul 13 06:00:21 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-3465915b-832e-4fb8-9228-30b3929d9fde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461297233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.461297233 |
| Directory | /workspace/19.uart_smoke/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all.411476201 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 187101528615 ps |
| CPU time | 276.29 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:04:30 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-40bd28b7-a3f8-42f2-aa81-46e5652b276f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411476201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.411476201 |
| Directory | /workspace/19.uart_stress_all/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1042307906 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 44575007530 ps |
| CPU time | 517.3 seconds |
| Started | Jul 13 05:59:51 PM PDT 24 |
| Finished | Jul 13 06:08:29 PM PDT 24 |
| Peak memory | 216428 kb |
| Host | smart-82773d0e-13e8-4459-af81-11f3351c9def |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042307906 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1042307906 |
| Directory | /workspace/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.uart_tx_ovrd.2285346025 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 7822875836 ps |
| CPU time | 11.42 seconds |
| Started | Jul 13 05:59:50 PM PDT 24 |
| Finished | Jul 13 06:00:02 PM PDT 24 |
| Peak memory | 199472 kb |
| Host | smart-a78b4702-c1cd-4585-98a5-b5000f5e0cd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285346025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2285346025 |
| Directory | /workspace/19.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/19.uart_tx_rx.3203863562 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 92936285529 ps |
| CPU time | 43.23 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:00:36 PM PDT 24 |
| Peak memory | 199624 kb |
| Host | smart-65b924bf-ee64-4b77-861b-ea9a7e84a65e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3203863562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3203863562 |
| Directory | /workspace/19.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/190.uart_fifo_reset.1698744896 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 191797393301 ps |
| CPU time | 113.5 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:06:06 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-195ea88d-615d-4fad-babd-035185b68c40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698744896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1698744896 |
| Directory | /workspace/190.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/191.uart_fifo_reset.4025468218 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 30916171491 ps |
| CPU time | 48.01 seconds |
| Started | Jul 13 06:04:09 PM PDT 24 |
| Finished | Jul 13 06:04:58 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-bb8f2c7d-6c8d-49b0-9b0e-af674a58cf11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025468218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4025468218 |
| Directory | /workspace/191.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/192.uart_fifo_reset.3081049923 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 34489637203 ps |
| CPU time | 30.17 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:04:42 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-6c780eb1-7714-4c77-be84-460d19cc1349 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081049923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3081049923 |
| Directory | /workspace/192.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/193.uart_fifo_reset.308359039 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 30655969268 ps |
| CPU time | 16.04 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:04:26 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-20b0b5ad-8aee-4654-8da2-18bda8de01b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308359039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.308359039 |
| Directory | /workspace/193.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/194.uart_fifo_reset.494623335 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 113764766768 ps |
| CPU time | 186.48 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:07:18 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-72a07b3d-0a10-4c3d-b00d-9d6602d06a27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494623335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.494623335 |
| Directory | /workspace/194.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/195.uart_fifo_reset.3073886535 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 149637658831 ps |
| CPU time | 201.58 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:07:32 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-ea99655c-79b1-4392-a303-137a4efceb97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073886535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3073886535 |
| Directory | /workspace/195.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/196.uart_fifo_reset.3698839007 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 93464054262 ps |
| CPU time | 41.32 seconds |
| Started | Jul 13 06:04:08 PM PDT 24 |
| Finished | Jul 13 06:04:50 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-00362d54-85a7-4ae6-9274-abc1ebbc943a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698839007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3698839007 |
| Directory | /workspace/196.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/197.uart_fifo_reset.3071984932 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 36209308370 ps |
| CPU time | 20.32 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:04:32 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-bdeba57f-69b8-466c-bf55-0e9393d3d0e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071984932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3071984932 |
| Directory | /workspace/197.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/198.uart_fifo_reset.2643634360 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 42821853104 ps |
| CPU time | 98.01 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:05:50 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-3598fc6b-32ec-4940-8bb5-c92bfd608719 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2643634360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2643634360 |
| Directory | /workspace/198.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/199.uart_fifo_reset.2538059183 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 194888221698 ps |
| CPU time | 41.72 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:04:53 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-f7bfbbfd-d2fb-4165-9048-0bb74682ef8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538059183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2538059183 |
| Directory | /workspace/199.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_alert_test.1796659298 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 18195335 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 05:58:48 PM PDT 24 |
| Peak memory | 195488 kb |
| Host | smart-8cc0bbbd-5da9-4696-8f4b-ed2f2b165b87 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796659298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1796659298 |
| Directory | /workspace/2.uart_alert_test/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_full.182105946 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 48574927960 ps |
| CPU time | 78.8 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 06:00:12 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-affb1a0d-71a5-4a21-ad27-e3c945733a3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182105946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.182105946 |
| Directory | /workspace/2.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_overflow.1692793655 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 15008490211 ps |
| CPU time | 24.38 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 05:59:16 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-8027e787-d165-477b-a80c-49550a638796 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1692793655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1692793655 |
| Directory | /workspace/2.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/2.uart_intr.3289509645 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 24025314730 ps |
| CPU time | 38.94 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 05:59:26 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-b79da110-50bb-430d-9ba1-cb28b02b5c6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289509645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3289509645 |
| Directory | /workspace/2.uart_intr/latest |
| Test location | /workspace/coverage/default/2.uart_long_xfer_wo_dly.3075706708 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 89827011484 ps |
| CPU time | 837.2 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 06:12:49 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-f1d2d5b1-90eb-465d-bc9b-248bd8e92932 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3075706708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3075706708 |
| Directory | /workspace/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/2.uart_loopback.1910767183 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1677489351 ps |
| CPU time | 1.99 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 05:58:50 PM PDT 24 |
| Peak memory | 195952 kb |
| Host | smart-ef805f28-5e8d-4d07-8864-4f57e048789a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910767183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1910767183 |
| Directory | /workspace/2.uart_loopback/latest |
| Test location | /workspace/coverage/default/2.uart_noise_filter.2809480313 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 199662214084 ps |
| CPU time | 23.78 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 05:59:11 PM PDT 24 |
| Peak memory | 200052 kb |
| Host | smart-3df3d655-b4b9-4e83-bbac-427c2c3d69dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809480313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2809480313 |
| Directory | /workspace/2.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/2.uart_perf.4283806612 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 17025118186 ps |
| CPU time | 843.11 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 06:12:51 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-18b3c986-bdd8-44f7-8653-ccda985be006 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4283806612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4283806612 |
| Directory | /workspace/2.uart_perf/latest |
| Test location | /workspace/coverage/default/2.uart_rx_oversample.1423728196 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 6056163656 ps |
| CPU time | 59.89 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 05:59:48 PM PDT 24 |
| Peak memory | 198116 kb |
| Host | smart-0b2639c3-1e34-4977-a2cb-015473219397 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1423728196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1423728196 |
| Directory | /workspace/2.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/2.uart_rx_parity_err.3976440793 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 54810599667 ps |
| CPU time | 86.08 seconds |
| Started | Jul 13 05:58:44 PM PDT 24 |
| Finished | Jul 13 06:00:11 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-3bc97e86-654c-4bbe-b21a-97223dad9bba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976440793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3976440793 |
| Directory | /workspace/2.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/2.uart_rx_start_bit_filter.3147212402 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 1005263110 ps |
| CPU time | 1.61 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:58:48 PM PDT 24 |
| Peak memory | 195312 kb |
| Host | smart-a0dea6a2-2388-4af8-8e39-440e83668321 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147212402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3147212402 |
| Directory | /workspace/2.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/2.uart_sec_cm.4030853077 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 88982836 ps |
| CPU time | 0.87 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 05:58:48 PM PDT 24 |
| Peak memory | 218248 kb |
| Host | smart-482ec4d6-8393-4f8e-94b8-91e1567ae2a9 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030853077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4030853077 |
| Directory | /workspace/2.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/2.uart_smoke.4255164306 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 953090470 ps |
| CPU time | 2.12 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 05:58:49 PM PDT 24 |
| Peak memory | 198216 kb |
| Host | smart-f31fe252-dc75-4dee-8192-9095c6ba6b3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255164306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4255164306 |
| Directory | /workspace/2.uart_smoke/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all.4036256907 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 349439839215 ps |
| CPU time | 163.24 seconds |
| Started | Jul 13 05:58:54 PM PDT 24 |
| Finished | Jul 13 06:01:38 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-f9b6f4c2-a245-4500-8fe5-8e1ac1c1603a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036256907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4036256907 |
| Directory | /workspace/2.uart_stress_all/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2241531425 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 55985930452 ps |
| CPU time | 307.28 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 06:03:55 PM PDT 24 |
| Peak memory | 215684 kb |
| Host | smart-e2f7d8e4-0998-4424-a134-71b83277d3d6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241531425 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2241531425 |
| Directory | /workspace/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.uart_tx_ovrd.1661878618 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 1549663550 ps |
| CPU time | 2.7 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 05:58:49 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-f3d3b738-a2fb-451d-898b-8268836dae12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661878618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1661878618 |
| Directory | /workspace/2.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/2.uart_tx_rx.775998964 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 170842091613 ps |
| CPU time | 36.8 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:59:23 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-b5411822-5296-47f3-bba4-bc4890839cef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775998964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.775998964 |
| Directory | /workspace/2.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/20.uart_alert_test.1322244676 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 12611693 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:00:02 PM PDT 24 |
| Peak memory | 194936 kb |
| Host | smart-10117739-b190-4ae0-b793-1e23110f1fdf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322244676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1322244676 |
| Directory | /workspace/20.uart_alert_test/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_full.2602846788 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 44177804023 ps |
| CPU time | 53.69 seconds |
| Started | Jul 13 05:59:51 PM PDT 24 |
| Finished | Jul 13 06:00:45 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-f3da1bd3-7fd4-4904-a708-de9d3a27d767 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602846788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2602846788 |
| Directory | /workspace/20.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_overflow.3006442100 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 202273203361 ps |
| CPU time | 170.24 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:02:43 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-123fa274-05eb-4eab-8ae0-9c4877250962 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3006442100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3006442100 |
| Directory | /workspace/20.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/20.uart_intr.1206943261 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 228212052208 ps |
| CPU time | 315.9 seconds |
| Started | Jul 13 05:59:51 PM PDT 24 |
| Finished | Jul 13 06:05:08 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-ba5eccb8-fea4-476e-b8d1-33e9a735afe6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206943261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1206943261 |
| Directory | /workspace/20.uart_intr/latest |
| Test location | /workspace/coverage/default/20.uart_long_xfer_wo_dly.2863825243 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 123996681858 ps |
| CPU time | 268.98 seconds |
| Started | Jul 13 05:59:53 PM PDT 24 |
| Finished | Jul 13 06:04:23 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-d072d583-99a9-4f9b-9530-211f46870866 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2863825243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2863825243 |
| Directory | /workspace/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/20.uart_loopback.1586074652 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 7931033405 ps |
| CPU time | 11.61 seconds |
| Started | Jul 13 05:59:54 PM PDT 24 |
| Finished | Jul 13 06:00:06 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-43554305-3a8a-4162-93ed-601852a87ebc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586074652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1586074652 |
| Directory | /workspace/20.uart_loopback/latest |
| Test location | /workspace/coverage/default/20.uart_noise_filter.2116637033 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 10830601691 ps |
| CPU time | 16.75 seconds |
| Started | Jul 13 05:59:54 PM PDT 24 |
| Finished | Jul 13 06:00:12 PM PDT 24 |
| Peak memory | 197116 kb |
| Host | smart-a115cfa3-3003-4882-a4c4-0cb9de511a2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116637033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2116637033 |
| Directory | /workspace/20.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/20.uart_perf.1606713466 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 21240717007 ps |
| CPU time | 316.38 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:05:10 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-15cf48d7-90a1-47cb-a290-f2a3e9a7627c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1606713466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1606713466 |
| Directory | /workspace/20.uart_perf/latest |
| Test location | /workspace/coverage/default/20.uart_rx_oversample.3468536669 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 3786625789 ps |
| CPU time | 3.53 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 05:59:56 PM PDT 24 |
| Peak memory | 199284 kb |
| Host | smart-ac371361-b3cd-4a26-a9c6-ad7550ccd086 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3468536669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3468536669 |
| Directory | /workspace/20.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/20.uart_rx_parity_err.3657893900 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 29012060210 ps |
| CPU time | 13.69 seconds |
| Started | Jul 13 05:59:54 PM PDT 24 |
| Finished | Jul 13 06:00:08 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-96956020-e128-43d6-9c39-7e0f50a7e837 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657893900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3657893900 |
| Directory | /workspace/20.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/20.uart_rx_start_bit_filter.2613165842 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1534810325 ps |
| CPU time | 1.83 seconds |
| Started | Jul 13 05:59:51 PM PDT 24 |
| Finished | Jul 13 05:59:53 PM PDT 24 |
| Peak memory | 195544 kb |
| Host | smart-724d0690-3c33-4355-83f1-e82755f8a45e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2613165842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2613165842 |
| Directory | /workspace/20.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/20.uart_smoke.2223053709 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 106820709 ps |
| CPU time | 0.88 seconds |
| Started | Jul 13 05:59:50 PM PDT 24 |
| Finished | Jul 13 05:59:51 PM PDT 24 |
| Peak memory | 196784 kb |
| Host | smart-b553f59f-a88b-4a08-a2d1-004a9796f83b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223053709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2223053709 |
| Directory | /workspace/20.uart_smoke/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all.2854975879 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 175547595610 ps |
| CPU time | 23.76 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:00:25 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-725b23cb-69cc-48e3-905d-7c8c04bf9b6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854975879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2854975879 |
| Directory | /workspace/20.uart_stress_all/latest |
| Test location | /workspace/coverage/default/20.uart_tx_ovrd.2704973101 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1152304981 ps |
| CPU time | 1.81 seconds |
| Started | Jul 13 05:59:53 PM PDT 24 |
| Finished | Jul 13 05:59:56 PM PDT 24 |
| Peak memory | 199536 kb |
| Host | smart-c3359c81-c0c9-490c-9913-4a2804ef2fef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704973101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2704973101 |
| Directory | /workspace/20.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/20.uart_tx_rx.2259772301 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 44890718899 ps |
| CPU time | 47.18 seconds |
| Started | Jul 13 05:59:52 PM PDT 24 |
| Finished | Jul 13 06:00:40 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-54b068dc-9a4d-4b19-89d8-9ba7a1afa341 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259772301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2259772301 |
| Directory | /workspace/20.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/200.uart_fifo_reset.2217193716 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 62482566863 ps |
| CPU time | 88.29 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:05:39 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-cad12be6-13c5-41cd-8738-869db3f060a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217193716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2217193716 |
| Directory | /workspace/200.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/201.uart_fifo_reset.1498657738 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 109447621844 ps |
| CPU time | 34.78 seconds |
| Started | Jul 13 06:04:10 PM PDT 24 |
| Finished | Jul 13 06:04:46 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-b5b26acd-4a52-4dbe-9fdc-e302347a384f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498657738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1498657738 |
| Directory | /workspace/201.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/202.uart_fifo_reset.3621448319 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 42509391984 ps |
| CPU time | 15.81 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:04:28 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-f5eaa0df-d773-4315-8510-82e16397480f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621448319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3621448319 |
| Directory | /workspace/202.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/203.uart_fifo_reset.2507886989 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 152319065191 ps |
| CPU time | 59.88 seconds |
| Started | Jul 13 06:04:09 PM PDT 24 |
| Finished | Jul 13 06:05:09 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-5468d12b-cd5d-4fcc-a30c-173a1682fb67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507886989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2507886989 |
| Directory | /workspace/203.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/205.uart_fifo_reset.2214443634 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 10741822421 ps |
| CPU time | 26.43 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:04:39 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-4accd887-d77d-4ef4-b193-e6117dc78cd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214443634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2214443634 |
| Directory | /workspace/205.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/207.uart_fifo_reset.3248077165 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 35751596606 ps |
| CPU time | 17.64 seconds |
| Started | Jul 13 06:04:11 PM PDT 24 |
| Finished | Jul 13 06:04:30 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-fc52292d-2cad-4f04-806f-3dd1819fd1e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3248077165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3248077165 |
| Directory | /workspace/207.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/208.uart_fifo_reset.649734138 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 98109160894 ps |
| CPU time | 38.8 seconds |
| Started | Jul 13 06:04:12 PM PDT 24 |
| Finished | Jul 13 06:04:52 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-dae5cfea-4a71-453f-a314-5134dbeb39b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649734138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.649734138 |
| Directory | /workspace/208.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/209.uart_fifo_reset.3791389481 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 46689636037 ps |
| CPU time | 38.09 seconds |
| Started | Jul 13 06:04:13 PM PDT 24 |
| Finished | Jul 13 06:04:51 PM PDT 24 |
| Peak memory | 200160 kb |
| Host | smart-999b374b-6460-4cb9-beb9-254c5ecec701 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791389481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3791389481 |
| Directory | /workspace/209.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_alert_test.3432052024 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 14847043 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 05:59:58 PM PDT 24 |
| Finished | Jul 13 05:59:58 PM PDT 24 |
| Peak memory | 194920 kb |
| Host | smart-004d54e3-eda6-454f-87d3-6b32d18662be |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432052024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3432052024 |
| Directory | /workspace/21.uart_alert_test/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_full.2680474053 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 169236635628 ps |
| CPU time | 593.38 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:09:54 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-1af812b7-ede0-435b-8f4a-bedb2677631c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680474053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2680474053 |
| Directory | /workspace/21.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_overflow.646260552 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 30346558439 ps |
| CPU time | 50.89 seconds |
| Started | Jul 13 06:00:02 PM PDT 24 |
| Finished | Jul 13 06:00:54 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-365a66cc-5331-455d-813d-390d753c1544 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646260552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.646260552 |
| Directory | /workspace/21.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_reset.2741800820 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 19470150525 ps |
| CPU time | 20.77 seconds |
| Started | Jul 13 05:59:59 PM PDT 24 |
| Finished | Jul 13 06:00:20 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-83e4f825-3029-4d57-b78d-a7251a5aaeb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2741800820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2741800820 |
| Directory | /workspace/21.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_intr.3245054250 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 7708985080 ps |
| CPU time | 3.29 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:00:04 PM PDT 24 |
| Peak memory | 196572 kb |
| Host | smart-1c47d894-b3fb-4e0b-96f2-726b1e66dd2e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245054250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3245054250 |
| Directory | /workspace/21.uart_intr/latest |
| Test location | /workspace/coverage/default/21.uart_long_xfer_wo_dly.3073985593 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 139764777168 ps |
| CPU time | 228.9 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:03:50 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-babc8c83-3b30-4a63-8c02-521311d14dfd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3073985593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3073985593 |
| Directory | /workspace/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/21.uart_loopback.3287943050 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 4278457805 ps |
| CPU time | 8.22 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:00:10 PM PDT 24 |
| Peak memory | 198520 kb |
| Host | smart-d629ca8e-b65f-4c28-871c-895ef7a8fb94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287943050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3287943050 |
| Directory | /workspace/21.uart_loopback/latest |
| Test location | /workspace/coverage/default/21.uart_noise_filter.512649701 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 129232250576 ps |
| CPU time | 51.12 seconds |
| Started | Jul 13 06:00:08 PM PDT 24 |
| Finished | Jul 13 06:01:00 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-b1185a7b-3ba7-41b4-8d4f-3c9bf2b94939 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512649701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.512649701 |
| Directory | /workspace/21.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/21.uart_perf.769993112 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 6391826145 ps |
| CPU time | 77.45 seconds |
| Started | Jul 13 05:59:59 PM PDT 24 |
| Finished | Jul 13 06:01:17 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-d118da6f-0f63-4dea-846f-925b025f748e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=769993112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.769993112 |
| Directory | /workspace/21.uart_perf/latest |
| Test location | /workspace/coverage/default/21.uart_rx_oversample.4273986289 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4197282580 ps |
| CPU time | 2.81 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:00:05 PM PDT 24 |
| Peak memory | 198428 kb |
| Host | smart-2dea660b-1c45-4548-989c-11d4fba25339 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4273986289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.4273986289 |
| Directory | /workspace/21.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/21.uart_rx_parity_err.4188920963 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 47087299711 ps |
| CPU time | 46.21 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:00:47 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-268527a1-2eb5-4419-a4bd-6add98142f12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188920963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4188920963 |
| Directory | /workspace/21.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/21.uart_rx_start_bit_filter.1552373429 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 594986496 ps |
| CPU time | 1.06 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:00:01 PM PDT 24 |
| Peak memory | 195504 kb |
| Host | smart-72fa0117-db38-4f2b-9ebe-c76796578254 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552373429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1552373429 |
| Directory | /workspace/21.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/21.uart_smoke.3227862076 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 689208887 ps |
| CPU time | 1.58 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:10 PM PDT 24 |
| Peak memory | 198900 kb |
| Host | smart-f47f1149-48d1-4e7a-bfd5-fee44c2d0ce1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227862076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3227862076 |
| Directory | /workspace/21.uart_smoke/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all.1525732211 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 23523159001 ps |
| CPU time | 274.01 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:04:36 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-2bc07d6c-cb6e-45e9-a29b-07e89030274c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525732211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1525732211 |
| Directory | /workspace/21.uart_stress_all/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2374539235 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 42504024553 ps |
| CPU time | 833.82 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:13:56 PM PDT 24 |
| Peak memory | 209552 kb |
| Host | smart-8dc43852-df24-4902-824f-bcb4c84ad3e9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374539235 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2374539235 |
| Directory | /workspace/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.uart_tx_ovrd.3837108764 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 2403543857 ps |
| CPU time | 2.75 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:00:05 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-93da8905-f59d-4edc-8454-9e5ef7dd5db3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837108764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3837108764 |
| Directory | /workspace/21.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/21.uart_tx_rx.174991971 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 64135749724 ps |
| CPU time | 23.76 seconds |
| Started | Jul 13 06:00:02 PM PDT 24 |
| Finished | Jul 13 06:00:27 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-f232b357-50be-4420-ac33-50847d20f104 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=174991971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.174991971 |
| Directory | /workspace/21.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/210.uart_fifo_reset.1314217979 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 40817462073 ps |
| CPU time | 27.98 seconds |
| Started | Jul 13 06:04:17 PM PDT 24 |
| Finished | Jul 13 06:04:47 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-ecff6cfd-687e-4d0b-b50c-3eaaf9bd1da0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314217979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1314217979 |
| Directory | /workspace/210.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/211.uart_fifo_reset.1089338963 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 7696564927 ps |
| CPU time | 4.94 seconds |
| Started | Jul 13 06:04:19 PM PDT 24 |
| Finished | Jul 13 06:04:25 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-639fc9d3-999b-439e-b77a-b473a58e17ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089338963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1089338963 |
| Directory | /workspace/211.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/212.uart_fifo_reset.1730309553 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 84987040014 ps |
| CPU time | 37 seconds |
| Started | Jul 13 06:04:19 PM PDT 24 |
| Finished | Jul 13 06:04:56 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-b93d3149-316c-403d-9c8c-f8ad9a064617 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730309553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1730309553 |
| Directory | /workspace/212.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/215.uart_fifo_reset.3059657347 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 10911685170 ps |
| CPU time | 17.03 seconds |
| Started | Jul 13 06:04:18 PM PDT 24 |
| Finished | Jul 13 06:04:36 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-719d81eb-ca78-4e83-a205-f95b2b208ef3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059657347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3059657347 |
| Directory | /workspace/215.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/216.uart_fifo_reset.3708992389 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 161231992963 ps |
| CPU time | 108.33 seconds |
| Started | Jul 13 06:04:18 PM PDT 24 |
| Finished | Jul 13 06:06:07 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-4eaccc7b-318f-4f40-a41b-774b250d1356 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708992389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3708992389 |
| Directory | /workspace/216.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/217.uart_fifo_reset.1738354645 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 46655105642 ps |
| CPU time | 32.62 seconds |
| Started | Jul 13 06:04:18 PM PDT 24 |
| Finished | Jul 13 06:04:52 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-6fa60df7-f7c5-452d-822a-d4702a9a05c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738354645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1738354645 |
| Directory | /workspace/217.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/218.uart_fifo_reset.3461945007 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 99806327313 ps |
| CPU time | 91.16 seconds |
| Started | Jul 13 06:04:20 PM PDT 24 |
| Finished | Jul 13 06:05:52 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-86a03f5a-cf88-4195-9888-f139316d9bf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461945007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3461945007 |
| Directory | /workspace/218.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/219.uart_fifo_reset.954362371 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 77184220264 ps |
| CPU time | 26.97 seconds |
| Started | Jul 13 06:04:17 PM PDT 24 |
| Finished | Jul 13 06:04:45 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-2fb2d496-9193-48f1-8568-6b78aea4914d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954362371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.954362371 |
| Directory | /workspace/219.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_alert_test.1417216159 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 38361113 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 06:00:02 PM PDT 24 |
| Finished | Jul 13 06:00:04 PM PDT 24 |
| Peak memory | 194484 kb |
| Host | smart-8050dfdc-7f29-4757-b2c2-c118573ea65f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417216159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1417216159 |
| Directory | /workspace/22.uart_alert_test/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_full.1954837762 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 168036685384 ps |
| CPU time | 405.55 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:06:48 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-e7249e2d-0171-424f-b6b3-8c5e10f3b2e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954837762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1954837762 |
| Directory | /workspace/22.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_overflow.991716093 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 121491216235 ps |
| CPU time | 176.27 seconds |
| Started | Jul 13 05:59:59 PM PDT 24 |
| Finished | Jul 13 06:02:55 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-2720e62f-b6b9-4b4d-9bba-87a061c771d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=991716093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.991716093 |
| Directory | /workspace/22.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_reset.290399645 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 141130377032 ps |
| CPU time | 95.23 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:01:36 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-02101454-1dd2-4b8d-87ef-5835b6989f1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290399645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.290399645 |
| Directory | /workspace/22.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_intr.1729697496 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 34352877058 ps |
| CPU time | 15.9 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:24 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-fdc9c90a-e770-458f-b0bb-6020e4d8d158 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729697496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1729697496 |
| Directory | /workspace/22.uart_intr/latest |
| Test location | /workspace/coverage/default/22.uart_long_xfer_wo_dly.3572735050 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 152799115506 ps |
| CPU time | 377.61 seconds |
| Started | Jul 13 06:00:02 PM PDT 24 |
| Finished | Jul 13 06:06:20 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-601e85f5-d84a-492e-b473-041fa5c5d704 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3572735050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3572735050 |
| Directory | /workspace/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/22.uart_loopback.2935185308 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 6543627158 ps |
| CPU time | 3.77 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:00:05 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-c42fc8c5-5609-4215-8f3a-432bf8bcd2ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935185308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2935185308 |
| Directory | /workspace/22.uart_loopback/latest |
| Test location | /workspace/coverage/default/22.uart_noise_filter.2481289578 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 11518869632 ps |
| CPU time | 19.39 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:00:21 PM PDT 24 |
| Peak memory | 199060 kb |
| Host | smart-6e217c5d-aca1-4d49-a62c-74621d7f47a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2481289578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2481289578 |
| Directory | /workspace/22.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/22.uart_perf.3943066849 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 17454876723 ps |
| CPU time | 657.95 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:11:00 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-7d9ec6ef-dd1d-4adb-90d6-423b32881dda |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3943066849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3943066849 |
| Directory | /workspace/22.uart_perf/latest |
| Test location | /workspace/coverage/default/22.uart_rx_oversample.2571431775 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2124121894 ps |
| CPU time | 8.2 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:17 PM PDT 24 |
| Peak memory | 197720 kb |
| Host | smart-fa44b1fa-67da-4738-a5bd-98ec878acf84 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2571431775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2571431775 |
| Directory | /workspace/22.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/22.uart_rx_parity_err.272616410 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 98471847714 ps |
| CPU time | 137.27 seconds |
| Started | Jul 13 06:00:02 PM PDT 24 |
| Finished | Jul 13 06:02:20 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-a0a42e80-3b4d-4c8b-9d44-f354708f657e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272616410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.272616410 |
| Directory | /workspace/22.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/22.uart_rx_start_bit_filter.2501849991 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 34068259008 ps |
| CPU time | 25.39 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:00:27 PM PDT 24 |
| Peak memory | 196124 kb |
| Host | smart-e75d112b-9ed2-4e93-b9ea-aa05e0bb3a7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501849991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2501849991 |
| Directory | /workspace/22.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/22.uart_smoke.3442671160 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 531451247 ps |
| CPU time | 1.29 seconds |
| Started | Jul 13 05:59:59 PM PDT 24 |
| Finished | Jul 13 06:00:00 PM PDT 24 |
| Peak memory | 198224 kb |
| Host | smart-2b54ffd8-db18-4ea4-baee-63a180f16061 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442671160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3442671160 |
| Directory | /workspace/22.uart_smoke/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all.3433298365 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 267551573086 ps |
| CPU time | 51.39 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:00:53 PM PDT 24 |
| Peak memory | 208340 kb |
| Host | smart-b1dc0fc9-8eed-4927-b058-06a960256ff2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433298365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3433298365 |
| Directory | /workspace/22.uart_stress_all/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1218478310 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1189935779224 ps |
| CPU time | 799.23 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:13:20 PM PDT 24 |
| Peak memory | 224912 kb |
| Host | smart-5e6d2d94-d97f-444c-b71a-21ac27f255b3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218478310 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1218478310 |
| Directory | /workspace/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.uart_tx_ovrd.502639184 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 843094073 ps |
| CPU time | 1.61 seconds |
| Started | Jul 13 06:00:01 PM PDT 24 |
| Finished | Jul 13 06:00:04 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-cc803cab-8f65-4507-b269-ee60d819f68d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502639184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.502639184 |
| Directory | /workspace/22.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/22.uart_tx_rx.1751195112 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 48587063241 ps |
| CPU time | 87.75 seconds |
| Started | Jul 13 06:00:00 PM PDT 24 |
| Finished | Jul 13 06:01:28 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-00adc5c6-174e-405f-b309-ffda890a3519 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751195112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1751195112 |
| Directory | /workspace/22.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/220.uart_fifo_reset.1937092742 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 148811484448 ps |
| CPU time | 254.36 seconds |
| Started | Jul 13 06:04:18 PM PDT 24 |
| Finished | Jul 13 06:08:33 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-5e1e8c62-e938-4521-9dbc-2e9e16c2b8c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937092742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1937092742 |
| Directory | /workspace/220.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/221.uart_fifo_reset.66276972 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 69005464830 ps |
| CPU time | 29.25 seconds |
| Started | Jul 13 06:04:18 PM PDT 24 |
| Finished | Jul 13 06:04:48 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-4b5ff95d-34ae-4347-b76c-c07e2edcc84e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66276972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.66276972 |
| Directory | /workspace/221.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/222.uart_fifo_reset.3700552971 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 26487606236 ps |
| CPU time | 38.38 seconds |
| Started | Jul 13 06:04:20 PM PDT 24 |
| Finished | Jul 13 06:04:59 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-181e8707-5a74-47aa-a457-8f15c94888b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700552971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3700552971 |
| Directory | /workspace/222.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/224.uart_fifo_reset.940724865 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 53265534611 ps |
| CPU time | 83.14 seconds |
| Started | Jul 13 06:04:18 PM PDT 24 |
| Finished | Jul 13 06:05:42 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-56ae494a-150e-4f89-be03-1ab375f3757f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=940724865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.940724865 |
| Directory | /workspace/224.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/225.uart_fifo_reset.4172081299 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 85884338217 ps |
| CPU time | 145.73 seconds |
| Started | Jul 13 06:04:18 PM PDT 24 |
| Finished | Jul 13 06:06:45 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-9da358c3-4218-4554-9650-50063e4f203b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172081299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.4172081299 |
| Directory | /workspace/225.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/226.uart_fifo_reset.2170884100 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 33949754131 ps |
| CPU time | 12.76 seconds |
| Started | Jul 13 06:04:18 PM PDT 24 |
| Finished | Jul 13 06:04:32 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-c83b5e00-54be-48aa-a107-60cdef4c667d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2170884100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2170884100 |
| Directory | /workspace/226.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/227.uart_fifo_reset.547044032 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 43292902877 ps |
| CPU time | 9.9 seconds |
| Started | Jul 13 06:04:21 PM PDT 24 |
| Finished | Jul 13 06:04:31 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-22c90950-bc00-45bc-87fd-105f3c2e1d0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547044032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.547044032 |
| Directory | /workspace/227.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/228.uart_fifo_reset.1332626181 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 35395557636 ps |
| CPU time | 33.16 seconds |
| Started | Jul 13 06:04:19 PM PDT 24 |
| Finished | Jul 13 06:04:53 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-59fe2b09-8882-41af-a648-26c9bd7ddf35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332626181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1332626181 |
| Directory | /workspace/228.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_alert_test.3371511149 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 48039253 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 06:00:05 PM PDT 24 |
| Finished | Jul 13 06:00:06 PM PDT 24 |
| Peak memory | 195236 kb |
| Host | smart-6fbfd27c-6a30-409b-97e5-b8d00d78f0fc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371511149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3371511149 |
| Directory | /workspace/23.uart_alert_test/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_full.2786367486 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 50198752567 ps |
| CPU time | 78.39 seconds |
| Started | Jul 13 06:00:05 PM PDT 24 |
| Finished | Jul 13 06:01:24 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-8988537f-0acb-4ead-bb00-79bead83b4e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786367486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2786367486 |
| Directory | /workspace/23.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_overflow.2499323662 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 35057954118 ps |
| CPU time | 13.97 seconds |
| Started | Jul 13 06:00:06 PM PDT 24 |
| Finished | Jul 13 06:00:21 PM PDT 24 |
| Peak memory | 198440 kb |
| Host | smart-6941d0c9-2466-4a39-9e51-91740db5f0ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499323662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2499323662 |
| Directory | /workspace/23.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_reset.3095822708 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 28411624379 ps |
| CPU time | 44.61 seconds |
| Started | Jul 13 06:00:06 PM PDT 24 |
| Finished | Jul 13 06:00:52 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-ffebb54c-ed75-4776-a1ae-65fd47e1d5c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095822708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3095822708 |
| Directory | /workspace/23.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_intr.799812305 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 60778487307 ps |
| CPU time | 108.34 seconds |
| Started | Jul 13 06:00:08 PM PDT 24 |
| Finished | Jul 13 06:01:57 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-8a9232f8-949a-40ff-abe6-5148c016bb74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799812305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.799812305 |
| Directory | /workspace/23.uart_intr/latest |
| Test location | /workspace/coverage/default/23.uart_long_xfer_wo_dly.3480028971 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 122421731833 ps |
| CPU time | 1243.59 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:20:52 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-8ee1d3e2-12be-45f6-a5da-8b742fe97646 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3480028971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3480028971 |
| Directory | /workspace/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/23.uart_loopback.520171615 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 10444287347 ps |
| CPU time | 9.05 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:17 PM PDT 24 |
| Peak memory | 198756 kb |
| Host | smart-8217f266-a36c-49e4-b4dc-c75786861be7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520171615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.520171615 |
| Directory | /workspace/23.uart_loopback/latest |
| Test location | /workspace/coverage/default/23.uart_noise_filter.2180753244 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 54453246487 ps |
| CPU time | 26.18 seconds |
| Started | Jul 13 06:00:06 PM PDT 24 |
| Finished | Jul 13 06:00:33 PM PDT 24 |
| Peak memory | 199120 kb |
| Host | smart-4a342d5f-b6d5-428e-9b29-df2ba66915b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180753244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2180753244 |
| Directory | /workspace/23.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/23.uart_perf.3599050919 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 25591630117 ps |
| CPU time | 191.98 seconds |
| Started | Jul 13 06:00:06 PM PDT 24 |
| Finished | Jul 13 06:03:19 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-02ef8297-2081-4c8b-a374-d530fdff1289 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3599050919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3599050919 |
| Directory | /workspace/23.uart_perf/latest |
| Test location | /workspace/coverage/default/23.uart_rx_oversample.882348258 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2445563160 ps |
| CPU time | 3.65 seconds |
| Started | Jul 13 06:00:08 PM PDT 24 |
| Finished | Jul 13 06:00:12 PM PDT 24 |
| Peak memory | 198068 kb |
| Host | smart-a0d2d704-26a1-48cd-b4ff-e8806dc58e2e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=882348258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.882348258 |
| Directory | /workspace/23.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/23.uart_rx_parity_err.345787912 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 53076584623 ps |
| CPU time | 81.72 seconds |
| Started | Jul 13 06:00:05 PM PDT 24 |
| Finished | Jul 13 06:01:28 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-504de16f-64ff-4ccb-95e2-d7509f18eb1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345787912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.345787912 |
| Directory | /workspace/23.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/23.uart_rx_start_bit_filter.2245731444 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 4487897702 ps |
| CPU time | 3.85 seconds |
| Started | Jul 13 06:00:05 PM PDT 24 |
| Finished | Jul 13 06:00:10 PM PDT 24 |
| Peak memory | 196368 kb |
| Host | smart-1c4fd6c8-f248-43c7-bb4d-cf337b35a861 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245731444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2245731444 |
| Directory | /workspace/23.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/23.uart_smoke.1286807907 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 5331148828 ps |
| CPU time | 10.82 seconds |
| Started | Jul 13 06:00:08 PM PDT 24 |
| Finished | Jul 13 06:00:20 PM PDT 24 |
| Peak memory | 199268 kb |
| Host | smart-c7dcd9d0-0eca-4f69-b298-0ea922016497 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286807907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1286807907 |
| Directory | /workspace/23.uart_smoke/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all.1333220879 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 226482520073 ps |
| CPU time | 728.18 seconds |
| Started | Jul 13 06:00:05 PM PDT 24 |
| Finished | Jul 13 06:12:14 PM PDT 24 |
| Peak memory | 200056 kb |
| Host | smart-4f9493f8-8963-4602-9adc-9f1d36b1bce1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333220879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1333220879 |
| Directory | /workspace/23.uart_stress_all/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3555882185 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 90574061732 ps |
| CPU time | 1249.85 seconds |
| Started | Jul 13 06:00:06 PM PDT 24 |
| Finished | Jul 13 06:20:57 PM PDT 24 |
| Peak memory | 216324 kb |
| Host | smart-72846412-e921-458d-9540-f12da656832d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555882185 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3555882185 |
| Directory | /workspace/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.uart_tx_ovrd.2483072486 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 12195437116 ps |
| CPU time | 39.86 seconds |
| Started | Jul 13 06:00:06 PM PDT 24 |
| Finished | Jul 13 06:00:47 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-4462691a-2565-460c-9fbd-433b10a6481e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483072486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2483072486 |
| Directory | /workspace/23.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/23.uart_tx_rx.2505058780 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 50985739226 ps |
| CPU time | 103.04 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:01:52 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-5774119b-8715-4974-95ef-582ba89e130f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505058780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2505058780 |
| Directory | /workspace/23.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/230.uart_fifo_reset.4232263239 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 33943796768 ps |
| CPU time | 67.29 seconds |
| Started | Jul 13 06:04:25 PM PDT 24 |
| Finished | Jul 13 06:05:33 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-39e92b68-de54-478d-b6e6-b51429eff8df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4232263239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4232263239 |
| Directory | /workspace/230.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/231.uart_fifo_reset.1169713520 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 75673443405 ps |
| CPU time | 57.88 seconds |
| Started | Jul 13 06:04:26 PM PDT 24 |
| Finished | Jul 13 06:05:25 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-50f64875-ea6b-4e31-a86a-8271e7683e65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169713520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1169713520 |
| Directory | /workspace/231.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/232.uart_fifo_reset.4044161082 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 126207020994 ps |
| CPU time | 12.4 seconds |
| Started | Jul 13 06:04:26 PM PDT 24 |
| Finished | Jul 13 06:04:39 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-56943987-7404-43fd-85ac-5b83530718cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044161082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4044161082 |
| Directory | /workspace/232.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/234.uart_fifo_reset.2115036365 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 26668349984 ps |
| CPU time | 27.94 seconds |
| Started | Jul 13 06:04:25 PM PDT 24 |
| Finished | Jul 13 06:04:54 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-6f8fa5dd-fcc4-48c8-977a-2b281c8d70ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2115036365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2115036365 |
| Directory | /workspace/234.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/235.uart_fifo_reset.2286688889 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 30469468252 ps |
| CPU time | 14.31 seconds |
| Started | Jul 13 06:04:25 PM PDT 24 |
| Finished | Jul 13 06:04:39 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-38bae27f-6129-45e5-8fae-63b960c2c364 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286688889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2286688889 |
| Directory | /workspace/235.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/236.uart_fifo_reset.3497733118 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 92594568842 ps |
| CPU time | 107.94 seconds |
| Started | Jul 13 06:04:26 PM PDT 24 |
| Finished | Jul 13 06:06:15 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-294a4398-fc22-4677-9d59-1850e11a111f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497733118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3497733118 |
| Directory | /workspace/236.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/237.uart_fifo_reset.1119388615 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 106278926554 ps |
| CPU time | 165.52 seconds |
| Started | Jul 13 06:04:27 PM PDT 24 |
| Finished | Jul 13 06:07:13 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-78e0191d-6987-49df-a88b-5929cf745048 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119388615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1119388615 |
| Directory | /workspace/237.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/238.uart_fifo_reset.3649402409 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 29877678310 ps |
| CPU time | 17.64 seconds |
| Started | Jul 13 06:04:28 PM PDT 24 |
| Finished | Jul 13 06:04:47 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-a2cc8aa6-f850-4309-aed2-18a1958ef74e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3649402409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3649402409 |
| Directory | /workspace/238.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/239.uart_fifo_reset.4010352748 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 16527272861 ps |
| CPU time | 24.72 seconds |
| Started | Jul 13 06:04:28 PM PDT 24 |
| Finished | Jul 13 06:04:54 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-cd24b169-16aa-4b86-ae84-949a9c51718a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010352748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4010352748 |
| Directory | /workspace/239.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_alert_test.3945517052 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 12891138 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:00:15 PM PDT 24 |
| Peak memory | 195236 kb |
| Host | smart-08f9aa75-3613-4b54-a73d-f297ea8e0aec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945517052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3945517052 |
| Directory | /workspace/24.uart_alert_test/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_full.963250222 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 64309120610 ps |
| CPU time | 45.77 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:53 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-498c4b58-407d-47ff-9df4-1f0e08b579bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963250222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.963250222 |
| Directory | /workspace/24.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_overflow.3902615916 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 77282717507 ps |
| CPU time | 53.48 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:01:02 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-c1ffcf91-9cdf-494e-a699-ffdb4a1c539f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3902615916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3902615916 |
| Directory | /workspace/24.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_reset.3669818163 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 9532321470 ps |
| CPU time | 14.42 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:22 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-0d64dab7-ac08-491b-b65a-5fc8f15b6cb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669818163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3669818163 |
| Directory | /workspace/24.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_intr.1989574246 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 417451007093 ps |
| CPU time | 356.78 seconds |
| Started | Jul 13 06:00:08 PM PDT 24 |
| Finished | Jul 13 06:06:06 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-058a8f9e-fb1d-4d2a-a177-8432187f095d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989574246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1989574246 |
| Directory | /workspace/24.uart_intr/latest |
| Test location | /workspace/coverage/default/24.uart_long_xfer_wo_dly.1212730233 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 142588292008 ps |
| CPU time | 299.38 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:05:15 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-44990b25-91c6-4b00-afdd-26412724484c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1212730233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1212730233 |
| Directory | /workspace/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/24.uart_loopback.872814028 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 4103895629 ps |
| CPU time | 1.89 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:10 PM PDT 24 |
| Peak memory | 199276 kb |
| Host | smart-64e92eee-dddd-4ec3-bebc-62d2eeb86dcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872814028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.872814028 |
| Directory | /workspace/24.uart_loopback/latest |
| Test location | /workspace/coverage/default/24.uart_noise_filter.4202972659 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 11564386769 ps |
| CPU time | 22.03 seconds |
| Started | Jul 13 06:00:06 PM PDT 24 |
| Finished | Jul 13 06:00:28 PM PDT 24 |
| Peak memory | 200012 kb |
| Host | smart-d85f41ce-8fba-4a4c-9ba5-54cfed358906 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202972659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4202972659 |
| Directory | /workspace/24.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/24.uart_perf.726133338 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5218827655 ps |
| CPU time | 268.71 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:04:44 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-84715450-45c6-4e17-aecd-01ae9546f0e0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=726133338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.726133338 |
| Directory | /workspace/24.uart_perf/latest |
| Test location | /workspace/coverage/default/24.uart_rx_oversample.2854574516 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 6182989279 ps |
| CPU time | 49.45 seconds |
| Started | Jul 13 06:00:08 PM PDT 24 |
| Finished | Jul 13 06:00:58 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-d190b647-71ee-44dd-aa27-c7ae4c073bfc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2854574516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2854574516 |
| Directory | /workspace/24.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/24.uart_rx_parity_err.171249031 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 143158770837 ps |
| CPU time | 96.96 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:01:44 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-2d4ddcba-5368-4446-a643-5a487d382246 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171249031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.171249031 |
| Directory | /workspace/24.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/24.uart_rx_start_bit_filter.2687302632 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 4310527732 ps |
| CPU time | 6.72 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:15 PM PDT 24 |
| Peak memory | 196368 kb |
| Host | smart-0664c79e-3de0-4d39-8c81-b77a9f72c57e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687302632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2687302632 |
| Directory | /workspace/24.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/24.uart_smoke.3499052513 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5996720155 ps |
| CPU time | 12.71 seconds |
| Started | Jul 13 06:00:06 PM PDT 24 |
| Finished | Jul 13 06:00:20 PM PDT 24 |
| Peak memory | 199224 kb |
| Host | smart-79d1537b-97fd-42d8-96fd-f4d93a9f0dbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499052513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3499052513 |
| Directory | /workspace/24.uart_smoke/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all.2342292030 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 385163957577 ps |
| CPU time | 960.96 seconds |
| Started | Jul 13 06:00:16 PM PDT 24 |
| Finished | Jul 13 06:16:18 PM PDT 24 |
| Peak memory | 216396 kb |
| Host | smart-703bbd31-8e32-4f10-9c2d-08793222683f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342292030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2342292030 |
| Directory | /workspace/24.uart_stress_all/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all_with_rand_reset.734769972 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 72968327524 ps |
| CPU time | 650.49 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:11:06 PM PDT 24 |
| Peak memory | 216380 kb |
| Host | smart-a95813f5-b321-4aa5-a355-d46edc8ab3c5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734769972 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.734769972 |
| Directory | /workspace/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.uart_tx_ovrd.787327790 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3853033160 ps |
| CPU time | 2.34 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:00:10 PM PDT 24 |
| Peak memory | 199964 kb |
| Host | smart-3bf36a09-34aa-4d82-8ea3-3c9fd44c80f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787327790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.787327790 |
| Directory | /workspace/24.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/24.uart_tx_rx.3332067048 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 103124780901 ps |
| CPU time | 123.94 seconds |
| Started | Jul 13 06:00:07 PM PDT 24 |
| Finished | Jul 13 06:02:12 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-89692824-1ce8-4748-b5c3-0b271cbad41d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332067048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3332067048 |
| Directory | /workspace/24.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/240.uart_fifo_reset.4184582390 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 30001750788 ps |
| CPU time | 13.67 seconds |
| Started | Jul 13 06:04:28 PM PDT 24 |
| Finished | Jul 13 06:04:43 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-3e516270-d936-4f11-acb7-384bfd4865fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184582390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4184582390 |
| Directory | /workspace/240.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/241.uart_fifo_reset.4003780425 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 70932545928 ps |
| CPU time | 32.11 seconds |
| Started | Jul 13 06:04:28 PM PDT 24 |
| Finished | Jul 13 06:05:01 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-53c36589-9d2b-4fad-9fa8-46999185e948 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003780425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4003780425 |
| Directory | /workspace/241.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/242.uart_fifo_reset.778917571 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 72112898440 ps |
| CPU time | 31.21 seconds |
| Started | Jul 13 06:04:28 PM PDT 24 |
| Finished | Jul 13 06:05:00 PM PDT 24 |
| Peak memory | 198552 kb |
| Host | smart-f24b05d5-a59a-40bd-975c-2e9726d81fd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778917571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.778917571 |
| Directory | /workspace/242.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/243.uart_fifo_reset.3804517496 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 75586399591 ps |
| CPU time | 215.57 seconds |
| Started | Jul 13 06:04:24 PM PDT 24 |
| Finished | Jul 13 06:08:01 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-82bd9a8b-ef57-4756-b934-713e8d9a190c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804517496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3804517496 |
| Directory | /workspace/243.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/244.uart_fifo_reset.2735954529 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 49945660780 ps |
| CPU time | 53.5 seconds |
| Started | Jul 13 06:04:27 PM PDT 24 |
| Finished | Jul 13 06:05:21 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-0948e66b-c680-4095-b727-763edacade9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735954529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2735954529 |
| Directory | /workspace/244.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/245.uart_fifo_reset.3271108829 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 64932430941 ps |
| CPU time | 36.25 seconds |
| Started | Jul 13 06:04:25 PM PDT 24 |
| Finished | Jul 13 06:05:02 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-754eed7a-9f9b-4c31-ab15-2d19f595e241 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271108829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3271108829 |
| Directory | /workspace/245.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/246.uart_fifo_reset.949744444 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 165637140282 ps |
| CPU time | 96.2 seconds |
| Started | Jul 13 06:04:34 PM PDT 24 |
| Finished | Jul 13 06:06:11 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-50ab8e53-15c0-45e4-aff9-1d53b3e1f4d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949744444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.949744444 |
| Directory | /workspace/246.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/247.uart_fifo_reset.1366383088 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 161682546681 ps |
| CPU time | 63.32 seconds |
| Started | Jul 13 06:04:34 PM PDT 24 |
| Finished | Jul 13 06:05:38 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-1571a6c3-da8d-4fcc-b47f-3561e9e4ba32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366383088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1366383088 |
| Directory | /workspace/247.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/248.uart_fifo_reset.3046203195 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 69621061375 ps |
| CPU time | 30.84 seconds |
| Started | Jul 13 06:04:39 PM PDT 24 |
| Finished | Jul 13 06:05:11 PM PDT 24 |
| Peak memory | 199552 kb |
| Host | smart-b36cbd75-c840-474f-afad-e8f9275b7b08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046203195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3046203195 |
| Directory | /workspace/248.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/249.uart_fifo_reset.3772753196 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 177126364890 ps |
| CPU time | 137.81 seconds |
| Started | Jul 13 06:04:35 PM PDT 24 |
| Finished | Jul 13 06:06:53 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-45ae8b17-1b32-4fca-ba61-b79e9b736997 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772753196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3772753196 |
| Directory | /workspace/249.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_alert_test.499084568 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 45521905 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:00:15 PM PDT 24 |
| Peak memory | 195172 kb |
| Host | smart-2bc8d3eb-a548-47fd-b88a-c8df680169d7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499084568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.499084568 |
| Directory | /workspace/25.uart_alert_test/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_full.2913848074 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 133896145327 ps |
| CPU time | 93.78 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:01:50 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-5b1c89a4-6ee1-4b99-9349-269c2d34f905 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913848074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2913848074 |
| Directory | /workspace/25.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_overflow.916108516 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 204682191971 ps |
| CPU time | 367.11 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:06:23 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-9fe44826-f26c-41bb-a0fb-e8a8079dd754 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916108516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.916108516 |
| Directory | /workspace/25.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_reset.3070039286 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 80667704389 ps |
| CPU time | 54.06 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:01:10 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-3ef57197-398c-4181-8233-14bc92f595df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3070039286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3070039286 |
| Directory | /workspace/25.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_intr.3401195711 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 9862526411 ps |
| CPU time | 23.2 seconds |
| Started | Jul 13 06:00:17 PM PDT 24 |
| Finished | Jul 13 06:00:41 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-8f3bed65-4763-46a5-9abe-d6f59aeb9b93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401195711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3401195711 |
| Directory | /workspace/25.uart_intr/latest |
| Test location | /workspace/coverage/default/25.uart_long_xfer_wo_dly.3924857655 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 207925333299 ps |
| CPU time | 359.19 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:06:14 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-c43aa306-861b-4dec-8ba6-d23ed6cdbcb4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3924857655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3924857655 |
| Directory | /workspace/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/25.uart_loopback.1853909622 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2775588014 ps |
| CPU time | 4.33 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:00:20 PM PDT 24 |
| Peak memory | 195672 kb |
| Host | smart-b1076b52-9c0e-4b80-98ac-c6d37b0daa49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853909622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1853909622 |
| Directory | /workspace/25.uart_loopback/latest |
| Test location | /workspace/coverage/default/25.uart_noise_filter.2893830411 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 80832852184 ps |
| CPU time | 34.1 seconds |
| Started | Jul 13 06:00:16 PM PDT 24 |
| Finished | Jul 13 06:00:51 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-d6949d45-daa5-45c9-a867-00f161a90639 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893830411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2893830411 |
| Directory | /workspace/25.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/25.uart_perf.1839314240 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 25547953708 ps |
| CPU time | 385.06 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:06:41 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-d0b7658e-dc61-4f1b-933e-def7c37b55a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1839314240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1839314240 |
| Directory | /workspace/25.uart_perf/latest |
| Test location | /workspace/coverage/default/25.uart_rx_oversample.325749598 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5626784772 ps |
| CPU time | 51.34 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:01:07 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-53432f58-ddb3-474d-8675-8157b1b23189 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=325749598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.325749598 |
| Directory | /workspace/25.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/25.uart_rx_parity_err.2651196358 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 63982173896 ps |
| CPU time | 51.27 seconds |
| Started | Jul 13 06:00:12 PM PDT 24 |
| Finished | Jul 13 06:01:05 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-7d1c509a-8026-40d6-8556-f5cca4055923 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2651196358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2651196358 |
| Directory | /workspace/25.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/25.uart_rx_start_bit_filter.3164370557 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 34005662775 ps |
| CPU time | 48.97 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:01:05 PM PDT 24 |
| Peak memory | 195632 kb |
| Host | smart-1ef650c7-e53e-492f-ab5f-b3489b39276f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164370557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3164370557 |
| Directory | /workspace/25.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/25.uart_smoke.4257220828 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 497526237 ps |
| CPU time | 2.21 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:00:18 PM PDT 24 |
| Peak memory | 198420 kb |
| Host | smart-0ae3d33d-0142-4478-ad4f-ddc997fa0a95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257220828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.4257220828 |
| Directory | /workspace/25.uart_smoke/latest |
| Test location | /workspace/coverage/default/25.uart_tx_ovrd.3460007670 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 6461104325 ps |
| CPU time | 21.66 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:00:38 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-4990d864-9d4b-42eb-bd70-489a39db0241 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3460007670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3460007670 |
| Directory | /workspace/25.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/25.uart_tx_rx.3208408829 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 53441540725 ps |
| CPU time | 76.41 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:01:32 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-1d422651-ae74-463c-8a1f-041359c03d7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208408829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3208408829 |
| Directory | /workspace/25.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/250.uart_fifo_reset.714541755 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 28835742436 ps |
| CPU time | 32.99 seconds |
| Started | Jul 13 06:04:37 PM PDT 24 |
| Finished | Jul 13 06:05:11 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-40944e05-ec86-4835-8f9a-9ded30fffa8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714541755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.714541755 |
| Directory | /workspace/250.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/252.uart_fifo_reset.2035155943 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 29139701513 ps |
| CPU time | 39.51 seconds |
| Started | Jul 13 06:04:36 PM PDT 24 |
| Finished | Jul 13 06:05:17 PM PDT 24 |
| Peak memory | 199972 kb |
| Host | smart-d4a8d062-b209-436b-8fce-f441c35ac903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2035155943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2035155943 |
| Directory | /workspace/252.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/253.uart_fifo_reset.1454420226 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 16825496458 ps |
| CPU time | 27.78 seconds |
| Started | Jul 13 06:04:35 PM PDT 24 |
| Finished | Jul 13 06:05:04 PM PDT 24 |
| Peak memory | 199340 kb |
| Host | smart-d33f6791-d73c-4fde-85e2-afc8a7a63e73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454420226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1454420226 |
| Directory | /workspace/253.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/254.uart_fifo_reset.4203959825 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 205162952254 ps |
| CPU time | 87.02 seconds |
| Started | Jul 13 06:04:36 PM PDT 24 |
| Finished | Jul 13 06:06:04 PM PDT 24 |
| Peak memory | 200196 kb |
| Host | smart-34533f3d-82e7-48a1-9ef1-da6eb9417ce0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4203959825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.4203959825 |
| Directory | /workspace/254.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/255.uart_fifo_reset.3551496269 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 64657957261 ps |
| CPU time | 19.05 seconds |
| Started | Jul 13 06:04:36 PM PDT 24 |
| Finished | Jul 13 06:04:56 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-2b527161-5e44-49c0-a546-18243f5c6031 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551496269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3551496269 |
| Directory | /workspace/255.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/256.uart_fifo_reset.3275232486 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 95346978514 ps |
| CPU time | 72.93 seconds |
| Started | Jul 13 06:04:34 PM PDT 24 |
| Finished | Jul 13 06:05:47 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-cfc899e7-46b0-43d3-9542-ab89adfda182 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275232486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3275232486 |
| Directory | /workspace/256.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/257.uart_fifo_reset.1654295470 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 48501230637 ps |
| CPU time | 71.26 seconds |
| Started | Jul 13 06:04:36 PM PDT 24 |
| Finished | Jul 13 06:05:48 PM PDT 24 |
| Peak memory | 199696 kb |
| Host | smart-348a378d-c414-4d55-ae10-92e65f5bf2d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654295470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1654295470 |
| Directory | /workspace/257.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/258.uart_fifo_reset.2547474278 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 62983741769 ps |
| CPU time | 15.51 seconds |
| Started | Jul 13 06:04:39 PM PDT 24 |
| Finished | Jul 13 06:04:55 PM PDT 24 |
| Peak memory | 199436 kb |
| Host | smart-01d5c612-b4d8-4fae-a58e-ea88d9e32f2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547474278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2547474278 |
| Directory | /workspace/258.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/259.uart_fifo_reset.849051985 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 66814803556 ps |
| CPU time | 112.69 seconds |
| Started | Jul 13 06:04:35 PM PDT 24 |
| Finished | Jul 13 06:06:29 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-e92fed38-2741-4002-bbb8-2ad39e17df12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=849051985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.849051985 |
| Directory | /workspace/259.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_alert_test.135520940 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 14617136 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 06:00:28 PM PDT 24 |
| Finished | Jul 13 06:00:30 PM PDT 24 |
| Peak memory | 195276 kb |
| Host | smart-53e1fd61-ff06-4aea-b212-f4967691e62a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135520940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.135520940 |
| Directory | /workspace/26.uart_alert_test/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_full.1879867470 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 102709014220 ps |
| CPU time | 186.58 seconds |
| Started | Jul 13 06:00:16 PM PDT 24 |
| Finished | Jul 13 06:03:23 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-ed9b58b2-9615-494a-9ab0-3eda675b1a97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879867470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1879867470 |
| Directory | /workspace/26.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_overflow.4190338940 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 33341110541 ps |
| CPU time | 9.08 seconds |
| Started | Jul 13 06:00:15 PM PDT 24 |
| Finished | Jul 13 06:00:25 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-ea99a444-e0a2-4f19-83d2-14244df66ff4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190338940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4190338940 |
| Directory | /workspace/26.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/26.uart_intr.2997044188 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 31566783934 ps |
| CPU time | 49.81 seconds |
| Started | Jul 13 06:00:21 PM PDT 24 |
| Finished | Jul 13 06:01:12 PM PDT 24 |
| Peak memory | 198832 kb |
| Host | smart-197e2421-9395-4759-9653-cba7053c7594 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997044188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2997044188 |
| Directory | /workspace/26.uart_intr/latest |
| Test location | /workspace/coverage/default/26.uart_long_xfer_wo_dly.3891715108 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 96962460139 ps |
| CPU time | 355.36 seconds |
| Started | Jul 13 06:00:23 PM PDT 24 |
| Finished | Jul 13 06:06:19 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-8be33f06-65ad-4b0b-9940-4d0a061d7131 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3891715108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3891715108 |
| Directory | /workspace/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/26.uart_loopback.4107961770 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 37638292 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 06:00:21 PM PDT 24 |
| Finished | Jul 13 06:00:23 PM PDT 24 |
| Peak memory | 195604 kb |
| Host | smart-9868bc62-fe22-4290-9494-bf1a56f34d80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4107961770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4107961770 |
| Directory | /workspace/26.uart_loopback/latest |
| Test location | /workspace/coverage/default/26.uart_noise_filter.4074756791 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 125604968346 ps |
| CPU time | 446.67 seconds |
| Started | Jul 13 06:00:23 PM PDT 24 |
| Finished | Jul 13 06:07:50 PM PDT 24 |
| Peak memory | 208120 kb |
| Host | smart-b6f6648b-896e-4b59-afed-b205cfc5d896 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074756791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4074756791 |
| Directory | /workspace/26.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/26.uart_perf.4243331376 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 10182662534 ps |
| CPU time | 292.45 seconds |
| Started | Jul 13 06:00:21 PM PDT 24 |
| Finished | Jul 13 06:05:15 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-dcd07a52-9a48-40a4-8e70-286c856705d4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4243331376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4243331376 |
| Directory | /workspace/26.uart_perf/latest |
| Test location | /workspace/coverage/default/26.uart_rx_oversample.4030769176 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 6553639175 ps |
| CPU time | 54.19 seconds |
| Started | Jul 13 06:00:20 PM PDT 24 |
| Finished | Jul 13 06:01:15 PM PDT 24 |
| Peak memory | 197916 kb |
| Host | smart-0435f609-a085-483d-b162-b3925a737338 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4030769176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4030769176 |
| Directory | /workspace/26.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/26.uart_rx_parity_err.1053405292 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 73276559413 ps |
| CPU time | 39.89 seconds |
| Started | Jul 13 06:00:21 PM PDT 24 |
| Finished | Jul 13 06:01:01 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-a0093ea8-e71b-4451-83f3-06982d864ef0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053405292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1053405292 |
| Directory | /workspace/26.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/26.uart_rx_start_bit_filter.3253223200 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 684607897 ps |
| CPU time | 1.6 seconds |
| Started | Jul 13 06:00:26 PM PDT 24 |
| Finished | Jul 13 06:00:27 PM PDT 24 |
| Peak memory | 195552 kb |
| Host | smart-4664ea0d-afcc-41ed-bb69-f5ee49f500a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253223200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3253223200 |
| Directory | /workspace/26.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/26.uart_smoke.3842456601 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 663198434 ps |
| CPU time | 2.06 seconds |
| Started | Jul 13 06:00:14 PM PDT 24 |
| Finished | Jul 13 06:00:16 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-8a9bbde1-4d72-4cef-8655-c862a8ea024d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842456601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3842456601 |
| Directory | /workspace/26.uart_smoke/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all.2465589209 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 52750069514 ps |
| CPU time | 80.72 seconds |
| Started | Jul 13 06:00:19 PM PDT 24 |
| Finished | Jul 13 06:01:40 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-68a77544-d80d-4b2a-8d8f-45486bf99904 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465589209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2465589209 |
| Directory | /workspace/26.uart_stress_all/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1936216681 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 82871876559 ps |
| CPU time | 466.53 seconds |
| Started | Jul 13 06:00:21 PM PDT 24 |
| Finished | Jul 13 06:08:09 PM PDT 24 |
| Peak memory | 210784 kb |
| Host | smart-90a43c73-7f38-409a-9356-128e70bd8cf4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936216681 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1936216681 |
| Directory | /workspace/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.uart_tx_ovrd.3300964119 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 4853675952 ps |
| CPU time | 1.86 seconds |
| Started | Jul 13 06:00:26 PM PDT 24 |
| Finished | Jul 13 06:00:28 PM PDT 24 |
| Peak memory | 198568 kb |
| Host | smart-7abc5126-e6b4-4572-9abf-284965689632 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300964119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3300964119 |
| Directory | /workspace/26.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/26.uart_tx_rx.2063840832 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 28577981740 ps |
| CPU time | 47.98 seconds |
| Started | Jul 13 06:00:16 PM PDT 24 |
| Finished | Jul 13 06:01:05 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-b0e57429-2716-44ca-beb8-68f53b31fc2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063840832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2063840832 |
| Directory | /workspace/26.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/260.uart_fifo_reset.2040484718 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 66358263394 ps |
| CPU time | 102.51 seconds |
| Started | Jul 13 06:04:36 PM PDT 24 |
| Finished | Jul 13 06:06:20 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-b4ad34d1-ff26-4b77-bdc9-20f2d8bdfef2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040484718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2040484718 |
| Directory | /workspace/260.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/261.uart_fifo_reset.1157143205 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 97238628769 ps |
| CPU time | 37.47 seconds |
| Started | Jul 13 06:04:34 PM PDT 24 |
| Finished | Jul 13 06:05:13 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-847aa756-416d-4c25-acf2-8382465eb114 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157143205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1157143205 |
| Directory | /workspace/261.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/262.uart_fifo_reset.2986812314 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 125538574728 ps |
| CPU time | 49.5 seconds |
| Started | Jul 13 06:04:34 PM PDT 24 |
| Finished | Jul 13 06:05:25 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-10d90f72-e9a8-45a8-9557-6da487c367d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986812314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2986812314 |
| Directory | /workspace/262.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/263.uart_fifo_reset.3250123279 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 27394581018 ps |
| CPU time | 40.76 seconds |
| Started | Jul 13 06:04:35 PM PDT 24 |
| Finished | Jul 13 06:05:17 PM PDT 24 |
| Peak memory | 199608 kb |
| Host | smart-f87edc3a-5842-410c-9acc-4bf22df90201 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3250123279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3250123279 |
| Directory | /workspace/263.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/264.uart_fifo_reset.1586141302 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 76060174327 ps |
| CPU time | 49.95 seconds |
| Started | Jul 13 06:04:34 PM PDT 24 |
| Finished | Jul 13 06:05:25 PM PDT 24 |
| Peak memory | 199472 kb |
| Host | smart-812ab23a-8767-4d3e-94c7-09b88de28ac5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586141302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1586141302 |
| Directory | /workspace/264.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/265.uart_fifo_reset.2669586209 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 28602542897 ps |
| CPU time | 49.27 seconds |
| Started | Jul 13 06:04:35 PM PDT 24 |
| Finished | Jul 13 06:05:25 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-eecaf7dd-8b40-4cf2-ba59-5e6d3774043d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669586209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2669586209 |
| Directory | /workspace/265.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/266.uart_fifo_reset.598300104 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 30928130424 ps |
| CPU time | 59.51 seconds |
| Started | Jul 13 06:04:34 PM PDT 24 |
| Finished | Jul 13 06:05:35 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-5b6dfcbd-066c-4fa9-901e-18f362ce7250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598300104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.598300104 |
| Directory | /workspace/266.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/267.uart_fifo_reset.2852459979 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 123349830669 ps |
| CPU time | 70.88 seconds |
| Started | Jul 13 06:04:34 PM PDT 24 |
| Finished | Jul 13 06:05:45 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-180c7c51-7d56-4145-8a3f-e1ebde3a7687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852459979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2852459979 |
| Directory | /workspace/267.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/269.uart_fifo_reset.438636990 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 151789586074 ps |
| CPU time | 232.11 seconds |
| Started | Jul 13 06:04:35 PM PDT 24 |
| Finished | Jul 13 06:08:28 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-5349ab5c-04c2-403a-ba0e-b80765666318 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438636990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.438636990 |
| Directory | /workspace/269.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_alert_test.741186010 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 19623180 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 06:00:28 PM PDT 24 |
| Finished | Jul 13 06:00:29 PM PDT 24 |
| Peak memory | 195168 kb |
| Host | smart-129e7bce-4438-4f9c-9a3b-dca7bb170dbd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741186010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.741186010 |
| Directory | /workspace/27.uart_alert_test/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_full.3749217743 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 9544791416 ps |
| CPU time | 5.28 seconds |
| Started | Jul 13 06:00:28 PM PDT 24 |
| Finished | Jul 13 06:00:34 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-1e651153-9f06-4cea-bbbc-58c914c56819 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749217743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3749217743 |
| Directory | /workspace/27.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_overflow.3109783571 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 49129555085 ps |
| CPU time | 36.74 seconds |
| Started | Jul 13 06:00:27 PM PDT 24 |
| Finished | Jul 13 06:01:04 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-f6e7538e-bc2d-49ad-a88f-73c6c4a209bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109783571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3109783571 |
| Directory | /workspace/27.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_reset.309793074 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 48894402549 ps |
| CPU time | 35.4 seconds |
| Started | Jul 13 06:00:27 PM PDT 24 |
| Finished | Jul 13 06:01:03 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-58b32a6b-1a95-4faf-928c-2dc4dda9081a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309793074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.309793074 |
| Directory | /workspace/27.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_intr.2429865816 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 10945173264 ps |
| CPU time | 16.56 seconds |
| Started | Jul 13 06:00:28 PM PDT 24 |
| Finished | Jul 13 06:00:45 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-9c858f49-9394-4a24-b9bd-13bc6f2a04ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429865816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2429865816 |
| Directory | /workspace/27.uart_intr/latest |
| Test location | /workspace/coverage/default/27.uart_long_xfer_wo_dly.2856298678 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 74919430528 ps |
| CPU time | 486.88 seconds |
| Started | Jul 13 06:00:29 PM PDT 24 |
| Finished | Jul 13 06:08:37 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-015dffe5-92a8-4c30-b98f-90ab25aa61a3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2856298678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2856298678 |
| Directory | /workspace/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/27.uart_loopback.2154135629 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 3185678282 ps |
| CPU time | 3.58 seconds |
| Started | Jul 13 06:00:30 PM PDT 24 |
| Finished | Jul 13 06:00:34 PM PDT 24 |
| Peak memory | 198688 kb |
| Host | smart-116033fa-cef4-48f6-a700-7b23be0eeb89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154135629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2154135629 |
| Directory | /workspace/27.uart_loopback/latest |
| Test location | /workspace/coverage/default/27.uart_noise_filter.2246998948 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 266222483053 ps |
| CPU time | 110.04 seconds |
| Started | Jul 13 06:00:29 PM PDT 24 |
| Finished | Jul 13 06:02:20 PM PDT 24 |
| Peak memory | 208188 kb |
| Host | smart-26ba2acb-aef0-4a7e-9992-8c96262424d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246998948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2246998948 |
| Directory | /workspace/27.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/27.uart_perf.2407743551 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 14463112115 ps |
| CPU time | 658.69 seconds |
| Started | Jul 13 06:00:29 PM PDT 24 |
| Finished | Jul 13 06:11:29 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-402cc211-118d-45b0-afe5-025691662709 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2407743551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2407743551 |
| Directory | /workspace/27.uart_perf/latest |
| Test location | /workspace/coverage/default/27.uart_rx_oversample.412912776 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3795412068 ps |
| CPU time | 15.68 seconds |
| Started | Jul 13 06:00:27 PM PDT 24 |
| Finished | Jul 13 06:00:43 PM PDT 24 |
| Peak memory | 197680 kb |
| Host | smart-dd2b5e3d-b10b-4c52-84e6-5c5b7e355557 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=412912776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.412912776 |
| Directory | /workspace/27.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/27.uart_rx_parity_err.2265806439 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 40338937749 ps |
| CPU time | 62.95 seconds |
| Started | Jul 13 06:00:29 PM PDT 24 |
| Finished | Jul 13 06:01:33 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-deae3798-d7af-4e95-84b4-98b92d947d3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265806439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2265806439 |
| Directory | /workspace/27.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/27.uart_rx_start_bit_filter.1825828228 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3462204495 ps |
| CPU time | 1.79 seconds |
| Started | Jul 13 06:00:30 PM PDT 24 |
| Finished | Jul 13 06:00:32 PM PDT 24 |
| Peak memory | 196376 kb |
| Host | smart-594948cd-9708-4c84-979c-2d67a36958df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825828228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1825828228 |
| Directory | /workspace/27.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/27.uart_smoke.2490544785 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 713937016 ps |
| CPU time | 2.47 seconds |
| Started | Jul 13 06:00:30 PM PDT 24 |
| Finished | Jul 13 06:00:33 PM PDT 24 |
| Peak memory | 198768 kb |
| Host | smart-7e5fa772-f9e1-4a67-b340-09811df34bca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490544785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2490544785 |
| Directory | /workspace/27.uart_smoke/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2646714800 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 197416164783 ps |
| CPU time | 220.87 seconds |
| Started | Jul 13 06:00:30 PM PDT 24 |
| Finished | Jul 13 06:04:11 PM PDT 24 |
| Peak memory | 216452 kb |
| Host | smart-2e45bb59-a479-4969-af51-9b64837757ff |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646714800 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2646714800 |
| Directory | /workspace/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.uart_tx_ovrd.332013799 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 1943308069 ps |
| CPU time | 2.33 seconds |
| Started | Jul 13 06:00:29 PM PDT 24 |
| Finished | Jul 13 06:00:32 PM PDT 24 |
| Peak memory | 199224 kb |
| Host | smart-f8cd9b87-eb29-4e01-93eb-fb4953e92e8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332013799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.332013799 |
| Directory | /workspace/27.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/27.uart_tx_rx.843713792 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 149927842073 ps |
| CPU time | 134.07 seconds |
| Started | Jul 13 06:00:28 PM PDT 24 |
| Finished | Jul 13 06:02:43 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-2ad555c3-0b74-43b5-a96c-9a3fec739462 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843713792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.843713792 |
| Directory | /workspace/27.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/270.uart_fifo_reset.1993083152 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 77914012190 ps |
| CPU time | 28.64 seconds |
| Started | Jul 13 06:04:43 PM PDT 24 |
| Finished | Jul 13 06:05:12 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-472ce31d-77ef-4c9d-982a-ea7e48671224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993083152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1993083152 |
| Directory | /workspace/270.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/271.uart_fifo_reset.1789904357 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 179578035088 ps |
| CPU time | 20.89 seconds |
| Started | Jul 13 06:04:43 PM PDT 24 |
| Finished | Jul 13 06:05:05 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-fcd43636-7412-407b-af4c-b2b616096ba7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789904357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1789904357 |
| Directory | /workspace/271.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/272.uart_fifo_reset.1782288268 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 35586861938 ps |
| CPU time | 15.78 seconds |
| Started | Jul 13 06:04:45 PM PDT 24 |
| Finished | Jul 13 06:05:01 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-45e5a28a-0f60-4167-960b-7ddbd40c4883 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782288268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1782288268 |
| Directory | /workspace/272.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/273.uart_fifo_reset.1658023794 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 51712593457 ps |
| CPU time | 105.42 seconds |
| Started | Jul 13 06:04:42 PM PDT 24 |
| Finished | Jul 13 06:06:28 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-a5fc6c0a-139a-4648-ba8d-13023f1c74d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658023794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1658023794 |
| Directory | /workspace/273.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/275.uart_fifo_reset.3025993814 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 120295567115 ps |
| CPU time | 12.17 seconds |
| Started | Jul 13 06:04:44 PM PDT 24 |
| Finished | Jul 13 06:04:57 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-5eec3690-8ac3-4f30-ab58-a55dd4edde57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025993814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3025993814 |
| Directory | /workspace/275.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/276.uart_fifo_reset.4172668026 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 232469974445 ps |
| CPU time | 149.01 seconds |
| Started | Jul 13 06:04:46 PM PDT 24 |
| Finished | Jul 13 06:07:16 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-e3484d6e-50f8-4339-ac57-00cc106c6843 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172668026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4172668026 |
| Directory | /workspace/276.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/277.uart_fifo_reset.66186638 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 77068360714 ps |
| CPU time | 55.92 seconds |
| Started | Jul 13 06:04:42 PM PDT 24 |
| Finished | Jul 13 06:05:39 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-2538d832-d3fc-41cb-bff2-3bbce1e6c371 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66186638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.66186638 |
| Directory | /workspace/277.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/279.uart_fifo_reset.2537768124 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 116513111735 ps |
| CPU time | 44.58 seconds |
| Started | Jul 13 06:04:45 PM PDT 24 |
| Finished | Jul 13 06:05:30 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-46ef025c-44b2-4c88-9ac4-741f23e05b00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537768124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2537768124 |
| Directory | /workspace/279.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_alert_test.3731173611 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 12955310 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 06:00:38 PM PDT 24 |
| Finished | Jul 13 06:00:39 PM PDT 24 |
| Peak memory | 195452 kb |
| Host | smart-2f9a83b5-96fc-40e8-a776-52b615bc962c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731173611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3731173611 |
| Directory | /workspace/28.uart_alert_test/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_full.2772689780 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 40488718843 ps |
| CPU time | 86 seconds |
| Started | Jul 13 06:00:29 PM PDT 24 |
| Finished | Jul 13 06:01:55 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-4a2160b0-5fbc-40cb-8683-106c52f24e78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772689780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2772689780 |
| Directory | /workspace/28.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_overflow.4095541064 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 74723887104 ps |
| CPU time | 107.12 seconds |
| Started | Jul 13 06:00:29 PM PDT 24 |
| Finished | Jul 13 06:02:17 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-f3680e24-498c-4ebe-93ce-dadf6fbb34e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095541064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4095541064 |
| Directory | /workspace/28.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_reset.184327954 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 24580528498 ps |
| CPU time | 14.8 seconds |
| Started | Jul 13 06:00:29 PM PDT 24 |
| Finished | Jul 13 06:00:44 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-67a2f5ad-148d-42d9-814a-a610aaa7c893 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184327954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.184327954 |
| Directory | /workspace/28.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_intr.3201718298 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 49438020892 ps |
| CPU time | 11.3 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:00:49 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-ce2a56fe-416d-40f4-8a04-d027dd9bcc19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201718298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3201718298 |
| Directory | /workspace/28.uart_intr/latest |
| Test location | /workspace/coverage/default/28.uart_long_xfer_wo_dly.3660894646 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 137416972346 ps |
| CPU time | 415.26 seconds |
| Started | Jul 13 06:00:36 PM PDT 24 |
| Finished | Jul 13 06:07:32 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-8b6d340f-65cb-4fbc-be4f-f975d234e8f3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3660894646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3660894646 |
| Directory | /workspace/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/28.uart_loopback.1157467072 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3711177228 ps |
| CPU time | 4.11 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:00:42 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-e8f72622-e925-4e6d-a8ea-209977607108 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157467072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1157467072 |
| Directory | /workspace/28.uart_loopback/latest |
| Test location | /workspace/coverage/default/28.uart_noise_filter.614026248 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 7768798873 ps |
| CPU time | 12.14 seconds |
| Started | Jul 13 06:00:38 PM PDT 24 |
| Finished | Jul 13 06:00:51 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-9ef8e21e-dc9c-4dfd-a27f-c506bc6699e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614026248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.614026248 |
| Directory | /workspace/28.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/28.uart_perf.649087735 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 20225996352 ps |
| CPU time | 481.36 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:08:39 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-df95ee8c-e114-4488-98f1-1d5cace40663 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=649087735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.649087735 |
| Directory | /workspace/28.uart_perf/latest |
| Test location | /workspace/coverage/default/28.uart_rx_oversample.993727747 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 3687382122 ps |
| CPU time | 6.7 seconds |
| Started | Jul 13 06:00:28 PM PDT 24 |
| Finished | Jul 13 06:00:35 PM PDT 24 |
| Peak memory | 198036 kb |
| Host | smart-d29ab264-effe-4ac7-8fad-3f86a1aa9757 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=993727747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.993727747 |
| Directory | /workspace/28.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/28.uart_rx_parity_err.242328350 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 19185692606 ps |
| CPU time | 30.2 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:01:08 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-04bb6a7e-4a3f-443b-85ea-4032ec457a39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242328350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.242328350 |
| Directory | /workspace/28.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/28.uart_rx_start_bit_filter.1838349278 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 5703372006 ps |
| CPU time | 4.93 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:00:43 PM PDT 24 |
| Peak memory | 196708 kb |
| Host | smart-5ff1e72b-44ed-40b6-a249-747449edc709 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838349278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1838349278 |
| Directory | /workspace/28.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/28.uart_smoke.1264182682 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5432103475 ps |
| CPU time | 18.6 seconds |
| Started | Jul 13 06:00:28 PM PDT 24 |
| Finished | Jul 13 06:00:48 PM PDT 24 |
| Peak memory | 199292 kb |
| Host | smart-3c8d87d9-a413-40c3-8865-ff66c32fb2d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264182682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1264182682 |
| Directory | /workspace/28.uart_smoke/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all.4139833262 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 188092539236 ps |
| CPU time | 153.99 seconds |
| Started | Jul 13 06:00:38 PM PDT 24 |
| Finished | Jul 13 06:03:13 PM PDT 24 |
| Peak memory | 208312 kb |
| Host | smart-2e059d0e-6ad0-450a-9d2e-69e544685e70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139833262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4139833262 |
| Directory | /workspace/28.uart_stress_all/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all_with_rand_reset.4065171302 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 31791742351 ps |
| CPU time | 362.12 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:06:40 PM PDT 24 |
| Peak memory | 216640 kb |
| Host | smart-fe497f37-e5ad-4adc-b8d8-e5909d86cd32 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065171302 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.4065171302 |
| Directory | /workspace/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.uart_tx_ovrd.1968983477 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 6463144546 ps |
| CPU time | 22.4 seconds |
| Started | Jul 13 06:00:35 PM PDT 24 |
| Finished | Jul 13 06:00:58 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-396b0e1c-aa60-4ef9-b79f-27f732f8774a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968983477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1968983477 |
| Directory | /workspace/28.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/28.uart_tx_rx.1778853008 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 26928368008 ps |
| CPU time | 21.78 seconds |
| Started | Jul 13 06:00:28 PM PDT 24 |
| Finished | Jul 13 06:00:51 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-f19e8174-6688-4cf9-9fcc-6cf10592e6b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778853008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1778853008 |
| Directory | /workspace/28.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/280.uart_fifo_reset.2689148046 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 110945164878 ps |
| CPU time | 57.4 seconds |
| Started | Jul 13 06:04:44 PM PDT 24 |
| Finished | Jul 13 06:05:42 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-ba6ab464-bbb3-4b1a-8794-5f01ae757e7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2689148046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2689148046 |
| Directory | /workspace/280.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/281.uart_fifo_reset.3325890148 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 15983716380 ps |
| CPU time | 12.45 seconds |
| Started | Jul 13 06:04:43 PM PDT 24 |
| Finished | Jul 13 06:04:56 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-6d30f610-e7ab-4dbb-a00c-eb512a6690e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325890148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3325890148 |
| Directory | /workspace/281.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/283.uart_fifo_reset.3802615572 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 18236187724 ps |
| CPU time | 34.66 seconds |
| Started | Jul 13 06:04:42 PM PDT 24 |
| Finished | Jul 13 06:05:17 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-b56a2724-e145-4311-babb-27c82c546280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802615572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3802615572 |
| Directory | /workspace/283.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/285.uart_fifo_reset.3330469721 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 12294972181 ps |
| CPU time | 5.82 seconds |
| Started | Jul 13 06:04:42 PM PDT 24 |
| Finished | Jul 13 06:04:49 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-05005b43-5ef1-4dc3-9868-439ebe88ff5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330469721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3330469721 |
| Directory | /workspace/285.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/286.uart_fifo_reset.1884447273 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 181418893383 ps |
| CPU time | 93.22 seconds |
| Started | Jul 13 06:04:44 PM PDT 24 |
| Finished | Jul 13 06:06:18 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-8a124a47-6f2a-4345-b286-a8d021b83bad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884447273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1884447273 |
| Directory | /workspace/286.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/287.uart_fifo_reset.1469922350 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 144694557060 ps |
| CPU time | 61.51 seconds |
| Started | Jul 13 06:04:55 PM PDT 24 |
| Finished | Jul 13 06:05:57 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-eed56ee8-201f-462f-8b7d-92409319b0a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469922350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1469922350 |
| Directory | /workspace/287.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/288.uart_fifo_reset.31444832 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 164221469783 ps |
| CPU time | 79.55 seconds |
| Started | Jul 13 06:04:51 PM PDT 24 |
| Finished | Jul 13 06:06:11 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-ccce7344-a928-49ca-97f6-4df5c5a2dd43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31444832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.31444832 |
| Directory | /workspace/288.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_alert_test.4169494588 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 15193178 ps |
| CPU time | 0.6 seconds |
| Started | Jul 13 06:00:49 PM PDT 24 |
| Finished | Jul 13 06:00:50 PM PDT 24 |
| Peak memory | 195184 kb |
| Host | smart-4aa58d73-8f48-4a1b-b467-93154018098c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169494588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4169494588 |
| Directory | /workspace/29.uart_alert_test/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_full.2396282951 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 179997759454 ps |
| CPU time | 137.1 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:02:54 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-7a8cbfaf-54ad-45a0-a9d0-054d5d035069 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396282951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2396282951 |
| Directory | /workspace/29.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_overflow.2907754092 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 142292418132 ps |
| CPU time | 69.88 seconds |
| Started | Jul 13 06:00:38 PM PDT 24 |
| Finished | Jul 13 06:01:48 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-bf3061e1-6f8b-4cc8-96da-0d5224095416 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907754092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2907754092 |
| Directory | /workspace/29.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_reset.1725391829 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 45824079413 ps |
| CPU time | 37.62 seconds |
| Started | Jul 13 06:00:35 PM PDT 24 |
| Finished | Jul 13 06:01:14 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-31508b9b-f29d-4175-a786-4d9070a5588a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725391829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1725391829 |
| Directory | /workspace/29.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_intr.131316243 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 4999748248 ps |
| CPU time | 4.7 seconds |
| Started | Jul 13 06:00:35 PM PDT 24 |
| Finished | Jul 13 06:00:40 PM PDT 24 |
| Peak memory | 196620 kb |
| Host | smart-d62fc18e-fec5-4221-a81d-52211b9e0e05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131316243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.131316243 |
| Directory | /workspace/29.uart_intr/latest |
| Test location | /workspace/coverage/default/29.uart_long_xfer_wo_dly.951354980 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 57276551519 ps |
| CPU time | 225.76 seconds |
| Started | Jul 13 06:00:51 PM PDT 24 |
| Finished | Jul 13 06:04:37 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-417896be-cc53-47f1-911d-948e038a2036 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=951354980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.951354980 |
| Directory | /workspace/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/29.uart_loopback.659036431 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 10361898458 ps |
| CPU time | 10.97 seconds |
| Started | Jul 13 06:00:50 PM PDT 24 |
| Finished | Jul 13 06:01:01 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-39504c1a-b44d-4eb1-97ee-7b93e9e17f01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659036431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.659036431 |
| Directory | /workspace/29.uart_loopback/latest |
| Test location | /workspace/coverage/default/29.uart_noise_filter.743235835 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 67218284126 ps |
| CPU time | 39.95 seconds |
| Started | Jul 13 06:00:36 PM PDT 24 |
| Finished | Jul 13 06:01:16 PM PDT 24 |
| Peak memory | 208148 kb |
| Host | smart-4c835090-6c0f-473b-b652-f17fe2e43d93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=743235835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.743235835 |
| Directory | /workspace/29.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/29.uart_perf.3401431536 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 18523374314 ps |
| CPU time | 865.96 seconds |
| Started | Jul 13 06:00:48 PM PDT 24 |
| Finished | Jul 13 06:15:14 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-2391fe88-f58f-42a2-ac43-c9376097a426 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3401431536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3401431536 |
| Directory | /workspace/29.uart_perf/latest |
| Test location | /workspace/coverage/default/29.uart_rx_oversample.3904335946 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 7792629158 ps |
| CPU time | 33.34 seconds |
| Started | Jul 13 06:00:36 PM PDT 24 |
| Finished | Jul 13 06:01:10 PM PDT 24 |
| Peak memory | 197980 kb |
| Host | smart-6af5138e-6965-44c7-b489-69cd0cead853 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3904335946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3904335946 |
| Directory | /workspace/29.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/29.uart_rx_parity_err.4264789517 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 25071421574 ps |
| CPU time | 11.54 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:00:49 PM PDT 24 |
| Peak memory | 199192 kb |
| Host | smart-6e97619f-6856-4cb3-916c-bbcc3b646769 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264789517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4264789517 |
| Directory | /workspace/29.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/29.uart_rx_start_bit_filter.2166985167 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 6813153979 ps |
| CPU time | 3.73 seconds |
| Started | Jul 13 06:00:36 PM PDT 24 |
| Finished | Jul 13 06:00:40 PM PDT 24 |
| Peak memory | 196668 kb |
| Host | smart-f31ec528-e725-470a-9c60-b7264e365814 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166985167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2166985167 |
| Directory | /workspace/29.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/29.uart_smoke.4237094244 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 5720978632 ps |
| CPU time | 16.35 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:00:54 PM PDT 24 |
| Peak memory | 199468 kb |
| Host | smart-0c527195-0c52-4de9-9763-3865572adbc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237094244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4237094244 |
| Directory | /workspace/29.uart_smoke/latest |
| Test location | /workspace/coverage/default/29.uart_stress_all.3215198169 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 122544644547 ps |
| CPU time | 969.21 seconds |
| Started | Jul 13 06:00:44 PM PDT 24 |
| Finished | Jul 13 06:16:54 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-ac370a02-076a-4f2f-ac14-eb8bab34455b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215198169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3215198169 |
| Directory | /workspace/29.uart_stress_all/latest |
| Test location | /workspace/coverage/default/29.uart_tx_ovrd.2009272798 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 1198017123 ps |
| CPU time | 2.83 seconds |
| Started | Jul 13 06:00:51 PM PDT 24 |
| Finished | Jul 13 06:00:54 PM PDT 24 |
| Peak memory | 199528 kb |
| Host | smart-a9870218-fbab-407e-b251-8f720bfc009f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009272798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2009272798 |
| Directory | /workspace/29.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/29.uart_tx_rx.3403256162 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 89509186060 ps |
| CPU time | 348.73 seconds |
| Started | Jul 13 06:00:37 PM PDT 24 |
| Finished | Jul 13 06:06:26 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-3ddd3b71-f925-43d1-acf3-767a74fc98cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403256162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3403256162 |
| Directory | /workspace/29.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/290.uart_fifo_reset.2997811560 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 25736395689 ps |
| CPU time | 39.66 seconds |
| Started | Jul 13 06:04:52 PM PDT 24 |
| Finished | Jul 13 06:05:33 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-46c77000-4927-4153-b90a-18dc72adfc28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997811560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2997811560 |
| Directory | /workspace/290.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/291.uart_fifo_reset.2613472355 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 63969634181 ps |
| CPU time | 50.33 seconds |
| Started | Jul 13 06:04:52 PM PDT 24 |
| Finished | Jul 13 06:05:43 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-dc27a0c0-d8da-4c51-87ad-20cb410c534a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2613472355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2613472355 |
| Directory | /workspace/291.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/292.uart_fifo_reset.2108521639 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 29020752402 ps |
| CPU time | 12.71 seconds |
| Started | Jul 13 06:04:52 PM PDT 24 |
| Finished | Jul 13 06:05:05 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-f5603002-d230-4584-a121-2369d7cfbdd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2108521639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2108521639 |
| Directory | /workspace/292.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/293.uart_fifo_reset.2290645880 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 10870944334 ps |
| CPU time | 32.89 seconds |
| Started | Jul 13 06:04:52 PM PDT 24 |
| Finished | Jul 13 06:05:25 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-7216df64-f420-4a6d-bd4f-9a939ec01b82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290645880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2290645880 |
| Directory | /workspace/293.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/294.uart_fifo_reset.3626726314 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 41447165392 ps |
| CPU time | 24.26 seconds |
| Started | Jul 13 06:04:56 PM PDT 24 |
| Finished | Jul 13 06:05:20 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-58536c7d-e0fa-41d0-ab58-eef870f5694d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626726314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3626726314 |
| Directory | /workspace/294.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/296.uart_fifo_reset.38106136 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 14909489733 ps |
| CPU time | 24.52 seconds |
| Started | Jul 13 06:04:52 PM PDT 24 |
| Finished | Jul 13 06:05:16 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-0dadb431-699c-4f6c-ac5f-cc78327af03b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38106136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.38106136 |
| Directory | /workspace/296.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/298.uart_fifo_reset.3673564825 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 66904705195 ps |
| CPU time | 113.01 seconds |
| Started | Jul 13 06:04:52 PM PDT 24 |
| Finished | Jul 13 06:06:46 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-c8f5ed7b-5e8a-40ea-b064-eb84f55a6df7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673564825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3673564825 |
| Directory | /workspace/298.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/299.uart_fifo_reset.3964508338 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 22472371056 ps |
| CPU time | 36.34 seconds |
| Started | Jul 13 06:04:55 PM PDT 24 |
| Finished | Jul 13 06:05:32 PM PDT 24 |
| Peak memory | 199660 kb |
| Host | smart-cc0ed30f-36ca-428a-ae48-36efdff36c81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964508338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3964508338 |
| Directory | /workspace/299.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_alert_test.3264622927 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 13893789 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 05:58:48 PM PDT 24 |
| Peak memory | 194892 kb |
| Host | smart-a23ebd7c-8b96-4e3c-a78f-23114cb6244b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264622927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3264622927 |
| Directory | /workspace/3.uart_alert_test/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_full.1263531923 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 88274828738 ps |
| CPU time | 173.13 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 06:01:41 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-229e9705-c088-483a-8917-0264efed5e03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263531923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1263531923 |
| Directory | /workspace/3.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_overflow.534725368 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 92366419108 ps |
| CPU time | 153.03 seconds |
| Started | Jul 13 05:58:44 PM PDT 24 |
| Finished | Jul 13 06:01:17 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-a54162ac-1b7b-4e2a-a94f-85519c324999 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534725368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.534725368 |
| Directory | /workspace/3.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/3.uart_intr.2870004804 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 26880673222 ps |
| CPU time | 21.63 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 05:59:08 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-37e58529-8be5-4722-b088-e363a6174509 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870004804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2870004804 |
| Directory | /workspace/3.uart_intr/latest |
| Test location | /workspace/coverage/default/3.uart_long_xfer_wo_dly.3619159304 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 216584502945 ps |
| CPU time | 362.84 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 06:04:51 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-76eac6b8-bc11-44fa-9eef-78c76f852f3c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3619159304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3619159304 |
| Directory | /workspace/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/3.uart_loopback.280913192 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3631227257 ps |
| CPU time | 3.68 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 05:58:52 PM PDT 24 |
| Peak memory | 199000 kb |
| Host | smart-b66411e7-5c2b-455a-ab65-03178c4576ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280913192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.280913192 |
| Directory | /workspace/3.uart_loopback/latest |
| Test location | /workspace/coverage/default/3.uart_noise_filter.1944813896 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 27134904134 ps |
| CPU time | 28.62 seconds |
| Started | Jul 13 05:58:49 PM PDT 24 |
| Finished | Jul 13 05:59:17 PM PDT 24 |
| Peak memory | 199604 kb |
| Host | smart-bfb6d4b0-b03c-441c-8969-bf61eca230e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944813896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1944813896 |
| Directory | /workspace/3.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/3.uart_perf.2386384275 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 38613644989 ps |
| CPU time | 283.13 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 06:03:29 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-2ce23746-9571-4758-ace1-8b5e3ca1ee23 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2386384275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2386384275 |
| Directory | /workspace/3.uart_perf/latest |
| Test location | /workspace/coverage/default/3.uart_rx_oversample.3433030366 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 5931931280 ps |
| CPU time | 27.22 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:59:14 PM PDT 24 |
| Peak memory | 198136 kb |
| Host | smart-9d4cb0ae-687f-4da4-9585-252eeb967078 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3433030366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3433030366 |
| Directory | /workspace/3.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/3.uart_rx_parity_err.312465332 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 67172102673 ps |
| CPU time | 28.51 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 05:59:16 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-4d45ef95-acc4-474a-a277-dfa49ab7d160 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312465332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.312465332 |
| Directory | /workspace/3.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/3.uart_rx_start_bit_filter.2514095893 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 3998245039 ps |
| CPU time | 5.86 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:58:52 PM PDT 24 |
| Peak memory | 196156 kb |
| Host | smart-c4e0c67c-340c-422b-8699-92a088114ab4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514095893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2514095893 |
| Directory | /workspace/3.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/3.uart_sec_cm.3297852445 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 299293575 ps |
| CPU time | 0.84 seconds |
| Started | Jul 13 05:58:45 PM PDT 24 |
| Finished | Jul 13 05:58:46 PM PDT 24 |
| Peak memory | 218244 kb |
| Host | smart-c5014f8d-9e4a-490a-8fb1-c93592aecab9 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297852445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3297852445 |
| Directory | /workspace/3.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/3.uart_smoke.588934693 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 117093477 ps |
| CPU time | 0.72 seconds |
| Started | Jul 13 05:58:47 PM PDT 24 |
| Finished | Jul 13 05:58:49 PM PDT 24 |
| Peak memory | 196848 kb |
| Host | smart-3a267ff8-3e39-4e77-b761-a217c499a6df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588934693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.588934693 |
| Directory | /workspace/3.uart_smoke/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all.2666384244 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 254774562090 ps |
| CPU time | 194.27 seconds |
| Started | Jul 13 05:58:53 PM PDT 24 |
| Finished | Jul 13 06:02:08 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-d2d07c89-e794-44d5-be69-00ecfe8b4736 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666384244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2666384244 |
| Directory | /workspace/3.uart_stress_all/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3586402198 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 146033815355 ps |
| CPU time | 937.6 seconds |
| Started | Jul 13 05:58:48 PM PDT 24 |
| Finished | Jul 13 06:14:26 PM PDT 24 |
| Peak memory | 224992 kb |
| Host | smart-4e18841e-e86b-4ca2-b877-295dae4f101f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586402198 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3586402198 |
| Directory | /workspace/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.uart_tx_ovrd.4143736258 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 7369332797 ps |
| CPU time | 7.6 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 05:59:00 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-f93efcad-724d-4edf-a95a-b49578b621ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4143736258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4143736258 |
| Directory | /workspace/3.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/3.uart_tx_rx.1439276103 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 53493941613 ps |
| CPU time | 120.77 seconds |
| Started | Jul 13 05:58:46 PM PDT 24 |
| Finished | Jul 13 06:00:48 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-fcfeb1c5-7cda-4304-b21e-4d059f15ddd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1439276103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1439276103 |
| Directory | /workspace/3.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/30.uart_alert_test.3445227086 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 21843391 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 06:00:48 PM PDT 24 |
| Finished | Jul 13 06:00:50 PM PDT 24 |
| Peak memory | 195204 kb |
| Host | smart-d8f8bdd9-345e-4fdd-85f0-eeca385b9865 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445227086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3445227086 |
| Directory | /workspace/30.uart_alert_test/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_full.230456674 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 159627558772 ps |
| CPU time | 128.33 seconds |
| Started | Jul 13 06:00:46 PM PDT 24 |
| Finished | Jul 13 06:02:55 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-040c8f54-0b77-4367-af33-075ba9865171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230456674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.230456674 |
| Directory | /workspace/30.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_overflow.451221939 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 17225172293 ps |
| CPU time | 23.72 seconds |
| Started | Jul 13 06:00:48 PM PDT 24 |
| Finished | Jul 13 06:01:12 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-3e8a9b44-6353-4d97-a20e-1fd98689ac26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451221939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.451221939 |
| Directory | /workspace/30.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_reset.854315964 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 81383985269 ps |
| CPU time | 116.93 seconds |
| Started | Jul 13 06:00:45 PM PDT 24 |
| Finished | Jul 13 06:02:42 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-ddb36427-4bcf-4a9f-8190-f070bb7d37c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854315964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.854315964 |
| Directory | /workspace/30.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/30.uart_intr.2542347666 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 31941318527 ps |
| CPU time | 12.38 seconds |
| Started | Jul 13 06:00:49 PM PDT 24 |
| Finished | Jul 13 06:01:02 PM PDT 24 |
| Peak memory | 199608 kb |
| Host | smart-6f53817b-c274-4290-ad35-e1d1e7307a9a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542347666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2542347666 |
| Directory | /workspace/30.uart_intr/latest |
| Test location | /workspace/coverage/default/30.uart_long_xfer_wo_dly.2286590929 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 104248628989 ps |
| CPU time | 267.31 seconds |
| Started | Jul 13 06:00:48 PM PDT 24 |
| Finished | Jul 13 06:05:16 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-4c6f2ec2-7f38-4653-8585-6d5798b1cd34 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2286590929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2286590929 |
| Directory | /workspace/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/30.uart_loopback.3968478537 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 7295178604 ps |
| CPU time | 5.64 seconds |
| Started | Jul 13 06:00:46 PM PDT 24 |
| Finished | Jul 13 06:00:52 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-47ebe3ff-b713-484f-bab4-96fc7405a289 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968478537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3968478537 |
| Directory | /workspace/30.uart_loopback/latest |
| Test location | /workspace/coverage/default/30.uart_noise_filter.4147050785 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 54802775544 ps |
| CPU time | 87.73 seconds |
| Started | Jul 13 06:00:47 PM PDT 24 |
| Finished | Jul 13 06:02:15 PM PDT 24 |
| Peak memory | 199668 kb |
| Host | smart-5878b683-ff45-4cf1-a445-fd26a588971d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147050785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.4147050785 |
| Directory | /workspace/30.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/30.uart_perf.3521296015 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 14448246085 ps |
| CPU time | 657.46 seconds |
| Started | Jul 13 06:00:47 PM PDT 24 |
| Finished | Jul 13 06:11:45 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-fd92a4a8-a23f-4f89-a95f-dc7c3a001113 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3521296015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3521296015 |
| Directory | /workspace/30.uart_perf/latest |
| Test location | /workspace/coverage/default/30.uart_rx_oversample.836390026 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 6008234916 ps |
| CPU time | 42.98 seconds |
| Started | Jul 13 06:00:45 PM PDT 24 |
| Finished | Jul 13 06:01:29 PM PDT 24 |
| Peak memory | 198068 kb |
| Host | smart-41d8b590-918f-42f0-8c05-91540ef7b1aa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=836390026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.836390026 |
| Directory | /workspace/30.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/30.uart_rx_parity_err.3931950276 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 391297792110 ps |
| CPU time | 107.13 seconds |
| Started | Jul 13 06:00:46 PM PDT 24 |
| Finished | Jul 13 06:02:34 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-50037fab-bb4e-495a-bb63-7aafd1533d18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3931950276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3931950276 |
| Directory | /workspace/30.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/30.uart_rx_start_bit_filter.2014443829 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 55646481858 ps |
| CPU time | 81.85 seconds |
| Started | Jul 13 06:00:46 PM PDT 24 |
| Finished | Jul 13 06:02:09 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-5581a5b5-21bb-48a7-9be7-90d05e1068d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014443829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2014443829 |
| Directory | /workspace/30.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/30.uart_smoke.4272341624 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 292724783 ps |
| CPU time | 1.44 seconds |
| Started | Jul 13 06:00:48 PM PDT 24 |
| Finished | Jul 13 06:00:50 PM PDT 24 |
| Peak memory | 198532 kb |
| Host | smart-22cde925-e622-4c6e-b903-515e7200b236 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272341624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.4272341624 |
| Directory | /workspace/30.uart_smoke/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1618972953 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 66446088470 ps |
| CPU time | 989.35 seconds |
| Started | Jul 13 06:00:47 PM PDT 24 |
| Finished | Jul 13 06:17:17 PM PDT 24 |
| Peak memory | 216708 kb |
| Host | smart-23c5dd5f-9077-4536-a9aa-a72c5c8115e7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618972953 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1618972953 |
| Directory | /workspace/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.uart_tx_ovrd.3193925839 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 667211081 ps |
| CPU time | 2.16 seconds |
| Started | Jul 13 06:00:47 PM PDT 24 |
| Finished | Jul 13 06:00:50 PM PDT 24 |
| Peak memory | 198576 kb |
| Host | smart-164fbef5-a4db-40df-8516-6315200f86dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193925839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3193925839 |
| Directory | /workspace/30.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/30.uart_tx_rx.4012302173 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 17610033293 ps |
| CPU time | 6.34 seconds |
| Started | Jul 13 06:00:50 PM PDT 24 |
| Finished | Jul 13 06:00:57 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-bce931e6-0753-4b10-97ad-71ee66ade41a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012302173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4012302173 |
| Directory | /workspace/30.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/31.uart_alert_test.1431894208 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 15423773 ps |
| CPU time | 0.61 seconds |
| Started | Jul 13 06:00:54 PM PDT 24 |
| Finished | Jul 13 06:00:55 PM PDT 24 |
| Peak memory | 195456 kb |
| Host | smart-3bd4cb05-50a6-4ae8-b6ec-d203a2158be3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431894208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1431894208 |
| Directory | /workspace/31.uart_alert_test/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_full.1025838072 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 30260884976 ps |
| CPU time | 14.11 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:01:10 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-1ee3574b-a193-4af7-ab0b-c11014d76461 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1025838072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1025838072 |
| Directory | /workspace/31.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_overflow.3217874640 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 21877571600 ps |
| CPU time | 10.78 seconds |
| Started | Jul 13 06:00:54 PM PDT 24 |
| Finished | Jul 13 06:01:06 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-9ccc8900-f541-47e7-982d-41196d15911b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217874640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3217874640 |
| Directory | /workspace/31.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_reset.387103989 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 24947772792 ps |
| CPU time | 20.61 seconds |
| Started | Jul 13 06:00:59 PM PDT 24 |
| Finished | Jul 13 06:01:20 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-a67bb059-20af-4682-a98d-e7d344b41cd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387103989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.387103989 |
| Directory | /workspace/31.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/31.uart_intr.2494325118 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 110437633565 ps |
| CPU time | 90.47 seconds |
| Started | Jul 13 06:00:59 PM PDT 24 |
| Finished | Jul 13 06:02:30 PM PDT 24 |
| Peak memory | 196876 kb |
| Host | smart-43813815-f556-4d06-ba39-df1b7ad348e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494325118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2494325118 |
| Directory | /workspace/31.uart_intr/latest |
| Test location | /workspace/coverage/default/31.uart_long_xfer_wo_dly.559899817 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 113490858230 ps |
| CPU time | 414.75 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:07:51 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-f01fbec4-d5fd-48fc-8336-0b309996c9b7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=559899817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.559899817 |
| Directory | /workspace/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/31.uart_loopback.996328877 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 9375480646 ps |
| CPU time | 5.46 seconds |
| Started | Jul 13 06:00:56 PM PDT 24 |
| Finished | Jul 13 06:01:02 PM PDT 24 |
| Peak memory | 198972 kb |
| Host | smart-c9b0e956-519d-4a90-9b59-0723efc72818 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996328877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.996328877 |
| Directory | /workspace/31.uart_loopback/latest |
| Test location | /workspace/coverage/default/31.uart_noise_filter.1020715413 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 94916510703 ps |
| CPU time | 33.88 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:01:29 PM PDT 24 |
| Peak memory | 199608 kb |
| Host | smart-c3becb35-adf7-41e7-89bb-18fedcf0ce7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020715413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1020715413 |
| Directory | /workspace/31.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/31.uart_perf.2948021618 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 15423476844 ps |
| CPU time | 789.76 seconds |
| Started | Jul 13 06:00:54 PM PDT 24 |
| Finished | Jul 13 06:14:05 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-6658df62-ca2d-4173-88fd-072d4290bb49 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2948021618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2948021618 |
| Directory | /workspace/31.uart_perf/latest |
| Test location | /workspace/coverage/default/31.uart_rx_oversample.3932345129 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3405769723 ps |
| CPU time | 7.36 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:01:03 PM PDT 24 |
| Peak memory | 198452 kb |
| Host | smart-94862fce-89b1-47a1-8a9f-305ec7ab3d2b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3932345129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3932345129 |
| Directory | /workspace/31.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/31.uart_rx_parity_err.923238998 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 19446687404 ps |
| CPU time | 27.87 seconds |
| Started | Jul 13 06:01:01 PM PDT 24 |
| Finished | Jul 13 06:01:29 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-c769445e-5737-43e9-b2ba-bc60c28f7fa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923238998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.923238998 |
| Directory | /workspace/31.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/31.uart_rx_start_bit_filter.211095087 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 5044172844 ps |
| CPU time | 8.24 seconds |
| Started | Jul 13 06:01:01 PM PDT 24 |
| Finished | Jul 13 06:01:10 PM PDT 24 |
| Peak memory | 196376 kb |
| Host | smart-02e3c664-d182-4c41-ae7a-538da1ac3c60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=211095087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.211095087 |
| Directory | /workspace/31.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/31.uart_smoke.4227147403 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 267621190 ps |
| CPU time | 1.43 seconds |
| Started | Jul 13 06:00:49 PM PDT 24 |
| Finished | Jul 13 06:00:51 PM PDT 24 |
| Peak memory | 198336 kb |
| Host | smart-72b4d3fa-0418-43b3-bbf7-a5044cb5e23b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4227147403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4227147403 |
| Directory | /workspace/31.uart_smoke/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all.4264487068 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 217104865451 ps |
| CPU time | 1620.01 seconds |
| Started | Jul 13 06:00:53 PM PDT 24 |
| Finished | Jul 13 06:27:54 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-ebd56885-6027-4f91-baa7-9fdbc0303ecd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264487068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.4264487068 |
| Directory | /workspace/31.uart_stress_all/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2626646806 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 57188020092 ps |
| CPU time | 344.85 seconds |
| Started | Jul 13 06:00:59 PM PDT 24 |
| Finished | Jul 13 06:06:44 PM PDT 24 |
| Peak memory | 212336 kb |
| Host | smart-0f77c3e0-69c1-41ac-b5d9-d65ff04118e8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626646806 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2626646806 |
| Directory | /workspace/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.uart_tx_ovrd.2202725615 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1432633180 ps |
| CPU time | 2.95 seconds |
| Started | Jul 13 06:00:52 PM PDT 24 |
| Finished | Jul 13 06:00:55 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-b5398790-ec4e-4463-90d8-e652766a5ee1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202725615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2202725615 |
| Directory | /workspace/31.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/31.uart_tx_rx.2005841583 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 16964619361 ps |
| CPU time | 13.28 seconds |
| Started | Jul 13 06:00:54 PM PDT 24 |
| Finished | Jul 13 06:01:08 PM PDT 24 |
| Peak memory | 196592 kb |
| Host | smart-d6d86a96-785a-4b08-9733-0b76551bea44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005841583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2005841583 |
| Directory | /workspace/31.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/32.uart_alert_test.290332594 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 33544160 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:01:04 PM PDT 24 |
| Peak memory | 195472 kb |
| Host | smart-4b739ec6-43ed-4e21-8ba1-a173fb39c460 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290332594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.290332594 |
| Directory | /workspace/32.uart_alert_test/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_full.3405071906 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 69121996603 ps |
| CPU time | 30.4 seconds |
| Started | Jul 13 06:00:56 PM PDT 24 |
| Finished | Jul 13 06:01:27 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-8f3b98fe-1d38-4b9a-ba4b-f63ca323378a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405071906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3405071906 |
| Directory | /workspace/32.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_overflow.3861646826 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 41967627764 ps |
| CPU time | 65.29 seconds |
| Started | Jul 13 06:00:53 PM PDT 24 |
| Finished | Jul 13 06:01:59 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-71cc19c7-2c3a-4ef0-b0a2-89a64d545488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861646826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3861646826 |
| Directory | /workspace/32.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_reset.4086599461 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 29905099992 ps |
| CPU time | 29.2 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:01:25 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-1afbe704-18da-4fb1-b617-04f4bb114510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086599461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.4086599461 |
| Directory | /workspace/32.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/32.uart_intr.4112860541 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 112596203250 ps |
| CPU time | 176.91 seconds |
| Started | Jul 13 06:00:54 PM PDT 24 |
| Finished | Jul 13 06:03:52 PM PDT 24 |
| Peak memory | 198880 kb |
| Host | smart-7efe86f8-980d-4da8-b4e7-8fda6ad89c52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112860541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4112860541 |
| Directory | /workspace/32.uart_intr/latest |
| Test location | /workspace/coverage/default/32.uart_long_xfer_wo_dly.2510988774 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 110925019895 ps |
| CPU time | 404.6 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:07:41 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-eeedb969-1902-4c90-a90d-65bf1c316e2a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2510988774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2510988774 |
| Directory | /workspace/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/32.uart_loopback.2670362795 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 4914381025 ps |
| CPU time | 2.22 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:00:58 PM PDT 24 |
| Peak memory | 197764 kb |
| Host | smart-13bed4f2-69f5-4798-90f5-d811903bf807 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670362795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2670362795 |
| Directory | /workspace/32.uart_loopback/latest |
| Test location | /workspace/coverage/default/32.uart_noise_filter.2641055675 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 101581671708 ps |
| CPU time | 84.69 seconds |
| Started | Jul 13 06:00:56 PM PDT 24 |
| Finished | Jul 13 06:02:21 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-3db39dc3-2aec-48c8-a464-01c98b8eeea2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641055675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2641055675 |
| Directory | /workspace/32.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/32.uart_perf.343279994 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 8899976147 ps |
| CPU time | 523.26 seconds |
| Started | Jul 13 06:01:02 PM PDT 24 |
| Finished | Jul 13 06:09:46 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-74c71062-b986-410d-a5e3-57b838c4c7a5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=343279994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.343279994 |
| Directory | /workspace/32.uart_perf/latest |
| Test location | /workspace/coverage/default/32.uart_rx_oversample.2045934478 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 5647738679 ps |
| CPU time | 3 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:00:59 PM PDT 24 |
| Peak memory | 198108 kb |
| Host | smart-cc2620e9-eab2-458b-a8b6-5e6f18fbfb8e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2045934478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2045934478 |
| Directory | /workspace/32.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/32.uart_rx_parity_err.4082574938 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 59514218388 ps |
| CPU time | 31.92 seconds |
| Started | Jul 13 06:00:54 PM PDT 24 |
| Finished | Jul 13 06:01:27 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-58511464-7f19-414f-bb27-74f309620c9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4082574938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4082574938 |
| Directory | /workspace/32.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/32.uart_rx_start_bit_filter.3566815213 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2781095099 ps |
| CPU time | 4.91 seconds |
| Started | Jul 13 06:00:54 PM PDT 24 |
| Finished | Jul 13 06:01:00 PM PDT 24 |
| Peak memory | 195888 kb |
| Host | smart-496b1679-df43-422f-8f77-95ec0d144dfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3566815213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3566815213 |
| Directory | /workspace/32.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/32.uart_smoke.2792826747 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 5910820290 ps |
| CPU time | 16.61 seconds |
| Started | Jul 13 06:00:54 PM PDT 24 |
| Finished | Jul 13 06:01:11 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-591cd289-6c62-4a8f-a974-a490b9d1595e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2792826747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2792826747 |
| Directory | /workspace/32.uart_smoke/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all.2459331422 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 87291869310 ps |
| CPU time | 145.13 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:03:29 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-4e5a5f70-98d9-43cc-88a9-4973e566c9b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459331422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2459331422 |
| Directory | /workspace/32.uart_stress_all/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2162285171 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 87302243326 ps |
| CPU time | 1271.91 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:22:08 PM PDT 24 |
| Peak memory | 217084 kb |
| Host | smart-41340b10-26af-4e52-939a-172dec82a3e6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162285171 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2162285171 |
| Directory | /workspace/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.uart_tx_ovrd.1223663481 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 6982092691 ps |
| CPU time | 14.4 seconds |
| Started | Jul 13 06:00:55 PM PDT 24 |
| Finished | Jul 13 06:01:11 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-d088c06a-391b-4e19-8bda-0028fb79e996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1223663481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1223663481 |
| Directory | /workspace/32.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/32.uart_tx_rx.2863166417 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 111879535369 ps |
| CPU time | 13.67 seconds |
| Started | Jul 13 06:00:56 PM PDT 24 |
| Finished | Jul 13 06:01:10 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-b26b1db2-0790-452a-912a-4e719e96abb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863166417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2863166417 |
| Directory | /workspace/32.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/33.uart_alert_test.680804515 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 13617212 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 06:01:04 PM PDT 24 |
| Finished | Jul 13 06:01:05 PM PDT 24 |
| Peak memory | 195236 kb |
| Host | smart-536c232c-f168-4f8c-8685-3065f93bc730 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680804515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.680804515 |
| Directory | /workspace/33.uart_alert_test/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_full.2203407747 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 179515402856 ps |
| CPU time | 122.8 seconds |
| Started | Jul 13 06:01:06 PM PDT 24 |
| Finished | Jul 13 06:03:09 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-61e7a4b9-52b6-4c89-a41f-0a77f1e3db93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203407747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2203407747 |
| Directory | /workspace/33.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_overflow.1158700486 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 52865975172 ps |
| CPU time | 24.3 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:01:28 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-c5b767f5-6ea3-4c39-b97c-82ea7609248e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158700486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1158700486 |
| Directory | /workspace/33.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_reset.1420753751 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 27514987897 ps |
| CPU time | 34.1 seconds |
| Started | Jul 13 06:01:02 PM PDT 24 |
| Finished | Jul 13 06:01:37 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-dc083287-c760-4ff5-b436-b1de7bdaa60a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420753751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1420753751 |
| Directory | /workspace/33.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/33.uart_intr.353098165 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 69818814305 ps |
| CPU time | 100.88 seconds |
| Started | Jul 13 06:01:02 PM PDT 24 |
| Finished | Jul 13 06:02:44 PM PDT 24 |
| Peak memory | 197940 kb |
| Host | smart-cb1a3c94-cbb8-46a1-acb6-2143dcb2094f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353098165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.353098165 |
| Directory | /workspace/33.uart_intr/latest |
| Test location | /workspace/coverage/default/33.uart_long_xfer_wo_dly.567894781 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 104688496919 ps |
| CPU time | 639.93 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:11:44 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-ac4f1b8a-5969-464f-9c19-cef0d681b381 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=567894781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.567894781 |
| Directory | /workspace/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/33.uart_loopback.1444509820 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 6438488668 ps |
| CPU time | 11.51 seconds |
| Started | Jul 13 06:01:02 PM PDT 24 |
| Finished | Jul 13 06:01:14 PM PDT 24 |
| Peak memory | 199564 kb |
| Host | smart-124106f6-ce69-4784-84a1-694ad327ecc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1444509820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1444509820 |
| Directory | /workspace/33.uart_loopback/latest |
| Test location | /workspace/coverage/default/33.uart_noise_filter.670606324 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 86696839174 ps |
| CPU time | 206.93 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:04:30 PM PDT 24 |
| Peak memory | 208072 kb |
| Host | smart-d116f237-6561-4187-89e1-b3bb8c67ef8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670606324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.670606324 |
| Directory | /workspace/33.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/33.uart_perf.1604721660 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 3273033523 ps |
| CPU time | 46.48 seconds |
| Started | Jul 13 06:01:02 PM PDT 24 |
| Finished | Jul 13 06:01:48 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-2ede68c0-1803-4711-b372-e28ba883e428 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1604721660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1604721660 |
| Directory | /workspace/33.uart_perf/latest |
| Test location | /workspace/coverage/default/33.uart_rx_oversample.1992512555 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2651658936 ps |
| CPU time | 4.91 seconds |
| Started | Jul 13 06:01:04 PM PDT 24 |
| Finished | Jul 13 06:01:09 PM PDT 24 |
| Peak memory | 198916 kb |
| Host | smart-0dc39a20-e9c6-4ad9-97f7-1a41bd3e7d70 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1992512555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1992512555 |
| Directory | /workspace/33.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/33.uart_rx_parity_err.813498151 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 81154020714 ps |
| CPU time | 115.02 seconds |
| Started | Jul 13 06:01:04 PM PDT 24 |
| Finished | Jul 13 06:02:59 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-50d26fa4-aef5-4a0b-997d-38cd69137f6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813498151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.813498151 |
| Directory | /workspace/33.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/33.uart_rx_start_bit_filter.3463883153 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2581069625 ps |
| CPU time | 2.79 seconds |
| Started | Jul 13 06:01:02 PM PDT 24 |
| Finished | Jul 13 06:01:05 PM PDT 24 |
| Peak memory | 196344 kb |
| Host | smart-7cbea369-def4-4298-9d31-903f01cbe402 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3463883153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3463883153 |
| Directory | /workspace/33.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/33.uart_smoke.47436964 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6206025657 ps |
| CPU time | 7.08 seconds |
| Started | Jul 13 06:01:02 PM PDT 24 |
| Finished | Jul 13 06:01:10 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-075a92e8-ebe6-4e61-9e6c-61f0fc633311 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47436964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.47436964 |
| Directory | /workspace/33.uart_smoke/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all.4060045649 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 72730177139 ps |
| CPU time | 247.49 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:05:11 PM PDT 24 |
| Peak memory | 200128 kb |
| Host | smart-99110795-bfaa-40db-9adc-1f64ffc7c036 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060045649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4060045649 |
| Directory | /workspace/33.uart_stress_all/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all_with_rand_reset.4191281801 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 467941183705 ps |
| CPU time | 343.07 seconds |
| Started | Jul 13 06:01:06 PM PDT 24 |
| Finished | Jul 13 06:06:49 PM PDT 24 |
| Peak memory | 216664 kb |
| Host | smart-f6771340-a333-4a8c-9a3d-77f82cf4ae24 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191281801 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.4191281801 |
| Directory | /workspace/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.uart_tx_ovrd.2139116798 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 6121729017 ps |
| CPU time | 16.47 seconds |
| Started | Jul 13 06:01:04 PM PDT 24 |
| Finished | Jul 13 06:01:21 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-055ab42e-a2e0-4a95-b625-61261e25cfcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139116798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2139116798 |
| Directory | /workspace/33.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/33.uart_tx_rx.113319819 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 7096082282 ps |
| CPU time | 9.16 seconds |
| Started | Jul 13 06:01:02 PM PDT 24 |
| Finished | Jul 13 06:01:12 PM PDT 24 |
| Peak memory | 197188 kb |
| Host | smart-18b106bc-e352-4734-8b55-b5fe9901f02d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113319819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.113319819 |
| Directory | /workspace/33.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/34.uart_alert_test.2735592907 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 12822178 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:01:15 PM PDT 24 |
| Peak memory | 195468 kb |
| Host | smart-7c2c3bd8-009a-4a50-bacb-b10db3336b4f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735592907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2735592907 |
| Directory | /workspace/34.uart_alert_test/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_full.1510104601 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 53774662202 ps |
| CPU time | 78.97 seconds |
| Started | Jul 13 06:01:07 PM PDT 24 |
| Finished | Jul 13 06:02:26 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-72a38bee-9271-4125-ae0e-e623679512af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510104601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1510104601 |
| Directory | /workspace/34.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_overflow.3172953835 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 41911528087 ps |
| CPU time | 29.78 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:01:33 PM PDT 24 |
| Peak memory | 199548 kb |
| Host | smart-81e2dd81-10fe-4746-a93b-720a541c9a69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172953835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3172953835 |
| Directory | /workspace/34.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_reset.971134320 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 4829206972 ps |
| CPU time | 7.74 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:01:11 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-9cc7b98b-2ce0-49df-823d-a69826e3411b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=971134320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.971134320 |
| Directory | /workspace/34.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/34.uart_intr.2474068631 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 12757388303 ps |
| CPU time | 11.21 seconds |
| Started | Jul 13 06:01:12 PM PDT 24 |
| Finished | Jul 13 06:01:23 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-2e371598-e3b9-48f4-b8b0-355f948d9e79 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474068631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2474068631 |
| Directory | /workspace/34.uart_intr/latest |
| Test location | /workspace/coverage/default/34.uart_long_xfer_wo_dly.1561761681 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 376780533534 ps |
| CPU time | 257.01 seconds |
| Started | Jul 13 06:01:12 PM PDT 24 |
| Finished | Jul 13 06:05:30 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-e6e10a02-9654-4b90-8ca6-47fcacf17cc5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1561761681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1561761681 |
| Directory | /workspace/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/34.uart_loopback.2644281634 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 3535998915 ps |
| CPU time | 5 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:01:19 PM PDT 24 |
| Peak memory | 198576 kb |
| Host | smart-7c021a25-a3ba-4d76-a5c2-ffea3220f065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644281634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2644281634 |
| Directory | /workspace/34.uart_loopback/latest |
| Test location | /workspace/coverage/default/34.uart_noise_filter.968501266 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 113345758437 ps |
| CPU time | 55.22 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:02:09 PM PDT 24 |
| Peak memory | 208252 kb |
| Host | smart-4a7a96d9-cf3e-4000-b00b-051903e85b85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968501266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.968501266 |
| Directory | /workspace/34.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/34.uart_perf.3040886142 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 13318809180 ps |
| CPU time | 666.97 seconds |
| Started | Jul 13 06:01:12 PM PDT 24 |
| Finished | Jul 13 06:12:20 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-c74dc113-8f1b-4cf8-b332-1f28069466ba |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3040886142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3040886142 |
| Directory | /workspace/34.uart_perf/latest |
| Test location | /workspace/coverage/default/34.uart_rx_oversample.802883151 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2947099448 ps |
| CPU time | 25.94 seconds |
| Started | Jul 13 06:01:01 PM PDT 24 |
| Finished | Jul 13 06:01:27 PM PDT 24 |
| Peak memory | 198284 kb |
| Host | smart-655b34f3-dd3b-49c2-8f05-ff82cc89deed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=802883151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.802883151 |
| Directory | /workspace/34.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/34.uart_rx_parity_err.149562177 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 35545768592 ps |
| CPU time | 26.8 seconds |
| Started | Jul 13 06:01:12 PM PDT 24 |
| Finished | Jul 13 06:01:39 PM PDT 24 |
| Peak memory | 199640 kb |
| Host | smart-37260f02-5960-4cbc-824e-1a68a3a5aa0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149562177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.149562177 |
| Directory | /workspace/34.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/34.uart_rx_start_bit_filter.2748279465 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 33249957796 ps |
| CPU time | 12.4 seconds |
| Started | Jul 13 06:01:14 PM PDT 24 |
| Finished | Jul 13 06:01:27 PM PDT 24 |
| Peak memory | 195740 kb |
| Host | smart-e52e6f5f-6463-4933-99c2-643faef05dce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748279465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2748279465 |
| Directory | /workspace/34.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/34.uart_smoke.641261716 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 473236608 ps |
| CPU time | 1.94 seconds |
| Started | Jul 13 06:01:03 PM PDT 24 |
| Finished | Jul 13 06:01:06 PM PDT 24 |
| Peak memory | 199592 kb |
| Host | smart-17f002c8-c88a-4dbf-94e7-df947348fd6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=641261716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.641261716 |
| Directory | /workspace/34.uart_smoke/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all.1482783351 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 331334197046 ps |
| CPU time | 458.64 seconds |
| Started | Jul 13 06:01:12 PM PDT 24 |
| Finished | Jul 13 06:08:51 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-ad654730-d9d0-4047-8d1e-ea19783ee702 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482783351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1482783351 |
| Directory | /workspace/34.uart_stress_all/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3442021746 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 138429939843 ps |
| CPU time | 413.31 seconds |
| Started | Jul 13 06:01:15 PM PDT 24 |
| Finished | Jul 13 06:08:09 PM PDT 24 |
| Peak memory | 225964 kb |
| Host | smart-2332c34d-7b8b-4440-add3-99971700a492 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442021746 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3442021746 |
| Directory | /workspace/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.uart_tx_ovrd.1992486111 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1013876775 ps |
| CPU time | 3.74 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:01:18 PM PDT 24 |
| Peak memory | 198740 kb |
| Host | smart-8d980a90-8be6-40d1-98c4-02b4ad1db303 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992486111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1992486111 |
| Directory | /workspace/34.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/34.uart_tx_rx.386491972 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 47501773636 ps |
| CPU time | 67.62 seconds |
| Started | Jul 13 06:01:06 PM PDT 24 |
| Finished | Jul 13 06:02:14 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-e3453706-d217-4267-85d1-77b4a29d9831 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386491972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.386491972 |
| Directory | /workspace/34.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/35.uart_alert_test.1525598188 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 21467649 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 06:01:20 PM PDT 24 |
| Finished | Jul 13 06:01:21 PM PDT 24 |
| Peak memory | 195240 kb |
| Host | smart-da053814-5a27-4a04-ada3-b174940978e0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525598188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1525598188 |
| Directory | /workspace/35.uart_alert_test/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_full.3271526884 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 110108314396 ps |
| CPU time | 78.01 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:02:31 PM PDT 24 |
| Peak memory | 199960 kb |
| Host | smart-1a515c41-739b-4cd6-b63a-7c58328a8aac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3271526884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3271526884 |
| Directory | /workspace/35.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_overflow.3238649903 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 27153204028 ps |
| CPU time | 25.31 seconds |
| Started | Jul 13 06:01:14 PM PDT 24 |
| Finished | Jul 13 06:01:40 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-db06acac-ccc2-4ec7-87bf-78a8e824c683 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238649903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3238649903 |
| Directory | /workspace/35.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_reset.3751419387 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 47409848790 ps |
| CPU time | 73.38 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:02:27 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-63b31fb5-b073-491c-915f-33435eba72f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751419387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3751419387 |
| Directory | /workspace/35.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/35.uart_intr.4078852883 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 52414048803 ps |
| CPU time | 10.63 seconds |
| Started | Jul 13 06:01:14 PM PDT 24 |
| Finished | Jul 13 06:01:25 PM PDT 24 |
| Peak memory | 199036 kb |
| Host | smart-d7031034-1708-4a91-9f0b-c1da5d036ce9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078852883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.4078852883 |
| Directory | /workspace/35.uart_intr/latest |
| Test location | /workspace/coverage/default/35.uart_long_xfer_wo_dly.2477966072 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 36647318839 ps |
| CPU time | 36.87 seconds |
| Started | Jul 13 06:01:15 PM PDT 24 |
| Finished | Jul 13 06:01:52 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-a8a1acac-4ea5-45ee-9486-5098070d8e00 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2477966072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2477966072 |
| Directory | /workspace/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/35.uart_loopback.3724409514 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 6747346028 ps |
| CPU time | 5.72 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:01:19 PM PDT 24 |
| Peak memory | 198936 kb |
| Host | smart-3b3dfbad-ca35-4549-9e65-89c352ec4f58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724409514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3724409514 |
| Directory | /workspace/35.uart_loopback/latest |
| Test location | /workspace/coverage/default/35.uart_noise_filter.2062386407 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 150895274594 ps |
| CPU time | 73.2 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:02:27 PM PDT 24 |
| Peak memory | 200004 kb |
| Host | smart-bd1db473-e700-4bfc-b4c9-c2251ed61d7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062386407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2062386407 |
| Directory | /workspace/35.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/35.uart_perf.4174651478 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 21799815436 ps |
| CPU time | 1255.74 seconds |
| Started | Jul 13 06:01:14 PM PDT 24 |
| Finished | Jul 13 06:22:10 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-20bdf2fb-6568-4f6b-ba0b-ebb02bf159da |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4174651478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.4174651478 |
| Directory | /workspace/35.uart_perf/latest |
| Test location | /workspace/coverage/default/35.uart_rx_oversample.2810176192 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4999861373 ps |
| CPU time | 46.84 seconds |
| Started | Jul 13 06:01:15 PM PDT 24 |
| Finished | Jul 13 06:02:03 PM PDT 24 |
| Peak memory | 199076 kb |
| Host | smart-79576122-8191-4339-9299-bcbdefa9d2b5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2810176192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2810176192 |
| Directory | /workspace/35.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/35.uart_rx_parity_err.445301415 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 10356266659 ps |
| CPU time | 15.47 seconds |
| Started | Jul 13 06:01:12 PM PDT 24 |
| Finished | Jul 13 06:01:28 PM PDT 24 |
| Peak memory | 199564 kb |
| Host | smart-3c768224-853b-477b-8ff9-f3e951daa66c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445301415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.445301415 |
| Directory | /workspace/35.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/35.uart_rx_start_bit_filter.768942139 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 2471766783 ps |
| CPU time | 1.09 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:01:15 PM PDT 24 |
| Peak memory | 195896 kb |
| Host | smart-5ae89ffd-912b-4183-9a2b-5caf0ec09f29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768942139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.768942139 |
| Directory | /workspace/35.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/35.uart_smoke.1176323521 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5904917670 ps |
| CPU time | 11.05 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:01:25 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-0e855bbc-f31f-4848-8743-ca488749c2fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176323521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1176323521 |
| Directory | /workspace/35.uart_smoke/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all.2363927456 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 210611565601 ps |
| CPU time | 181.51 seconds |
| Started | Jul 13 06:01:21 PM PDT 24 |
| Finished | Jul 13 06:04:23 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-5897919b-1317-4563-87d5-cb692faece81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363927456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2363927456 |
| Directory | /workspace/35.uart_stress_all/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all_with_rand_reset.4113820455 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 76552644745 ps |
| CPU time | 398.13 seconds |
| Started | Jul 13 06:01:20 PM PDT 24 |
| Finished | Jul 13 06:07:59 PM PDT 24 |
| Peak memory | 216476 kb |
| Host | smart-a2764e8e-3ffa-4dd1-8087-cad5175b35b3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113820455 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.4113820455 |
| Directory | /workspace/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.uart_tx_ovrd.3376328034 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1003648748 ps |
| CPU time | 3.4 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:01:18 PM PDT 24 |
| Peak memory | 198392 kb |
| Host | smart-a9853407-cdbe-49af-b3f5-5f2939e1c850 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376328034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3376328034 |
| Directory | /workspace/35.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/35.uart_tx_rx.1016274086 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 52142773564 ps |
| CPU time | 22.44 seconds |
| Started | Jul 13 06:01:13 PM PDT 24 |
| Finished | Jul 13 06:01:36 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-2ed5b758-4f31-41d2-930f-b445022f9b97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1016274086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1016274086 |
| Directory | /workspace/35.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/36.uart_alert_test.257851176 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 35913108 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 06:01:22 PM PDT 24 |
| Finished | Jul 13 06:01:23 PM PDT 24 |
| Peak memory | 195240 kb |
| Host | smart-777fb411-2b62-49c1-aa14-da7933bd33a6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257851176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.257851176 |
| Directory | /workspace/36.uart_alert_test/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_full.3275270250 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 143260430079 ps |
| CPU time | 788.64 seconds |
| Started | Jul 13 06:01:24 PM PDT 24 |
| Finished | Jul 13 06:14:33 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-8847dbd2-34e9-4ca1-baeb-050733607b18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275270250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3275270250 |
| Directory | /workspace/36.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_overflow.967948569 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 39304580163 ps |
| CPU time | 23.2 seconds |
| Started | Jul 13 06:01:22 PM PDT 24 |
| Finished | Jul 13 06:01:46 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-f5b469f2-49a4-4f6e-b803-5ffb1c6fc5cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967948569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.967948569 |
| Directory | /workspace/36.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_reset.3350696739 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 79048395077 ps |
| CPU time | 110.52 seconds |
| Started | Jul 13 06:01:20 PM PDT 24 |
| Finished | Jul 13 06:03:11 PM PDT 24 |
| Peak memory | 199696 kb |
| Host | smart-564783c9-f909-403a-a64a-c746762c43ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350696739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3350696739 |
| Directory | /workspace/36.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/36.uart_intr.4268667861 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 356285245167 ps |
| CPU time | 130.39 seconds |
| Started | Jul 13 06:01:21 PM PDT 24 |
| Finished | Jul 13 06:03:32 PM PDT 24 |
| Peak memory | 197240 kb |
| Host | smart-757360f4-eeb2-49da-89db-1f98d1555525 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268667861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.4268667861 |
| Directory | /workspace/36.uart_intr/latest |
| Test location | /workspace/coverage/default/36.uart_long_xfer_wo_dly.1823709991 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 350195402701 ps |
| CPU time | 257.95 seconds |
| Started | Jul 13 06:01:20 PM PDT 24 |
| Finished | Jul 13 06:05:39 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-fd00c978-7270-4db0-a64e-639deab52d56 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1823709991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1823709991 |
| Directory | /workspace/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/36.uart_loopback.2760692890 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 10573401643 ps |
| CPU time | 7.21 seconds |
| Started | Jul 13 06:01:22 PM PDT 24 |
| Finished | Jul 13 06:01:29 PM PDT 24 |
| Peak memory | 199588 kb |
| Host | smart-c791902c-02a1-4e5b-bc9e-1db3cb2d5d3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760692890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2760692890 |
| Directory | /workspace/36.uart_loopback/latest |
| Test location | /workspace/coverage/default/36.uart_perf.1804767411 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 16748187358 ps |
| CPU time | 129.58 seconds |
| Started | Jul 13 06:01:20 PM PDT 24 |
| Finished | Jul 13 06:03:31 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-21599397-d53f-4dff-b2bc-c6cb675da48b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1804767411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1804767411 |
| Directory | /workspace/36.uart_perf/latest |
| Test location | /workspace/coverage/default/36.uart_rx_oversample.427469432 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4252459553 ps |
| CPU time | 5.2 seconds |
| Started | Jul 13 06:01:20 PM PDT 24 |
| Finished | Jul 13 06:01:26 PM PDT 24 |
| Peak memory | 198004 kb |
| Host | smart-79a57486-abfc-48e2-9a0b-d12cc4de1844 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=427469432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.427469432 |
| Directory | /workspace/36.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/36.uart_rx_parity_err.3748031276 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 36662498385 ps |
| CPU time | 16.74 seconds |
| Started | Jul 13 06:01:22 PM PDT 24 |
| Finished | Jul 13 06:01:39 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-826dae9e-0703-4b48-8bbb-898409b5f078 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748031276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3748031276 |
| Directory | /workspace/36.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/36.uart_rx_start_bit_filter.1235607539 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 40625985068 ps |
| CPU time | 39.55 seconds |
| Started | Jul 13 06:01:19 PM PDT 24 |
| Finished | Jul 13 06:01:59 PM PDT 24 |
| Peak memory | 195820 kb |
| Host | smart-a1f992fb-0d35-467a-8688-90bc5523eed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235607539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1235607539 |
| Directory | /workspace/36.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/36.uart_smoke.2060700928 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 680482433 ps |
| CPU time | 1.25 seconds |
| Started | Jul 13 06:01:19 PM PDT 24 |
| Finished | Jul 13 06:01:21 PM PDT 24 |
| Peak memory | 198580 kb |
| Host | smart-11ec1992-a026-47c1-9c42-731e31293410 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060700928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2060700928 |
| Directory | /workspace/36.uart_smoke/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all.1556815151 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 187941608341 ps |
| CPU time | 478.69 seconds |
| Started | Jul 13 06:01:18 PM PDT 24 |
| Finished | Jul 13 06:09:17 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-cbbf4437-28b0-4e00-81b1-db555e8b74da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556815151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1556815151 |
| Directory | /workspace/36.uart_stress_all/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3664156547 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 75777723615 ps |
| CPU time | 201.35 seconds |
| Started | Jul 13 06:01:20 PM PDT 24 |
| Finished | Jul 13 06:04:41 PM PDT 24 |
| Peak memory | 216564 kb |
| Host | smart-d790084e-d024-4b67-94f6-b15622e6c14b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664156547 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3664156547 |
| Directory | /workspace/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.uart_tx_ovrd.825779675 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 1630526639 ps |
| CPU time | 1.61 seconds |
| Started | Jul 13 06:01:19 PM PDT 24 |
| Finished | Jul 13 06:01:21 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-a88999a3-84c4-4b53-96dc-9bf09c5cea90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825779675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.825779675 |
| Directory | /workspace/36.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/36.uart_tx_rx.3773242823 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 89293976690 ps |
| CPU time | 150.29 seconds |
| Started | Jul 13 06:01:22 PM PDT 24 |
| Finished | Jul 13 06:03:53 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-2c3081ad-37a6-4e4d-91af-5a6e8b382f4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773242823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3773242823 |
| Directory | /workspace/36.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/37.uart_alert_test.4035150143 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 13281439 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 06:01:30 PM PDT 24 |
| Finished | Jul 13 06:01:31 PM PDT 24 |
| Peak memory | 195532 kb |
| Host | smart-0c72236b-a26d-4058-83b2-bdda57fbed6a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035150143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.4035150143 |
| Directory | /workspace/37.uart_alert_test/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_full.3217079864 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 30569151592 ps |
| CPU time | 47.64 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:02:16 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-472819d2-1d81-4bbd-b4c9-a6a3ea9492ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217079864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3217079864 |
| Directory | /workspace/37.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_overflow.1225359698 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 277560901464 ps |
| CPU time | 98.68 seconds |
| Started | Jul 13 06:01:26 PM PDT 24 |
| Finished | Jul 13 06:03:05 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-1ac83b66-8aeb-4829-955a-3e8eafcfe9ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1225359698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1225359698 |
| Directory | /workspace/37.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_reset.587162940 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 190151887012 ps |
| CPU time | 110.24 seconds |
| Started | Jul 13 06:01:30 PM PDT 24 |
| Finished | Jul 13 06:03:21 PM PDT 24 |
| Peak memory | 200136 kb |
| Host | smart-2f92b6e2-f01a-490d-8ef9-130d9bab3d48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587162940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.587162940 |
| Directory | /workspace/37.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/37.uart_intr.2668692009 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 35091803280 ps |
| CPU time | 20.12 seconds |
| Started | Jul 13 06:01:31 PM PDT 24 |
| Finished | Jul 13 06:01:51 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-0ba90730-d407-4aea-9f42-967a005ccc4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668692009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2668692009 |
| Directory | /workspace/37.uart_intr/latest |
| Test location | /workspace/coverage/default/37.uart_long_xfer_wo_dly.3038014236 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 114287665230 ps |
| CPU time | 587.9 seconds |
| Started | Jul 13 06:01:30 PM PDT 24 |
| Finished | Jul 13 06:11:19 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-ca0c5714-750c-428a-b0fb-6b07382df881 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3038014236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3038014236 |
| Directory | /workspace/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/37.uart_loopback.3386056031 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 4927259548 ps |
| CPU time | 3.87 seconds |
| Started | Jul 13 06:01:28 PM PDT 24 |
| Finished | Jul 13 06:01:32 PM PDT 24 |
| Peak memory | 198876 kb |
| Host | smart-766d543a-65d8-476f-82da-081a159745fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386056031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3386056031 |
| Directory | /workspace/37.uart_loopback/latest |
| Test location | /workspace/coverage/default/37.uart_noise_filter.2562396550 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 18249426477 ps |
| CPU time | 12.72 seconds |
| Started | Jul 13 06:01:28 PM PDT 24 |
| Finished | Jul 13 06:01:41 PM PDT 24 |
| Peak memory | 194512 kb |
| Host | smart-87bbac4d-4ad6-487a-9032-82be339c9b06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562396550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2562396550 |
| Directory | /workspace/37.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/37.uart_perf.3488173121 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 11868171728 ps |
| CPU time | 600.15 seconds |
| Started | Jul 13 06:01:26 PM PDT 24 |
| Finished | Jul 13 06:11:27 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-a6b9e1f7-86cb-4e35-b470-315ffbe4ba60 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3488173121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3488173121 |
| Directory | /workspace/37.uart_perf/latest |
| Test location | /workspace/coverage/default/37.uart_rx_oversample.925535348 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1500082242 ps |
| CPU time | 4.28 seconds |
| Started | Jul 13 06:01:31 PM PDT 24 |
| Finished | Jul 13 06:01:36 PM PDT 24 |
| Peak memory | 197692 kb |
| Host | smart-ecaea54b-efcd-4555-8b4d-72da2465c20a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=925535348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.925535348 |
| Directory | /workspace/37.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/37.uart_rx_parity_err.3614370094 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 162837610144 ps |
| CPU time | 278.84 seconds |
| Started | Jul 13 06:01:29 PM PDT 24 |
| Finished | Jul 13 06:06:09 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-bb460d69-5c31-407c-a1bf-53c43232b62b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3614370094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3614370094 |
| Directory | /workspace/37.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/37.uart_rx_start_bit_filter.2601014054 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 563410457 ps |
| CPU time | 1.43 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:01:30 PM PDT 24 |
| Peak memory | 195356 kb |
| Host | smart-84e5d8e4-6621-458c-a0e6-a43e0ca08b49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601014054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2601014054 |
| Directory | /workspace/37.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/37.uart_smoke.842430192 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 774224639 ps |
| CPU time | 1.22 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:01:29 PM PDT 24 |
| Peak memory | 198208 kb |
| Host | smart-a0235d2b-1ea4-45da-9046-b4941139d05b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842430192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.842430192 |
| Directory | /workspace/37.uart_smoke/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all.1495803069 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 689300072734 ps |
| CPU time | 270.76 seconds |
| Started | Jul 13 06:01:29 PM PDT 24 |
| Finished | Jul 13 06:06:01 PM PDT 24 |
| Peak memory | 208228 kb |
| Host | smart-ee12ad28-8259-4c2c-b289-0745eec4c0c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495803069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1495803069 |
| Directory | /workspace/37.uart_stress_all/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1611654825 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 210558496136 ps |
| CPU time | 819.98 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:15:07 PM PDT 24 |
| Peak memory | 216512 kb |
| Host | smart-c65a29ae-648f-4158-8e16-897628547e1c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611654825 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1611654825 |
| Directory | /workspace/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.uart_tx_ovrd.2581060555 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1630596613 ps |
| CPU time | 3.08 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:01:30 PM PDT 24 |
| Peak memory | 198820 kb |
| Host | smart-0156f830-6954-43ac-92b9-8c8660ec4df9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581060555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2581060555 |
| Directory | /workspace/37.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/37.uart_tx_rx.3567805322 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 73094352815 ps |
| CPU time | 127.54 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:03:35 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-6c8562b6-08f2-42b5-bbc8-b345f5cb76a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567805322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3567805322 |
| Directory | /workspace/37.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/38.uart_alert_test.1036319830 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 12445626 ps |
| CPU time | 0.59 seconds |
| Started | Jul 13 06:01:38 PM PDT 24 |
| Finished | Jul 13 06:01:39 PM PDT 24 |
| Peak memory | 195520 kb |
| Host | smart-b2cebba7-9fc8-4a28-aea7-4e92a6ae8858 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036319830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1036319830 |
| Directory | /workspace/38.uart_alert_test/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_full.2406494571 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 106781987297 ps |
| CPU time | 101.6 seconds |
| Started | Jul 13 06:01:28 PM PDT 24 |
| Finished | Jul 13 06:03:10 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-0a73f752-7796-43d1-a56e-9acd4ea706ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406494571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2406494571 |
| Directory | /workspace/38.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_overflow.3122429144 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 27379942756 ps |
| CPU time | 13.41 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:01:42 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-de471324-363e-4f54-97f6-556539bc8d03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122429144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3122429144 |
| Directory | /workspace/38.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_reset.1237114573 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 22431124763 ps |
| CPU time | 33.28 seconds |
| Started | Jul 13 06:01:29 PM PDT 24 |
| Finished | Jul 13 06:02:03 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-fdd80cca-65cd-4210-9615-1f80c2fd10c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237114573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1237114573 |
| Directory | /workspace/38.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/38.uart_intr.1363587116 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 31270649976 ps |
| CPU time | 21.74 seconds |
| Started | Jul 13 06:01:26 PM PDT 24 |
| Finished | Jul 13 06:01:48 PM PDT 24 |
| Peak memory | 197376 kb |
| Host | smart-58fa35e4-f226-4647-8851-c5c3ba2e0437 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363587116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1363587116 |
| Directory | /workspace/38.uart_intr/latest |
| Test location | /workspace/coverage/default/38.uart_long_xfer_wo_dly.3905415078 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 162110523938 ps |
| CPU time | 227.06 seconds |
| Started | Jul 13 06:01:35 PM PDT 24 |
| Finished | Jul 13 06:05:23 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-d317fe30-ebf8-47ce-ab3f-1e61a8c06e6c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3905415078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3905415078 |
| Directory | /workspace/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/38.uart_loopback.2007108079 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 8469401626 ps |
| CPU time | 7.12 seconds |
| Started | Jul 13 06:01:38 PM PDT 24 |
| Finished | Jul 13 06:01:46 PM PDT 24 |
| Peak memory | 199632 kb |
| Host | smart-ab3b5874-c17c-4379-8e73-3f16c9ef432f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007108079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2007108079 |
| Directory | /workspace/38.uart_loopback/latest |
| Test location | /workspace/coverage/default/38.uart_noise_filter.672852683 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 55680479355 ps |
| CPU time | 85.36 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:02:53 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-445ff906-bae1-42f1-85df-f6646ddbb466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672852683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.672852683 |
| Directory | /workspace/38.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/38.uart_perf.2878620587 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 21277917137 ps |
| CPU time | 1171.26 seconds |
| Started | Jul 13 06:01:37 PM PDT 24 |
| Finished | Jul 13 06:21:09 PM PDT 24 |
| Peak memory | 199572 kb |
| Host | smart-7a97404e-eab7-4d22-92d4-cd104426042e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2878620587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2878620587 |
| Directory | /workspace/38.uart_perf/latest |
| Test location | /workspace/coverage/default/38.uart_rx_oversample.368159022 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 4569137885 ps |
| CPU time | 22.58 seconds |
| Started | Jul 13 06:01:28 PM PDT 24 |
| Finished | Jul 13 06:01:51 PM PDT 24 |
| Peak memory | 198116 kb |
| Host | smart-2fad21d2-2fba-456a-8461-25616fdb1c42 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=368159022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.368159022 |
| Directory | /workspace/38.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/38.uart_rx_parity_err.2096234279 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 118816249114 ps |
| CPU time | 51.97 seconds |
| Started | Jul 13 06:01:29 PM PDT 24 |
| Finished | Jul 13 06:02:21 PM PDT 24 |
| Peak memory | 199660 kb |
| Host | smart-4d2aa79a-8b5f-4702-9f8c-aacf6a8bf460 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096234279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2096234279 |
| Directory | /workspace/38.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/38.uart_rx_start_bit_filter.2800783952 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 3838391470 ps |
| CPU time | 3.14 seconds |
| Started | Jul 13 06:01:31 PM PDT 24 |
| Finished | Jul 13 06:01:34 PM PDT 24 |
| Peak memory | 196088 kb |
| Host | smart-f641f89d-5e67-457d-a117-523ec4bd6b48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800783952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2800783952 |
| Directory | /workspace/38.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/38.uart_smoke.979002924 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 6272630308 ps |
| CPU time | 33.45 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:02:01 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-afcad149-f7a4-4e62-9632-5a0e38a16b52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979002924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.979002924 |
| Directory | /workspace/38.uart_smoke/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all.3467442478 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 126667958880 ps |
| CPU time | 115.23 seconds |
| Started | Jul 13 06:01:37 PM PDT 24 |
| Finished | Jul 13 06:03:33 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-f4d43ce8-9a6a-47cc-a25a-18c6ab0e80a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467442478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3467442478 |
| Directory | /workspace/38.uart_stress_all/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3570112763 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 86209182918 ps |
| CPU time | 823.47 seconds |
| Started | Jul 13 06:01:36 PM PDT 24 |
| Finished | Jul 13 06:15:20 PM PDT 24 |
| Peak memory | 230728 kb |
| Host | smart-f8196c02-0145-4698-a915-833d0c4a835b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570112763 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3570112763 |
| Directory | /workspace/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.uart_tx_ovrd.1525101906 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 1680478611 ps |
| CPU time | 1.66 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:01:30 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-ed18ec16-fb8e-4f56-9d01-1e1df9d4f32f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525101906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1525101906 |
| Directory | /workspace/38.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/38.uart_tx_rx.3885158866 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 84813585717 ps |
| CPU time | 46.1 seconds |
| Started | Jul 13 06:01:27 PM PDT 24 |
| Finished | Jul 13 06:02:14 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-37fe4c7a-7420-44be-ac8c-5991dbf49708 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885158866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3885158866 |
| Directory | /workspace/38.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/39.uart_alert_test.1299464798 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 10742182 ps |
| CPU time | 0.63 seconds |
| Started | Jul 13 06:01:51 PM PDT 24 |
| Finished | Jul 13 06:01:52 PM PDT 24 |
| Peak memory | 195256 kb |
| Host | smart-83beabba-875c-4ec8-9ec7-c781a4aaf155 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299464798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1299464798 |
| Directory | /workspace/39.uart_alert_test/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_full.1408038511 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 15226375059 ps |
| CPU time | 25.32 seconds |
| Started | Jul 13 06:01:37 PM PDT 24 |
| Finished | Jul 13 06:02:03 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-a7c34113-f7c3-4b34-9276-8c3a7e76d2fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408038511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1408038511 |
| Directory | /workspace/39.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_overflow.1533445667 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 31364286708 ps |
| CPU time | 49.98 seconds |
| Started | Jul 13 06:01:34 PM PDT 24 |
| Finished | Jul 13 06:02:25 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-6efb5248-3e77-49eb-8f2e-130b379fce21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1533445667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1533445667 |
| Directory | /workspace/39.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_reset.2925618572 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 31993621446 ps |
| CPU time | 22.1 seconds |
| Started | Jul 13 06:01:38 PM PDT 24 |
| Finished | Jul 13 06:02:01 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-f63a9d77-61cb-4440-9a4d-465e19e0ce30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925618572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2925618572 |
| Directory | /workspace/39.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/39.uart_intr.3810903123 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 57220887060 ps |
| CPU time | 118.64 seconds |
| Started | Jul 13 06:01:39 PM PDT 24 |
| Finished | Jul 13 06:03:38 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-4e3cbc45-1432-430b-918e-881b4f5d8ec7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810903123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3810903123 |
| Directory | /workspace/39.uart_intr/latest |
| Test location | /workspace/coverage/default/39.uart_long_xfer_wo_dly.529727846 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 128435251308 ps |
| CPU time | 440.47 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:09:12 PM PDT 24 |
| Peak memory | 199384 kb |
| Host | smart-8eb9e55d-359e-4f1f-b2cb-164599a7c3b6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=529727846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.529727846 |
| Directory | /workspace/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/39.uart_loopback.130893887 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 8430947664 ps |
| CPU time | 9.2 seconds |
| Started | Jul 13 06:01:37 PM PDT 24 |
| Finished | Jul 13 06:01:47 PM PDT 24 |
| Peak memory | 199160 kb |
| Host | smart-6fd10890-9e5b-4f7a-9793-696834170fe5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130893887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.130893887 |
| Directory | /workspace/39.uart_loopback/latest |
| Test location | /workspace/coverage/default/39.uart_noise_filter.2507987846 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 37910511122 ps |
| CPU time | 17.41 seconds |
| Started | Jul 13 06:01:37 PM PDT 24 |
| Finished | Jul 13 06:01:55 PM PDT 24 |
| Peak memory | 200024 kb |
| Host | smart-6af7c7aa-53ef-447e-92c7-01c981593bbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507987846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2507987846 |
| Directory | /workspace/39.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/39.uart_perf.1241591913 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 21414704053 ps |
| CPU time | 89.51 seconds |
| Started | Jul 13 06:01:51 PM PDT 24 |
| Finished | Jul 13 06:03:21 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-830f68ae-de2d-4130-8031-3fdb7437669a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1241591913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1241591913 |
| Directory | /workspace/39.uart_perf/latest |
| Test location | /workspace/coverage/default/39.uart_rx_oversample.4059588653 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 7117242692 ps |
| CPU time | 63 seconds |
| Started | Jul 13 06:01:38 PM PDT 24 |
| Finished | Jul 13 06:02:41 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-15056520-1575-4eaa-8f03-c6e485cab802 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4059588653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.4059588653 |
| Directory | /workspace/39.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/39.uart_rx_parity_err.237529719 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 100767565884 ps |
| CPU time | 39.26 seconds |
| Started | Jul 13 06:01:38 PM PDT 24 |
| Finished | Jul 13 06:02:17 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-dd4af7b4-4043-44c2-999d-e1f5460b9a68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237529719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.237529719 |
| Directory | /workspace/39.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/39.uart_rx_start_bit_filter.4175771419 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1684042814 ps |
| CPU time | 1.89 seconds |
| Started | Jul 13 06:01:37 PM PDT 24 |
| Finished | Jul 13 06:01:40 PM PDT 24 |
| Peak memory | 194992 kb |
| Host | smart-14e98ff5-a66d-4839-ac6e-8576ba4acbbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175771419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4175771419 |
| Directory | /workspace/39.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/39.uart_smoke.2677642790 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 105671699 ps |
| CPU time | 0.81 seconds |
| Started | Jul 13 06:01:37 PM PDT 24 |
| Finished | Jul 13 06:01:39 PM PDT 24 |
| Peak memory | 196848 kb |
| Host | smart-08d85142-1758-4f1d-b251-71c66ab9f633 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677642790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2677642790 |
| Directory | /workspace/39.uart_smoke/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all.3796977977 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 80503868699 ps |
| CPU time | 136.46 seconds |
| Started | Jul 13 06:01:49 PM PDT 24 |
| Finished | Jul 13 06:04:05 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-8efc8036-8725-40e1-9973-339e95e2accc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796977977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3796977977 |
| Directory | /workspace/39.uart_stress_all/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3735159494 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 49304936038 ps |
| CPU time | 1015.61 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:18:47 PM PDT 24 |
| Peak memory | 208512 kb |
| Host | smart-55f94b88-a662-4457-8529-1f2a3e10ed86 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735159494 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3735159494 |
| Directory | /workspace/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.uart_tx_ovrd.1452186313 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1694973390 ps |
| CPU time | 2.45 seconds |
| Started | Jul 13 06:01:35 PM PDT 24 |
| Finished | Jul 13 06:01:37 PM PDT 24 |
| Peak memory | 198444 kb |
| Host | smart-7ef4088f-0850-420a-8aa2-f6240c860cc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452186313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1452186313 |
| Directory | /workspace/39.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/39.uart_tx_rx.1746979109 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 104433237640 ps |
| CPU time | 68.77 seconds |
| Started | Jul 13 06:01:36 PM PDT 24 |
| Finished | Jul 13 06:02:45 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-60a58def-a5f9-49ff-aaf7-c94d65e0fd7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746979109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1746979109 |
| Directory | /workspace/39.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.uart_alert_test.1385026725 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 21650060 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 05:59:01 PM PDT 24 |
| Finished | Jul 13 05:59:02 PM PDT 24 |
| Peak memory | 194256 kb |
| Host | smart-e95feead-bbbe-4cf9-9504-fd05c07ffbb7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385026725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1385026725 |
| Directory | /workspace/4.uart_alert_test/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_full.109325085 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 142892356095 ps |
| CPU time | 43.07 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 05:59:36 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-99bca2a4-37b2-4b37-bfc0-3f1c633374d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109325085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.109325085 |
| Directory | /workspace/4.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_overflow.3696493456 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 88991719084 ps |
| CPU time | 41.72 seconds |
| Started | Jul 13 05:58:53 PM PDT 24 |
| Finished | Jul 13 05:59:35 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-54faa923-26c9-4ec4-8a69-bf2c86d2ed05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696493456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3696493456 |
| Directory | /workspace/4.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_reset.1548854241 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 32635652925 ps |
| CPU time | 25.19 seconds |
| Started | Jul 13 05:58:54 PM PDT 24 |
| Finished | Jul 13 05:59:20 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-de27a6c6-75de-4412-a76a-8b01c260f6ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548854241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1548854241 |
| Directory | /workspace/4.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/4.uart_intr.2187370990 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 159387793480 ps |
| CPU time | 208.29 seconds |
| Started | Jul 13 05:58:54 PM PDT 24 |
| Finished | Jul 13 06:02:24 PM PDT 24 |
| Peak memory | 199460 kb |
| Host | smart-c861e92d-d661-432a-9b47-5631057ccab9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187370990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2187370990 |
| Directory | /workspace/4.uart_intr/latest |
| Test location | /workspace/coverage/default/4.uart_long_xfer_wo_dly.2846654832 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 73893902984 ps |
| CPU time | 511.6 seconds |
| Started | Jul 13 05:58:56 PM PDT 24 |
| Finished | Jul 13 06:07:28 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-6fc61d1d-da31-460e-9d6b-678bc425cd25 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2846654832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2846654832 |
| Directory | /workspace/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/4.uart_loopback.2283084828 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 7389008398 ps |
| CPU time | 12 seconds |
| Started | Jul 13 05:58:54 PM PDT 24 |
| Finished | Jul 13 05:59:07 PM PDT 24 |
| Peak memory | 199512 kb |
| Host | smart-91ede95d-f4d2-46c5-b2b0-01320079f48c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283084828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2283084828 |
| Directory | /workspace/4.uart_loopback/latest |
| Test location | /workspace/coverage/default/4.uart_noise_filter.3564684586 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 62676723805 ps |
| CPU time | 102.41 seconds |
| Started | Jul 13 05:58:54 PM PDT 24 |
| Finished | Jul 13 06:00:37 PM PDT 24 |
| Peak memory | 200068 kb |
| Host | smart-7f14b9da-7621-4143-ba6c-db00feb69a95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564684586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3564684586 |
| Directory | /workspace/4.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/4.uart_perf.1752560898 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 12341050663 ps |
| CPU time | 158.42 seconds |
| Started | Jul 13 05:58:55 PM PDT 24 |
| Finished | Jul 13 06:01:34 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-542fc00b-fc51-4918-b834-5e1655231979 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1752560898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1752560898 |
| Directory | /workspace/4.uart_perf/latest |
| Test location | /workspace/coverage/default/4.uart_rx_oversample.287683546 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 4295829403 ps |
| CPU time | 38.13 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 05:59:35 PM PDT 24 |
| Peak memory | 198820 kb |
| Host | smart-f7c35837-ee67-431f-b258-09f32f00f1e8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=287683546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.287683546 |
| Directory | /workspace/4.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/4.uart_rx_parity_err.2801078114 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 25049473093 ps |
| CPU time | 18.33 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 05:59:16 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-fbcf9c4c-7ff6-499a-9e62-8bce675e5223 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801078114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2801078114 |
| Directory | /workspace/4.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/4.uart_rx_start_bit_filter.772692359 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 3475054985 ps |
| CPU time | 1.88 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 05:58:55 PM PDT 24 |
| Peak memory | 196376 kb |
| Host | smart-e55d6d0d-ce77-4f4d-a0e9-32e6c44c5bb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772692359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.772692359 |
| Directory | /workspace/4.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/4.uart_sec_cm.4217510667 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 38122179 ps |
| CPU time | 0.76 seconds |
| Started | Jul 13 05:58:55 PM PDT 24 |
| Finished | Jul 13 05:58:57 PM PDT 24 |
| Peak memory | 218232 kb |
| Host | smart-3d2cb58b-0c7a-48f1-b1e3-5f852660f830 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217510667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.4217510667 |
| Directory | /workspace/4.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/4.uart_smoke.554061845 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 646865265 ps |
| CPU time | 1.52 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 05:58:55 PM PDT 24 |
| Peak memory | 198228 kb |
| Host | smart-e43b9eae-aaae-4ffd-869a-968de0271007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=554061845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.554061845 |
| Directory | /workspace/4.uart_smoke/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all.1524942908 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 94723624767 ps |
| CPU time | 27.05 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 05:59:24 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-b21d7f58-4439-4d3b-ab9a-db429966df3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524942908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1524942908 |
| Directory | /workspace/4.uart_stress_all/latest |
| Test location | /workspace/coverage/default/4.uart_tx_ovrd.695094410 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 12257273584 ps |
| CPU time | 31.86 seconds |
| Started | Jul 13 05:59:05 PM PDT 24 |
| Finished | Jul 13 05:59:38 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-f4de6163-1fd8-4ec2-9f27-a0e3156c22f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695094410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.695094410 |
| Directory | /workspace/4.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/4.uart_tx_rx.83782191 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 139791409314 ps |
| CPU time | 62.46 seconds |
| Started | Jul 13 05:58:55 PM PDT 24 |
| Finished | Jul 13 05:59:58 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-575de0e9-871d-4246-9d06-1daefbc4d68b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83782191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.83782191 |
| Directory | /workspace/4.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/40.uart_alert_test.2606734785 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 33400187 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 06:01:51 PM PDT 24 |
| Finished | Jul 13 06:01:52 PM PDT 24 |
| Peak memory | 195468 kb |
| Host | smart-6277e63b-1883-4c40-93b9-6c593fb8d412 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606734785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2606734785 |
| Directory | /workspace/40.uart_alert_test/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_full.676829043 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 53762406973 ps |
| CPU time | 24.58 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:02:16 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-2c254df4-f054-4834-88b0-05b518197dde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676829043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.676829043 |
| Directory | /workspace/40.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_overflow.301827671 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 33892033013 ps |
| CPU time | 12.65 seconds |
| Started | Jul 13 06:01:52 PM PDT 24 |
| Finished | Jul 13 06:02:05 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-2e288099-d07e-4d35-b944-cf8a5b7b31cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301827671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.301827671 |
| Directory | /workspace/40.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_reset.2799868211 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 12422183821 ps |
| CPU time | 17.82 seconds |
| Started | Jul 13 06:01:53 PM PDT 24 |
| Finished | Jul 13 06:02:11 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-9eb7ed05-e601-48ef-9255-fa114e9b75ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799868211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2799868211 |
| Directory | /workspace/40.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/40.uart_intr.40937317 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 26215044137 ps |
| CPU time | 41.77 seconds |
| Started | Jul 13 06:01:51 PM PDT 24 |
| Finished | Jul 13 06:02:34 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-276521cf-dc84-43d8-972a-d223ae69722e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.40937317 |
| Directory | /workspace/40.uart_intr/latest |
| Test location | /workspace/coverage/default/40.uart_long_xfer_wo_dly.1708443816 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 92276895425 ps |
| CPU time | 256.79 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:06:07 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-876604d3-142f-4a9f-a6a8-b480466e74c8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1708443816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1708443816 |
| Directory | /workspace/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/40.uart_loopback.3929023050 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1979424834 ps |
| CPU time | 2.25 seconds |
| Started | Jul 13 06:01:49 PM PDT 24 |
| Finished | Jul 13 06:01:52 PM PDT 24 |
| Peak memory | 195988 kb |
| Host | smart-9cf6e01a-3056-479f-a757-7dd0bfe2ef17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929023050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3929023050 |
| Directory | /workspace/40.uart_loopback/latest |
| Test location | /workspace/coverage/default/40.uart_noise_filter.3071938894 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 192516926142 ps |
| CPU time | 141.05 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:04:12 PM PDT 24 |
| Peak memory | 199996 kb |
| Host | smart-6b0853b8-3c50-466f-b6d1-4567ae850b6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071938894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3071938894 |
| Directory | /workspace/40.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/40.uart_perf.1414843611 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 12162280659 ps |
| CPU time | 526.62 seconds |
| Started | Jul 13 06:01:52 PM PDT 24 |
| Finished | Jul 13 06:10:39 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-165d78c2-21fb-4c74-bfeb-584a80e4e888 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1414843611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1414843611 |
| Directory | /workspace/40.uart_perf/latest |
| Test location | /workspace/coverage/default/40.uart_rx_oversample.1506234139 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4203811851 ps |
| CPU time | 28.67 seconds |
| Started | Jul 13 06:01:49 PM PDT 24 |
| Finished | Jul 13 06:02:19 PM PDT 24 |
| Peak memory | 198696 kb |
| Host | smart-9ac14fe8-c67f-4d6d-b415-85d1171f406d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1506234139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1506234139 |
| Directory | /workspace/40.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/40.uart_rx_parity_err.3719533195 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 110453125021 ps |
| CPU time | 35.54 seconds |
| Started | Jul 13 06:01:49 PM PDT 24 |
| Finished | Jul 13 06:02:25 PM PDT 24 |
| Peak memory | 199652 kb |
| Host | smart-97517a9f-c828-4ec6-9c89-8b062c636fb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719533195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3719533195 |
| Directory | /workspace/40.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/40.uart_rx_start_bit_filter.146906751 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 41130509689 ps |
| CPU time | 13.18 seconds |
| Started | Jul 13 06:01:51 PM PDT 24 |
| Finished | Jul 13 06:02:05 PM PDT 24 |
| Peak memory | 195548 kb |
| Host | smart-fdcd6e00-7d37-45c0-9461-c4409fad5661 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146906751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.146906751 |
| Directory | /workspace/40.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/40.uart_smoke.3932230522 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 119912578 ps |
| CPU time | 0.86 seconds |
| Started | Jul 13 06:02:16 PM PDT 24 |
| Finished | Jul 13 06:02:17 PM PDT 24 |
| Peak memory | 197164 kb |
| Host | smart-d10d798d-69fa-4f94-9081-577bca817b38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932230522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3932230522 |
| Directory | /workspace/40.uart_smoke/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all.3846366569 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 143880954633 ps |
| CPU time | 716.86 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:13:48 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-14199865-af9b-4d5a-821b-341075dec016 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846366569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3846366569 |
| Directory | /workspace/40.uart_stress_all/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1232981461 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6142444685 ps |
| CPU time | 67.49 seconds |
| Started | Jul 13 06:01:49 PM PDT 24 |
| Finished | Jul 13 06:02:57 PM PDT 24 |
| Peak memory | 216620 kb |
| Host | smart-4b39171e-22cd-4a1b-8a62-e5f5ba6fd541 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232981461 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1232981461 |
| Directory | /workspace/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.uart_tx_ovrd.431989718 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 793713681 ps |
| CPU time | 2.71 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:01:54 PM PDT 24 |
| Peak memory | 198264 kb |
| Host | smart-9c2726b3-0409-4fc7-a83f-28bf53c28513 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431989718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.431989718 |
| Directory | /workspace/40.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/40.uart_tx_rx.1670399557 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 85467631096 ps |
| CPU time | 73.56 seconds |
| Started | Jul 13 06:01:49 PM PDT 24 |
| Finished | Jul 13 06:03:04 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-12c7a026-a521-4805-9699-917fa22b6173 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670399557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1670399557 |
| Directory | /workspace/40.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/41.uart_alert_test.4287322902 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 16490118 ps |
| CPU time | 0.58 seconds |
| Started | Jul 13 06:02:01 PM PDT 24 |
| Finished | Jul 13 06:02:02 PM PDT 24 |
| Peak memory | 195204 kb |
| Host | smart-e38533b9-d04f-41ea-b1ae-f46279c05ccb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287322902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4287322902 |
| Directory | /workspace/41.uart_alert_test/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_full.2969727494 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 82331773469 ps |
| CPU time | 18.87 seconds |
| Started | Jul 13 06:01:49 PM PDT 24 |
| Finished | Jul 13 06:02:09 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-683cd64f-c6ef-443f-86c5-8df862c81e17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969727494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2969727494 |
| Directory | /workspace/41.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_overflow.1490971072 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 151914402477 ps |
| CPU time | 54.5 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:02:45 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-b6794c19-44ab-4d0c-91a6-5b080263bca7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490971072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1490971072 |
| Directory | /workspace/41.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_reset.3549382769 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 25615592723 ps |
| CPU time | 45.67 seconds |
| Started | Jul 13 06:01:51 PM PDT 24 |
| Finished | Jul 13 06:02:37 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-7d535bfe-3785-4c8f-bb62-ca91e2035edb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549382769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3549382769 |
| Directory | /workspace/41.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/41.uart_intr.4193053564 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 13010506502 ps |
| CPU time | 25.45 seconds |
| Started | Jul 13 06:01:58 PM PDT 24 |
| Finished | Jul 13 06:02:24 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-e064ee77-45ac-4d97-9301-1962fd2d296a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193053564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4193053564 |
| Directory | /workspace/41.uart_intr/latest |
| Test location | /workspace/coverage/default/41.uart_long_xfer_wo_dly.2268232114 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 96903453282 ps |
| CPU time | 769.66 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:14:52 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-51edf449-02f3-40a7-8518-a59907e14435 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2268232114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2268232114 |
| Directory | /workspace/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/41.uart_loopback.1447488318 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 5840100213 ps |
| CPU time | 4.21 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:02:08 PM PDT 24 |
| Peak memory | 199340 kb |
| Host | smart-2c627212-e648-4687-a40d-5d150612ac7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447488318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1447488318 |
| Directory | /workspace/41.uart_loopback/latest |
| Test location | /workspace/coverage/default/41.uart_noise_filter.342978805 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 65378881744 ps |
| CPU time | 17.66 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:02:17 PM PDT 24 |
| Peak memory | 199660 kb |
| Host | smart-7dc74b38-145a-4e6a-9a28-1a86f6635944 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342978805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.342978805 |
| Directory | /workspace/41.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/41.uart_perf.901491355 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 12425998232 ps |
| CPU time | 707.16 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:13:47 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-5b3e306a-620b-4b86-9f30-7085e837e6ac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=901491355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.901491355 |
| Directory | /workspace/41.uart_perf/latest |
| Test location | /workspace/coverage/default/41.uart_rx_oversample.2794814743 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 3089296304 ps |
| CPU time | 3.18 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:02:06 PM PDT 24 |
| Peak memory | 198004 kb |
| Host | smart-3c4f9f4c-79e9-4466-a8f8-c84009fc0019 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2794814743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2794814743 |
| Directory | /workspace/41.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/41.uart_rx_parity_err.1174000152 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 79453589198 ps |
| CPU time | 104.04 seconds |
| Started | Jul 13 06:02:01 PM PDT 24 |
| Finished | Jul 13 06:03:45 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-95f21580-0648-4a71-8a8f-cdd3a43f488c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174000152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1174000152 |
| Directory | /workspace/41.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/41.uart_rx_start_bit_filter.3552404034 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2021409765 ps |
| CPU time | 1.5 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:02:02 PM PDT 24 |
| Peak memory | 195384 kb |
| Host | smart-8db0cc92-e69c-4fb6-8395-7ebea745126c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552404034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3552404034 |
| Directory | /workspace/41.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/41.uart_smoke.2444710468 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 110760597 ps |
| CPU time | 0.87 seconds |
| Started | Jul 13 06:01:49 PM PDT 24 |
| Finished | Jul 13 06:01:50 PM PDT 24 |
| Peak memory | 196880 kb |
| Host | smart-48fa72c1-2f2c-4414-84a9-b51f6cf4955c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444710468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2444710468 |
| Directory | /workspace/41.uart_smoke/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all.265761073 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 44100038659 ps |
| CPU time | 1708.46 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:30:28 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-d5d6dd03-496f-48e7-bc30-bdd75e6e5dd9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265761073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.265761073 |
| Directory | /workspace/41.uart_stress_all/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all_with_rand_reset.830625316 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 37951203793 ps |
| CPU time | 374.26 seconds |
| Started | Jul 13 06:02:01 PM PDT 24 |
| Finished | Jul 13 06:08:16 PM PDT 24 |
| Peak memory | 216560 kb |
| Host | smart-92249c13-94e5-47e3-a936-a8c42d224445 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830625316 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.830625316 |
| Directory | /workspace/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.uart_tx_ovrd.3420074385 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 944555054 ps |
| CPU time | 2.37 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:02:03 PM PDT 24 |
| Peak memory | 198712 kb |
| Host | smart-149bcc98-e045-491a-8f1f-a00ec1241c64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420074385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3420074385 |
| Directory | /workspace/41.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/41.uart_tx_rx.3142942171 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 188566143277 ps |
| CPU time | 15.53 seconds |
| Started | Jul 13 06:01:50 PM PDT 24 |
| Finished | Jul 13 06:02:06 PM PDT 24 |
| Peak memory | 197800 kb |
| Host | smart-e1b753d5-6833-4215-9f32-83c9ad99ac04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142942171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3142942171 |
| Directory | /workspace/41.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/42.uart_alert_test.2088022800 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 12281257 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:02:04 PM PDT 24 |
| Peak memory | 195236 kb |
| Host | smart-3753cc77-ef60-4fe0-bdbe-26d05f203498 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088022800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2088022800 |
| Directory | /workspace/42.uart_alert_test/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_full.1680159975 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 108151730647 ps |
| CPU time | 65.57 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:03:06 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-f46663da-8103-4a03-973c-19765de1c207 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680159975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1680159975 |
| Directory | /workspace/42.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_overflow.1259923836 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 55966120686 ps |
| CPU time | 92.23 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:03:33 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-da021b7e-7853-4d15-abff-f26097af8d47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259923836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1259923836 |
| Directory | /workspace/42.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_reset.2619398873 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 29416362083 ps |
| CPU time | 44.38 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:02:46 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-f153de13-6075-4c1b-996a-fc8eba8bd7bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619398873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2619398873 |
| Directory | /workspace/42.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/42.uart_intr.3054078940 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 11439688284 ps |
| CPU time | 11.21 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:02:14 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-d073b700-5dc4-4bf5-8b7b-9667117b7837 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054078940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3054078940 |
| Directory | /workspace/42.uart_intr/latest |
| Test location | /workspace/coverage/default/42.uart_long_xfer_wo_dly.2390560356 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 114301861607 ps |
| CPU time | 284.47 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:06:48 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-dc76eaeb-efcb-4d2a-ba95-34cb61cd1b69 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2390560356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2390560356 |
| Directory | /workspace/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/42.uart_loopback.1171993988 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1570125790 ps |
| CPU time | 1.99 seconds |
| Started | Jul 13 06:01:58 PM PDT 24 |
| Finished | Jul 13 06:02:01 PM PDT 24 |
| Peak memory | 195912 kb |
| Host | smart-937e23f1-1871-4cc4-890a-33df51c2a6b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171993988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1171993988 |
| Directory | /workspace/42.uart_loopback/latest |
| Test location | /workspace/coverage/default/42.uart_noise_filter.2388109898 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 81728076559 ps |
| CPU time | 31.44 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:02:31 PM PDT 24 |
| Peak memory | 200056 kb |
| Host | smart-2e29cd4c-63df-4b8c-86c9-0d7e19c7c568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388109898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2388109898 |
| Directory | /workspace/42.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/42.uart_perf.3558150956 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 12917145736 ps |
| CPU time | 185.02 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:05:04 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-6297136b-9ede-4b5f-8acf-bad58a71b324 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3558150956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3558150956 |
| Directory | /workspace/42.uart_perf/latest |
| Test location | /workspace/coverage/default/42.uart_rx_oversample.3780532514 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 6177847476 ps |
| CPU time | 14.37 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:02:15 PM PDT 24 |
| Peak memory | 198724 kb |
| Host | smart-e591318b-66b8-45f4-b360-01035854ae67 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3780532514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3780532514 |
| Directory | /workspace/42.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/42.uart_rx_parity_err.2610616990 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 16845718303 ps |
| CPU time | 27.91 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:02:27 PM PDT 24 |
| Peak memory | 198560 kb |
| Host | smart-6911244b-a9d1-4525-9356-a45add7168b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610616990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2610616990 |
| Directory | /workspace/42.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/42.uart_rx_start_bit_filter.3977467944 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 42108141662 ps |
| CPU time | 35.72 seconds |
| Started | Jul 13 06:02:03 PM PDT 24 |
| Finished | Jul 13 06:02:39 PM PDT 24 |
| Peak memory | 195888 kb |
| Host | smart-42f16419-e12c-49d5-8e00-0a91fd712d64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977467944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3977467944 |
| Directory | /workspace/42.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/42.uart_smoke.1814198546 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 283523660 ps |
| CPU time | 1.05 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:02:00 PM PDT 24 |
| Peak memory | 198580 kb |
| Host | smart-2f987ac3-88ef-4c0f-b612-a406e8143e87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814198546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1814198546 |
| Directory | /workspace/42.uart_smoke/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all.1078077120 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 233771158374 ps |
| CPU time | 472.17 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:09:53 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-2b7363c4-45f6-440e-ae2b-de0ba430b1ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078077120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1078077120 |
| Directory | /workspace/42.uart_stress_all/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2421952695 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 158836037258 ps |
| CPU time | 562.78 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:11:23 PM PDT 24 |
| Peak memory | 224768 kb |
| Host | smart-ff707ffa-c21e-4c3b-8e6b-31bfd3d29fd6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421952695 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2421952695 |
| Directory | /workspace/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.uart_tx_ovrd.1813671169 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2344138338 ps |
| CPU time | 1.96 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:02:05 PM PDT 24 |
| Peak memory | 198260 kb |
| Host | smart-e76cc3ec-244d-4ba8-90cc-4ffa7579e04d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813671169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1813671169 |
| Directory | /workspace/42.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/42.uart_tx_rx.2491338036 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 184238602911 ps |
| CPU time | 43.82 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:02:44 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-053277d6-721d-409e-a025-4e51cd91af9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491338036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2491338036 |
| Directory | /workspace/42.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/43.uart_alert_test.3060225407 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 13118982 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 06:02:08 PM PDT 24 |
| Finished | Jul 13 06:02:09 PM PDT 24 |
| Peak memory | 195520 kb |
| Host | smart-2b8eb6b0-8df5-490a-8449-413cc0d66316 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060225407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3060225407 |
| Directory | /workspace/43.uart_alert_test/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_full.1976587490 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 37337382167 ps |
| CPU time | 53.03 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:02:54 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-efd556da-d509-4b3d-b859-ff8699bd578a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976587490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1976587490 |
| Directory | /workspace/43.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_overflow.1108151418 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 155388250683 ps |
| CPU time | 54.94 seconds |
| Started | Jul 13 06:02:02 PM PDT 24 |
| Finished | Jul 13 06:02:57 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-e75ee7df-27f5-4514-8ebe-c02574bd4b39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108151418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1108151418 |
| Directory | /workspace/43.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/43.uart_intr.813505495 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 38064804199 ps |
| CPU time | 18.31 seconds |
| Started | Jul 13 06:02:00 PM PDT 24 |
| Finished | Jul 13 06:02:19 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-68e74cab-436c-44b0-8680-4b670373401e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813505495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.813505495 |
| Directory | /workspace/43.uart_intr/latest |
| Test location | /workspace/coverage/default/43.uart_long_xfer_wo_dly.2980219947 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 68930642619 ps |
| CPU time | 218.97 seconds |
| Started | Jul 13 06:02:11 PM PDT 24 |
| Finished | Jul 13 06:05:50 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-66f78a73-00f5-4ed4-b47e-406dcdd5b136 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2980219947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2980219947 |
| Directory | /workspace/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/43.uart_loopback.4043076992 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 922602097 ps |
| CPU time | 1.17 seconds |
| Started | Jul 13 06:02:07 PM PDT 24 |
| Finished | Jul 13 06:02:09 PM PDT 24 |
| Peak memory | 197368 kb |
| Host | smart-3f9320a6-e202-4761-bc1e-c3830a7abb42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043076992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4043076992 |
| Directory | /workspace/43.uart_loopback/latest |
| Test location | /workspace/coverage/default/43.uart_perf.3959448757 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 8276362291 ps |
| CPU time | 325.87 seconds |
| Started | Jul 13 06:02:06 PM PDT 24 |
| Finished | Jul 13 06:07:32 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-0d7400fd-281e-4b41-88f7-ad4eaae221a2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3959448757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3959448757 |
| Directory | /workspace/43.uart_perf/latest |
| Test location | /workspace/coverage/default/43.uart_rx_oversample.3477642283 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1596179164 ps |
| CPU time | 3.41 seconds |
| Started | Jul 13 06:02:01 PM PDT 24 |
| Finished | Jul 13 06:02:05 PM PDT 24 |
| Peak memory | 197840 kb |
| Host | smart-536d15ee-341c-4d26-8ff7-5087c046d9c5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3477642283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3477642283 |
| Directory | /workspace/43.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/43.uart_rx_start_bit_filter.1067337563 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 49919427706 ps |
| CPU time | 39.34 seconds |
| Started | Jul 13 06:02:07 PM PDT 24 |
| Finished | Jul 13 06:02:47 PM PDT 24 |
| Peak memory | 195716 kb |
| Host | smart-bd1b1a02-04c8-44f6-9dfa-59fc686a53c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067337563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1067337563 |
| Directory | /workspace/43.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/43.uart_smoke.586418764 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 918004410 ps |
| CPU time | 2.55 seconds |
| Started | Jul 13 06:01:59 PM PDT 24 |
| Finished | Jul 13 06:02:02 PM PDT 24 |
| Peak memory | 198832 kb |
| Host | smart-0875af0d-f50e-4812-a835-726a1f4a817c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586418764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.586418764 |
| Directory | /workspace/43.uart_smoke/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all.72631446 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 25965149848 ps |
| CPU time | 37.84 seconds |
| Started | Jul 13 06:02:07 PM PDT 24 |
| Finished | Jul 13 06:02:46 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-7e55b088-8407-40b4-a35d-69563cfa2709 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72631446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.72631446 |
| Directory | /workspace/43.uart_stress_all/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all_with_rand_reset.961178014 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 77790818934 ps |
| CPU time | 388.05 seconds |
| Started | Jul 13 06:02:07 PM PDT 24 |
| Finished | Jul 13 06:08:36 PM PDT 24 |
| Peak memory | 216432 kb |
| Host | smart-6bdad71f-8c81-4c63-962e-40c8770df9a5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961178014 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.961178014 |
| Directory | /workspace/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_tx_ovrd.1224601894 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 979713234 ps |
| CPU time | 2.76 seconds |
| Started | Jul 13 06:02:08 PM PDT 24 |
| Finished | Jul 13 06:02:11 PM PDT 24 |
| Peak memory | 199448 kb |
| Host | smart-8e44d038-b32d-4990-94a2-844ae91cbbb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224601894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1224601894 |
| Directory | /workspace/43.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/43.uart_tx_rx.1250343311 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 50210471363 ps |
| CPU time | 86.74 seconds |
| Started | Jul 13 06:02:03 PM PDT 24 |
| Finished | Jul 13 06:03:30 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-7ba6c6f9-15f7-4abb-b558-2be96871ac82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250343311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1250343311 |
| Directory | /workspace/43.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/44.uart_alert_test.1402002227 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 10803181 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 06:02:10 PM PDT 24 |
| Finished | Jul 13 06:02:11 PM PDT 24 |
| Peak memory | 194692 kb |
| Host | smart-384e1010-6854-4ae0-8e68-7dcf740ac839 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402002227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1402002227 |
| Directory | /workspace/44.uart_alert_test/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_full.1404331550 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 83740229204 ps |
| CPU time | 35.27 seconds |
| Started | Jul 13 06:02:09 PM PDT 24 |
| Finished | Jul 13 06:02:45 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-c2fddedd-0f8f-4c73-8d89-cb5d9fc27b39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404331550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1404331550 |
| Directory | /workspace/44.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_overflow.1022664368 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 32567715028 ps |
| CPU time | 18.41 seconds |
| Started | Jul 13 06:02:10 PM PDT 24 |
| Finished | Jul 13 06:02:29 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-a4433217-6c4f-4371-b51f-22ad51d7d04c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022664368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1022664368 |
| Directory | /workspace/44.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_reset.2462526854 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 85202676251 ps |
| CPU time | 127.59 seconds |
| Started | Jul 13 06:02:08 PM PDT 24 |
| Finished | Jul 13 06:04:17 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-793dac79-1e36-4bc2-a021-a0a82b1c572e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2462526854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2462526854 |
| Directory | /workspace/44.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/44.uart_intr.3850101990 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 21675089311 ps |
| CPU time | 9 seconds |
| Started | Jul 13 06:02:09 PM PDT 24 |
| Finished | Jul 13 06:02:19 PM PDT 24 |
| Peak memory | 199632 kb |
| Host | smart-0ca3c592-ff00-447c-8a9b-4f257e67c1f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850101990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3850101990 |
| Directory | /workspace/44.uart_intr/latest |
| Test location | /workspace/coverage/default/44.uart_long_xfer_wo_dly.2333688774 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 79423455695 ps |
| CPU time | 412.07 seconds |
| Started | Jul 13 06:02:09 PM PDT 24 |
| Finished | Jul 13 06:09:02 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-29c7a3f9-0988-486a-a2ef-c01d0f17b904 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2333688774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2333688774 |
| Directory | /workspace/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/44.uart_loopback.676835241 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4978415278 ps |
| CPU time | 11.16 seconds |
| Started | Jul 13 06:02:09 PM PDT 24 |
| Finished | Jul 13 06:02:21 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-8d011889-4db9-49e8-b0e7-136d985722ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676835241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.676835241 |
| Directory | /workspace/44.uart_loopback/latest |
| Test location | /workspace/coverage/default/44.uart_noise_filter.3341980976 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 140752067221 ps |
| CPU time | 328.45 seconds |
| Started | Jul 13 06:02:12 PM PDT 24 |
| Finished | Jul 13 06:07:41 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-c7b88172-094a-42cb-9a79-4a6e1fffaa90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341980976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3341980976 |
| Directory | /workspace/44.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/44.uart_perf.526596125 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 10282539775 ps |
| CPU time | 604.45 seconds |
| Started | Jul 13 06:02:12 PM PDT 24 |
| Finished | Jul 13 06:12:16 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-a084ee4f-bd15-4361-9a7c-506847954e3d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=526596125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.526596125 |
| Directory | /workspace/44.uart_perf/latest |
| Test location | /workspace/coverage/default/44.uart_rx_oversample.3823804380 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 2933892327 ps |
| CPU time | 20.78 seconds |
| Started | Jul 13 06:02:10 PM PDT 24 |
| Finished | Jul 13 06:02:31 PM PDT 24 |
| Peak memory | 198276 kb |
| Host | smart-dcbda307-883c-459f-871f-dfffd53dcf37 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3823804380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3823804380 |
| Directory | /workspace/44.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/44.uart_rx_parity_err.3327859856 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 58214653458 ps |
| CPU time | 55.25 seconds |
| Started | Jul 13 06:02:08 PM PDT 24 |
| Finished | Jul 13 06:03:04 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-cb157efa-c551-4ab0-a802-acf1a035407b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3327859856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3327859856 |
| Directory | /workspace/44.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/44.uart_rx_start_bit_filter.3723727727 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4381669918 ps |
| CPU time | 6.35 seconds |
| Started | Jul 13 06:02:06 PM PDT 24 |
| Finished | Jul 13 06:02:13 PM PDT 24 |
| Peak memory | 196176 kb |
| Host | smart-5c3ad4c7-6a6e-40b7-932f-f3d3996b8a3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723727727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3723727727 |
| Directory | /workspace/44.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/44.uart_smoke.2183188501 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1010975440 ps |
| CPU time | 2.02 seconds |
| Started | Jul 13 06:02:07 PM PDT 24 |
| Finished | Jul 13 06:02:09 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-c9d4b1d3-a945-4728-b7a3-bf8707627f44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183188501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2183188501 |
| Directory | /workspace/44.uart_smoke/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all.976677093 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 193970569753 ps |
| CPU time | 286.53 seconds |
| Started | Jul 13 06:02:08 PM PDT 24 |
| Finished | Jul 13 06:06:55 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-c437143e-20be-44ec-84be-bace74cbfb8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976677093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.976677093 |
| Directory | /workspace/44.uart_stress_all/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all_with_rand_reset.4047832730 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 243343846663 ps |
| CPU time | 780.8 seconds |
| Started | Jul 13 06:02:08 PM PDT 24 |
| Finished | Jul 13 06:15:09 PM PDT 24 |
| Peak memory | 224992 kb |
| Host | smart-5667e097-0bb9-4110-9deb-0b03bfac5287 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047832730 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.4047832730 |
| Directory | /workspace/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.uart_tx_ovrd.1968931706 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 952196149 ps |
| CPU time | 1.35 seconds |
| Started | Jul 13 06:02:06 PM PDT 24 |
| Finished | Jul 13 06:02:08 PM PDT 24 |
| Peak memory | 198260 kb |
| Host | smart-788e622f-b094-4952-add0-df0cd724cad2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968931706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1968931706 |
| Directory | /workspace/44.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/44.uart_tx_rx.2108849624 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 96430114399 ps |
| CPU time | 37.87 seconds |
| Started | Jul 13 06:02:07 PM PDT 24 |
| Finished | Jul 13 06:02:46 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-cf8507e2-9b6b-4413-8081-a446ff0833f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2108849624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2108849624 |
| Directory | /workspace/44.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/45.uart_alert_test.3490391359 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11862892 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 06:02:14 PM PDT 24 |
| Finished | Jul 13 06:02:15 PM PDT 24 |
| Peak memory | 193996 kb |
| Host | smart-a9b83194-4619-4791-9dc6-783e62ad28d3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490391359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3490391359 |
| Directory | /workspace/45.uart_alert_test/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_full.2825914468 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 34313244107 ps |
| CPU time | 12.38 seconds |
| Started | Jul 13 06:02:09 PM PDT 24 |
| Finished | Jul 13 06:02:22 PM PDT 24 |
| Peak memory | 199056 kb |
| Host | smart-ab7b4539-93a8-4438-85a6-fda6f4d538f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825914468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2825914468 |
| Directory | /workspace/45.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_overflow.3230259032 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 118405410635 ps |
| CPU time | 50.85 seconds |
| Started | Jul 13 06:02:10 PM PDT 24 |
| Finished | Jul 13 06:03:02 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-c27dc9f9-3fab-475b-ac36-9b5808d60d5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230259032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3230259032 |
| Directory | /workspace/45.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/45.uart_intr.1113513561 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 415122909125 ps |
| CPU time | 662.1 seconds |
| Started | Jul 13 06:02:15 PM PDT 24 |
| Finished | Jul 13 06:13:18 PM PDT 24 |
| Peak memory | 198956 kb |
| Host | smart-9c88801c-7b3a-4885-8656-ade5435f5405 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113513561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1113513561 |
| Directory | /workspace/45.uart_intr/latest |
| Test location | /workspace/coverage/default/45.uart_long_xfer_wo_dly.846248413 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 186334792035 ps |
| CPU time | 219.69 seconds |
| Started | Jul 13 06:02:15 PM PDT 24 |
| Finished | Jul 13 06:05:55 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-c814291f-cd8c-491f-8faa-7c98ecd922d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=846248413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.846248413 |
| Directory | /workspace/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/45.uart_loopback.1935122874 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 1215268348 ps |
| CPU time | 1.84 seconds |
| Started | Jul 13 06:02:15 PM PDT 24 |
| Finished | Jul 13 06:02:17 PM PDT 24 |
| Peak memory | 198684 kb |
| Host | smart-82adbf74-3353-49da-82c7-3ed0c9016bc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935122874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1935122874 |
| Directory | /workspace/45.uart_loopback/latest |
| Test location | /workspace/coverage/default/45.uart_noise_filter.949769009 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 123661104528 ps |
| CPU time | 61.29 seconds |
| Started | Jul 13 06:02:19 PM PDT 24 |
| Finished | Jul 13 06:03:21 PM PDT 24 |
| Peak memory | 208228 kb |
| Host | smart-da5b8e5f-dc99-4736-ba04-71cf0e54666a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949769009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.949769009 |
| Directory | /workspace/45.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/45.uart_perf.937297892 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 11565981602 ps |
| CPU time | 526.45 seconds |
| Started | Jul 13 06:02:19 PM PDT 24 |
| Finished | Jul 13 06:11:06 PM PDT 24 |
| Peak memory | 199008 kb |
| Host | smart-db94bdb5-0487-445c-9672-aa405368fd54 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=937297892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.937297892 |
| Directory | /workspace/45.uart_perf/latest |
| Test location | /workspace/coverage/default/45.uart_rx_oversample.2262904850 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5070033638 ps |
| CPU time | 10.03 seconds |
| Started | Jul 13 06:02:14 PM PDT 24 |
| Finished | Jul 13 06:02:25 PM PDT 24 |
| Peak memory | 198160 kb |
| Host | smart-20d802ab-dd23-4c38-ab3d-86d3047fdade |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2262904850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2262904850 |
| Directory | /workspace/45.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/45.uart_rx_parity_err.3595883894 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 70046697941 ps |
| CPU time | 53 seconds |
| Started | Jul 13 06:02:16 PM PDT 24 |
| Finished | Jul 13 06:03:09 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-d9332b85-73df-4222-8e38-d7f8c6fa34a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595883894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3595883894 |
| Directory | /workspace/45.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/45.uart_rx_start_bit_filter.3482209752 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 42710154294 ps |
| CPU time | 15.33 seconds |
| Started | Jul 13 06:02:19 PM PDT 24 |
| Finished | Jul 13 06:02:35 PM PDT 24 |
| Peak memory | 196332 kb |
| Host | smart-78c9f09a-dcb7-4041-aa21-c737816776f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482209752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3482209752 |
| Directory | /workspace/45.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/45.uart_smoke.4037763040 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 558258276 ps |
| CPU time | 1.31 seconds |
| Started | Jul 13 06:02:07 PM PDT 24 |
| Finished | Jul 13 06:02:09 PM PDT 24 |
| Peak memory | 198976 kb |
| Host | smart-1346bc23-3158-4c00-9a08-c8e3cbbb8ef2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037763040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.4037763040 |
| Directory | /workspace/45.uart_smoke/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all.108650645 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 288650973813 ps |
| CPU time | 822.79 seconds |
| Started | Jul 13 06:02:17 PM PDT 24 |
| Finished | Jul 13 06:16:00 PM PDT 24 |
| Peak memory | 216144 kb |
| Host | smart-c6d3a0d8-aaea-453b-a646-f0bcbd2a7f0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108650645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.108650645 |
| Directory | /workspace/45.uart_stress_all/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2380841461 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 153823973272 ps |
| CPU time | 1278.72 seconds |
| Started | Jul 13 06:02:16 PM PDT 24 |
| Finished | Jul 13 06:23:35 PM PDT 24 |
| Peak memory | 224656 kb |
| Host | smart-77fb75ec-b83e-48dd-8257-a7e3acbb69fb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380841461 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2380841461 |
| Directory | /workspace/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.uart_tx_ovrd.191746259 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 2079828773 ps |
| CPU time | 2.43 seconds |
| Started | Jul 13 06:02:19 PM PDT 24 |
| Finished | Jul 13 06:02:22 PM PDT 24 |
| Peak memory | 197760 kb |
| Host | smart-6b95d59f-cf58-4430-9cb6-2dc2cdbea7d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191746259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.191746259 |
| Directory | /workspace/45.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/45.uart_tx_rx.445741526 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 19929625800 ps |
| CPU time | 8.22 seconds |
| Started | Jul 13 06:02:08 PM PDT 24 |
| Finished | Jul 13 06:02:18 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-528cf223-4144-414a-848f-fb06eb433d40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445741526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.445741526 |
| Directory | /workspace/45.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/46.uart_alert_test.3575299984 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 31406677 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 06:02:28 PM PDT 24 |
| Finished | Jul 13 06:02:30 PM PDT 24 |
| Peak memory | 195168 kb |
| Host | smart-cee38ea2-df6b-4705-bef9-feb9942d7cc8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575299984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3575299984 |
| Directory | /workspace/46.uart_alert_test/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_full.2901464056 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 35727316059 ps |
| CPU time | 62.69 seconds |
| Started | Jul 13 06:02:16 PM PDT 24 |
| Finished | Jul 13 06:03:19 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-941963a1-d237-4114-88f4-bc56831e55b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901464056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2901464056 |
| Directory | /workspace/46.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_overflow.1612759425 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 158571426128 ps |
| CPU time | 232.95 seconds |
| Started | Jul 13 06:02:13 PM PDT 24 |
| Finished | Jul 13 06:06:07 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-c8428dff-0c65-4aba-9cbc-83aa414cebe0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612759425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1612759425 |
| Directory | /workspace/46.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/46.uart_intr.2525245072 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 34991164477 ps |
| CPU time | 16.02 seconds |
| Started | Jul 13 06:02:14 PM PDT 24 |
| Finished | Jul 13 06:02:31 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-49986f52-9073-4617-8637-5cd708167fb3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525245072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2525245072 |
| Directory | /workspace/46.uart_intr/latest |
| Test location | /workspace/coverage/default/46.uart_long_xfer_wo_dly.2685703018 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 197246057630 ps |
| CPU time | 671.29 seconds |
| Started | Jul 13 06:02:22 PM PDT 24 |
| Finished | Jul 13 06:13:34 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-a0e45fd6-34d0-4fa6-8d33-9b6f2434033f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2685703018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2685703018 |
| Directory | /workspace/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/46.uart_loopback.3998806468 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3196106532 ps |
| CPU time | 2.49 seconds |
| Started | Jul 13 06:02:23 PM PDT 24 |
| Finished | Jul 13 06:02:26 PM PDT 24 |
| Peak memory | 198824 kb |
| Host | smart-18e2116a-e3ae-4ab5-8b03-780876018779 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998806468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3998806468 |
| Directory | /workspace/46.uart_loopback/latest |
| Test location | /workspace/coverage/default/46.uart_noise_filter.74195691 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 45608488991 ps |
| CPU time | 44.85 seconds |
| Started | Jul 13 06:02:15 PM PDT 24 |
| Finished | Jul 13 06:03:01 PM PDT 24 |
| Peak memory | 200052 kb |
| Host | smart-6c96e193-caf1-4baf-98ff-238654b1d983 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74195691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.74195691 |
| Directory | /workspace/46.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/46.uart_perf.2911785908 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 18331946603 ps |
| CPU time | 225.22 seconds |
| Started | Jul 13 06:02:24 PM PDT 24 |
| Finished | Jul 13 06:06:09 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-a25dd162-a1e1-40d2-bcad-b2238ce49a5a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2911785908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2911785908 |
| Directory | /workspace/46.uart_perf/latest |
| Test location | /workspace/coverage/default/46.uart_rx_oversample.3804681982 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 6964865208 ps |
| CPU time | 14.61 seconds |
| Started | Jul 13 06:02:15 PM PDT 24 |
| Finished | Jul 13 06:02:30 PM PDT 24 |
| Peak memory | 198816 kb |
| Host | smart-27cd7405-8d82-448a-a881-33c3fdf82594 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3804681982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3804681982 |
| Directory | /workspace/46.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/46.uart_rx_parity_err.3869807764 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 293349425311 ps |
| CPU time | 101.09 seconds |
| Started | Jul 13 06:02:24 PM PDT 24 |
| Finished | Jul 13 06:04:05 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-53e43a88-6eff-4cc9-87b6-12bdd51938eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869807764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3869807764 |
| Directory | /workspace/46.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/46.uart_rx_start_bit_filter.1153598503 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 3141477434 ps |
| CPU time | 1.91 seconds |
| Started | Jul 13 06:02:14 PM PDT 24 |
| Finished | Jul 13 06:02:16 PM PDT 24 |
| Peak memory | 195876 kb |
| Host | smart-79e63539-06dd-4b14-9ff0-cd75999e4d87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153598503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1153598503 |
| Directory | /workspace/46.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/46.uart_smoke.920619985 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 507393311 ps |
| CPU time | 1.01 seconds |
| Started | Jul 13 06:02:14 PM PDT 24 |
| Finished | Jul 13 06:02:15 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-180bec51-9d5b-4031-922e-73bff219ae2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920619985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.920619985 |
| Directory | /workspace/46.uart_smoke/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all.678214967 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 146881340359 ps |
| CPU time | 1429.17 seconds |
| Started | Jul 13 06:02:29 PM PDT 24 |
| Finished | Jul 13 06:26:19 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-e1c17c7f-f015-4b53-a185-88cc97d5bd9d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678214967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.678214967 |
| Directory | /workspace/46.uart_stress_all/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1704816455 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 78677682877 ps |
| CPU time | 679.61 seconds |
| Started | Jul 13 06:02:23 PM PDT 24 |
| Finished | Jul 13 06:13:43 PM PDT 24 |
| Peak memory | 224756 kb |
| Host | smart-28b59414-e7a8-45ce-aa0f-e534ca3d5836 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704816455 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1704816455 |
| Directory | /workspace/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.uart_tx_ovrd.832811725 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 6214092284 ps |
| CPU time | 1.52 seconds |
| Started | Jul 13 06:02:23 PM PDT 24 |
| Finished | Jul 13 06:02:25 PM PDT 24 |
| Peak memory | 198624 kb |
| Host | smart-ca9a1ccb-424f-46fd-8755-5cb1e43ea40e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832811725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.832811725 |
| Directory | /workspace/46.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/46.uart_tx_rx.870178824 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 38289590087 ps |
| CPU time | 72.91 seconds |
| Started | Jul 13 06:02:15 PM PDT 24 |
| Finished | Jul 13 06:03:28 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-95aad907-4946-4449-9e25-958b7cb9ace6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870178824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.870178824 |
| Directory | /workspace/46.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/47.uart_alert_test.2042589852 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 22564278 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 06:02:32 PM PDT 24 |
| Finished | Jul 13 06:02:33 PM PDT 24 |
| Peak memory | 195524 kb |
| Host | smart-f0fef160-cb67-4fc4-8ef9-ff8ad1c5a77a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042589852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2042589852 |
| Directory | /workspace/47.uart_alert_test/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_full.243974089 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 19613671902 ps |
| CPU time | 31.05 seconds |
| Started | Jul 13 06:02:29 PM PDT 24 |
| Finished | Jul 13 06:03:00 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-e8d771d8-d993-462f-b67f-fb8eaa7944cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243974089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.243974089 |
| Directory | /workspace/47.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_overflow.676451004 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 104926488725 ps |
| CPU time | 167 seconds |
| Started | Jul 13 06:02:23 PM PDT 24 |
| Finished | Jul 13 06:05:11 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-786bafdd-3f8e-403a-af2a-24e312bb7a7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676451004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.676451004 |
| Directory | /workspace/47.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_reset.2811616996 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 91464449016 ps |
| CPU time | 68.01 seconds |
| Started | Jul 13 06:02:23 PM PDT 24 |
| Finished | Jul 13 06:03:31 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-aa719192-d55f-44ba-9f12-912ef455c374 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811616996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2811616996 |
| Directory | /workspace/47.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/47.uart_intr.1618001439 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 106238939155 ps |
| CPU time | 69.2 seconds |
| Started | Jul 13 06:02:22 PM PDT 24 |
| Finished | Jul 13 06:03:32 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-789f429f-b036-4283-bc32-445b659d520c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618001439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1618001439 |
| Directory | /workspace/47.uart_intr/latest |
| Test location | /workspace/coverage/default/47.uart_long_xfer_wo_dly.122691255 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 104620534418 ps |
| CPU time | 503.51 seconds |
| Started | Jul 13 06:02:33 PM PDT 24 |
| Finished | Jul 13 06:10:57 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-a57ade15-9cbc-4793-b19d-aac5c5ab9744 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=122691255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.122691255 |
| Directory | /workspace/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/47.uart_loopback.4290078788 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2789202271 ps |
| CPU time | 5.04 seconds |
| Started | Jul 13 06:02:32 PM PDT 24 |
| Finished | Jul 13 06:02:38 PM PDT 24 |
| Peak memory | 197392 kb |
| Host | smart-94d927df-ace7-4c45-90ef-a1defe670105 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290078788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.4290078788 |
| Directory | /workspace/47.uart_loopback/latest |
| Test location | /workspace/coverage/default/47.uart_noise_filter.3685810280 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 17616276878 ps |
| CPU time | 29.5 seconds |
| Started | Jul 13 06:02:33 PM PDT 24 |
| Finished | Jul 13 06:03:03 PM PDT 24 |
| Peak memory | 196244 kb |
| Host | smart-51662a9e-5ca0-48cc-8507-5b4dc999be4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685810280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3685810280 |
| Directory | /workspace/47.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/47.uart_perf.425692763 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 28061598871 ps |
| CPU time | 86.37 seconds |
| Started | Jul 13 06:02:31 PM PDT 24 |
| Finished | Jul 13 06:03:57 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-5bb45e7a-6a95-4c58-98d3-1332e8496160 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=425692763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.425692763 |
| Directory | /workspace/47.uart_perf/latest |
| Test location | /workspace/coverage/default/47.uart_rx_oversample.272804453 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3734487459 ps |
| CPU time | 7.19 seconds |
| Started | Jul 13 06:02:23 PM PDT 24 |
| Finished | Jul 13 06:02:31 PM PDT 24 |
| Peak memory | 198056 kb |
| Host | smart-e2717649-0a86-42c4-8245-93f66bb68962 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=272804453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.272804453 |
| Directory | /workspace/47.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/47.uart_rx_parity_err.774916082 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 43490986641 ps |
| CPU time | 37.51 seconds |
| Started | Jul 13 06:02:32 PM PDT 24 |
| Finished | Jul 13 06:03:10 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-8595ad9a-fcbf-408d-8c31-43ceabe5342d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=774916082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.774916082 |
| Directory | /workspace/47.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/47.uart_rx_start_bit_filter.3765405324 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1890298364 ps |
| CPU time | 3.12 seconds |
| Started | Jul 13 06:02:33 PM PDT 24 |
| Finished | Jul 13 06:02:37 PM PDT 24 |
| Peak memory | 195172 kb |
| Host | smart-f87fab19-7270-4cf0-820c-2afb6f248ca9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765405324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3765405324 |
| Directory | /workspace/47.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/47.uart_smoke.243272873 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 532385530 ps |
| CPU time | 1.48 seconds |
| Started | Jul 13 06:02:22 PM PDT 24 |
| Finished | Jul 13 06:02:24 PM PDT 24 |
| Peak memory | 198156 kb |
| Host | smart-67d34273-d118-482f-a52f-e44bc248208b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243272873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.243272873 |
| Directory | /workspace/47.uart_smoke/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all.1551084363 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 261899656681 ps |
| CPU time | 1727.44 seconds |
| Started | Jul 13 06:02:32 PM PDT 24 |
| Finished | Jul 13 06:31:20 PM PDT 24 |
| Peak memory | 208236 kb |
| Host | smart-4992f2b8-4576-40da-9144-ac121682db5a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551084363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1551084363 |
| Directory | /workspace/47.uart_stress_all/latest |
| Test location | /workspace/coverage/default/47.uart_tx_ovrd.98228245 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1530535971 ps |
| CPU time | 2.4 seconds |
| Started | Jul 13 06:02:32 PM PDT 24 |
| Finished | Jul 13 06:02:35 PM PDT 24 |
| Peak memory | 198236 kb |
| Host | smart-287dadff-7ce7-4047-9497-bd369e8973b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98228245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.98228245 |
| Directory | /workspace/47.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/47.uart_tx_rx.3350063795 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 127681085277 ps |
| CPU time | 47.89 seconds |
| Started | Jul 13 06:02:23 PM PDT 24 |
| Finished | Jul 13 06:03:12 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-890a933a-c0ac-4687-a7cf-195d58f3378f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350063795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3350063795 |
| Directory | /workspace/47.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/48.uart_alert_test.2055413929 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 38430730 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 06:02:42 PM PDT 24 |
| Finished | Jul 13 06:02:43 PM PDT 24 |
| Peak memory | 195188 kb |
| Host | smart-f3bf538a-6069-4652-a559-11c4cd91cd9c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055413929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2055413929 |
| Directory | /workspace/48.uart_alert_test/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_full.4209809878 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 159725764585 ps |
| CPU time | 146.29 seconds |
| Started | Jul 13 06:02:33 PM PDT 24 |
| Finished | Jul 13 06:05:00 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-80cd2926-01b2-4826-bd5d-38d8c9708615 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209809878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.4209809878 |
| Directory | /workspace/48.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_overflow.3809011593 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 170871618341 ps |
| CPU time | 253 seconds |
| Started | Jul 13 06:02:32 PM PDT 24 |
| Finished | Jul 13 06:06:45 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-508f3ca2-1a51-4450-839f-eb265c91f538 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809011593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3809011593 |
| Directory | /workspace/48.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_reset.3854129849 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 54663406758 ps |
| CPU time | 22.74 seconds |
| Started | Jul 13 06:02:33 PM PDT 24 |
| Finished | Jul 13 06:02:56 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-aac8d203-d224-4935-a043-0345d80a7ad6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854129849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3854129849 |
| Directory | /workspace/48.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/48.uart_intr.1581913834 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 184713024155 ps |
| CPU time | 249.04 seconds |
| Started | Jul 13 06:02:33 PM PDT 24 |
| Finished | Jul 13 06:06:43 PM PDT 24 |
| Peak memory | 198232 kb |
| Host | smart-71eea64e-0960-42c2-a102-4a0520c5c3b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581913834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1581913834 |
| Directory | /workspace/48.uart_intr/latest |
| Test location | /workspace/coverage/default/48.uart_long_xfer_wo_dly.3444404906 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 237452581915 ps |
| CPU time | 207.47 seconds |
| Started | Jul 13 06:02:39 PM PDT 24 |
| Finished | Jul 13 06:06:07 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-17b4f391-a6ad-49ee-aab9-e0f6491e0ea6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3444404906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3444404906 |
| Directory | /workspace/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/48.uart_loopback.3055600987 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1396543791 ps |
| CPU time | 4.13 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:02:44 PM PDT 24 |
| Peak memory | 198280 kb |
| Host | smart-d95e03f1-d093-4a6e-8e0b-2aa524e5fb40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055600987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3055600987 |
| Directory | /workspace/48.uart_loopback/latest |
| Test location | /workspace/coverage/default/48.uart_noise_filter.285177536 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 249912959480 ps |
| CPU time | 49.06 seconds |
| Started | Jul 13 06:02:32 PM PDT 24 |
| Finished | Jul 13 06:03:22 PM PDT 24 |
| Peak memory | 208356 kb |
| Host | smart-c13d692b-aa32-4b50-9832-10aec2f8471c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=285177536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.285177536 |
| Directory | /workspace/48.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/48.uart_perf.3690295029 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 28869006974 ps |
| CPU time | 412.41 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:09:33 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-1cf6dca3-0897-49a1-8666-8aac427736c4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3690295029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3690295029 |
| Directory | /workspace/48.uart_perf/latest |
| Test location | /workspace/coverage/default/48.uart_rx_oversample.1673030857 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 6157221945 ps |
| CPU time | 28.24 seconds |
| Started | Jul 13 06:02:31 PM PDT 24 |
| Finished | Jul 13 06:03:00 PM PDT 24 |
| Peak memory | 198244 kb |
| Host | smart-81ebdd7d-a729-474d-a007-ed4bd9d6477d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1673030857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1673030857 |
| Directory | /workspace/48.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/48.uart_rx_parity_err.2501241533 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 8635404847 ps |
| CPU time | 11.58 seconds |
| Started | Jul 13 06:02:31 PM PDT 24 |
| Finished | Jul 13 06:02:43 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-6228887d-f603-45cd-a430-13bde818d0ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501241533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2501241533 |
| Directory | /workspace/48.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/48.uart_rx_start_bit_filter.1762722619 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 38382736414 ps |
| CPU time | 8.14 seconds |
| Started | Jul 13 06:02:32 PM PDT 24 |
| Finished | Jul 13 06:02:41 PM PDT 24 |
| Peak memory | 195864 kb |
| Host | smart-4db2e216-fe79-402b-9452-7b681f5cac80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762722619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1762722619 |
| Directory | /workspace/48.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/48.uart_smoke.3342857085 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5484417846 ps |
| CPU time | 21.84 seconds |
| Started | Jul 13 06:02:31 PM PDT 24 |
| Finished | Jul 13 06:02:54 PM PDT 24 |
| Peak memory | 199188 kb |
| Host | smart-0d1a2a34-290e-4c09-94cb-36fbb92a187b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342857085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3342857085 |
| Directory | /workspace/48.uart_smoke/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1703534929 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 37607731408 ps |
| CPU time | 253.75 seconds |
| Started | Jul 13 06:02:41 PM PDT 24 |
| Finished | Jul 13 06:06:55 PM PDT 24 |
| Peak memory | 213820 kb |
| Host | smart-02ac9cfa-ea5f-455d-b107-a239fb2fd2e9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703534929 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1703534929 |
| Directory | /workspace/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.uart_tx_ovrd.2332265674 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1239409381 ps |
| CPU time | 2.19 seconds |
| Started | Jul 13 06:02:48 PM PDT 24 |
| Finished | Jul 13 06:02:50 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-b083730e-9d74-4955-b119-6ea028ab8b3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332265674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2332265674 |
| Directory | /workspace/48.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/48.uart_tx_rx.471999585 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 153531873855 ps |
| CPU time | 14.64 seconds |
| Started | Jul 13 06:02:33 PM PDT 24 |
| Finished | Jul 13 06:02:49 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-ad7eefda-df5d-45ef-8605-2e1965a64d6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471999585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.471999585 |
| Directory | /workspace/48.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/49.uart_alert_test.3233512647 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 12219206 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:02:52 PM PDT 24 |
| Peak memory | 195524 kb |
| Host | smart-78304215-c6f4-45b6-8c0e-57830d5ab2b8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233512647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3233512647 |
| Directory | /workspace/49.uart_alert_test/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_full.654007190 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 63272880657 ps |
| CPU time | 29.55 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:03:10 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-06de0e2e-64ad-42c1-bd5b-ac0426c48d0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654007190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.654007190 |
| Directory | /workspace/49.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_overflow.1062377117 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 87441493608 ps |
| CPU time | 39.54 seconds |
| Started | Jul 13 06:02:39 PM PDT 24 |
| Finished | Jul 13 06:03:19 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-b90e6e4a-872e-4a39-a9f8-1f310e686577 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062377117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1062377117 |
| Directory | /workspace/49.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_reset.3215098209 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 68176553347 ps |
| CPU time | 28.63 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:03:09 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-d7fc3fcd-ad5a-4dfc-bc82-11025cfb6eac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215098209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3215098209 |
| Directory | /workspace/49.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/49.uart_intr.880564278 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 35290336870 ps |
| CPU time | 30.38 seconds |
| Started | Jul 13 06:02:41 PM PDT 24 |
| Finished | Jul 13 06:03:12 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-30ff9544-84b9-444e-bc8d-8672a1a7bebc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880564278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.880564278 |
| Directory | /workspace/49.uart_intr/latest |
| Test location | /workspace/coverage/default/49.uart_long_xfer_wo_dly.3463999306 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 114699598390 ps |
| CPU time | 265.14 seconds |
| Started | Jul 13 06:02:39 PM PDT 24 |
| Finished | Jul 13 06:07:04 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-e6c739f3-b47e-43f0-8431-8a57a8eadb15 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3463999306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3463999306 |
| Directory | /workspace/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/49.uart_loopback.2327751392 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 4373216010 ps |
| CPU time | 9.38 seconds |
| Started | Jul 13 06:02:38 PM PDT 24 |
| Finished | Jul 13 06:02:48 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-1116ba72-58ce-4b16-b431-68eba57173ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2327751392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2327751392 |
| Directory | /workspace/49.uart_loopback/latest |
| Test location | /workspace/coverage/default/49.uart_noise_filter.3910189877 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 39311743781 ps |
| CPU time | 16.24 seconds |
| Started | Jul 13 06:02:39 PM PDT 24 |
| Finished | Jul 13 06:02:56 PM PDT 24 |
| Peak memory | 196876 kb |
| Host | smart-2fd9c5cb-4a6e-468b-b6fd-c0a26c18dd59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3910189877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3910189877 |
| Directory | /workspace/49.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/49.uart_perf.86591115 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 7977703863 ps |
| CPU time | 144.69 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:05:05 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-03b59abd-c82d-4bd8-b9a1-6415f006c809 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=86591115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.86591115 |
| Directory | /workspace/49.uart_perf/latest |
| Test location | /workspace/coverage/default/49.uart_rx_oversample.137295409 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 4294819076 ps |
| CPU time | 8.46 seconds |
| Started | Jul 13 06:02:43 PM PDT 24 |
| Finished | Jul 13 06:02:51 PM PDT 24 |
| Peak memory | 198328 kb |
| Host | smart-a3ec04fd-1736-4124-acab-7e3cacf2102d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=137295409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.137295409 |
| Directory | /workspace/49.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/49.uart_rx_parity_err.502738387 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 100834434194 ps |
| CPU time | 152.91 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:05:13 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-3ca3f719-2c9e-4244-be34-c63469abb577 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502738387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.502738387 |
| Directory | /workspace/49.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/49.uart_rx_start_bit_filter.3197101631 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 37997498856 ps |
| CPU time | 48.02 seconds |
| Started | Jul 13 06:02:39 PM PDT 24 |
| Finished | Jul 13 06:03:28 PM PDT 24 |
| Peak memory | 195620 kb |
| Host | smart-ec7d3024-2437-4db5-97ff-18fd1eb2e915 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197101631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3197101631 |
| Directory | /workspace/49.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/49.uart_smoke.725904848 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 5354349235 ps |
| CPU time | 11.68 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:02:52 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-826de02b-c5bd-4e2c-9085-c2bb079d2092 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725904848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.725904848 |
| Directory | /workspace/49.uart_smoke/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all.3380141256 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 187813298197 ps |
| CPU time | 488.29 seconds |
| Started | Jul 13 06:02:41 PM PDT 24 |
| Finished | Jul 13 06:10:50 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-37d250fd-bcc5-48f1-a518-9950160bcf06 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380141256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3380141256 |
| Directory | /workspace/49.uart_stress_all/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3708322659 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 171300029014 ps |
| CPU time | 481.46 seconds |
| Started | Jul 13 06:02:40 PM PDT 24 |
| Finished | Jul 13 06:10:42 PM PDT 24 |
| Peak memory | 216476 kb |
| Host | smart-4f2f6ef6-df1d-4c80-bf39-7de57e4e7c75 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708322659 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3708322659 |
| Directory | /workspace/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.uart_tx_ovrd.1385838774 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 715893396 ps |
| CPU time | 2.27 seconds |
| Started | Jul 13 06:02:41 PM PDT 24 |
| Finished | Jul 13 06:02:44 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-e0a60763-dd46-4d4f-96d0-eb824e79cfea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385838774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1385838774 |
| Directory | /workspace/49.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/49.uart_tx_rx.469091424 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 97412326889 ps |
| CPU time | 441.06 seconds |
| Started | Jul 13 06:02:41 PM PDT 24 |
| Finished | Jul 13 06:10:02 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-b5562c33-e2e9-4369-b13b-3742f6f07148 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=469091424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.469091424 |
| Directory | /workspace/49.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/5.uart_alert_test.2948538605 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 13027900 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 05:58:58 PM PDT 24 |
| Peak memory | 195240 kb |
| Host | smart-24e97aa6-c08d-4c77-ad61-1afaec1492f4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948538605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2948538605 |
| Directory | /workspace/5.uart_alert_test/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_full.2270756210 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 115959209821 ps |
| CPU time | 43.89 seconds |
| Started | Jul 13 05:59:02 PM PDT 24 |
| Finished | Jul 13 05:59:47 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-1fc601b7-e3fc-49a8-9718-7d77ca542a1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270756210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2270756210 |
| Directory | /workspace/5.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_overflow.1027869788 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 155857436743 ps |
| CPU time | 269.47 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 06:03:27 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-97c2b1e4-c83e-4362-9540-d8ba3057d7f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027869788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1027869788 |
| Directory | /workspace/5.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_reset.926242812 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 112892709132 ps |
| CPU time | 31.35 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 05:59:29 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-548ce524-1b63-46e8-9067-461e27e1b439 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926242812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.926242812 |
| Directory | /workspace/5.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/5.uart_intr.254552657 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 81408123837 ps |
| CPU time | 18.94 seconds |
| Started | Jul 13 05:58:55 PM PDT 24 |
| Finished | Jul 13 05:59:15 PM PDT 24 |
| Peak memory | 196800 kb |
| Host | smart-f19297a0-ed59-43ca-9dba-1d10c93fcc62 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254552657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.254552657 |
| Directory | /workspace/5.uart_intr/latest |
| Test location | /workspace/coverage/default/5.uart_long_xfer_wo_dly.4231392573 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 83415791691 ps |
| CPU time | 131.83 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 06:01:05 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-994149ff-e3e4-4bba-80bb-98ccc584ae5b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4231392573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4231392573 |
| Directory | /workspace/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/5.uart_loopback.3708168665 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6033573705 ps |
| CPU time | 12.44 seconds |
| Started | Jul 13 05:58:53 PM PDT 24 |
| Finished | Jul 13 05:59:06 PM PDT 24 |
| Peak memory | 199252 kb |
| Host | smart-620b4de6-bbcf-41b6-bca1-e06d5ee9e9e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708168665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3708168665 |
| Directory | /workspace/5.uart_loopback/latest |
| Test location | /workspace/coverage/default/5.uart_noise_filter.2281684874 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 152113157648 ps |
| CPU time | 18.29 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 05:59:16 PM PDT 24 |
| Peak memory | 200108 kb |
| Host | smart-928c3f69-edbf-4174-9841-3bfd203ea629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281684874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2281684874 |
| Directory | /workspace/5.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/5.uart_perf.828377331 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 9418257265 ps |
| CPU time | 37.59 seconds |
| Started | Jul 13 05:58:54 PM PDT 24 |
| Finished | Jul 13 05:59:33 PM PDT 24 |
| Peak memory | 200068 kb |
| Host | smart-f51f91f7-eec0-47de-be7e-b6daa7fcb8d4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=828377331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.828377331 |
| Directory | /workspace/5.uart_perf/latest |
| Test location | /workspace/coverage/default/5.uart_rx_oversample.889866493 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2310319604 ps |
| CPU time | 7.92 seconds |
| Started | Jul 13 05:58:54 PM PDT 24 |
| Finished | Jul 13 05:59:02 PM PDT 24 |
| Peak memory | 198160 kb |
| Host | smart-69f2b0d2-83ba-4e71-86c8-3b2dc4b4d2d9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=889866493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.889866493 |
| Directory | /workspace/5.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/5.uart_rx_parity_err.1586871428 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 163422961806 ps |
| CPU time | 436.95 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 06:06:15 PM PDT 24 |
| Peak memory | 199148 kb |
| Host | smart-4cdc02b7-c3f5-45a0-8fbc-25f8cda0138a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586871428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1586871428 |
| Directory | /workspace/5.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/5.uart_rx_start_bit_filter.2708909066 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4308857606 ps |
| CPU time | 1.36 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 05:58:59 PM PDT 24 |
| Peak memory | 196708 kb |
| Host | smart-890356c4-b374-48e7-b5da-4e4d812862ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708909066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2708909066 |
| Directory | /workspace/5.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/5.uart_smoke.2110626534 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 654369230 ps |
| CPU time | 1.94 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 05:58:55 PM PDT 24 |
| Peak memory | 198404 kb |
| Host | smart-3f433600-82d1-4a31-9018-f9eb6a35e7ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110626534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2110626534 |
| Directory | /workspace/5.uart_smoke/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all_with_rand_reset.4202082267 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 249072878857 ps |
| CPU time | 1122.74 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 06:17:41 PM PDT 24 |
| Peak memory | 215568 kb |
| Host | smart-8a59adaf-121c-40ba-a714-724a0fbc77e0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202082267 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.4202082267 |
| Directory | /workspace/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.uart_tx_ovrd.3240389888 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 6789554769 ps |
| CPU time | 9.34 seconds |
| Started | Jul 13 05:58:56 PM PDT 24 |
| Finished | Jul 13 05:59:06 PM PDT 24 |
| Peak memory | 199436 kb |
| Host | smart-211809a3-4ce0-48f8-bec1-040701628e03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240389888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3240389888 |
| Directory | /workspace/5.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/5.uart_tx_rx.449677214 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 85836885409 ps |
| CPU time | 38.91 seconds |
| Started | Jul 13 05:58:59 PM PDT 24 |
| Finished | Jul 13 05:59:38 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-b432d034-ebdf-46cf-a0df-a606387f3bb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=449677214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.449677214 |
| Directory | /workspace/5.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/50.uart_fifo_reset.1961431294 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 26963781139 ps |
| CPU time | 10.63 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:03:02 PM PDT 24 |
| Peak memory | 199940 kb |
| Host | smart-0986d818-81b2-4696-a5dd-0bba1d5cf4e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1961431294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1961431294 |
| Directory | /workspace/50.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1971300916 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 50307947925 ps |
| CPU time | 438.13 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:10:10 PM PDT 24 |
| Peak memory | 224744 kb |
| Host | smart-748a69bb-6e55-4174-8a81-d0a8ac31d4b1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971300916 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1971300916 |
| Directory | /workspace/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/51.uart_fifo_reset.2927118690 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 123017920502 ps |
| CPU time | 45.89 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:03:36 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-7e77c816-490c-4a8f-b1bd-7fe95cdfc22c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2927118690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2927118690 |
| Directory | /workspace/51.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/52.uart_fifo_reset.4183440414 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5302713215 ps |
| CPU time | 7.25 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:02:58 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-30d16618-e4a4-479e-8066-40c09c5bac0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183440414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4183440414 |
| Directory | /workspace/52.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2832122149 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 25460425864 ps |
| CPU time | 379.96 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:09:11 PM PDT 24 |
| Peak memory | 215684 kb |
| Host | smart-7219235f-1ab8-4f08-8c18-384176cc8332 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832122149 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2832122149 |
| Directory | /workspace/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/54.uart_fifo_reset.3783266114 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 18131075033 ps |
| CPU time | 25.37 seconds |
| Started | Jul 13 06:02:49 PM PDT 24 |
| Finished | Jul 13 06:03:15 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-ff345aad-2451-402c-a2ac-1a858c455dc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783266114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3783266114 |
| Directory | /workspace/54.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/54.uart_stress_all_with_rand_reset.996803006 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2355430630636 ps |
| CPU time | 1898.48 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:34:30 PM PDT 24 |
| Peak memory | 228556 kb |
| Host | smart-f1ea4c66-f043-45f0-b731-4a563458bd74 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996803006 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.996803006 |
| Directory | /workspace/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/55.uart_fifo_reset.1730868447 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 220614343353 ps |
| CPU time | 472.84 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:10:44 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-f42506bf-a6ec-4e2e-9fd3-bd037e83f760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730868447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1730868447 |
| Directory | /workspace/55.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/56.uart_fifo_reset.3686209197 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 45658493007 ps |
| CPU time | 20.04 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:03:12 PM PDT 24 |
| Peak memory | 199664 kb |
| Host | smart-c23d749e-e3ef-4579-9307-6f05e6fd01ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686209197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3686209197 |
| Directory | /workspace/56.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3976678684 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 34890536526 ps |
| CPU time | 237.07 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:06:48 PM PDT 24 |
| Peak memory | 215876 kb |
| Host | smart-bd407d3d-1dc2-4f50-b8fd-f5021481cec4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976678684 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3976678684 |
| Directory | /workspace/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/57.uart_fifo_reset.3627856240 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 204044893245 ps |
| CPU time | 87.84 seconds |
| Started | Jul 13 06:02:50 PM PDT 24 |
| Finished | Jul 13 06:04:19 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-60db532f-7b2e-4d0f-8812-de82b810fd6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627856240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3627856240 |
| Directory | /workspace/57.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2389990585 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 11382208315 ps |
| CPU time | 169.65 seconds |
| Started | Jul 13 06:02:49 PM PDT 24 |
| Finished | Jul 13 06:05:39 PM PDT 24 |
| Peak memory | 209612 kb |
| Host | smart-b16a2bbd-33d8-40a0-953b-82099c1d6f1d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389990585 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2389990585 |
| Directory | /workspace/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/58.uart_fifo_reset.4180496603 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 106602921796 ps |
| CPU time | 170.1 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:05:42 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-6e1ce3d9-6eee-4f92-81ad-6ad5bde0e576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180496603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4180496603 |
| Directory | /workspace/58.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2395915520 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 44189842625 ps |
| CPU time | 174.63 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:05:46 PM PDT 24 |
| Peak memory | 216372 kb |
| Host | smart-b9dc0372-cd7f-4326-aba7-06ba148ac688 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395915520 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2395915520 |
| Directory | /workspace/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/59.uart_fifo_reset.2066329924 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 36375341915 ps |
| CPU time | 15.42 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:03:07 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-b286a48e-deb4-4b30-b473-c323c83d27fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2066329924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2066329924 |
| Directory | /workspace/59.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3959438169 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 10882111606 ps |
| CPU time | 60.76 seconds |
| Started | Jul 13 06:02:51 PM PDT 24 |
| Finished | Jul 13 06:03:53 PM PDT 24 |
| Peak memory | 215480 kb |
| Host | smart-f5a55bc5-7916-4aa9-b172-006d9a0f6b8f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959438169 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3959438169 |
| Directory | /workspace/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_alert_test.3426111475 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 90122519 ps |
| CPU time | 0.55 seconds |
| Started | Jul 13 05:59:05 PM PDT 24 |
| Finished | Jul 13 05:59:06 PM PDT 24 |
| Peak memory | 195172 kb |
| Host | smart-82cd0bd1-611b-492a-8aff-893c73f42371 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426111475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3426111475 |
| Directory | /workspace/6.uart_alert_test/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_full.3378071281 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 36380322344 ps |
| CPU time | 52.08 seconds |
| Started | Jul 13 05:58:52 PM PDT 24 |
| Finished | Jul 13 05:59:45 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-05b80105-2dbb-41d4-87fb-9535ef40e754 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378071281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3378071281 |
| Directory | /workspace/6.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_overflow.1323222092 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 14473255212 ps |
| CPU time | 12.79 seconds |
| Started | Jul 13 05:58:55 PM PDT 24 |
| Finished | Jul 13 05:59:09 PM PDT 24 |
| Peak memory | 199648 kb |
| Host | smart-e47bd1c1-fa9a-46e1-a7a5-6344e2da2dd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323222092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1323222092 |
| Directory | /workspace/6.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_reset.241940986 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 111279334584 ps |
| CPU time | 97.67 seconds |
| Started | Jul 13 05:58:54 PM PDT 24 |
| Finished | Jul 13 06:00:33 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-8edd1645-2ecc-4b01-814d-40f4795ea2b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=241940986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.241940986 |
| Directory | /workspace/6.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/6.uart_intr.1196441556 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 180143035258 ps |
| CPU time | 57.61 seconds |
| Started | Jul 13 05:59:05 PM PDT 24 |
| Finished | Jul 13 06:00:03 PM PDT 24 |
| Peak memory | 196104 kb |
| Host | smart-4e95c073-94f3-4d23-9431-b4e3a5752e14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196441556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1196441556 |
| Directory | /workspace/6.uart_intr/latest |
| Test location | /workspace/coverage/default/6.uart_long_xfer_wo_dly.1301863878 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 70566826751 ps |
| CPU time | 399.05 seconds |
| Started | Jul 13 05:59:06 PM PDT 24 |
| Finished | Jul 13 06:05:45 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-1308f8eb-9e08-4f08-8f08-63a97cf32f12 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1301863878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1301863878 |
| Directory | /workspace/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/6.uart_loopback.2558286620 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 6527762145 ps |
| CPU time | 4.16 seconds |
| Started | Jul 13 05:59:08 PM PDT 24 |
| Finished | Jul 13 05:59:13 PM PDT 24 |
| Peak memory | 198588 kb |
| Host | smart-dbc33078-0538-45d0-9afb-b157f9cd3f04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558286620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2558286620 |
| Directory | /workspace/6.uart_loopback/latest |
| Test location | /workspace/coverage/default/6.uart_noise_filter.1290778836 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 295682434690 ps |
| CPU time | 81.05 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 06:00:19 PM PDT 24 |
| Peak memory | 200076 kb |
| Host | smart-815913cf-8a8f-42c5-8fec-9c9671484bc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290778836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1290778836 |
| Directory | /workspace/6.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/6.uart_perf.484777736 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 4435667761 ps |
| CPU time | 139.4 seconds |
| Started | Jul 13 05:59:01 PM PDT 24 |
| Finished | Jul 13 06:01:21 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-ee4489ff-e2bd-4540-854b-4897319ab171 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=484777736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.484777736 |
| Directory | /workspace/6.uart_perf/latest |
| Test location | /workspace/coverage/default/6.uart_rx_oversample.1605169279 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 2764910216 ps |
| CPU time | 4.93 seconds |
| Started | Jul 13 05:58:55 PM PDT 24 |
| Finished | Jul 13 05:59:01 PM PDT 24 |
| Peak memory | 199128 kb |
| Host | smart-c494b49d-ff3f-4be7-9133-d49c18e61359 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1605169279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1605169279 |
| Directory | /workspace/6.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/6.uart_rx_parity_err.2350691722 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 68422991784 ps |
| CPU time | 23.6 seconds |
| Started | Jul 13 05:59:01 PM PDT 24 |
| Finished | Jul 13 05:59:25 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-3b2f398b-b48e-465a-be8c-f7bc943ef3ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350691722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2350691722 |
| Directory | /workspace/6.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/6.uart_rx_start_bit_filter.3655784787 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1946516637 ps |
| CPU time | 1.33 seconds |
| Started | Jul 13 05:59:02 PM PDT 24 |
| Finished | Jul 13 05:59:04 PM PDT 24 |
| Peak memory | 195448 kb |
| Host | smart-ccdfd4f3-5acf-41ff-a62f-ba185ba9b73d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655784787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3655784787 |
| Directory | /workspace/6.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/6.uart_smoke.1286948230 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 491448335 ps |
| CPU time | 1.25 seconds |
| Started | Jul 13 05:58:56 PM PDT 24 |
| Finished | Jul 13 05:58:58 PM PDT 24 |
| Peak memory | 198272 kb |
| Host | smart-d682e929-7ac8-4045-82f2-befe35c646f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286948230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1286948230 |
| Directory | /workspace/6.uart_smoke/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all.4168955840 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 97209613998 ps |
| CPU time | 148.84 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 06:01:40 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-52b99fa4-91f5-4c4f-9852-0dbb09d310d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168955840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4168955840 |
| Directory | /workspace/6.uart_stress_all/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all_with_rand_reset.4275847870 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 8086552445 ps |
| CPU time | 75.17 seconds |
| Started | Jul 13 05:59:01 PM PDT 24 |
| Finished | Jul 13 06:00:17 PM PDT 24 |
| Peak memory | 208356 kb |
| Host | smart-7daed11e-f9b5-48b9-b8e8-b359ed479d0b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275847870 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.4275847870 |
| Directory | /workspace/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_tx_ovrd.2590677780 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 6529737252 ps |
| CPU time | 17.72 seconds |
| Started | Jul 13 05:59:03 PM PDT 24 |
| Finished | Jul 13 05:59:21 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-336e2ed4-f8ec-4378-a072-42b503c0efa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590677780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2590677780 |
| Directory | /workspace/6.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/6.uart_tx_rx.1978338466 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 131674167370 ps |
| CPU time | 53.76 seconds |
| Started | Jul 13 05:58:57 PM PDT 24 |
| Finished | Jul 13 05:59:52 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-01db68c8-6345-4e65-b58c-33d3654aaebd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978338466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1978338466 |
| Directory | /workspace/6.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/60.uart_fifo_reset.1072517008 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 21223142513 ps |
| CPU time | 38.24 seconds |
| Started | Jul 13 06:02:48 PM PDT 24 |
| Finished | Jul 13 06:03:27 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-45b4f6e3-30e7-4541-a32f-b67c5c741103 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072517008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1072517008 |
| Directory | /workspace/60.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3759606356 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 61814774260 ps |
| CPU time | 760.62 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:15:46 PM PDT 24 |
| Peak memory | 231580 kb |
| Host | smart-af6e1773-65b3-4541-a4e0-b7a121cb50b0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759606356 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3759606356 |
| Directory | /workspace/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/61.uart_fifo_reset.1736326712 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 10612116727 ps |
| CPU time | 17.78 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:03:24 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-c718b0d6-3cb9-4afe-9487-8b15c782b047 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1736326712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1736326712 |
| Directory | /workspace/61.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/61.uart_stress_all_with_rand_reset.4204161328 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 73303908146 ps |
| CPU time | 632.43 seconds |
| Started | Jul 13 06:03:07 PM PDT 24 |
| Finished | Jul 13 06:13:41 PM PDT 24 |
| Peak memory | 226084 kb |
| Host | smart-bbb6e0b5-62e3-4117-8c9f-7e02ebef4a49 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204161328 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.4204161328 |
| Directory | /workspace/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/62.uart_fifo_reset.992590960 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 216034344063 ps |
| CPU time | 131.46 seconds |
| Started | Jul 13 06:03:06 PM PDT 24 |
| Finished | Jul 13 06:05:19 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-bf6bf036-7538-430f-a553-4f1fa1ed231a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992590960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.992590960 |
| Directory | /workspace/62.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/62.uart_stress_all_with_rand_reset.212205886 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 25568845747 ps |
| CPU time | 798.38 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:16:24 PM PDT 24 |
| Peak memory | 216568 kb |
| Host | smart-5218cc76-c88e-46fd-b3e8-7fd89f67b777 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212205886 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.212205886 |
| Directory | /workspace/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/64.uart_fifo_reset.175829876 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 31192807349 ps |
| CPU time | 13.77 seconds |
| Started | Jul 13 06:03:06 PM PDT 24 |
| Finished | Jul 13 06:03:21 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-5d19cc58-e245-4ed9-9dfd-e42273d76852 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175829876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.175829876 |
| Directory | /workspace/64.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2999742731 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 65958318151 ps |
| CPU time | 376.69 seconds |
| Started | Jul 13 06:03:03 PM PDT 24 |
| Finished | Jul 13 06:09:20 PM PDT 24 |
| Peak memory | 216176 kb |
| Host | smart-6cca02bc-4b82-4e46-985a-dcbd18bc41ff |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999742731 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2999742731 |
| Directory | /workspace/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/65.uart_fifo_reset.743575756 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 11902789045 ps |
| CPU time | 19.97 seconds |
| Started | Jul 13 06:03:04 PM PDT 24 |
| Finished | Jul 13 06:03:25 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-7fa48db6-36c3-44fa-85da-ec9452217d84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=743575756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.743575756 |
| Directory | /workspace/65.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3404753532 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 25033447960 ps |
| CPU time | 209.67 seconds |
| Started | Jul 13 06:03:07 PM PDT 24 |
| Finished | Jul 13 06:06:38 PM PDT 24 |
| Peak memory | 208480 kb |
| Host | smart-9d51eb4c-80d9-45aa-84d7-31f9ef82e279 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404753532 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3404753532 |
| Directory | /workspace/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/66.uart_fifo_reset.3569673064 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 136576389840 ps |
| CPU time | 95.9 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:04:42 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-f0fc6017-6efb-4ba9-9cae-9751720bad2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3569673064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3569673064 |
| Directory | /workspace/66.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2786194107 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 240027683539 ps |
| CPU time | 894.42 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:18:00 PM PDT 24 |
| Peak memory | 216648 kb |
| Host | smart-96c11f6a-9ae8-496a-9cfd-5c203cfa8621 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786194107 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2786194107 |
| Directory | /workspace/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/67.uart_fifo_reset.3909088726 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 106299777595 ps |
| CPU time | 31.55 seconds |
| Started | Jul 13 06:03:03 PM PDT 24 |
| Finished | Jul 13 06:03:35 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-92c48f7f-0b9b-45ef-b2aa-b7e074fdd8ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909088726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3909088726 |
| Directory | /workspace/67.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2174884323 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 220282116409 ps |
| CPU time | 388.15 seconds |
| Started | Jul 13 06:03:04 PM PDT 24 |
| Finished | Jul 13 06:09:32 PM PDT 24 |
| Peak memory | 225432 kb |
| Host | smart-b3524264-00c0-4514-95be-33f2ef72a98e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174884323 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2174884323 |
| Directory | /workspace/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/68.uart_fifo_reset.67491037 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 38674155140 ps |
| CPU time | 17.41 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:03:24 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-ba5621c1-4e50-4ad1-9bae-3ada581bc634 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67491037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.67491037 |
| Directory | /workspace/68.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2088160137 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 58008448559 ps |
| CPU time | 118.3 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:05:04 PM PDT 24 |
| Peak memory | 215564 kb |
| Host | smart-cbbb9a9a-bc7c-4ead-96a1-3f4dac3c94eb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088160137 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2088160137 |
| Directory | /workspace/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/69.uart_fifo_reset.2757720801 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 131891763430 ps |
| CPU time | 86.5 seconds |
| Started | Jul 13 06:03:06 PM PDT 24 |
| Finished | Jul 13 06:04:34 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-e61a5979-3307-4a6b-83a5-c98f8ac52b60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2757720801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2757720801 |
| Directory | /workspace/69.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3581196530 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 11744687062 ps |
| CPU time | 242.03 seconds |
| Started | Jul 13 06:03:04 PM PDT 24 |
| Finished | Jul 13 06:07:06 PM PDT 24 |
| Peak memory | 208264 kb |
| Host | smart-1a53b2eb-6b86-49aa-aacb-d77e19c2455d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581196530 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3581196530 |
| Directory | /workspace/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_alert_test.2283985292 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 98321922 ps |
| CPU time | 0.57 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 05:59:05 PM PDT 24 |
| Peak memory | 195224 kb |
| Host | smart-9966372d-983d-4c0c-9dc9-3de05e5ec526 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283985292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2283985292 |
| Directory | /workspace/7.uart_alert_test/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_full.2521907928 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 58397258647 ps |
| CPU time | 55.63 seconds |
| Started | Jul 13 05:59:03 PM PDT 24 |
| Finished | Jul 13 06:00:00 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-4946c1f9-03a6-447d-82ea-df40831b0799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521907928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2521907928 |
| Directory | /workspace/7.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_overflow.413063984 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 49867970257 ps |
| CPU time | 29.99 seconds |
| Started | Jul 13 05:59:01 PM PDT 24 |
| Finished | Jul 13 05:59:32 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-98d7313e-7594-4572-8936-28c37026a23a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=413063984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.413063984 |
| Directory | /workspace/7.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_reset.226775204 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 251053615829 ps |
| CPU time | 376.74 seconds |
| Started | Jul 13 05:59:02 PM PDT 24 |
| Finished | Jul 13 06:05:19 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-b9b8b0ca-54c4-4b8b-acdf-ed6fb0bde0e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226775204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.226775204 |
| Directory | /workspace/7.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/7.uart_intr.4197032984 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 45454809718 ps |
| CPU time | 72.99 seconds |
| Started | Jul 13 05:59:06 PM PDT 24 |
| Finished | Jul 13 06:00:20 PM PDT 24 |
| Peak memory | 198896 kb |
| Host | smart-04cfdd83-85bf-4cf0-9fa9-88dd4bfe93ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197032984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.4197032984 |
| Directory | /workspace/7.uart_intr/latest |
| Test location | /workspace/coverage/default/7.uart_long_xfer_wo_dly.2898915675 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 124732442179 ps |
| CPU time | 338.18 seconds |
| Started | Jul 13 05:59:08 PM PDT 24 |
| Finished | Jul 13 06:04:47 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-c140ed71-c75e-4c65-9bec-89e6d683221e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2898915675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2898915675 |
| Directory | /workspace/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/7.uart_loopback.4166233593 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 9323554024 ps |
| CPU time | 9.79 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 05:59:15 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-7b555625-366b-41d3-86ae-62724daeb177 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166233593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.4166233593 |
| Directory | /workspace/7.uart_loopback/latest |
| Test location | /workspace/coverage/default/7.uart_noise_filter.4216759921 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 45087811902 ps |
| CPU time | 16.42 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 05:59:21 PM PDT 24 |
| Peak memory | 198496 kb |
| Host | smart-0e18df10-1439-4686-bb1d-7ea62f4986d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216759921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4216759921 |
| Directory | /workspace/7.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/7.uart_perf.408660145 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 12464870876 ps |
| CPU time | 167.68 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 06:01:52 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-c99c06b9-7c2d-4bc5-89de-839a8cd7297e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=408660145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.408660145 |
| Directory | /workspace/7.uart_perf/latest |
| Test location | /workspace/coverage/default/7.uart_rx_oversample.3780092270 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 6787202191 ps |
| CPU time | 4.6 seconds |
| Started | Jul 13 05:59:00 PM PDT 24 |
| Finished | Jul 13 05:59:05 PM PDT 24 |
| Peak memory | 198032 kb |
| Host | smart-afa8fcdf-7bed-4c1f-8ffc-5f3fcd259598 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3780092270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3780092270 |
| Directory | /workspace/7.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/7.uart_rx_parity_err.1011108621 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 54250079062 ps |
| CPU time | 9.98 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 05:59:14 PM PDT 24 |
| Peak memory | 198240 kb |
| Host | smart-5fea3dc0-9ac2-42a6-9d2a-4622549e2d83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011108621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1011108621 |
| Directory | /workspace/7.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/7.uart_rx_start_bit_filter.4025646380 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4840993411 ps |
| CPU time | 6.98 seconds |
| Started | Jul 13 05:59:01 PM PDT 24 |
| Finished | Jul 13 05:59:08 PM PDT 24 |
| Peak memory | 196160 kb |
| Host | smart-d1587e32-6894-4d56-a8c6-0945416e04f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025646380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4025646380 |
| Directory | /workspace/7.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/7.uart_smoke.1986936912 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 646614444 ps |
| CPU time | 1.64 seconds |
| Started | Jul 13 05:59:08 PM PDT 24 |
| Finished | Jul 13 05:59:10 PM PDT 24 |
| Peak memory | 198824 kb |
| Host | smart-c566c668-5f9f-43dd-be8c-5481ba0d77f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986936912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1986936912 |
| Directory | /workspace/7.uart_smoke/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all.3087289738 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 255388412340 ps |
| CPU time | 927.91 seconds |
| Started | Jul 13 05:59:08 PM PDT 24 |
| Finished | Jul 13 06:14:36 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-32d779f3-48da-4009-afd7-8a910bdce22b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087289738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3087289738 |
| Directory | /workspace/7.uart_stress_all/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3824495922 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 17629276215 ps |
| CPU time | 192.68 seconds |
| Started | Jul 13 05:59:00 PM PDT 24 |
| Finished | Jul 13 06:02:13 PM PDT 24 |
| Peak memory | 215424 kb |
| Host | smart-83164405-844f-450f-a3ae-25af5d74f1ae |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824495922 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3824495922 |
| Directory | /workspace/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_tx_ovrd.664941725 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 962133727 ps |
| CPU time | 4.06 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 05:59:14 PM PDT 24 |
| Peak memory | 198364 kb |
| Host | smart-5205ffa6-090b-4a3a-ae26-b68caa9ee82c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664941725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.664941725 |
| Directory | /workspace/7.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/7.uart_tx_rx.2654120841 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 15314565076 ps |
| CPU time | 13.03 seconds |
| Started | Jul 13 05:59:03 PM PDT 24 |
| Finished | Jul 13 05:59:17 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-a761cf08-bc18-421d-b48f-f1c3d47f6e7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654120841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2654120841 |
| Directory | /workspace/7.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/70.uart_fifo_reset.3040772672 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 44232381303 ps |
| CPU time | 37.13 seconds |
| Started | Jul 13 06:03:04 PM PDT 24 |
| Finished | Jul 13 06:03:41 PM PDT 24 |
| Peak memory | 199460 kb |
| Host | smart-72df7738-8764-48fa-b033-9c76e04879be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040772672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3040772672 |
| Directory | /workspace/70.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/71.uart_fifo_reset.3110900528 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 32357754453 ps |
| CPU time | 49.85 seconds |
| Started | Jul 13 06:03:06 PM PDT 24 |
| Finished | Jul 13 06:03:57 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-d1904377-29ed-4791-a7e0-0a6d6d9ec3e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110900528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3110900528 |
| Directory | /workspace/71.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/72.uart_fifo_reset.171792235 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 39902914705 ps |
| CPU time | 22.5 seconds |
| Started | Jul 13 06:03:06 PM PDT 24 |
| Finished | Jul 13 06:03:31 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-60bba081-3868-4b9d-89fd-b692bb4675ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171792235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.171792235 |
| Directory | /workspace/72.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1658701796 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 35827065047 ps |
| CPU time | 452.67 seconds |
| Started | Jul 13 06:03:07 PM PDT 24 |
| Finished | Jul 13 06:10:41 PM PDT 24 |
| Peak memory | 215636 kb |
| Host | smart-1ce695d0-4d99-49af-bd61-ff793001ed23 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658701796 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1658701796 |
| Directory | /workspace/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/73.uart_fifo_reset.2764159721 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 90871197033 ps |
| CPU time | 23.7 seconds |
| Started | Jul 13 06:03:04 PM PDT 24 |
| Finished | Jul 13 06:03:28 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-66773a35-8085-4bcc-b148-67ea29d77b2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2764159721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2764159721 |
| Directory | /workspace/73.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2728429152 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 44813616652 ps |
| CPU time | 312.32 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:08:18 PM PDT 24 |
| Peak memory | 216648 kb |
| Host | smart-d30801c9-222c-41d1-9df7-68117af99a6b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728429152 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2728429152 |
| Directory | /workspace/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/74.uart_fifo_reset.909472711 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 45109087530 ps |
| CPU time | 20.07 seconds |
| Started | Jul 13 06:03:04 PM PDT 24 |
| Finished | Jul 13 06:03:25 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-9eb0507e-7925-4b7b-a6f0-3c5cd1aee5cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909472711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.909472711 |
| Directory | /workspace/74.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3082687310 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 88321051171 ps |
| CPU time | 601.71 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:13:08 PM PDT 24 |
| Peak memory | 224868 kb |
| Host | smart-a1245a39-9372-403d-b8da-528c124b852f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082687310 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3082687310 |
| Directory | /workspace/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/75.uart_fifo_reset.351380920 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 26249865926 ps |
| CPU time | 66.28 seconds |
| Started | Jul 13 06:03:06 PM PDT 24 |
| Finished | Jul 13 06:04:13 PM PDT 24 |
| Peak memory | 200084 kb |
| Host | smart-eb2ed2f6-5a4d-4c9b-8ee4-37a36da3c25c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=351380920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.351380920 |
| Directory | /workspace/75.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2126723420 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 91282090862 ps |
| CPU time | 940.71 seconds |
| Started | Jul 13 06:03:05 PM PDT 24 |
| Finished | Jul 13 06:18:47 PM PDT 24 |
| Peak memory | 208304 kb |
| Host | smart-2009deb3-b646-4d27-aa3d-8352f0e86719 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126723420 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2126723420 |
| Directory | /workspace/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/76.uart_fifo_reset.2420549267 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 232526265171 ps |
| CPU time | 383.5 seconds |
| Started | Jul 13 06:03:06 PM PDT 24 |
| Finished | Jul 13 06:09:31 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-f61ca981-81dc-4f42-9cca-a2351d781bd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2420549267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2420549267 |
| Directory | /workspace/76.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3788494199 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 160036906051 ps |
| CPU time | 786.81 seconds |
| Started | Jul 13 06:03:06 PM PDT 24 |
| Finished | Jul 13 06:16:14 PM PDT 24 |
| Peak memory | 216644 kb |
| Host | smart-b606d462-1a6d-4e3a-b557-903be34ef9e1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788494199 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3788494199 |
| Directory | /workspace/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/77.uart_fifo_reset.2518245020 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 25996170260 ps |
| CPU time | 29.01 seconds |
| Started | Jul 13 06:03:07 PM PDT 24 |
| Finished | Jul 13 06:03:37 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-8d2828c2-62f4-4d7b-a236-48f7be5d5e9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2518245020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2518245020 |
| Directory | /workspace/77.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/77.uart_stress_all_with_rand_reset.682374175 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 43481703923 ps |
| CPU time | 131.45 seconds |
| Started | Jul 13 06:03:14 PM PDT 24 |
| Finished | Jul 13 06:05:27 PM PDT 24 |
| Peak memory | 211792 kb |
| Host | smart-2eb9e4a2-c38b-4aee-8176-6ed9c31660c4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682374175 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.682374175 |
| Directory | /workspace/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3167139387 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 198692078459 ps |
| CPU time | 359.98 seconds |
| Started | Jul 13 06:03:12 PM PDT 24 |
| Finished | Jul 13 06:09:14 PM PDT 24 |
| Peak memory | 216452 kb |
| Host | smart-a6903aee-a7b4-4bac-b26d-e5122719d1a7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167139387 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3167139387 |
| Directory | /workspace/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/79.uart_fifo_reset.866908688 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 118445973740 ps |
| CPU time | 185.47 seconds |
| Started | Jul 13 06:03:14 PM PDT 24 |
| Finished | Jul 13 06:06:21 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-320488c5-3c0f-4bec-b37e-f67f951b71d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866908688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.866908688 |
| Directory | /workspace/79.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1938131114 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 20824340355 ps |
| CPU time | 380.5 seconds |
| Started | Jul 13 06:03:18 PM PDT 24 |
| Finished | Jul 13 06:09:40 PM PDT 24 |
| Peak memory | 216220 kb |
| Host | smart-5dde6530-ea9f-48c7-9719-ba17cb24194d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938131114 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1938131114 |
| Directory | /workspace/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_alert_test.1729968723 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 38076787 ps |
| CPU time | 0.54 seconds |
| Started | Jul 13 05:59:03 PM PDT 24 |
| Finished | Jul 13 05:59:04 PM PDT 24 |
| Peak memory | 195156 kb |
| Host | smart-f011433d-5181-4f80-a723-3ea777419b03 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729968723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1729968723 |
| Directory | /workspace/8.uart_alert_test/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_full.85894211 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 94464706689 ps |
| CPU time | 141.95 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 06:01:32 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-080cb3b2-8b70-4310-b300-357aa5807c44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85894211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.85894211 |
| Directory | /workspace/8.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_overflow.2016175663 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 20426798910 ps |
| CPU time | 33.27 seconds |
| Started | Jul 13 05:59:05 PM PDT 24 |
| Finished | Jul 13 05:59:38 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-dd8861d3-24a9-4ac6-9279-535afbb28003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016175663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2016175663 |
| Directory | /workspace/8.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_reset.2156185372 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4612761628 ps |
| CPU time | 6.9 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 05:59:12 PM PDT 24 |
| Peak memory | 198468 kb |
| Host | smart-63445a84-6553-4ee5-bb69-d5a7f58921ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156185372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2156185372 |
| Directory | /workspace/8.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/8.uart_intr.386860310 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 269170064553 ps |
| CPU time | 380.44 seconds |
| Started | Jul 13 05:59:01 PM PDT 24 |
| Finished | Jul 13 06:05:22 PM PDT 24 |
| Peak memory | 198868 kb |
| Host | smart-9d177ed7-e094-4e90-ad45-362956d1bf2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386860310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.386860310 |
| Directory | /workspace/8.uart_intr/latest |
| Test location | /workspace/coverage/default/8.uart_long_xfer_wo_dly.447686751 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 42043062337 ps |
| CPU time | 41.39 seconds |
| Started | Jul 13 05:59:07 PM PDT 24 |
| Finished | Jul 13 05:59:49 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-0ca4c637-dba4-4110-8527-8c20f6d8dec6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=447686751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.447686751 |
| Directory | /workspace/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/8.uart_loopback.9240472 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4219685830 ps |
| CPU time | 1.51 seconds |
| Started | Jul 13 05:59:02 PM PDT 24 |
| Finished | Jul 13 05:59:04 PM PDT 24 |
| Peak memory | 197692 kb |
| Host | smart-bb4dde25-0d38-450f-ad6a-a83516688a52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9240472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.9240472 |
| Directory | /workspace/8.uart_loopback/latest |
| Test location | /workspace/coverage/default/8.uart_noise_filter.2771390469 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 74468698811 ps |
| CPU time | 59.85 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 06:00:05 PM PDT 24 |
| Peak memory | 199492 kb |
| Host | smart-d41d6397-59b5-4ef6-a45a-6584dfb0a3bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2771390469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2771390469 |
| Directory | /workspace/8.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/8.uart_perf.4251828347 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 27640534683 ps |
| CPU time | 1545.87 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 06:24:51 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-516ebfe1-e592-4ae6-b43f-cd603594c77a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4251828347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.4251828347 |
| Directory | /workspace/8.uart_perf/latest |
| Test location | /workspace/coverage/default/8.uart_rx_oversample.3137699721 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 6554067574 ps |
| CPU time | 14.36 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 05:59:24 PM PDT 24 |
| Peak memory | 198972 kb |
| Host | smart-65ade42d-3806-44ac-a341-b33d0f08ae83 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3137699721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3137699721 |
| Directory | /workspace/8.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/8.uart_rx_parity_err.1615215521 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 13156770874 ps |
| CPU time | 13.01 seconds |
| Started | Jul 13 05:59:03 PM PDT 24 |
| Finished | Jul 13 05:59:16 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-cf08d212-13a1-43c0-aacd-c5e1db31b8e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615215521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1615215521 |
| Directory | /workspace/8.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/8.uart_rx_start_bit_filter.323261388 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1456975531 ps |
| CPU time | 1.7 seconds |
| Started | Jul 13 05:59:04 PM PDT 24 |
| Finished | Jul 13 05:59:06 PM PDT 24 |
| Peak memory | 195080 kb |
| Host | smart-e41cd338-e783-4030-99a7-7f5a0f03e670 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323261388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.323261388 |
| Directory | /workspace/8.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/8.uart_smoke.169570791 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 669083544 ps |
| CPU time | 4.1 seconds |
| Started | Jul 13 05:59:05 PM PDT 24 |
| Finished | Jul 13 05:59:10 PM PDT 24 |
| Peak memory | 198356 kb |
| Host | smart-077c342f-5ac5-4cae-ad83-bf5e8e6b821a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=169570791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.169570791 |
| Directory | /workspace/8.uart_smoke/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all.3880960968 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 802782491178 ps |
| CPU time | 304 seconds |
| Started | Jul 13 05:59:03 PM PDT 24 |
| Finished | Jul 13 06:04:08 PM PDT 24 |
| Peak memory | 208100 kb |
| Host | smart-e8d01ecf-e348-44d6-bf4d-f299798cb98d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880960968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3880960968 |
| Directory | /workspace/8.uart_stress_all/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1043068351 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 28496172042 ps |
| CPU time | 237.19 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 06:03:07 PM PDT 24 |
| Peak memory | 212600 kb |
| Host | smart-57cc0896-4739-4453-add8-9c0ab1a8277a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043068351 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1043068351 |
| Directory | /workspace/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_tx_ovrd.1982247229 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6484607869 ps |
| CPU time | 52.73 seconds |
| Started | Jul 13 05:59:05 PM PDT 24 |
| Finished | Jul 13 05:59:59 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-01e578bb-1dd3-4eb7-9e10-453fe25d5382 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982247229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1982247229 |
| Directory | /workspace/8.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/8.uart_tx_rx.744599375 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 42816957564 ps |
| CPU time | 63.84 seconds |
| Started | Jul 13 05:59:03 PM PDT 24 |
| Finished | Jul 13 06:00:08 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-35b59b12-c077-4422-af42-16f3f9d29823 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744599375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.744599375 |
| Directory | /workspace/8.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/80.uart_fifo_reset.4084967272 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 42979057009 ps |
| CPU time | 30.28 seconds |
| Started | Jul 13 06:03:16 PM PDT 24 |
| Finished | Jul 13 06:03:48 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-6ec6929a-8bf0-457b-b524-bf09b8d16437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084967272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4084967272 |
| Directory | /workspace/80.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/80.uart_stress_all_with_rand_reset.969014919 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 26762770133 ps |
| CPU time | 119.67 seconds |
| Started | Jul 13 06:03:21 PM PDT 24 |
| Finished | Jul 13 06:05:22 PM PDT 24 |
| Peak memory | 216152 kb |
| Host | smart-0231dcb8-c159-4eb5-bc18-4223aab0d95b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969014919 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.969014919 |
| Directory | /workspace/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/81.uart_fifo_reset.1785485602 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 64744602878 ps |
| CPU time | 107.99 seconds |
| Started | Jul 13 06:03:19 PM PDT 24 |
| Finished | Jul 13 06:05:08 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-ffcf3e9b-6d45-4968-bfd2-b2a110a42450 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785485602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1785485602 |
| Directory | /workspace/81.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1343441333 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 26788285352 ps |
| CPU time | 307.08 seconds |
| Started | Jul 13 06:03:15 PM PDT 24 |
| Finished | Jul 13 06:08:24 PM PDT 24 |
| Peak memory | 216360 kb |
| Host | smart-283ef19d-bbf7-4149-b103-9bbbd3155c7d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343441333 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1343441333 |
| Directory | /workspace/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/82.uart_fifo_reset.495952915 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 74371244435 ps |
| CPU time | 126.69 seconds |
| Started | Jul 13 06:03:14 PM PDT 24 |
| Finished | Jul 13 06:05:22 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-3a030864-2367-4b58-8e4e-b95257c04658 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495952915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.495952915 |
| Directory | /workspace/82.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/82.uart_stress_all_with_rand_reset.912501455 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 29562138378 ps |
| CPU time | 247.43 seconds |
| Started | Jul 13 06:03:22 PM PDT 24 |
| Finished | Jul 13 06:07:31 PM PDT 24 |
| Peak memory | 216596 kb |
| Host | smart-efe07286-0aa0-478e-b062-c0b679bc9f20 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912501455 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.912501455 |
| Directory | /workspace/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/83.uart_fifo_reset.2564219201 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 88733558598 ps |
| CPU time | 173.01 seconds |
| Started | Jul 13 06:03:15 PM PDT 24 |
| Finished | Jul 13 06:06:09 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-b28e5e3a-31f5-4719-aecf-861f7a2c15d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2564219201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2564219201 |
| Directory | /workspace/83.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2295765258 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 66532760739 ps |
| CPU time | 124.97 seconds |
| Started | Jul 13 06:03:18 PM PDT 24 |
| Finished | Jul 13 06:05:24 PM PDT 24 |
| Peak memory | 216388 kb |
| Host | smart-399e2936-a908-42b5-a140-6ffad272b12e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295765258 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2295765258 |
| Directory | /workspace/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/84.uart_fifo_reset.2202032764 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 329445825275 ps |
| CPU time | 108.06 seconds |
| Started | Jul 13 06:03:16 PM PDT 24 |
| Finished | Jul 13 06:05:06 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-3448bf7d-ed4a-42ac-b07c-902e3b6528f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202032764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2202032764 |
| Directory | /workspace/84.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/84.uart_stress_all_with_rand_reset.799014904 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 140500254351 ps |
| CPU time | 486.69 seconds |
| Started | Jul 13 06:03:16 PM PDT 24 |
| Finished | Jul 13 06:11:24 PM PDT 24 |
| Peak memory | 216576 kb |
| Host | smart-49cfbfcf-b57a-4c95-a6a2-792386c6d031 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799014904 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.799014904 |
| Directory | /workspace/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/85.uart_fifo_reset.955858120 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 280878001769 ps |
| CPU time | 66.3 seconds |
| Started | Jul 13 06:03:12 PM PDT 24 |
| Finished | Jul 13 06:04:20 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-8f543f8f-0470-4cb4-baac-90c981a41934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955858120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.955858120 |
| Directory | /workspace/85.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/85.uart_stress_all_with_rand_reset.821458876 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 19110452836 ps |
| CPU time | 219.91 seconds |
| Started | Jul 13 06:03:15 PM PDT 24 |
| Finished | Jul 13 06:06:57 PM PDT 24 |
| Peak memory | 215964 kb |
| Host | smart-fa521ec9-7b46-4df2-a31d-4a8365211c64 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821458876 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.821458876 |
| Directory | /workspace/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/86.uart_fifo_reset.3143479745 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 30386006304 ps |
| CPU time | 20.14 seconds |
| Started | Jul 13 06:03:14 PM PDT 24 |
| Finished | Jul 13 06:03:36 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-4b215500-53b7-4d12-bc75-1f16173ac636 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143479745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3143479745 |
| Directory | /workspace/86.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2764468137 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 13666546482 ps |
| CPU time | 131.57 seconds |
| Started | Jul 13 06:03:12 PM PDT 24 |
| Finished | Jul 13 06:05:25 PM PDT 24 |
| Peak memory | 216436 kb |
| Host | smart-29e53515-7a6c-4f18-a238-d59849dad693 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764468137 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2764468137 |
| Directory | /workspace/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/87.uart_fifo_reset.1752400199 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 47941614868 ps |
| CPU time | 16.61 seconds |
| Started | Jul 13 06:03:15 PM PDT 24 |
| Finished | Jul 13 06:03:33 PM PDT 24 |
| Peak memory | 199936 kb |
| Host | smart-3878ea0c-7692-4bb3-866e-86ed6c037b5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752400199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1752400199 |
| Directory | /workspace/87.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1006069246 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 112659351840 ps |
| CPU time | 766.98 seconds |
| Started | Jul 13 06:03:13 PM PDT 24 |
| Finished | Jul 13 06:16:01 PM PDT 24 |
| Peak memory | 227136 kb |
| Host | smart-e26ae2d9-7e28-4b4d-a004-6ac1688ddc70 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006069246 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1006069246 |
| Directory | /workspace/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/88.uart_fifo_reset.4019343683 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 115017100159 ps |
| CPU time | 47.29 seconds |
| Started | Jul 13 06:03:15 PM PDT 24 |
| Finished | Jul 13 06:04:04 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-e97af8ca-148f-4302-987e-3795dd6679b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019343683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.4019343683 |
| Directory | /workspace/88.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/88.uart_stress_all_with_rand_reset.204370496 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 46821444806 ps |
| CPU time | 553.95 seconds |
| Started | Jul 13 06:03:15 PM PDT 24 |
| Finished | Jul 13 06:12:31 PM PDT 24 |
| Peak memory | 216324 kb |
| Host | smart-5dd678bd-94ed-4010-927b-39bba86566a7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204370496 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.204370496 |
| Directory | /workspace/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/89.uart_fifo_reset.931907134 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 18549506191 ps |
| CPU time | 13.84 seconds |
| Started | Jul 13 06:03:12 PM PDT 24 |
| Finished | Jul 13 06:03:27 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-2b05fec1-58ad-4cb7-a9f9-c22104ffb44e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931907134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.931907134 |
| Directory | /workspace/89.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2375305764 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 73833512340 ps |
| CPU time | 866.28 seconds |
| Started | Jul 13 06:03:21 PM PDT 24 |
| Finished | Jul 13 06:17:48 PM PDT 24 |
| Peak memory | 216644 kb |
| Host | smart-94c17c65-cd12-4ea3-8e37-608a61d5d9ec |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375305764 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2375305764 |
| Directory | /workspace/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_alert_test.537470563 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 50719550 ps |
| CPU time | 0.56 seconds |
| Started | Jul 13 05:59:12 PM PDT 24 |
| Finished | Jul 13 05:59:13 PM PDT 24 |
| Peak memory | 194656 kb |
| Host | smart-02ee91a8-e5ad-4c0b-a23c-ad8ae0f4f7dd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537470563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.537470563 |
| Directory | /workspace/9.uart_alert_test/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_full.2933331503 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 18489938048 ps |
| CPU time | 27.7 seconds |
| Started | Jul 13 05:59:08 PM PDT 24 |
| Finished | Jul 13 05:59:37 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-fde525e0-f094-4cc6-9a24-cb11c46f0060 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933331503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2933331503 |
| Directory | /workspace/9.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_overflow.1011192968 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 85308631475 ps |
| CPU time | 66.53 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 06:00:16 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-d360baa9-3cc9-43c8-a19f-91570284981f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011192968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1011192968 |
| Directory | /workspace/9.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_reset.2801584105 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 77560347381 ps |
| CPU time | 34.5 seconds |
| Started | Jul 13 05:59:14 PM PDT 24 |
| Finished | Jul 13 05:59:49 PM PDT 24 |
| Peak memory | 199640 kb |
| Host | smart-40af8b2a-efc6-4f51-a6ae-d055ecc62c62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801584105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2801584105 |
| Directory | /workspace/9.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/9.uart_long_xfer_wo_dly.610880078 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 136539446418 ps |
| CPU time | 1156.65 seconds |
| Started | Jul 13 05:59:13 PM PDT 24 |
| Finished | Jul 13 06:18:30 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-e89215ef-abcc-49f1-9f51-7ee0c2dbcf50 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=610880078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.610880078 |
| Directory | /workspace/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/9.uart_loopback.512158681 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 7618035709 ps |
| CPU time | 15.35 seconds |
| Started | Jul 13 05:59:13 PM PDT 24 |
| Finished | Jul 13 05:59:29 PM PDT 24 |
| Peak memory | 199524 kb |
| Host | smart-97a62ac4-adf6-4c97-b686-d2c5e16a455d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512158681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.512158681 |
| Directory | /workspace/9.uart_loopback/latest |
| Test location | /workspace/coverage/default/9.uart_noise_filter.3101652827 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 62806425398 ps |
| CPU time | 110.58 seconds |
| Started | Jul 13 05:59:12 PM PDT 24 |
| Finished | Jul 13 06:01:04 PM PDT 24 |
| Peak memory | 200076 kb |
| Host | smart-9bd9849a-9966-48a3-ad75-7611ef7d6a5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101652827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3101652827 |
| Directory | /workspace/9.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/9.uart_perf.1949189327 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5291941628 ps |
| CPU time | 302.48 seconds |
| Started | Jul 13 05:59:08 PM PDT 24 |
| Finished | Jul 13 06:04:11 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-88e82e2d-5d5f-4bde-9782-e23a6f4e9546 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1949189327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1949189327 |
| Directory | /workspace/9.uart_perf/latest |
| Test location | /workspace/coverage/default/9.uart_rx_oversample.3222087200 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1402244696 ps |
| CPU time | 0.82 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 05:59:12 PM PDT 24 |
| Peak memory | 196904 kb |
| Host | smart-81e48282-ec71-449a-809f-6822b69aeb15 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3222087200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3222087200 |
| Directory | /workspace/9.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/9.uart_rx_parity_err.827148713 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 163009646262 ps |
| CPU time | 77.94 seconds |
| Started | Jul 13 05:59:09 PM PDT 24 |
| Finished | Jul 13 06:00:28 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-260ea757-bdb6-44ae-85e1-07f64fde9c99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=827148713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.827148713 |
| Directory | /workspace/9.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/9.uart_rx_start_bit_filter.2879875654 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2147335465 ps |
| CPU time | 3.68 seconds |
| Started | Jul 13 05:59:10 PM PDT 24 |
| Finished | Jul 13 05:59:14 PM PDT 24 |
| Peak memory | 195244 kb |
| Host | smart-9298b2cd-1050-4456-be87-cb0116ae2d7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879875654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2879875654 |
| Directory | /workspace/9.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/9.uart_smoke.3517830000 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 5527582799 ps |
| CPU time | 25.71 seconds |
| Started | Jul 13 05:59:02 PM PDT 24 |
| Finished | Jul 13 05:59:28 PM PDT 24 |
| Peak memory | 199192 kb |
| Host | smart-9b3021ad-f51d-4244-b646-67c6cfd91143 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517830000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3517830000 |
| Directory | /workspace/9.uart_smoke/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all.1045003281 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 47711253341 ps |
| CPU time | 50.21 seconds |
| Started | Jul 13 05:59:07 PM PDT 24 |
| Finished | Jul 13 05:59:58 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-afffbba4-a784-40cf-a79d-dd0b27f26bae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045003281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1045003281 |
| Directory | /workspace/9.uart_stress_all/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all_with_rand_reset.201666118 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 126035273297 ps |
| CPU time | 595.61 seconds |
| Started | Jul 13 05:59:08 PM PDT 24 |
| Finished | Jul 13 06:09:05 PM PDT 24 |
| Peak memory | 216636 kb |
| Host | smart-dbb8cd9b-e046-4bca-8269-26f6c26261e0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201666118 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.201666118 |
| Directory | /workspace/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_tx_ovrd.3890053293 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 557552324 ps |
| CPU time | 1.89 seconds |
| Started | Jul 13 05:59:11 PM PDT 24 |
| Finished | Jul 13 05:59:14 PM PDT 24 |
| Peak memory | 198620 kb |
| Host | smart-59acf8ad-d1b0-49e7-a95c-46e42ef7ff85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890053293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3890053293 |
| Directory | /workspace/9.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/9.uart_tx_rx.615934895 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 35317775720 ps |
| CPU time | 15.11 seconds |
| Started | Jul 13 05:59:07 PM PDT 24 |
| Finished | Jul 13 05:59:22 PM PDT 24 |
| Peak memory | 197292 kb |
| Host | smart-8d52c166-b45b-4e6b-8272-b7c3aa59b0f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615934895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.615934895 |
| Directory | /workspace/9.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/90.uart_fifo_reset.3366186194 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 95310859412 ps |
| CPU time | 57.12 seconds |
| Started | Jul 13 06:03:16 PM PDT 24 |
| Finished | Jul 13 06:04:15 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-76e2f2a3-ca0d-40e4-a39d-54c03e4c30f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366186194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3366186194 |
| Directory | /workspace/90.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/91.uart_fifo_reset.2025337276 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 140343261583 ps |
| CPU time | 57.42 seconds |
| Started | Jul 13 06:03:13 PM PDT 24 |
| Finished | Jul 13 06:04:11 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-71ee7ede-0f78-4874-a051-1d6f8b5487eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025337276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2025337276 |
| Directory | /workspace/91.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1921849040 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 117676987777 ps |
| CPU time | 594.23 seconds |
| Started | Jul 13 06:03:22 PM PDT 24 |
| Finished | Jul 13 06:13:17 PM PDT 24 |
| Peak memory | 216452 kb |
| Host | smart-bdf72ae6-a4a7-4272-98c8-a683062ff7d3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921849040 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1921849040 |
| Directory | /workspace/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/92.uart_fifo_reset.4278049031 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 106233581425 ps |
| CPU time | 17.61 seconds |
| Started | Jul 13 06:03:14 PM PDT 24 |
| Finished | Jul 13 06:03:33 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-d3bf074c-7a7a-4c31-b643-fe48cd0bf650 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278049031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4278049031 |
| Directory | /workspace/92.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1346062675 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 153718791600 ps |
| CPU time | 358.95 seconds |
| Started | Jul 13 06:03:13 PM PDT 24 |
| Finished | Jul 13 06:09:13 PM PDT 24 |
| Peak memory | 224824 kb |
| Host | smart-9d7443ee-ff12-4481-aa91-4379faec58e5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346062675 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1346062675 |
| Directory | /workspace/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/93.uart_fifo_reset.2896906504 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 47318731704 ps |
| CPU time | 44.58 seconds |
| Started | Jul 13 06:03:21 PM PDT 24 |
| Finished | Jul 13 06:04:07 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-60e793f1-d41d-4702-93ae-e35c88349866 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896906504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2896906504 |
| Directory | /workspace/93.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3775035300 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 484127531705 ps |
| CPU time | 663.66 seconds |
| Started | Jul 13 06:03:22 PM PDT 24 |
| Finished | Jul 13 06:14:27 PM PDT 24 |
| Peak memory | 216428 kb |
| Host | smart-b79520f8-f67b-4936-a33a-8154e6ad1086 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775035300 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3775035300 |
| Directory | /workspace/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/94.uart_fifo_reset.3627500782 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 148896781272 ps |
| CPU time | 30.15 seconds |
| Started | Jul 13 06:03:21 PM PDT 24 |
| Finished | Jul 13 06:03:52 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-40efb2e1-e20e-42eb-972f-56cc2e25fb84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627500782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3627500782 |
| Directory | /workspace/94.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/95.uart_fifo_reset.646771014 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 31993880809 ps |
| CPU time | 47.38 seconds |
| Started | Jul 13 06:03:30 PM PDT 24 |
| Finished | Jul 13 06:04:17 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-594e63a7-7fdd-4c5a-9a0e-6f3f62b12159 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646771014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.646771014 |
| Directory | /workspace/95.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/96.uart_fifo_reset.3538910440 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 53611482747 ps |
| CPU time | 20.17 seconds |
| Started | Jul 13 06:03:23 PM PDT 24 |
| Finished | Jul 13 06:03:45 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-5b1eb902-634e-485d-b09e-d4a1a480a5d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538910440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3538910440 |
| Directory | /workspace/96.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2742425132 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 48441372287 ps |
| CPU time | 639.26 seconds |
| Started | Jul 13 06:03:23 PM PDT 24 |
| Finished | Jul 13 06:14:04 PM PDT 24 |
| Peak memory | 224824 kb |
| Host | smart-f69d9d94-a341-4460-bb06-ff387edbc794 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742425132 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2742425132 |
| Directory | /workspace/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/97.uart_fifo_reset.63153644 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 43588124103 ps |
| CPU time | 63.38 seconds |
| Started | Jul 13 06:03:22 PM PDT 24 |
| Finished | Jul 13 06:04:28 PM PDT 24 |
| Peak memory | 199648 kb |
| Host | smart-d3b671d8-dbf4-4b24-81ec-b9101f0f4820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63153644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.63153644 |
| Directory | /workspace/97.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/98.uart_fifo_reset.1309715955 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 105733795108 ps |
| CPU time | 148.69 seconds |
| Started | Jul 13 06:03:23 PM PDT 24 |
| Finished | Jul 13 06:05:54 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-2a5683e9-08b4-426a-a749-1cbe31ab270e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1309715955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1309715955 |
| Directory | /workspace/98.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1043787389 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 128467677318 ps |
| CPU time | 548.04 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:12:33 PM PDT 24 |
| Peak memory | 216620 kb |
| Host | smart-8eaf6441-8473-4d4f-a41c-c2bad5ed4c8f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043787389 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1043787389 |
| Directory | /workspace/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/99.uart_fifo_reset.737418636 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 18468788706 ps |
| CPU time | 27.64 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:03:53 PM PDT 24 |
| Peak memory | 200008 kb |
| Host | smart-6baaf346-c2da-40e2-aa97-9f06edf40bd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737418636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.737418636 |
| Directory | /workspace/99.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/99.uart_stress_all_with_rand_reset.559915848 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 72101116954 ps |
| CPU time | 814.22 seconds |
| Started | Jul 13 06:03:24 PM PDT 24 |
| Finished | Jul 13 06:17:00 PM PDT 24 |
| Peak memory | 216404 kb |
| Host | smart-efdd9f6e-b82f-4798-b836-f2084c2ba3e9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559915848 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.559915848 |
| Directory | /workspace/99.uart_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |