Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	110381	1			T1	64		T2	2		T3	18
all_values[1]	110381	1			T1	64		T2	2		T3	18
all_values[2]	110381	1			T1	64		T2	2		T3	18
all_values[3]	110381	1			T1	64		T2	2		T3	18
all_values[4]	110381	1			T1	64		T2	2		T3	18
all_values[5]	110381	1			T1	64		T2	2		T3	18
all_values[6]	110381	1			T1	64		T2	2		T3	18
all_values[7]	110381	1			T1	64		T2	2		T3	18
all_values[8]	110381	1			T1	64		T2	2		T3	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

498424

1

T1

295

T2

18

T3

71

auto[1]

495005

1

T1

281

T3

91

T4

187

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

897968

1

T1

487

T2

13

T3

102

auto[1]

95461

1

T1

89

T2

5

T3

60

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33308	1			T1	24		T4	11		T6	6
all_values[0]	auto[0]	auto[1]	23179	1			T1	26		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	30842	1			T1	1		T4	15		T6	29
all_values[0]	auto[1]	auto[1]	23052	1			T1	13		T3	16		T4	3
all_values[1]	auto[0]	auto[0]	51094	1			T1	51		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	1840	1			T3	10		T17	3		T18	9
all_values[1]	auto[1]	auto[0]	55680	1			T1	13		T3	5		T4	18
all_values[1]	auto[1]	auto[1]	1767	1			T13	1		T12	24		T20	2
all_values[2]	auto[0]	auto[0]	53000	1			T1	6		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2802	1			T2	1		T3	1		T4	3
all_values[2]	auto[1]	auto[0]	52013	1			T1	52		T3	12		T4	20
all_values[2]	auto[1]	auto[1]	2566	1			T1	6		T3	4		T4	4
all_values[3]	auto[0]	auto[0]	53607	1			T1	9		T2	2		T3	9
all_values[3]	auto[0]	auto[1]	374	1			T11	1		T13	4		T12	4
all_values[3]	auto[1]	auto[0]	56029	1			T1	55		T3	7		T4	21
all_values[3]	auto[1]	auto[1]	371	1			T3	2		T13	2		T12	2
all_values[4]	auto[0]	auto[0]	50348	1			T1	14		T2	2		T3	8
all_values[4]	auto[0]	auto[1]	553	1			T12	1		T20	12		T21	2
all_values[4]	auto[1]	auto[0]	58958	1			T1	50		T3	10		T4	26
all_values[4]	auto[1]	auto[1]	522	1			T14	5		T13	2		T12	12
all_values[5]	auto[0]	auto[0]	56324	1			T1	57		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	232	1			T13	5		T12	4		T20	1
all_values[5]	auto[1]	auto[0]	53619	1			T1	7		T3	14		T4	26
all_values[5]	auto[1]	auto[1]	206	1			T12	5		T31	2		T32	1
all_values[6]	auto[0]	auto[0]	57360	1			T1	47		T2	2		T3	15
all_values[6]	auto[0]	auto[1]	200	1			T12	2		T31	2		T132	4
all_values[6]	auto[1]	auto[0]	52597	1			T1	17		T3	3		T4	24
all_values[6]	auto[1]	auto[1]	224	1			T13	5		T12	2		T20	4
all_values[7]	auto[0]	auto[0]	60193	1			T1	12		T2	2		T3	5
all_values[7]	auto[0]	auto[1]	350	1			T1	2		T3	2		T13	1
all_values[7]	auto[1]	auto[0]	49372	1			T1	42		T3	5		T4	12
all_values[7]	auto[1]	auto[1]	466	1			T1	8		T3	6		T11	1
all_values[8]	auto[0]	auto[0]	36154	1			T1	28		T3	1		T4	10
all_values[8]	auto[0]	auto[1]	17506	1			T1	19		T2	2		T3	10
all_values[8]	auto[1]	auto[0]	37470	1			T1	2		T4	16		T7	202
all_values[8]	auto[1]	auto[1]	19251	1			T1	15		T3	7		T4	2