Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2393	1			T1	1		T18	1		T19	3
auto[BaudRate115200]	2034	1			T4	2		T7	1		T18	2
auto[BaudRate230400]	2088	1			T1	1		T3	2		T4	1
auto[BaudRate128Kbps]	2114	1			T1	1		T3	1		T7	3
auto[BaudRate256Kbps]	2280	1			T1	2		T3	1		T4	11
auto[BaudRate1Mbps]	1767	1			T1	1		T2	1		T3	1
auto[BaudRate1p5Mbps]	1322	1			T2	1		T3	3		T8	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1514	1			T7	10		T10	6		T43	7
freqs[25]	1432	1			T8	9		T13	27		T20	81
freqs[48]	717	1			T38	8		T12	81		T21	13
freqs[50]	436	1			T275	7		T128	4		T331	10
freqs[100]	1088	1			T2	2		T30	44		T42	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	264	1			T144	1		T299	1		T337	1
auto[BaudRate9600]	freqs[25]	191	1			T13	2		T20	19		T139	11
auto[BaudRate9600]	freqs[48]	132	1			T38	4		T12	20		T21	1
auto[BaudRate9600]	freqs[50]	77	1			T331	1		T210	3		T336	13
auto[BaudRate9600]	freqs[100]	152	1			T30	8		T42	1		T285	2
auto[BaudRate115200]	freqs[24]	213	1			T7	1		T271	2		T144	2
auto[BaudRate115200]	freqs[25]	219	1			T13	2		T20	15		T276	2
auto[BaudRate115200]	freqs[48]	105	1			T38	1		T12	8		T21	2
auto[BaudRate115200]	freqs[50]	58	1			T128	3		T210	1		T336	18
auto[BaudRate115200]	freqs[100]	149	1			T30	6		T42	1		T285	1
auto[BaudRate230400]	freqs[24]	207	1			T7	3		T10	1		T271	2
auto[BaudRate230400]	freqs[25]	246	1			T13	3		T20	9		T276	1
auto[BaudRate230400]	freqs[48]	92	1			T38	1		T12	16		T21	2
auto[BaudRate230400]	freqs[50]	42	1			T331	1		T210	2		T336	4
auto[BaudRate230400]	freqs[100]	156	1			T30	7		T42	1		T285	1
auto[BaudRate128Kbps]	freqs[24]	217	1			T7	3		T10	2		T271	4
auto[BaudRate128Kbps]	freqs[25]	231	1			T13	6		T20	10		T276	2
auto[BaudRate128Kbps]	freqs[48]	103	1			T38	1		T12	8		T21	5
auto[BaudRate128Kbps]	freqs[50]	73	1			T128	1		T331	1		T226	2
auto[BaudRate128Kbps]	freqs[100]	125	1			T42	1		T285	1		T189	2
auto[BaudRate256Kbps]	freqs[24]	247	1			T7	3		T43	4		T338	1
auto[BaudRate256Kbps]	freqs[25]	227	1			T8	3		T13	6		T20	9
auto[BaudRate256Kbps]	freqs[48]	104	1			T38	1		T12	12		T21	1
auto[BaudRate256Kbps]	freqs[50]	59	1			T275	3		T331	2		T226	2
auto[BaudRate256Kbps]	freqs[100]	152	1			T30	3		T42	1		T285	2
auto[BaudRate1Mbps]	freqs[24]	240	1			T10	2		T43	3		T271	2
auto[BaudRate1Mbps]	freqs[25]	195	1			T8	4		T13	8		T20	5
auto[BaudRate1Mbps]	freqs[48]	85	1			T12	8		T21	1		T204	1
auto[BaudRate1Mbps]	freqs[50]	63	1			T275	4		T331	4		T210	1
auto[BaudRate1Mbps]	freqs[100]	153	1			T2	1		T30	11		T42	3
auto[BaudRate1p5Mbps]	freqs[25]	123	1			T8	2		T20	14		T279	2
auto[BaudRate1p5Mbps]	freqs[48]	96	1			T12	9		T21	1		T204	2
auto[BaudRate1p5Mbps]	freqs[50]	64	1			T331	1		T226	1		T210	1
auto[BaudRate1p5Mbps]	freqs[100]	201	1			T2	1		T30	9		T42	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded