Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31675875	1			T1	208		T3	45		T4	44075
all_levels[1]	191083	1			T1	55		T3	3		T4	3620
all_levels[2]	2596	1			T1	9		T3	1		T8	11
all_levels[3]	1098	1			T3	2		T19	5		T11	1
all_levels[4]	711	1			T3	2		T17	2		T19	4
all_levels[5]	508	1			T1	1		T17	2		T38	2
all_levels[6]	461	1			T1	1		T3	3		T17	2
all_levels[7]	352	1			T1	1		T3	1		T17	2
all_levels[8]	303	1			T1	2		T3	1		T17	2
all_levels[9]	282	1			T120	2		T12	3		T133	1
all_levels[10]	252	1			T3	1		T17	1		T34	1
all_levels[11]	225	1			T1	2		T17	2		T34	1
all_levels[12]	192	1			T33	2		T120	1		T20	1
all_levels[13]	149	1			T3	1		T134	1		T16	1
all_levels[14]	162	1			T3	1		T17	3		T13	1
all_levels[15]	115	1			T17	1		T135	1		T124	1
all_levels[16]	115	1			T17	1		T34	1		T16	1
all_levels[17]	108	1			T1	1		T3	1		T13	3
all_levels[18]	103	1			T1	1		T3	1		T17	1
all_levels[19]	95	1			T3	2		T124	1		T31	1
all_levels[20]	89	1			T133	1		T135	1		T124	1
all_levels[21]	80	1			T17	1		T12	3		T20	1
all_levels[22]	78	1			T1	3		T34	1		T20	1
all_levels[23]	65	1			T127	1		T126	1		T136	2
all_levels[24]	60	1			T3	1		T11	1		T137	1
all_levels[25]	62	1			T11	1		T14	1		T124	1
all_levels[26]	44	1			T17	1		T12	1		T135	1
all_levels[27]	52	1			T1	1		T133	1		T138	1
all_levels[28]	51	1			T1	1		T134	1		T16	1
all_levels[29]	41	1			T31	1		T139	1		T123	1
all_levels[30]	33	1			T140	1		T141	1		T142	1
all_levels[31]	44	1			T18	1		T20	1		T137	1
all_levels[32]	36	1			T134	1		T12	1		T126	1
all_levels[33]	32	1			T16	1		T143	2		T112	1
all_levels[34]	41	1			T144	1		T145	3		T146	1
all_levels[35]	27	1			T135	1		T147	1		T148	1
all_levels[36]	27	1			T1	1		T18	1		T149	1
all_levels[37]	28	1			T17	1		T34	1		T115	1
all_levels[38]	27	1			T11	1		T137	1		T150	1
all_levels[39]	24	1			T151	1		T152	1		T114	1
all_levels[40]	22	1			T153	1		T154	2		T155	1
all_levels[41]	27	1			T12	1		T127	1		T123	1
all_levels[42]	22	1			T42	1		T126	1		T132	1
all_levels[43]	15	1			T138	1		T114	1		T156	1
all_levels[44]	24	1			T17	1		T135	6		T132	1
all_levels[45]	17	1			T1	1		T146	1		T157	1
all_levels[46]	14	1			T134	1		T158	1		T114	1
all_levels[47]	16	1			T47	1		T140	1		T155	1
all_levels[48]	12	1			T127	1		T123	1		T159	1
all_levels[49]	16	1			T49	2		T160	1		T161	1
all_levels[50]	18	1			T162	1		T163	1		T50	1
all_levels[51]	17	1			T3	1		T49	2		T153	1
all_levels[52]	10	1			T164	1		T165	1		T166	4
all_levels[53]	14	1			T167	1		T153	1		T168	2
all_levels[54]	16	1			T21	1		T42	1		T169	1
all_levels[55]	7	1			T170	1		T171	1		T172	1
all_levels[56]	15	1			T46	1		T152	1		T156	1
all_levels[57]	13	1			T13	1		T31	1		T173	1
all_levels[58]	11	1			T31	1		T174	2		T175	1
all_levels[59]	9	1			T176	3		T173	1		T177	1
all_levels[60]	10	1			T178	1		T179	1		T180	1
all_levels[61]	9	1			T181	1		T182	1		T183	1
all_levels[62]	8	1			T140	1		T161	2		T184	3
all_levels[63]	14	1			T18	1		T20	1		T138	2
all_levels[64]	119	1			T3	1		T11	2		T122	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31871178

1

T1

288

T3

68

T4

47695

auto[1]

5023

1

T17

7

T18

7

T19

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[30] , all_levels[31]]	[auto[1]]	--	--	2
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[45] , all_levels[46]]	[auto[1]]	--	--	2
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31671348	1			T1	208		T3	45		T4	44075
all_levels[0]	auto[1]	4527	1			T17	7		T18	7		T19	6
all_levels[1]	auto[0]	190994	1			T1	55		T3	3		T4	3620
all_levels[1]	auto[1]	89	1			T35	2		T39	1		T120	1
all_levels[2]	auto[0]	2568	1			T1	9		T3	1		T8	11
all_levels[2]	auto[1]	28	1			T185	1		T186	1		T187	1
all_levels[3]	auto[0]	1079	1			T3	2		T19	5		T11	1
all_levels[3]	auto[1]	19	1			T188	1		T174	1		T152	3
all_levels[4]	auto[0]	675	1			T3	2		T17	2		T19	4
all_levels[4]	auto[1]	36	1			T39	1		T122	2		T189	2
all_levels[5]	auto[0]	494	1			T1	1		T17	2		T38	2
all_levels[5]	auto[1]	14	1			T142	1		T190	1		T191	2
all_levels[6]	auto[0]	432	1			T1	1		T3	3		T17	2
all_levels[6]	auto[1]	29	1			T192	1		T193	1		T194	2
all_levels[7]	auto[0]	341	1			T1	1		T3	1		T17	2
all_levels[7]	auto[1]	11	1			T195	2		T196	2		T197	2
all_levels[8]	auto[0]	287	1			T1	2		T3	1		T17	2
all_levels[8]	auto[1]	16	1			T146	2		T192	3		T198	1
all_levels[9]	auto[0]	271	1			T120	2		T12	3		T133	1
all_levels[9]	auto[1]	11	1			T114	5		T199	1		T200	2
all_levels[10]	auto[0]	242	1			T3	1		T17	1		T34	1
all_levels[10]	auto[1]	10	1			T201	1		T202	2		T203	1
all_levels[11]	auto[0]	212	1			T1	2		T17	2		T34	1
all_levels[11]	auto[1]	13	1			T137	1		T204	1		T205	1
all_levels[12]	auto[0]	182	1			T33	1		T120	1		T20	1
all_levels[12]	auto[1]	10	1			T33	1		T47	4		T206	1
all_levels[13]	auto[0]	145	1			T3	1		T134	1		T16	1
all_levels[13]	auto[1]	4	1			T207	2		T208	1		T209	1
all_levels[14]	auto[0]	150	1			T3	1		T17	3		T13	1
all_levels[14]	auto[1]	12	1			T65	1		T210	1		T148	1
all_levels[15]	auto[0]	108	1			T17	1		T135	1		T124	1
all_levels[15]	auto[1]	7	1			T211	2		T142	1		T212	1
all_levels[16]	auto[0]	109	1			T17	1		T34	1		T16	1
all_levels[16]	auto[1]	6	1			T137	1		T50	2		T213	1
all_levels[17]	auto[0]	93	1			T1	1		T3	1		T13	1
all_levels[17]	auto[1]	15	1			T13	2		T204	4		T192	1
all_levels[18]	auto[0]	97	1			T1	1		T3	1		T17	1
all_levels[18]	auto[1]	6	1			T39	1		T214	1		T52	1
all_levels[19]	auto[0]	89	1			T3	2		T124	1		T31	1
all_levels[19]	auto[1]	6	1			T109	1		T116	1		T215	1
all_levels[20]	auto[0]	79	1			T133	1		T135	1		T124	1
all_levels[20]	auto[1]	10	1			T199	1		T216	1		T217	2
all_levels[21]	auto[0]	69	1			T17	1		T12	3		T20	1
all_levels[21]	auto[1]	11	1			T188	4		T218	1		T219	1
all_levels[22]	auto[0]	74	1			T1	3		T34	1		T20	1
all_levels[22]	auto[1]	4	1			T109	1		T202	1		T220	1
all_levels[23]	auto[0]	57	1			T127	1		T126	1		T136	1
all_levels[23]	auto[1]	8	1			T136	1		T221	3		T220	2
all_levels[24]	auto[0]	56	1			T3	1		T11	1		T137	1
all_levels[24]	auto[1]	4	1			T222	1		T223	1		T224	2
all_levels[25]	auto[0]	57	1			T11	1		T14	1		T124	1
all_levels[25]	auto[1]	5	1			T218	1		T50	1		T225	1
all_levels[26]	auto[0]	41	1			T17	1		T12	1		T135	1
all_levels[26]	auto[1]	3	1			T226	1		T227	1		T228	1
all_levels[27]	auto[0]	50	1			T1	1		T133	1		T138	1
all_levels[27]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[28]	auto[0]	45	1			T1	1		T134	1		T16	1
all_levels[28]	auto[1]	6	1			T135	2		T207	1		T231	1
all_levels[29]	auto[0]	32	1			T31	1		T139	1		T123	1
all_levels[29]	auto[1]	9	1			T116	2		T232	3		T233	1
all_levels[30]	auto[0]	33	1			T140	1		T141	1		T142	1
all_levels[31]	auto[0]	44	1			T18	1		T20	1		T137	1
all_levels[32]	auto[0]	34	1			T134	1		T12	1		T126	1
all_levels[32]	auto[1]	2	1			T193	1		T222	1		-	-
all_levels[33]	auto[0]	31	1			T16	1		T143	1		T112	1
all_levels[33]	auto[1]	1	1			T143	1		-	-		-	-
all_levels[34]	auto[0]	33	1			T144	1		T145	1		T146	1
all_levels[34]	auto[1]	8	1			T145	2		T234	1		T235	5
all_levels[35]	auto[0]	23	1			T135	1		T147	1		T148	1
all_levels[35]	auto[1]	4	1			T236	1		T237	3		-	-
all_levels[36]	auto[0]	26	1			T1	1		T18	1		T149	1
all_levels[36]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[37]	auto[0]	21	1			T17	1		T34	1		T115	1
all_levels[37]	auto[1]	7	1			T239	3		T240	1		T241	3
all_levels[38]	auto[0]	25	1			T11	1		T137	1		T150	1
all_levels[38]	auto[1]	2	1			T242	1		T243	1		-	-
all_levels[39]	auto[0]	23	1			T151	1		T152	1		T114	1
all_levels[39]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[40]	auto[0]	18	1			T153	1		T154	1		T155	1
all_levels[40]	auto[1]	4	1			T154	1		T245	2		T246	1
all_levels[41]	auto[0]	26	1			T12	1		T127	1		T123	1
all_levels[41]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[42]	auto[0]	22	1			T42	1		T126	1		T132	1
all_levels[43]	auto[0]	14	1			T138	1		T114	1		T156	1
all_levels[43]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[44]	auto[0]	18	1			T17	1		T135	1		T132	1
all_levels[44]	auto[1]	6	1			T135	5		T232	1		-	-
all_levels[45]	auto[0]	17	1			T1	1		T146	1		T157	1
all_levels[46]	auto[0]	14	1			T134	1		T158	1		T114	1
all_levels[47]	auto[0]	12	1			T47	1		T140	1		T155	1
all_levels[47]	auto[1]	4	1			T249	1		T250	3		-	-
all_levels[48]	auto[0]	12	1			T127	1		T123	1		T159	1
all_levels[49]	auto[0]	13	1			T49	1		T160	1		T161	1
all_levels[49]	auto[1]	3	1			T49	1		T251	1		T252	1
all_levels[50]	auto[0]	15	1			T162	1		T163	1		T50	1
all_levels[50]	auto[1]	3	1			T253	3		-	-		-	-
all_levels[51]	auto[0]	14	1			T3	1		T49	2		T153	1
all_levels[51]	auto[1]	3	1			T254	1		T255	2		-	-
all_levels[52]	auto[0]	8	1			T164	1		T165	1		T166	2
all_levels[52]	auto[1]	2	1			T166	2		-	-		-	-
all_levels[53]	auto[0]	12	1			T167	1		T153	1		T168	2
all_levels[53]	auto[1]	2	1			T256	2		-	-		-	-
all_levels[54]	auto[0]	11	1			T21	1		T42	1		T169	1
all_levels[54]	auto[1]	5	1			T257	2		T258	3		-	-
all_levels[55]	auto[0]	7	1			T170	1		T171	1		T172	1
all_levels[56]	auto[0]	12	1			T46	1		T152	1		T156	1
all_levels[56]	auto[1]	3	1			T259	1		T260	2		-	-
all_levels[57]	auto[0]	12	1			T13	1		T31	1		T173	1
all_levels[57]	auto[1]	1	1			T261	1		-	-		-	-
all_levels[58]	auto[0]	7	1			T31	1		T174	1		T175	1
all_levels[58]	auto[1]	4	1			T174	1		T262	1		T222	2
all_levels[59]	auto[0]	7	1			T176	1		T173	1		T177	1
all_levels[59]	auto[1]	2	1			T176	2		-	-		-	-
all_levels[60]	auto[0]	7	1			T178	1		T179	1		T180	1
all_levels[60]	auto[1]	3	1			T263	3		-	-		-	-
all_levels[61]	auto[0]	6	1			T181	1		T182	1		T183	1
all_levels[61]	auto[1]	3	1			T264	3		-	-		-	-
all_levels[62]	auto[0]	5	1			T140	1		T161	1		T184	1
all_levels[62]	auto[1]	3	1			T161	1		T184	2		-	-
all_levels[63]	auto[0]	14	1			T18	1		T20	1		T138	2
all_levels[64]	auto[0]	106	1			T3	1		T11	2		T122	1
all_levels[64]	auto[1]	13	1			T172	2		T265	1		T266	1