Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	110381	1			T1	64		T2	2		T3	18
all_pins[1]	110381	1			T1	64		T2	2		T3	18
all_pins[2]	110381	1			T1	64		T2	2		T3	18
all_pins[3]	110381	1			T1	64		T2	2		T3	18
all_pins[4]	110381	1			T1	64		T2	2		T3	18
all_pins[5]	110381	1			T1	64		T2	2		T3	18
all_pins[6]	110381	1			T1	64		T2	2		T3	18
all_pins[7]	110381	1			T1	64		T2	2		T3	18
all_pins[8]	110381	1			T1	64		T2	2		T3	18

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	944024	1			T1	534		T2	18		T3	127
values[0x1]	49405	1			T1	42		T3	35		T4	9
transitions[0x0=>0x1]	38585	1			T1	29		T3	27		T4	9
transitions[0x1=>0x0]	38368	1			T1	28		T3	26		T4	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	87252	1			T1	51		T2	2		T3	2
all_pins[0]	values[0x1]	23129	1			T1	13		T3	16		T4	3
all_pins[0]	transitions[0x0=>0x1]	22523	1			T1	13		T3	16		T4	3
all_pins[0]	transitions[0x1=>0x0]	1153	1			T13	1		T12	23		T21	6
all_pins[1]	values[0x0]	108622	1			T1	64		T2	2		T3	18
all_pins[1]	values[0x1]	1759	1			T13	1		T12	24		T20	2
all_pins[1]	transitions[0x0=>0x1]	1651	1			T12	24		T20	2		T21	8
all_pins[1]	transitions[0x1=>0x0]	2513	1			T1	6		T3	4		T4	4
all_pins[2]	values[0x0]	107760	1			T1	58		T2	2		T3	14
all_pins[2]	values[0x1]	2621	1			T1	6		T3	4		T4	4
all_pins[2]	transitions[0x0=>0x1]	2537	1			T1	6		T3	3		T4	4
all_pins[2]	transitions[0x1=>0x0]	287	1			T3	1		T13	2		T12	2
all_pins[3]	values[0x0]	110010	1			T1	64		T2	2		T3	16
all_pins[3]	values[0x1]	371	1			T3	2		T13	2		T12	2
all_pins[3]	transitions[0x0=>0x1]	326	1			T3	2		T13	2		T12	2
all_pins[3]	transitions[0x1=>0x0]	477	1			T14	5		T13	2		T12	12
all_pins[4]	values[0x0]	109859	1			T1	64		T2	2		T3	18
all_pins[4]	values[0x1]	522	1			T14	5		T13	2		T12	12
all_pins[4]	transitions[0x0=>0x1]	453	1			T14	4		T13	2		T12	7
all_pins[4]	transitions[0x1=>0x0]	192	1			T12	1		T20	1		T31	3
all_pins[5]	values[0x0]	110120	1			T1	64		T2	2		T3	18
all_pins[5]	values[0x1]	261	1			T14	1		T12	6		T20	1
all_pins[5]	transitions[0x0=>0x1]	201	1			T14	1		T12	4		T20	1
all_pins[5]	transitions[0x1=>0x0]	889	1			T13	6		T39	1		T20	24
all_pins[6]	values[0x0]	109432	1			T1	64		T2	2		T3	18
all_pins[6]	values[0x1]	949	1			T13	6		T39	1		T12	2
all_pins[6]	transitions[0x0=>0x1]	886	1			T13	2		T39	1		T12	2
all_pins[6]	transitions[0x1=>0x0]	403	1			T1	8		T3	6		T11	1
all_pins[7]	values[0x0]	109915	1			T1	56		T2	2		T3	12
all_pins[7]	values[0x1]	466	1			T1	8		T3	6		T11	1
all_pins[7]	transitions[0x0=>0x1]	271	1			T1	6		T3	6		T11	1
all_pins[7]	transitions[0x1=>0x0]	19132	1			T1	13		T3	7		T4	2
all_pins[8]	values[0x0]	91054	1			T1	49		T2	2		T3	11
all_pins[8]	values[0x1]	19327	1			T1	15		T3	7		T4	2
all_pins[8]	transitions[0x0=>0x1]	9737	1			T1	4		T4	2		T7	1
all_pins[8]	transitions[0x1=>0x0]	13322	1			T1	1		T3	8		T4	3