Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7928738	1			T1	154		T3	63		T4	8238
all_levels[1]	1648012	1			T1	2		T3	2		T4	45
all_levels[2]	327407	1			T1	7		T4	45		T6	87
all_levels[3]	474034	1			T4	36		T6	85		T7	1532
all_levels[4]	315678	1			T1	1		T3	1		T4	41
all_levels[5]	326989	1			T1	4		T4	40		T6	90
all_levels[6]	225308	1			T4	47		T6	86		T7	1531
all_levels[7]	263877	1			T1	1		T4	45		T6	104
all_levels[8]	340119	1			T1	8		T4	35		T6	89
all_levels[9]	219019	1			T1	5		T4	47		T6	98
all_levels[10]	220167	1			T1	4		T4	45		T6	107
all_levels[11]	258642	1			T1	6		T3	2		T4	37
all_levels[12]	215387	1			T1	3		T4	48		T6	98
all_levels[13]	386533	1			T1	7		T4	44		T6	84
all_levels[14]	611513	1			T1	13		T4	39		T6	97
all_levels[15]	201087	1			T1	4		T4	32		T6	91
all_levels[16]	274418	1			T1	2		T4	41		T6	74
all_levels[17]	216040	1			T1	5		T4	40		T6	89
all_levels[18]	354407	1			T1	2		T4	47		T6	99
all_levels[19]	392358	1			T1	2		T4	38		T6	67
all_levels[20]	207944	1			T1	5		T4	34		T6	105
all_levels[21]	253054	1			T1	3		T4	44		T6	82
all_levels[22]	195896	1			T1	2		T4	45		T6	83
all_levels[23]	289295	1			T1	1		T4	40		T6	93
all_levels[24]	342490	1			T4	34		T6	83		T7	1016
all_levels[25]	353588	1			T1	2		T4	43		T6	75
all_levels[26]	503828	1			T1	7		T4	42		T6	99
all_levels[27]	217577	1			T1	8		T4	46		T6	88
all_levels[28]	231148	1			T1	3		T4	39		T6	103
all_levels[29]	226370	1			T1	3		T4	38		T6	94
all_levels[30]	251893	1			T1	4		T4	41		T6	87
all_levels[31]	565977	1			T1	4		T4	1029		T6	2174
all_levels[32]	13036908	1			T1	16		T4	37192		T6	31889

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31871178

1

T1

288

T3

68

T4

47695

auto[1]

4523

1

T4

2

T7

1

T8

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7926013	1			T1	154		T3	63		T4	8238
all_levels[0]	auto[1]	2725	1			T17	2		T18	3		T11	1
all_levels[1]	auto[0]	1647669	1			T1	2		T3	2		T4	45
all_levels[1]	auto[1]	343	1			T17	6		T18	3		T19	4
all_levels[2]	auto[0]	327361	1			T1	7		T4	45		T6	87
all_levels[2]	auto[1]	46	1			T7	1		T18	1		T290	1
all_levels[3]	auto[0]	473911	1			T4	36		T6	85		T7	1532
all_levels[3]	auto[1]	123	1			T127	1		T282	28		T144	1
all_levels[4]	auto[0]	315651	1			T1	1		T3	1		T4	41
all_levels[4]	auto[1]	27	1			T39	1		T31	2		T340	1
all_levels[5]	auto[0]	326971	1			T1	4		T4	40		T6	90
all_levels[5]	auto[1]	18	1			T281	3		T42	1		T301	1
all_levels[6]	auto[0]	225279	1			T4	47		T6	86		T7	1531
all_levels[6]	auto[1]	29	1			T34	1		T29	3		T137	1
all_levels[7]	auto[0]	263738	1			T1	1		T4	45		T6	104
all_levels[7]	auto[1]	139	1			T12	1		T136	1		T129	2
all_levels[8]	auto[0]	340095	1			T1	8		T4	35		T6	89
all_levels[8]	auto[1]	24	1			T39	1		T132	1		T288	1
all_levels[9]	auto[0]	218995	1			T1	5		T4	47		T6	98
all_levels[9]	auto[1]	24	1			T277	1		T62	1		T154	1
all_levels[10]	auto[0]	220146	1			T1	4		T4	45		T6	107
all_levels[10]	auto[1]	21	1			T33	2		T149	1		T49	1
all_levels[11]	auto[0]	258620	1			T1	6		T3	2		T4	37
all_levels[11]	auto[1]	22	1			T188	4		T174	3		T62	1
all_levels[12]	auto[0]	215352	1			T1	3		T4	48		T6	98
all_levels[12]	auto[1]	35	1			T286	2		T274	1		T293	1
all_levels[13]	auto[0]	386521	1			T1	7		T4	44		T6	84
all_levels[13]	auto[1]	12	1			T47	1		T149	3		T341	2
all_levels[14]	auto[0]	611493	1			T1	13		T4	39		T6	97
all_levels[14]	auto[1]	20	1			T31	1		T65	1		T182	1
all_levels[15]	auto[0]	201025	1			T1	4		T4	32		T6	91
all_levels[15]	auto[1]	62	1			T35	2		T39	1		T282	1
all_levels[16]	auto[0]	274406	1			T1	2		T4	41		T6	74
all_levels[16]	auto[1]	12	1			T144	1		T210	1		T326	1
all_levels[17]	auto[0]	216021	1			T1	5		T4	40		T6	89
all_levels[17]	auto[1]	19	1			T42	1		T148	1		T342	2
all_levels[18]	auto[0]	354382	1			T1	2		T4	47		T6	99
all_levels[18]	auto[1]	25	1			T42	2		T271	1		T331	2
all_levels[19]	auto[0]	392341	1			T1	2		T4	38		T6	67
all_levels[19]	auto[1]	17	1			T143	1		T343	1		T344	1
all_levels[20]	auto[0]	207928	1			T1	5		T4	34		T6	105
all_levels[20]	auto[1]	16	1			T269	2		T299	1		T254	2
all_levels[21]	auto[0]	253040	1			T1	3		T4	44		T6	82
all_levels[21]	auto[1]	14	1			T192	1		T309	1		T345	1
all_levels[22]	auto[0]	195873	1			T1	2		T4	45		T6	83
all_levels[22]	auto[1]	23	1			T149	1		T346	1		T183	1
all_levels[23]	auto[0]	289281	1			T1	1		T4	40		T6	93
all_levels[23]	auto[1]	14	1			T35	1		T151	1		T347	3
all_levels[24]	auto[0]	342466	1			T4	34		T6	83		T7	1016
all_levels[24]	auto[1]	24	1			T204	1		T47	4		T348	4
all_levels[25]	auto[0]	353566	1			T1	2		T4	43		T6	75
all_levels[25]	auto[1]	22	1			T19	3		T122	3		T146	1
all_levels[26]	auto[0]	503807	1			T1	7		T4	42		T6	99
all_levels[26]	auto[1]	21	1			T34	1		T31	1		T226	2
all_levels[27]	auto[0]	217556	1			T1	8		T4	46		T6	88
all_levels[27]	auto[1]	21	1			T349	2		T350	1		T351	2
all_levels[28]	auto[0]	231134	1			T1	3		T4	39		T6	103
all_levels[28]	auto[1]	14	1			T119	1		T149	1		T352	1
all_levels[29]	auto[0]	226360	1			T1	3		T4	38		T6	94
all_levels[29]	auto[1]	10	1			T202	1		T172	1		T117	3
all_levels[30]	auto[0]	251873	1			T1	4		T4	41		T6	87
all_levels[30]	auto[1]	20	1			T332	1		T330	1		T112	1
all_levels[31]	auto[0]	565957	1			T1	4		T4	1029		T6	2174
all_levels[31]	auto[1]	20	1			T353	1		T354	5		T355	2
all_levels[32]	auto[0]	13036347	1			T1	16		T4	37190		T6	31889
all_levels[32]	auto[1]	561	1			T4	2		T8	1		T17	1