Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	936	1			T13	7		T12	14		T20	11
all_values[1]	936	1			T13	7		T12	14		T20	11
all_values[2]	936	1			T13	7		T12	14		T20	11
all_values[3]	936	1			T13	7		T12	14		T20	11
all_values[4]	936	1			T13	7		T12	14		T20	11
all_values[5]	936	1			T13	7		T12	14		T20	11
all_values[6]	936	1			T13	7		T12	14		T20	11
all_values[7]	936	1			T13	7		T12	14		T20	11
all_values[8]	936	1			T13	7		T12	14		T20	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4519

1

T13

35

T12

67

T20

62

auto[1]

3905

1

T13

28

T12

59

T20

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2828

1

T13

14

T12

46

T20

40

auto[1]

5596

1

T13

49

T12

80

T20

59

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4974

1

T13

34

T12

70

T20

64

auto[1]

3450

1

T13

29

T12

56

T20

35

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	300	1			T13	1		T12	6		T20	4
all_values[0]	auto[0]	auto[1]	auto[1]	241	1			T13	1		T12	3		T20	4
all_values[0]	auto[1]	auto[0]	auto[1]	226	1			T13	2		T12	3		T20	1
all_values[0]	auto[1]	auto[1]	auto[1]	169	1			T13	3		T12	2		T20	2
all_values[1]	auto[0]	auto[0]	auto[0]	266	1			T13	1		T12	6		T20	7
all_values[1]	auto[0]	auto[1]	auto[0]	271	1			T13	3		T12	4		T20	1
all_values[1]	auto[1]	auto[0]	auto[1]	217	1			T13	3		T12	3		T20	3
all_values[1]	auto[1]	auto[1]	auto[1]	182	1			T12	1		T21	1		T32	1
all_values[2]	auto[0]	auto[0]	auto[0]	218	1			T13	2		T12	2		T20	4
all_values[2]	auto[0]	auto[0]	auto[1]	88	1			T13	3		T12	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	193	1			T12	6		T20	3		T21	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T32	1		T49	2		T131	1
all_values[2]	auto[1]	auto[0]	auto[1]	199	1			T13	1		T12	1		T20	3
all_values[2]	auto[1]	auto[1]	auto[1]	155	1			T13	1		T12	4		T31	1
all_values[3]	auto[0]	auto[0]	auto[0]	204	1			T12	5		T20	1		T21	2
all_values[3]	auto[0]	auto[0]	auto[1]	93	1			T13	3		T20	1		T132	1
all_values[3]	auto[0]	auto[1]	auto[0]	171	1			T12	3		T20	1		T21	2
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T13	1		T20	2		T132	1
all_values[3]	auto[1]	auto[0]	auto[1]	208	1			T12	2		T20	3		T31	2
all_values[3]	auto[1]	auto[1]	auto[1]	179	1			T13	3		T12	4		T20	3
all_values[4]	auto[0]	auto[0]	auto[0]	231	1			T13	3		T12	2		T20	3
all_values[4]	auto[0]	auto[0]	auto[1]	93	1			T20	2		T21	1		T132	1
all_values[4]	auto[0]	auto[1]	auto[0]	178	1			T13	1		T12	4		T20	2
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T13	1		T12	3		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	192	1			T13	2		T12	2		T20	1
all_values[4]	auto[1]	auto[1]	auto[1]	158	1			T12	3		T20	2		T21	3
all_values[5]	auto[0]	auto[0]	auto[0]	203	1			T13	1		T12	3		T20	7
all_values[5]	auto[0]	auto[0]	auto[1]	92	1			T13	2		T12	1		T31	2
all_values[5]	auto[0]	auto[1]	auto[0]	155	1			T20	1		T21	4		T132	1
all_values[5]	auto[0]	auto[1]	auto[1]	91	1			T12	2		T31	1		T132	1
all_values[5]	auto[1]	auto[0]	auto[1]	232	1			T13	3		T12	4		T20	3
all_values[5]	auto[1]	auto[1]	auto[1]	163	1			T13	1		T12	4		T132	1
all_values[6]	auto[0]	auto[0]	auto[0]	193	1			T12	7		T20	3		T31	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T31	2		T132	1		T49	2
all_values[6]	auto[0]	auto[1]	auto[0]	165	1			T13	1		T20	2		T21	1
all_values[6]	auto[0]	auto[1]	auto[1]	95	1			T13	1		T12	1		T20	2
all_values[6]	auto[1]	auto[0]	auto[1]	193	1			T13	1		T12	4		T20	2
all_values[6]	auto[1]	auto[1]	auto[1]	207	1			T13	4		T12	2		T20	2
all_values[7]	auto[0]	auto[0]	auto[0]	200	1			T13	2		T12	3		T20	3
all_values[7]	auto[0]	auto[0]	auto[1]	93	1			T21	1		T32	2		T132	3
all_values[7]	auto[0]	auto[1]	auto[0]	180	1			T12	1		T20	2		T31	2
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T13	2		T12	3		T20	2
all_values[7]	auto[1]	auto[0]	auto[1]	202	1			T12	3		T20	1		T21	2
all_values[7]	auto[1]	auto[1]	auto[1]	180	1			T13	3		T12	4		T20	3
all_values[8]	auto[0]	auto[0]	auto[1]	290	1			T13	4		T12	3		T20	4
all_values[8]	auto[0]	auto[1]	auto[1]	258	1			T13	1		T12	1		T20	1
all_values[8]	auto[1]	auto[0]	auto[1]	203	1			T13	1		T12	6		T20	5
all_values[8]	auto[1]	auto[1]	auto[1]	185	1			T13	1		T12	4		T20	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal