Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.59


Total test records in report: 1316
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T1254 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.16366221 Jul 14 04:53:18 PM PDT 24 Jul 14 04:53:19 PM PDT 24 63283827 ps
T1255 /workspace/coverage/cover_reg_top/12.uart_csr_rw.4165125156 Jul 14 04:53:26 PM PDT 24 Jul 14 04:53:27 PM PDT 24 16106246 ps
T1256 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4243042110 Jul 14 04:53:26 PM PDT 24 Jul 14 04:53:28 PM PDT 24 30047770 ps
T1257 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3747589930 Jul 14 04:53:16 PM PDT 24 Jul 14 04:53:17 PM PDT 24 48506876 ps
T1258 /workspace/coverage/cover_reg_top/36.uart_intr_test.2958688399 Jul 14 04:53:39 PM PDT 24 Jul 14 04:53:41 PM PDT 24 35020980 ps
T1259 /workspace/coverage/cover_reg_top/15.uart_csr_rw.369902754 Jul 14 04:53:27 PM PDT 24 Jul 14 04:53:28 PM PDT 24 16275702 ps
T1260 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4054848294 Jul 14 04:53:33 PM PDT 24 Jul 14 04:53:35 PM PDT 24 17216392 ps
T1261 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1337353979 Jul 14 04:53:05 PM PDT 24 Jul 14 04:53:09 PM PDT 24 218048738 ps
T1262 /workspace/coverage/cover_reg_top/35.uart_intr_test.4241800245 Jul 14 04:53:39 PM PDT 24 Jul 14 04:53:40 PM PDT 24 16441369 ps
T1263 /workspace/coverage/cover_reg_top/16.uart_intr_test.567256474 Jul 14 04:53:35 PM PDT 24 Jul 14 04:53:36 PM PDT 24 90101387 ps
T1264 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3099772166 Jul 14 04:53:25 PM PDT 24 Jul 14 04:53:27 PM PDT 24 65982439 ps
T1265 /workspace/coverage/cover_reg_top/34.uart_intr_test.230014457 Jul 14 04:53:41 PM PDT 24 Jul 14 04:53:42 PM PDT 24 68813024 ps
T70 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1185372418 Jul 14 04:53:05 PM PDT 24 Jul 14 04:53:08 PM PDT 24 408526002 ps
T1266 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.255164273 Jul 14 04:53:33 PM PDT 24 Jul 14 04:53:34 PM PDT 24 28949887 ps
T1267 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2396192356 Jul 14 04:53:25 PM PDT 24 Jul 14 04:53:27 PM PDT 24 46367104 ps
T1268 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2342181702 Jul 14 04:53:12 PM PDT 24 Jul 14 04:53:14 PM PDT 24 259793696 ps
T1269 /workspace/coverage/cover_reg_top/27.uart_intr_test.2268019004 Jul 14 04:53:40 PM PDT 24 Jul 14 04:53:42 PM PDT 24 43051905 ps
T1270 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2375884917 Jul 14 04:52:52 PM PDT 24 Jul 14 04:52:54 PM PDT 24 30811404 ps
T1271 /workspace/coverage/cover_reg_top/29.uart_intr_test.546056577 Jul 14 04:53:40 PM PDT 24 Jul 14 04:53:42 PM PDT 24 13828525 ps
T1272 /workspace/coverage/cover_reg_top/3.uart_tl_errors.7365887 Jul 14 04:52:59 PM PDT 24 Jul 14 04:53:01 PM PDT 24 378943906 ps
T1273 /workspace/coverage/cover_reg_top/7.uart_csr_rw.712820107 Jul 14 04:53:13 PM PDT 24 Jul 14 04:53:14 PM PDT 24 31011811 ps
T1274 /workspace/coverage/cover_reg_top/13.uart_tl_errors.822792604 Jul 14 04:53:26 PM PDT 24 Jul 14 04:53:29 PM PDT 24 246852556 ps
T1275 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.585710528 Jul 14 04:52:58 PM PDT 24 Jul 14 04:52:59 PM PDT 24 21365524 ps
T1276 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1358915242 Jul 14 04:53:18 PM PDT 24 Jul 14 04:53:19 PM PDT 24 48383568 ps
T1277 /workspace/coverage/cover_reg_top/13.uart_intr_test.212748211 Jul 14 04:53:25 PM PDT 24 Jul 14 04:53:26 PM PDT 24 16308870 ps
T1278 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1515489259 Jul 14 04:53:33 PM PDT 24 Jul 14 04:53:35 PM PDT 24 91636903 ps
T1279 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3090730209 Jul 14 04:52:58 PM PDT 24 Jul 14 04:53:01 PM PDT 24 60598855 ps
T1280 /workspace/coverage/cover_reg_top/30.uart_intr_test.2392135870 Jul 14 04:53:41 PM PDT 24 Jul 14 04:53:43 PM PDT 24 15333036 ps
T1281 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1096430233 Jul 14 04:52:52 PM PDT 24 Jul 14 04:52:54 PM PDT 24 55197521 ps
T82 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3060157885 Jul 14 04:53:09 PM PDT 24 Jul 14 04:53:10 PM PDT 24 116320460 ps
T1282 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1996736099 Jul 14 04:53:33 PM PDT 24 Jul 14 04:53:35 PM PDT 24 99492047 ps
T1283 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3393320637 Jul 14 04:52:58 PM PDT 24 Jul 14 04:53:00 PM PDT 24 11107126 ps
T1284 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1899877618 Jul 14 04:53:06 PM PDT 24 Jul 14 04:53:07 PM PDT 24 16505068 ps
T1285 /workspace/coverage/cover_reg_top/16.uart_tl_errors.82003275 Jul 14 04:53:25 PM PDT 24 Jul 14 04:53:28 PM PDT 24 81554583 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2233483951 Jul 14 04:52:50 PM PDT 24 Jul 14 04:52:52 PM PDT 24 19012175 ps
T1287 /workspace/coverage/cover_reg_top/2.uart_tl_errors.925016191 Jul 14 04:52:58 PM PDT 24 Jul 14 04:53:01 PM PDT 24 372370702 ps
T1288 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2652115697 Jul 14 04:52:57 PM PDT 24 Jul 14 04:52:59 PM PDT 24 364383037 ps
T99 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3471349640 Jul 14 04:53:39 PM PDT 24 Jul 14 04:53:40 PM PDT 24 175308489 ps
T1289 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1492054557 Jul 14 04:53:06 PM PDT 24 Jul 14 04:53:09 PM PDT 24 32386794 ps
T1290 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3425826755 Jul 14 04:52:58 PM PDT 24 Jul 14 04:52:59 PM PDT 24 50932111 ps
T1291 /workspace/coverage/cover_reg_top/32.uart_intr_test.1861879175 Jul 14 04:53:42 PM PDT 24 Jul 14 04:53:43 PM PDT 24 11147254 ps
T1292 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2762245879 Jul 14 04:53:12 PM PDT 24 Jul 14 04:53:14 PM PDT 24 24797837 ps
T1293 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3446426272 Jul 14 04:52:52 PM PDT 24 Jul 14 04:52:55 PM PDT 24 11817429 ps
T1294 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1387020574 Jul 14 04:53:33 PM PDT 24 Jul 14 04:53:35 PM PDT 24 14707050 ps
T1295 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3899294036 Jul 14 04:53:39 PM PDT 24 Jul 14 04:53:40 PM PDT 24 32809436 ps
T1296 /workspace/coverage/cover_reg_top/5.uart_intr_test.3311574254 Jul 14 04:53:06 PM PDT 24 Jul 14 04:53:07 PM PDT 24 16068964 ps
T1297 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1200786444 Jul 14 04:53:25 PM PDT 24 Jul 14 04:53:27 PM PDT 24 21625562 ps
T1298 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3331575018 Jul 14 04:53:13 PM PDT 24 Jul 14 04:53:14 PM PDT 24 23987912 ps
T1299 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1134193732 Jul 14 04:53:13 PM PDT 24 Jul 14 04:53:15 PM PDT 24 33357393 ps
T1300 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2199470324 Jul 14 04:53:33 PM PDT 24 Jul 14 04:53:36 PM PDT 24 123192820 ps
T1301 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.342478024 Jul 14 04:53:12 PM PDT 24 Jul 14 04:53:14 PM PDT 24 75371611 ps
T1302 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1724321466 Jul 14 04:53:39 PM PDT 24 Jul 14 04:53:40 PM PDT 24 26016758 ps
T1303 /workspace/coverage/cover_reg_top/44.uart_intr_test.337271070 Jul 14 04:53:40 PM PDT 24 Jul 14 04:53:42 PM PDT 24 13997092 ps
T1304 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3105958111 Jul 14 04:53:04 PM PDT 24 Jul 14 04:53:06 PM PDT 24 43980475 ps
T1305 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3201613074 Jul 14 04:53:19 PM PDT 24 Jul 14 04:53:20 PM PDT 24 42152411 ps
T1306 /workspace/coverage/cover_reg_top/11.uart_intr_test.4139974802 Jul 14 04:53:18 PM PDT 24 Jul 14 04:53:20 PM PDT 24 40860546 ps
T1307 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1318757829 Jul 14 04:52:52 PM PDT 24 Jul 14 04:52:55 PM PDT 24 78763638 ps
T1308 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3604628475 Jul 14 04:52:58 PM PDT 24 Jul 14 04:52:59 PM PDT 24 36645253 ps
T1309 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2692673758 Jul 14 04:53:33 PM PDT 24 Jul 14 04:53:35 PM PDT 24 81418349 ps
T1310 /workspace/coverage/cover_reg_top/7.uart_tl_errors.755524471 Jul 14 04:53:15 PM PDT 24 Jul 14 04:53:17 PM PDT 24 1637529390 ps
T1311 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3454784876 Jul 14 04:52:59 PM PDT 24 Jul 14 04:53:02 PM PDT 24 729970015 ps
T1312 /workspace/coverage/cover_reg_top/8.uart_csr_rw.893832280 Jul 14 04:53:11 PM PDT 24 Jul 14 04:53:12 PM PDT 24 18388652 ps
T1313 /workspace/coverage/cover_reg_top/47.uart_intr_test.1181900141 Jul 14 04:53:45 PM PDT 24 Jul 14 04:53:46 PM PDT 24 12416861 ps
T1314 /workspace/coverage/cover_reg_top/3.uart_intr_test.4034822761 Jul 14 04:52:58 PM PDT 24 Jul 14 04:53:00 PM PDT 24 77180576 ps
T1315 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1627518574 Jul 14 04:53:28 PM PDT 24 Jul 14 04:53:29 PM PDT 24 13829897 ps
T1316 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.177055263 Jul 14 04:53:07 PM PDT 24 Jul 14 04:53:09 PM PDT 24 67142754 ps

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.704995360
Short name T6
Test name
Test status
Simulation time 172912860661 ps
CPU time 382.24 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:32:01 PM PDT 24
Peak memory 199744 kb
Host smart-68629734-a9b9-4028-b799-053909931908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704995360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.704995360
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.384821652
Short name T20
Test name
Test status
Simulation time 409255525685 ps
CPU time 640.39 seconds
Started Jul 14 04:25:40 PM PDT 24
Finished Jul 14 04:36:22 PM PDT 24
Peak memory 224676 kb
Host smart-6a92f011-4f7f-4107-9063-03460132798d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384821652 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.384821652
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1717939993
Short name T12
Test name
Test status
Simulation time 284271930319 ps
CPU time 1065.52 seconds
Started Jul 14 04:26:18 PM PDT 24
Finished Jul 14 04:44:05 PM PDT 24
Peak memory 216312 kb
Host smart-e8e64177-bdff-4efb-81db-e09d49325c27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717939993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1717939993
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3021367401
Short name T31
Test name
Test status
Simulation time 84121330414 ps
CPU time 1022.05 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:41:29 PM PDT 24
Peak memory 216244 kb
Host smart-b0915044-8927-4baf-9ba7-39c9cba751ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021367401 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3021367401
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2712748047
Short name T49
Test name
Test status
Simulation time 547442074998 ps
CPU time 1572.71 seconds
Started Jul 14 04:24:13 PM PDT 24
Finished Jul 14 04:50:27 PM PDT 24
Peak memory 230548 kb
Host smart-ccea9da5-f509-4570-9059-d48aa083972a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712748047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2712748047
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.3992891117
Short name T139
Test name
Test status
Simulation time 333271978169 ps
CPU time 477.74 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:32:32 PM PDT 24
Peak memory 199736 kb
Host smart-f0ff1ca7-ff94-4293-8203-6fe44341ff77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992891117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3992891117
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.4012470934
Short name T14
Test name
Test status
Simulation time 29174173873 ps
CPU time 687.79 seconds
Started Jul 14 04:25:53 PM PDT 24
Finished Jul 14 04:37:21 PM PDT 24
Peak memory 215228 kb
Host smart-8af68611-f057-4b63-8f2d-83a58b95588e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012470934 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.4012470934
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.4006706978
Short name T132
Test name
Test status
Simulation time 696718360172 ps
CPU time 1001.39 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:42:18 PM PDT 24
Peak memory 216156 kb
Host smart-5bf9c158-f459-43f6-b463-6f7c4460aa7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006706978 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4006706978
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3875510810
Short name T26
Test name
Test status
Simulation time 83046005 ps
CPU time 0.73 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:23:37 PM PDT 24
Peak memory 218088 kb
Host smart-dc969dae-d910-468c-98ef-466d27bcebd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875510810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3875510810
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/9.uart_stress_all.2689454847
Short name T268
Test name
Test status
Simulation time 353307966906 ps
CPU time 1409.85 seconds
Started Jul 14 04:23:56 PM PDT 24
Finished Jul 14 04:47:27 PM PDT 24
Peak memory 199720 kb
Host smart-8179e4cb-3ab3-408c-95a4-ad5a80d73e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689454847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2689454847
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2933089965
Short name T1
Test name
Test status
Simulation time 101648427672 ps
CPU time 157.53 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 199716 kb
Host smart-e9d92bb0-f070-4d0a-ace1-43cf4895add1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933089965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2933089965
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2667740381
Short name T46
Test name
Test status
Simulation time 349229534058 ps
CPU time 202.75 seconds
Started Jul 14 04:24:29 PM PDT 24
Finished Jul 14 04:27:53 PM PDT 24
Peak memory 199704 kb
Host smart-3fa8c759-9b01-40aa-97a4-fcb27ffeafbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667740381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2667740381
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.860427510
Short name T140
Test name
Test status
Simulation time 28298607788 ps
CPU time 18.28 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:26:14 PM PDT 24
Peak memory 199748 kb
Host smart-0ebf54af-505a-4839-8164-8bed74c1ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860427510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.860427510
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_stress_all.846395024
Short name T314
Test name
Test status
Simulation time 167351410553 ps
CPU time 447.1 seconds
Started Jul 14 04:25:27 PM PDT 24
Finished Jul 14 04:32:58 PM PDT 24
Peak memory 199816 kb
Host smart-a18f8596-ba18-4bc6-a206-cb79fc50e7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846395024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.846395024
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1591940344
Short name T112
Test name
Test status
Simulation time 74471526720 ps
CPU time 810.49 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:39:51 PM PDT 24
Peak memory 224604 kb
Host smart-179542dd-85ea-452d-acf1-5bf3eccfed5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591940344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1591940344
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.4204499610
Short name T69
Test name
Test status
Simulation time 15279600 ps
CPU time 0.59 seconds
Started Jul 14 04:53:34 PM PDT 24
Finished Jul 14 04:53:36 PM PDT 24
Peak memory 196148 kb
Host smart-52879bd0-12ca-4b4c-9a70-930ef30be536
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204499610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.4204499610
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1321288721
Short name T94
Test name
Test status
Simulation time 489775961 ps
CPU time 1.36 seconds
Started Jul 14 04:53:19 PM PDT 24
Finished Jul 14 04:53:21 PM PDT 24
Peak memory 200028 kb
Host smart-9c92ac62-f642-4ae8-a0fd-f8a776cef153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321288721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1321288721
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/41.uart_stress_all.4182823062
Short name T158
Test name
Test status
Simulation time 118391663739 ps
CPU time 233.41 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:29:33 PM PDT 24
Peak memory 208176 kb
Host smart-58bc3169-09df-4b22-8e8c-7aeae190a8d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182823062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4182823062
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.128967376
Short name T17
Test name
Test status
Simulation time 15665182629 ps
CPU time 42.37 seconds
Started Jul 14 04:26:44 PM PDT 24
Finished Jul 14 04:27:28 PM PDT 24
Peak memory 199768 kb
Host smart-83500e06-4563-43a9-b3e1-1b6780a77d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128967376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.128967376
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3894267012
Short name T421
Test name
Test status
Simulation time 31451339 ps
CPU time 0.5 seconds
Started Jul 14 04:24:01 PM PDT 24
Finished Jul 14 04:24:03 PM PDT 24
Peak memory 194524 kb
Host smart-2d543a77-65a7-4770-8154-f4611678dff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894267012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3894267012
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1039596001
Short name T124
Test name
Test status
Simulation time 210651115308 ps
CPU time 415.71 seconds
Started Jul 14 04:25:36 PM PDT 24
Finished Jul 14 04:32:34 PM PDT 24
Peak memory 199836 kb
Host smart-8065c875-8a1c-4750-9ef7-e4c2d64bc752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039596001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1039596001
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2958005122
Short name T50
Test name
Test status
Simulation time 335974755014 ps
CPU time 736.13 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:38:37 PM PDT 24
Peak memory 216252 kb
Host smart-c7ec444e-c78e-4fdf-b25c-9ea0ee97dced
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958005122 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2958005122
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all.1095934947
Short name T156
Test name
Test status
Simulation time 290778295639 ps
CPU time 184.85 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:28:36 PM PDT 24
Peak memory 199624 kb
Host smart-eb788a90-c5c7-4d39-968a-d02fb2f641be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095934947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1095934947
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2422055453
Short name T210
Test name
Test status
Simulation time 182550124612 ps
CPU time 227.81 seconds
Started Jul 14 04:27:01 PM PDT 24
Finished Jul 14 04:30:50 PM PDT 24
Peak memory 199756 kb
Host smart-45e05349-0cc4-4d9a-853c-bf0b3964d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422055453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2422055453
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_perf.3970908325
Short name T316
Test name
Test status
Simulation time 22522386279 ps
CPU time 316.1 seconds
Started Jul 14 04:23:45 PM PDT 24
Finished Jul 14 04:29:02 PM PDT 24
Peak memory 199628 kb
Host smart-31f2a8e2-dbb1-4120-8db8-53bedd0e80e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3970908325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3970908325
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1818419060
Short name T149
Test name
Test status
Simulation time 130598792986 ps
CPU time 76.84 seconds
Started Jul 14 04:24:34 PM PDT 24
Finished Jul 14 04:25:53 PM PDT 24
Peak memory 199796 kb
Host smart-fac5d50e-6f9f-4351-a6fa-8df7f93d61dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818419060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1818419060
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3528046856
Short name T148
Test name
Test status
Simulation time 115375688408 ps
CPU time 402.36 seconds
Started Jul 14 04:27:00 PM PDT 24
Finished Jul 14 04:33:43 PM PDT 24
Peak memory 199888 kb
Host smart-6f7508c8-c0c7-4c93-9b12-909981cdb7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528046856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3528046856
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.8914117
Short name T164
Test name
Test status
Simulation time 187785790683 ps
CPU time 329.73 seconds
Started Jul 14 04:23:35 PM PDT 24
Finished Jul 14 04:29:07 PM PDT 24
Peak memory 199660 kb
Host smart-7913ef0a-e345-4745-be54-da0a94d3d634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8914117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.8914117
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4181060928
Short name T286
Test name
Test status
Simulation time 398898941404 ps
CPU time 370.38 seconds
Started Jul 14 04:24:20 PM PDT 24
Finished Jul 14 04:30:35 PM PDT 24
Peak memory 216456 kb
Host smart-c5043fe5-d6a7-4cf6-a601-68fb2922b7a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181060928 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4181060928
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1533953712
Short name T116
Test name
Test status
Simulation time 253432705989 ps
CPU time 296.15 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:30:06 PM PDT 24
Peak memory 209980 kb
Host smart-7931eecb-e236-4b74-92c6-3b3e60d736eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533953712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1533953712
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3034545782
Short name T326
Test name
Test status
Simulation time 136877171049 ps
CPU time 209.19 seconds
Started Jul 14 04:24:08 PM PDT 24
Finished Jul 14 04:27:38 PM PDT 24
Peak memory 199740 kb
Host smart-e5eb275a-e0e2-4d5f-beef-3248ff90e875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034545782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3034545782
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.1611194027
Short name T250
Test name
Test status
Simulation time 178986021102 ps
CPU time 982.53 seconds
Started Jul 14 04:24:10 PM PDT 24
Finished Jul 14 04:40:33 PM PDT 24
Peak memory 199772 kb
Host smart-ff3168bb-da53-4ac0-bee4-9ed9745e7f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611194027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1611194027
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3857450974
Short name T96
Test name
Test status
Simulation time 80047458 ps
CPU time 1.28 seconds
Started Jul 14 04:53:22 PM PDT 24
Finished Jul 14 04:53:24 PM PDT 24
Peak memory 199768 kb
Host smart-7b11df5c-4c23-45c7-91f2-4994fb3c8716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857450974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3857450974
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.363524749
Short name T275
Test name
Test status
Simulation time 100656692876 ps
CPU time 435.02 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:30:47 PM PDT 24
Peak memory 199604 kb
Host smart-d3f1e16e-a4a1-4cb2-aa3d-398cdf620ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363524749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.363524749
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_perf.2733346574
Short name T276
Test name
Test status
Simulation time 22294995883 ps
CPU time 301.67 seconds
Started Jul 14 04:25:04 PM PDT 24
Finished Jul 14 04:30:06 PM PDT 24
Peak memory 199736 kb
Host smart-af4655bf-36a8-48be-9c1e-3d74a42f2d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733346574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2733346574
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4165088966
Short name T144
Test name
Test status
Simulation time 51383954672 ps
CPU time 22.81 seconds
Started Jul 14 04:27:29 PM PDT 24
Finished Jul 14 04:27:53 PM PDT 24
Peak memory 199800 kb
Host smart-eee6e651-ed78-4318-8cbf-33931d36a032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165088966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4165088966
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1456025719
Short name T193
Test name
Test status
Simulation time 15183964436 ps
CPU time 17.65 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:25:48 PM PDT 24
Peak memory 199648 kb
Host smart-46e568a4-2c46-465e-a5d4-060448900812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456025719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1456025719
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.249022059
Short name T238
Test name
Test status
Simulation time 71034277539 ps
CPU time 159.38 seconds
Started Jul 14 04:26:05 PM PDT 24
Finished Jul 14 04:28:45 PM PDT 24
Peak memory 199656 kb
Host smart-9779778f-fc80-466d-a189-44e1f75584e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249022059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.249022059
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3773228377
Short name T1017
Test name
Test status
Simulation time 98025193834 ps
CPU time 541.16 seconds
Started Jul 14 04:26:18 PM PDT 24
Finished Jul 14 04:35:21 PM PDT 24
Peak memory 224628 kb
Host smart-2af39941-ed6c-4804-8fde-18230d9b2aae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773228377 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3773228377
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3253349399
Short name T335
Test name
Test status
Simulation time 106151564901 ps
CPU time 685.47 seconds
Started Jul 14 04:26:28 PM PDT 24
Finished Jul 14 04:37:55 PM PDT 24
Peak memory 224692 kb
Host smart-5fc286f3-50b4-4ae1-a8df-6c245fa3f904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253349399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3253349399
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.4009838665
Short name T179
Test name
Test status
Simulation time 277315089780 ps
CPU time 452.12 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:31:16 PM PDT 24
Peak memory 199780 kb
Host smart-49ac5cdb-6069-46a7-a8f6-e542323ded8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009838665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.4009838665
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.251474495
Short name T202
Test name
Test status
Simulation time 34927055274 ps
CPU time 17.17 seconds
Started Jul 14 04:26:50 PM PDT 24
Finished Jul 14 04:27:07 PM PDT 24
Peak memory 199756 kb
Host smart-af6c40d9-4b38-4217-81e5-2094baf48ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251474495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.251474495
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3267646800
Short name T199
Test name
Test status
Simulation time 14830813850 ps
CPU time 23.06 seconds
Started Jul 14 04:27:17 PM PDT 24
Finished Jul 14 04:27:40 PM PDT 24
Peak memory 199724 kb
Host smart-efd5dabc-d2ad-42dd-8d83-9b21c57a0cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267646800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3267646800
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.952601718
Short name T182
Test name
Test status
Simulation time 17644675979 ps
CPU time 30.67 seconds
Started Jul 14 04:24:58 PM PDT 24
Finished Jul 14 04:25:30 PM PDT 24
Peak memory 199784 kb
Host smart-3a55a4b3-337d-4798-b28a-0093a55cf43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952601718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.952601718
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1270541048
Short name T188
Test name
Test status
Simulation time 48584738428 ps
CPU time 31.32 seconds
Started Jul 14 04:26:38 PM PDT 24
Finished Jul 14 04:27:11 PM PDT 24
Peak memory 199728 kb
Host smart-4a0eff66-4039-4d61-97a4-8d89a390d6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270541048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1270541048
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.4016965568
Short name T246
Test name
Test status
Simulation time 173822439988 ps
CPU time 44.21 seconds
Started Jul 14 04:26:53 PM PDT 24
Finished Jul 14 04:27:37 PM PDT 24
Peak memory 199764 kb
Host smart-a2742038-ccaf-4914-b486-50d12b677493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016965568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.4016965568
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.101339307
Short name T1044
Test name
Test status
Simulation time 8346379156 ps
CPU time 13.59 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:24:39 PM PDT 24
Peak memory 199676 kb
Host smart-109b64c9-a03f-4849-a8e4-d9acbae5482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101339307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.101339307
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.523157241
Short name T222
Test name
Test status
Simulation time 434996191044 ps
CPU time 110.5 seconds
Started Jul 14 04:27:02 PM PDT 24
Finished Jul 14 04:28:53 PM PDT 24
Peak memory 199632 kb
Host smart-0f1d8ea7-ef5e-43c8-944a-5b64f0d2b1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523157241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.523157241
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2570670685
Short name T11
Test name
Test status
Simulation time 31595833782 ps
CPU time 15.73 seconds
Started Jul 14 04:25:34 PM PDT 24
Finished Jul 14 04:25:51 PM PDT 24
Peak memory 196832 kb
Host smart-b1eef121-6ef4-4d65-8c05-828c9198ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570670685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2570670685
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4140428392
Short name T290
Test name
Test status
Simulation time 129846502809 ps
CPU time 106 seconds
Started Jul 14 04:27:20 PM PDT 24
Finished Jul 14 04:29:07 PM PDT 24
Peak memory 199708 kb
Host smart-c364f87c-043a-44d4-a99a-b49fe9bffe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140428392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4140428392
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2779272763
Short name T259
Test name
Test status
Simulation time 130436368159 ps
CPU time 217.55 seconds
Started Jul 14 04:26:09 PM PDT 24
Finished Jul 14 04:29:47 PM PDT 24
Peak memory 199748 kb
Host smart-e1b76921-945e-4ded-8193-e14de2ead88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779272763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2779272763
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3228038203
Short name T146
Test name
Test status
Simulation time 38190049244 ps
CPU time 33.41 seconds
Started Jul 14 04:26:18 PM PDT 24
Finished Jul 14 04:26:53 PM PDT 24
Peak memory 199732 kb
Host smart-64113c45-3a45-471e-ba15-77480ad0781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228038203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3228038203
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.4271029361
Short name T39
Test name
Test status
Simulation time 28171860374 ps
CPU time 44.9 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:27:14 PM PDT 24
Peak memory 199724 kb
Host smart-ce89c8a2-d4a1-4cf2-8c95-970d7c77a482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271029361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4271029361
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.649387205
Short name T263
Test name
Test status
Simulation time 65480706307 ps
CPU time 25.17 seconds
Started Jul 14 04:23:21 PM PDT 24
Finished Jul 14 04:23:48 PM PDT 24
Peak memory 199792 kb
Host smart-ea6c27c8-f669-44a9-9f92-ab63b86316f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649387205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.649387205
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.382641290
Short name T161
Test name
Test status
Simulation time 273284240265 ps
CPU time 421.79 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:30:44 PM PDT 24
Peak memory 199784 kb
Host smart-71fa2cd9-70ea-4e71-8349-35838214951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382641290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.382641290
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2874169456
Short name T143
Test name
Test status
Simulation time 50383478885 ps
CPU time 83.35 seconds
Started Jul 14 04:26:37 PM PDT 24
Finished Jul 14 04:28:02 PM PDT 24
Peak memory 199708 kb
Host smart-8a3fe343-b527-4c46-b93e-17e2a80ec656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874169456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2874169456
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1404245895
Short name T237
Test name
Test status
Simulation time 67180918424 ps
CPU time 28.98 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:27:07 PM PDT 24
Peak memory 199748 kb
Host smart-54fb1adf-43cf-4b09-8a6b-7b9b15dd6f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404245895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1404245895
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2325847893
Short name T244
Test name
Test status
Simulation time 60739264290 ps
CPU time 20.93 seconds
Started Jul 14 04:24:05 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 199716 kb
Host smart-0e03d12f-f002-4cf9-8709-53e91b38d629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325847893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2325847893
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2997564586
Short name T190
Test name
Test status
Simulation time 162983720807 ps
CPU time 65.5 seconds
Started Jul 14 04:26:38 PM PDT 24
Finished Jul 14 04:27:45 PM PDT 24
Peak memory 199692 kb
Host smart-8c87618f-212b-4285-83e7-7fada3743e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997564586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2997564586
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1371634272
Short name T229
Test name
Test status
Simulation time 123433669701 ps
CPU time 52.64 seconds
Started Jul 14 04:26:50 PM PDT 24
Finished Jul 14 04:27:43 PM PDT 24
Peak memory 199616 kb
Host smart-cb060aaa-e106-4471-90b3-c6513b27bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371634272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1371634272
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3325074231
Short name T258
Test name
Test status
Simulation time 50593048810 ps
CPU time 22.57 seconds
Started Jul 14 04:26:46 PM PDT 24
Finished Jul 14 04:27:09 PM PDT 24
Peak memory 199580 kb
Host smart-910b7c3a-e387-465c-ba54-6fe374fba371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325074231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3325074231
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2171766356
Short name T655
Test name
Test status
Simulation time 78523586213 ps
CPU time 238.96 seconds
Started Jul 14 04:24:13 PM PDT 24
Finished Jul 14 04:28:13 PM PDT 24
Peak memory 216328 kb
Host smart-79ee116c-9fd1-4be6-b904-000e260fbc6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171766356 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2171766356
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.517491543
Short name T227
Test name
Test status
Simulation time 32239098590 ps
CPU time 51.91 seconds
Started Jul 14 04:26:43 PM PDT 24
Finished Jul 14 04:27:36 PM PDT 24
Peak memory 199884 kb
Host smart-286e3c74-660c-47f2-88c8-751ce33db5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517491543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.517491543
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3412565503
Short name T253
Test name
Test status
Simulation time 212966320076 ps
CPU time 36.32 seconds
Started Jul 14 04:26:45 PM PDT 24
Finished Jul 14 04:27:22 PM PDT 24
Peak memory 199624 kb
Host smart-a1557311-3cdb-4c64-9b80-582fb289233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412565503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3412565503
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2781505490
Short name T248
Test name
Test status
Simulation time 130373372954 ps
CPU time 216.93 seconds
Started Jul 14 04:26:46 PM PDT 24
Finished Jul 14 04:30:23 PM PDT 24
Peak memory 199708 kb
Host smart-8b3ccfa1-ae7f-4d62-b923-3d0772a5885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781505490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2781505490
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.471745423
Short name T243
Test name
Test status
Simulation time 63617139566 ps
CPU time 44.71 seconds
Started Jul 14 04:26:52 PM PDT 24
Finished Jul 14 04:27:37 PM PDT 24
Peak memory 199764 kb
Host smart-3acf1b61-c34e-4086-81f8-308a0ffb5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471745423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.471745423
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.306609655
Short name T207
Test name
Test status
Simulation time 330620744912 ps
CPU time 157 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:26:59 PM PDT 24
Peak memory 199780 kb
Host smart-7e684d2a-3693-4679-b32d-4e1a603ff82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306609655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.306609655
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2438469541
Short name T247
Test name
Test status
Simulation time 102987226112 ps
CPU time 32.55 seconds
Started Jul 14 04:26:52 PM PDT 24
Finished Jul 14 04:27:25 PM PDT 24
Peak memory 199628 kb
Host smart-e71ca3dc-a988-4163-9741-d81b8f422b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438469541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2438469541
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1873127753
Short name T256
Test name
Test status
Simulation time 118079994367 ps
CPU time 187.79 seconds
Started Jul 14 04:26:53 PM PDT 24
Finished Jul 14 04:30:01 PM PDT 24
Peak memory 199740 kb
Host smart-17ed6a30-6e6e-478a-a07a-cdf42afc9c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873127753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1873127753
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.985356176
Short name T240
Test name
Test status
Simulation time 7987568002 ps
CPU time 11.27 seconds
Started Jul 14 04:26:59 PM PDT 24
Finished Jul 14 04:27:11 PM PDT 24
Peak memory 199804 kb
Host smart-4320a235-2924-4868-b6d2-64a384b9c77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985356176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.985356176
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.336415530
Short name T255
Test name
Test status
Simulation time 141866315886 ps
CPU time 46.39 seconds
Started Jul 14 04:27:00 PM PDT 24
Finished Jul 14 04:27:47 PM PDT 24
Peak memory 199804 kb
Host smart-874e4277-3e58-4131-95d4-0cffb87adfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336415530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.336415530
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3251657153
Short name T232
Test name
Test status
Simulation time 22322910756 ps
CPU time 10.58 seconds
Started Jul 14 04:27:10 PM PDT 24
Finished Jul 14 04:27:22 PM PDT 24
Peak memory 199632 kb
Host smart-9626a015-3b79-40a5-8377-04b572140011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251657153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3251657153
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_smoke.1896980981
Short name T60
Test name
Test status
Simulation time 5554065994 ps
CPU time 33.38 seconds
Started Jul 14 04:25:47 PM PDT 24
Finished Jul 14 04:26:21 PM PDT 24
Peak memory 199540 kb
Host smart-7387250a-8a9a-486a-af34-7fa0c680fef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896980981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1896980981
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2590353671
Short name T145
Test name
Test status
Simulation time 26845373585 ps
CPU time 34.83 seconds
Started Jul 14 04:27:21 PM PDT 24
Finished Jul 14 04:27:56 PM PDT 24
Peak memory 199768 kb
Host smart-fff2d5f6-147c-4d0a-b6ff-655940a3cd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590353671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2590353671
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1732649935
Short name T261
Test name
Test status
Simulation time 105553377809 ps
CPU time 132.16 seconds
Started Jul 14 04:25:27 PM PDT 24
Finished Jul 14 04:27:42 PM PDT 24
Peak memory 216780 kb
Host smart-07807a7a-efe3-45e1-87f6-8f8cb48f036a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732649935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1732649935
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2185559020
Short name T264
Test name
Test status
Simulation time 86079032692 ps
CPU time 795.78 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:39:37 PM PDT 24
Peak memory 225000 kb
Host smart-831cbf85-62e9-4714-a854-0a3b20adf37c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185559020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2185559020
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2173006970
Short name T176
Test name
Test status
Simulation time 16028039916 ps
CPU time 6.7 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:23:53 PM PDT 24
Peak memory 199204 kb
Host smart-679758eb-cbd8-4e6c-9958-386957fdfe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173006970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2173006970
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2992816150
Short name T166
Test name
Test status
Simulation time 49674330388 ps
CPU time 32.81 seconds
Started Jul 14 04:26:30 PM PDT 24
Finished Jul 14 04:27:04 PM PDT 24
Peak memory 199740 kb
Host smart-c736de09-df5c-40bc-a5de-dabe63c6e847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992816150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2992816150
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3025051194
Short name T1247
Test name
Test status
Simulation time 38288193 ps
CPU time 0.66 seconds
Started Jul 14 04:52:50 PM PDT 24
Finished Jul 14 04:52:51 PM PDT 24
Peak memory 196036 kb
Host smart-48cac121-e457-431b-85f6-ba2ebd66bc21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025051194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3025051194
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.509866081
Short name T1250
Test name
Test status
Simulation time 68562708 ps
CPU time 1.48 seconds
Started Jul 14 04:52:51 PM PDT 24
Finished Jul 14 04:52:54 PM PDT 24
Peak memory 198492 kb
Host smart-1f7d29d3-3834-4949-8973-cd6a61505f6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509866081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.509866081
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3694297457
Short name T1223
Test name
Test status
Simulation time 38139143 ps
CPU time 0.57 seconds
Started Jul 14 04:52:53 PM PDT 24
Finished Jul 14 04:52:55 PM PDT 24
Peak memory 196060 kb
Host smart-6f7e117a-98a9-434b-87c0-1533bced075e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694297457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3694297457
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2233483951
Short name T1286
Test name
Test status
Simulation time 19012175 ps
CPU time 0.89 seconds
Started Jul 14 04:52:50 PM PDT 24
Finished Jul 14 04:52:52 PM PDT 24
Peak memory 200424 kb
Host smart-b33b1356-fd6d-4600-a5d2-dc8d95f9ed13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233483951 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2233483951
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3446426272
Short name T1293
Test name
Test status
Simulation time 11817429 ps
CPU time 0.61 seconds
Started Jul 14 04:52:52 PM PDT 24
Finished Jul 14 04:52:55 PM PDT 24
Peak memory 196060 kb
Host smart-0551f42f-f8d0-44d8-b943-3e34d933bc43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446426272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3446426272
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.415922477
Short name T1209
Test name
Test status
Simulation time 47034760 ps
CPU time 0.57 seconds
Started Jul 14 04:52:52 PM PDT 24
Finished Jul 14 04:52:54 PM PDT 24
Peak memory 195056 kb
Host smart-4d3f87c5-a909-48cc-b1ac-c7a9699e2dce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415922477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.415922477
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1239062429
Short name T86
Test name
Test status
Simulation time 57595549 ps
CPU time 0.75 seconds
Started Jul 14 04:52:52 PM PDT 24
Finished Jul 14 04:52:54 PM PDT 24
Peak memory 196520 kb
Host smart-8397f8d7-b152-4e3e-8281-772555885c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239062429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1239062429
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2375884917
Short name T1270
Test name
Test status
Simulation time 30811404 ps
CPU time 1.31 seconds
Started Jul 14 04:52:52 PM PDT 24
Finished Jul 14 04:52:54 PM PDT 24
Peak memory 200668 kb
Host smart-428c3c48-aead-4114-a870-a8b4f47e2b63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375884917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2375884917
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1318757829
Short name T1307
Test name
Test status
Simulation time 78763638 ps
CPU time 1.03 seconds
Started Jul 14 04:52:52 PM PDT 24
Finished Jul 14 04:52:55 PM PDT 24
Peak memory 199824 kb
Host smart-7c154bc4-f4f5-40fb-9cb6-334cd96c985b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318757829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1318757829
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1113737338
Short name T67
Test name
Test status
Simulation time 50521171 ps
CPU time 0.8 seconds
Started Jul 14 04:52:59 PM PDT 24
Finished Jul 14 04:53:01 PM PDT 24
Peak memory 196960 kb
Host smart-d46d04ce-72b9-4211-86c9-034235c2c65d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113737338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1113737338
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1386859712
Short name T1196
Test name
Test status
Simulation time 176533010 ps
CPU time 2.53 seconds
Started Jul 14 04:52:56 PM PDT 24
Finished Jul 14 04:52:59 PM PDT 24
Peak memory 198400 kb
Host smart-55aa02aa-cdec-466c-8ea1-e94a4a153b02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386859712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1386859712
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1587404163
Short name T1235
Test name
Test status
Simulation time 96728524 ps
CPU time 0.6 seconds
Started Jul 14 04:52:52 PM PDT 24
Finished Jul 14 04:52:53 PM PDT 24
Peak memory 196060 kb
Host smart-bd58f24c-ac4d-4270-bc03-454119f7cc30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587404163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1587404163
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.220275635
Short name T1180
Test name
Test status
Simulation time 56841794 ps
CPU time 0.93 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:00 PM PDT 24
Peak memory 200460 kb
Host smart-eafe8e40-8101-45b2-8f08-13f1ad65d492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220275635 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.220275635
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3425826755
Short name T1290
Test name
Test status
Simulation time 50932111 ps
CPU time 0.57 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:52:59 PM PDT 24
Peak memory 196040 kb
Host smart-637c32d6-0de5-46f9-8bcd-a5bd03d35350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425826755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3425826755
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.377391676
Short name T1181
Test name
Test status
Simulation time 16374117 ps
CPU time 0.59 seconds
Started Jul 14 04:52:51 PM PDT 24
Finished Jul 14 04:52:53 PM PDT 24
Peak memory 195004 kb
Host smart-911619fb-5278-4212-affc-19bd3a067e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377391676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.377391676
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3140525355
Short name T1213
Test name
Test status
Simulation time 18810813 ps
CPU time 0.68 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:00 PM PDT 24
Peak memory 196536 kb
Host smart-febc1076-36d5-4146-b7d6-28e3d5e3224d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140525355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3140525355
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3628098922
Short name T1249
Test name
Test status
Simulation time 571497042 ps
CPU time 1.77 seconds
Started Jul 14 04:52:51 PM PDT 24
Finished Jul 14 04:52:53 PM PDT 24
Peak memory 200696 kb
Host smart-7b976ab7-9a56-49a8-aa67-c757148a23df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628098922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3628098922
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1096430233
Short name T1281
Test name
Test status
Simulation time 55197521 ps
CPU time 1.02 seconds
Started Jul 14 04:52:52 PM PDT 24
Finished Jul 14 04:52:54 PM PDT 24
Peak memory 199960 kb
Host smart-621b2f14-62c8-48ed-ad4c-5606deaf808e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096430233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1096430233
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3730381114
Short name T1237
Test name
Test status
Simulation time 48074912 ps
CPU time 0.67 seconds
Started Jul 14 04:53:23 PM PDT 24
Finished Jul 14 04:53:24 PM PDT 24
Peak memory 198220 kb
Host smart-43305dd5-8a7f-4800-91bf-27c07cdc1b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730381114 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3730381114
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.722759498
Short name T72
Test name
Test status
Simulation time 19855058 ps
CPU time 0.59 seconds
Started Jul 14 04:53:18 PM PDT 24
Finished Jul 14 04:53:19 PM PDT 24
Peak memory 196052 kb
Host smart-43f45fc8-b20a-4202-8a73-8e06037f85e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722759498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.722759498
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1291734244
Short name T1210
Test name
Test status
Simulation time 23925087 ps
CPU time 0.57 seconds
Started Jul 14 04:53:20 PM PDT 24
Finished Jul 14 04:53:21 PM PDT 24
Peak memory 194932 kb
Host smart-e54c9b02-49bd-49c9-8b08-4f0042a7b603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291734244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1291734244
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2841603783
Short name T84
Test name
Test status
Simulation time 26604018 ps
CPU time 0.76 seconds
Started Jul 14 04:53:18 PM PDT 24
Finished Jul 14 04:53:19 PM PDT 24
Peak memory 197624 kb
Host smart-483b23fa-cc36-4a50-a58e-dc9f0f4da9ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841603783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2841603783
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3044934714
Short name T1199
Test name
Test status
Simulation time 29743256 ps
CPU time 1.41 seconds
Started Jul 14 04:53:20 PM PDT 24
Finished Jul 14 04:53:21 PM PDT 24
Peak memory 200676 kb
Host smart-d6d75604-3f2a-4523-8fd6-60435932ff9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044934714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3044934714
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3189651150
Short name T95
Test name
Test status
Simulation time 89574590 ps
CPU time 1.31 seconds
Started Jul 14 04:53:20 PM PDT 24
Finished Jul 14 04:53:22 PM PDT 24
Peak memory 199944 kb
Host smart-caced907-1065-46a7-9cbb-ec613c96fc98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189651150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3189651150
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1358915242
Short name T1276
Test name
Test status
Simulation time 48383568 ps
CPU time 0.85 seconds
Started Jul 14 04:53:18 PM PDT 24
Finished Jul 14 04:53:19 PM PDT 24
Peak memory 200796 kb
Host smart-24851b75-ca04-4963-9639-d31ae054ecb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358915242 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1358915242
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.467040159
Short name T1231
Test name
Test status
Simulation time 59614204 ps
CPU time 0.6 seconds
Started Jul 14 04:53:23 PM PDT 24
Finished Jul 14 04:53:24 PM PDT 24
Peak memory 196072 kb
Host smart-7cc20f43-a6d9-408c-80ff-05a85030e014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467040159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.467040159
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4139974802
Short name T1306
Test name
Test status
Simulation time 40860546 ps
CPU time 0.59 seconds
Started Jul 14 04:53:18 PM PDT 24
Finished Jul 14 04:53:20 PM PDT 24
Peak memory 194936 kb
Host smart-e5d60ca6-7389-42f8-80ea-678aa941afe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139974802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4139974802
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3201613074
Short name T1305
Test name
Test status
Simulation time 42152411 ps
CPU time 0.66 seconds
Started Jul 14 04:53:19 PM PDT 24
Finished Jul 14 04:53:20 PM PDT 24
Peak memory 196104 kb
Host smart-7ac30a7d-0c5d-418f-9632-63cb862b4a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201613074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3201613074
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3326429521
Short name T1177
Test name
Test status
Simulation time 106476405 ps
CPU time 2.1 seconds
Started Jul 14 04:53:19 PM PDT 24
Finished Jul 14 04:53:22 PM PDT 24
Peak memory 200744 kb
Host smart-15686bad-7250-43d5-8f9b-a260d2cf6575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326429521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3326429521
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2107384898
Short name T1201
Test name
Test status
Simulation time 34808477 ps
CPU time 0.88 seconds
Started Jul 14 04:53:26 PM PDT 24
Finished Jul 14 04:53:28 PM PDT 24
Peak memory 200456 kb
Host smart-8c08197b-b299-4b65-afe0-26e28d9f1063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107384898 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2107384898
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.4165125156
Short name T1255
Test name
Test status
Simulation time 16106246 ps
CPU time 0.6 seconds
Started Jul 14 04:53:26 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 196016 kb
Host smart-306ec409-ba1b-42a8-9582-0e76f4d683f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165125156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4165125156
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.668576074
Short name T1182
Test name
Test status
Simulation time 137004148 ps
CPU time 0.58 seconds
Started Jul 14 04:53:18 PM PDT 24
Finished Jul 14 04:53:19 PM PDT 24
Peak memory 195060 kb
Host smart-84fe93be-dcdf-4082-b935-fa958152b125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668576074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.668576074
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1296905790
Short name T91
Test name
Test status
Simulation time 115616707 ps
CPU time 0.71 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 196464 kb
Host smart-dae648f3-0ec2-4b1c-9ac7-5547c65a0941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296905790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1296905790
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1736989873
Short name T1193
Test name
Test status
Simulation time 95562459 ps
CPU time 1.43 seconds
Started Jul 14 04:53:20 PM PDT 24
Finished Jul 14 04:53:22 PM PDT 24
Peak memory 200680 kb
Host smart-9623cfd3-8009-43c3-b38b-fab44d0702bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736989873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1736989873
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4243042110
Short name T1256
Test name
Test status
Simulation time 30047770 ps
CPU time 0.8 seconds
Started Jul 14 04:53:26 PM PDT 24
Finished Jul 14 04:53:28 PM PDT 24
Peak memory 199980 kb
Host smart-ee2bee4b-d60d-4f0c-abb8-a0806610d472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243042110 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.4243042110
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2252045017
Short name T90
Test name
Test status
Simulation time 63394792 ps
CPU time 0.63 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 196388 kb
Host smart-0ea04b16-c745-4e29-bcd2-404c3425871f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252045017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2252045017
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.212748211
Short name T1277
Test name
Test status
Simulation time 16308870 ps
CPU time 0.54 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:26 PM PDT 24
Peak memory 194956 kb
Host smart-c67cf386-2791-4346-a484-80c8990fc0c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212748211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.212748211
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1627518574
Short name T1315
Test name
Test status
Simulation time 13829897 ps
CPU time 0.68 seconds
Started Jul 14 04:53:28 PM PDT 24
Finished Jul 14 04:53:29 PM PDT 24
Peak memory 195584 kb
Host smart-0f21082c-dd78-410e-920e-9601bdc1f7d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627518574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1627518574
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.822792604
Short name T1274
Test name
Test status
Simulation time 246852556 ps
CPU time 1.77 seconds
Started Jul 14 04:53:26 PM PDT 24
Finished Jul 14 04:53:29 PM PDT 24
Peak memory 200784 kb
Host smart-903b3919-e1e7-4612-a00d-c491c945f35d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822792604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.822792604
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2023059433
Short name T1225
Test name
Test status
Simulation time 375143930 ps
CPU time 0.99 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 199704 kb
Host smart-e5f97d0d-da50-431a-b61c-380b48796147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023059433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2023059433
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1899836525
Short name T1222
Test name
Test status
Simulation time 105965198 ps
CPU time 0.9 seconds
Started Jul 14 04:53:27 PM PDT 24
Finished Jul 14 04:53:28 PM PDT 24
Peak memory 200464 kb
Host smart-381ccf95-e7cf-4f9c-9b07-c2a8e094440a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899836525 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1899836525
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.745033876
Short name T71
Test name
Test status
Simulation time 23933739 ps
CPU time 0.63 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:26 PM PDT 24
Peak memory 196116 kb
Host smart-52dab25e-0935-4ac7-b7f5-0f41a1413e02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745033876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.745033876
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.593306586
Short name T1186
Test name
Test status
Simulation time 24081494 ps
CPU time 0.56 seconds
Started Jul 14 04:53:24 PM PDT 24
Finished Jul 14 04:53:25 PM PDT 24
Peak memory 195024 kb
Host smart-933160a4-647b-4746-9a7c-9577d0867753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593306586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.593306586
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2396192356
Short name T1267
Test name
Test status
Simulation time 46367104 ps
CPU time 0.71 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 196448 kb
Host smart-b8fe62b2-e0a4-450c-ac66-4888130c6cce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396192356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2396192356
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1200786444
Short name T1297
Test name
Test status
Simulation time 21625562 ps
CPU time 1.05 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 200800 kb
Host smart-1fdc6e99-e937-473e-91b3-ea92af219fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200786444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1200786444
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1709916287
Short name T93
Test name
Test status
Simulation time 72240500 ps
CPU time 1.3 seconds
Started Jul 14 04:53:26 PM PDT 24
Finished Jul 14 04:53:28 PM PDT 24
Peak memory 200060 kb
Host smart-88a53adc-ddf7-408d-a897-a24bb9d17d57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709916287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1709916287
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1089686516
Short name T1179
Test name
Test status
Simulation time 133559929 ps
CPU time 0.79 seconds
Started Jul 14 04:53:24 PM PDT 24
Finished Jul 14 04:53:25 PM PDT 24
Peak memory 199312 kb
Host smart-f10e70de-a2f0-4cc5-8cce-12198752e925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089686516 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1089686516
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.369902754
Short name T1259
Test name
Test status
Simulation time 16275702 ps
CPU time 0.63 seconds
Started Jul 14 04:53:27 PM PDT 24
Finished Jul 14 04:53:28 PM PDT 24
Peak memory 196144 kb
Host smart-db545859-1c26-4abb-9afa-a45dade5dc20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369902754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.369902754
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2218929567
Short name T1229
Test name
Test status
Simulation time 37419456 ps
CPU time 0.58 seconds
Started Jul 14 04:53:27 PM PDT 24
Finished Jul 14 04:53:28 PM PDT 24
Peak memory 195124 kb
Host smart-e4db53c6-f5d0-4965-a072-a89298aa2df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218929567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2218929567
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3688574905
Short name T1251
Test name
Test status
Simulation time 18154988 ps
CPU time 0.62 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 196204 kb
Host smart-aa13a076-5a67-484f-8a10-3184a01e1404
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688574905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3688574905
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.612235055
Short name T1227
Test name
Test status
Simulation time 122837883 ps
CPU time 1.84 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 200696 kb
Host smart-5630e447-762a-44ae-a60b-25077afe07ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612235055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.612235055
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3099772166
Short name T1264
Test name
Test status
Simulation time 65982439 ps
CPU time 0.96 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:27 PM PDT 24
Peak memory 199772 kb
Host smart-d04c9e0e-8fc9-4f14-a767-adf0218affcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099772166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3099772166
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.255164273
Short name T1266
Test name
Test status
Simulation time 28949887 ps
CPU time 0.87 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:34 PM PDT 24
Peak memory 200528 kb
Host smart-7f399131-40b5-4e68-9253-920f3b4c1724
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255164273 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.255164273
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1724321466
Short name T1302
Test name
Test status
Simulation time 26016758 ps
CPU time 0.6 seconds
Started Jul 14 04:53:39 PM PDT 24
Finished Jul 14 04:53:40 PM PDT 24
Peak memory 195928 kb
Host smart-9ccfff57-5308-40d0-8b4b-4ec1a9e1845d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724321466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1724321466
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.567256474
Short name T1263
Test name
Test status
Simulation time 90101387 ps
CPU time 0.56 seconds
Started Jul 14 04:53:35 PM PDT 24
Finished Jul 14 04:53:36 PM PDT 24
Peak memory 195112 kb
Host smart-a4b5665b-a467-4a71-8cdf-90640e521249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567256474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.567256474
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1387020574
Short name T1294
Test name
Test status
Simulation time 14707050 ps
CPU time 0.74 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 197628 kb
Host smart-d9274b9c-49f6-4ea9-b8a3-a7eb55ded2fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387020574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1387020574
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.82003275
Short name T1285
Test name
Test status
Simulation time 81554583 ps
CPU time 1.71 seconds
Started Jul 14 04:53:25 PM PDT 24
Finished Jul 14 04:53:28 PM PDT 24
Peak memory 200724 kb
Host smart-67b44943-a375-4dc5-8511-fc51c588fe61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82003275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.82003275
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3471349640
Short name T99
Test name
Test status
Simulation time 175308489 ps
CPU time 0.94 seconds
Started Jul 14 04:53:39 PM PDT 24
Finished Jul 14 04:53:40 PM PDT 24
Peak memory 199108 kb
Host smart-2d7cedc6-e318-4512-b46a-4b9e78b81ef2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471349640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3471349640
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3509655601
Short name T1185
Test name
Test status
Simulation time 27375891 ps
CPU time 1.31 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 200640 kb
Host smart-c94974c7-f5dd-4cd4-91ab-e65bc80fcab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509655601 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3509655601
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1411083967
Short name T1203
Test name
Test status
Simulation time 19716070 ps
CPU time 0.57 seconds
Started Jul 14 04:53:34 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 194980 kb
Host smart-c15aa57f-892b-4eed-8fb3-19526336ade2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411083967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1411083967
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2692673758
Short name T1309
Test name
Test status
Simulation time 81418349 ps
CPU time 0.66 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 196648 kb
Host smart-c059ffd8-3baa-47e4-ac46-8942c24053f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692673758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2692673758
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1920740571
Short name T1202
Test name
Test status
Simulation time 147983052 ps
CPU time 1.88 seconds
Started Jul 14 04:53:36 PM PDT 24
Finished Jul 14 04:53:38 PM PDT 24
Peak memory 200704 kb
Host smart-9d987227-bd83-409b-8c81-462514c20057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920740571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1920740571
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1996736099
Short name T1282
Test name
Test status
Simulation time 99492047 ps
CPU time 0.99 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 199904 kb
Host smart-0c9265c9-cff4-4172-9d9b-1c6cefcd45fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996736099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1996736099
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1368602461
Short name T1187
Test name
Test status
Simulation time 113790260 ps
CPU time 1.52 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 200716 kb
Host smart-7cbf258c-7807-49b7-be30-cd83d6ab7b03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368602461 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1368602461
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1642243641
Short name T1242
Test name
Test status
Simulation time 21607580 ps
CPU time 0.6 seconds
Started Jul 14 04:53:35 PM PDT 24
Finished Jul 14 04:53:36 PM PDT 24
Peak memory 196180 kb
Host smart-9fab4d4f-89ff-495d-8108-80afffbb4840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642243641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1642243641
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4250644841
Short name T1243
Test name
Test status
Simulation time 20508753 ps
CPU time 0.6 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:34 PM PDT 24
Peak memory 194988 kb
Host smart-7468c5cb-e9af-4135-a113-d014e6920bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250644841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4250644841
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4054848294
Short name T1260
Test name
Test status
Simulation time 17216392 ps
CPU time 0.81 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 197800 kb
Host smart-cb78b007-2bc7-4902-b10d-cc714698f5e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054848294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.4054848294
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1134428745
Short name T1200
Test name
Test status
Simulation time 76152816 ps
CPU time 1.15 seconds
Started Jul 14 04:53:32 PM PDT 24
Finished Jul 14 04:53:34 PM PDT 24
Peak memory 200612 kb
Host smart-167b51c3-153b-4cad-a9a6-8aa9b89f5dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134428745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1134428745
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.192571240
Short name T92
Test name
Test status
Simulation time 555715622 ps
CPU time 1.5 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:36 PM PDT 24
Peak memory 199916 kb
Host smart-aef83652-1f6d-4643-ad6c-e33de1df1fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192571240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.192571240
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.641237621
Short name T1183
Test name
Test status
Simulation time 31586867 ps
CPU time 0.83 seconds
Started Jul 14 04:53:36 PM PDT 24
Finished Jul 14 04:53:37 PM PDT 24
Peak memory 200292 kb
Host smart-755957c3-fb92-4e35-9447-3ff0e58e8520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641237621 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.641237621
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3899294036
Short name T1295
Test name
Test status
Simulation time 32809436 ps
CPU time 0.62 seconds
Started Jul 14 04:53:39 PM PDT 24
Finished Jul 14 04:53:40 PM PDT 24
Peak memory 196220 kb
Host smart-8cfc7f45-a843-4fb7-b040-2ba9f8814610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899294036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3899294036
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1935563310
Short name T1226
Test name
Test status
Simulation time 42873400 ps
CPU time 0.59 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 195048 kb
Host smart-a483789f-c247-4c42-b693-0b6e80cad13b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935563310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1935563310
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3268258597
Short name T87
Test name
Test status
Simulation time 13506102 ps
CPU time 0.63 seconds
Started Jul 14 04:53:32 PM PDT 24
Finished Jul 14 04:53:33 PM PDT 24
Peak memory 196308 kb
Host smart-511fd472-c7ee-4e13-8c53-165f6446cfbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268258597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3268258597
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2199470324
Short name T1300
Test name
Test status
Simulation time 123192820 ps
CPU time 2.54 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:36 PM PDT 24
Peak memory 200688 kb
Host smart-a25c3a11-ef1b-4714-b35c-cfd03ddb106f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199470324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2199470324
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1515489259
Short name T1278
Test name
Test status
Simulation time 91636903 ps
CPU time 1.37 seconds
Started Jul 14 04:53:33 PM PDT 24
Finished Jul 14 04:53:35 PM PDT 24
Peak memory 199900 kb
Host smart-238364f4-7035-474c-abe2-99bf691b609f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515489259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1515489259
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3194411320
Short name T1206
Test name
Test status
Simulation time 21224702 ps
CPU time 0.68 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:00 PM PDT 24
Peak memory 195444 kb
Host smart-4b350c1c-0462-4bfb-92ca-19b21dbcca78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194411320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3194411320
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2622240997
Short name T1248
Test name
Test status
Simulation time 1120034046 ps
CPU time 2.4 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:02 PM PDT 24
Peak memory 197840 kb
Host smart-4c74c87c-d32b-4eb0-985a-0ea501687938
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622240997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2622240997
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2624172232
Short name T1214
Test name
Test status
Simulation time 181214339 ps
CPU time 0.61 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:52:59 PM PDT 24
Peak memory 196000 kb
Host smart-b807eca4-9d03-4765-a046-ffc09a8a77ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624172232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2624172232
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.577808820
Short name T1212
Test name
Test status
Simulation time 18638140 ps
CPU time 0.91 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:00 PM PDT 24
Peak memory 200460 kb
Host smart-b97fe1ef-acf2-497e-8127-4d24dd0c86c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577808820 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.577808820
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3631741317
Short name T83
Test name
Test status
Simulation time 16957285 ps
CPU time 0.64 seconds
Started Jul 14 04:52:59 PM PDT 24
Finished Jul 14 04:53:01 PM PDT 24
Peak memory 196096 kb
Host smart-c3917316-9524-43a5-b022-6e18f0f7e582
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631741317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3631741317
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1318554653
Short name T1228
Test name
Test status
Simulation time 15720360 ps
CPU time 0.59 seconds
Started Jul 14 04:52:59 PM PDT 24
Finished Jul 14 04:53:01 PM PDT 24
Peak memory 195040 kb
Host smart-cadddedb-41f6-4342-b37c-05655dba3efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318554653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1318554653
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.585710528
Short name T1275
Test name
Test status
Simulation time 21365524 ps
CPU time 0.81 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:52:59 PM PDT 24
Peak memory 197708 kb
Host smart-848e1476-d9b2-4127-a01b-88a3c8b949d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585710528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.585710528
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.925016191
Short name T1287
Test name
Test status
Simulation time 372370702 ps
CPU time 2.12 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:01 PM PDT 24
Peak memory 200700 kb
Host smart-253afe78-8dbe-484c-8f5f-7ab488aa8eae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925016191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.925016191
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3454784876
Short name T1311
Test name
Test status
Simulation time 729970015 ps
CPU time 1.36 seconds
Started Jul 14 04:52:59 PM PDT 24
Finished Jul 14 04:53:02 PM PDT 24
Peak memory 200180 kb
Host smart-9ef7e221-8bac-4d70-b6b2-74b797f1e7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454784876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3454784876
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1277276553
Short name T1178
Test name
Test status
Simulation time 14132815 ps
CPU time 0.59 seconds
Started Jul 14 04:53:39 PM PDT 24
Finished Jul 14 04:53:40 PM PDT 24
Peak memory 195016 kb
Host smart-d8ae604a-8cca-460c-a887-9800f90b877c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277276553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1277276553
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3982406549
Short name T1190
Test name
Test status
Simulation time 58087167 ps
CPU time 0.59 seconds
Started Jul 14 04:53:32 PM PDT 24
Finished Jul 14 04:53:33 PM PDT 24
Peak memory 195080 kb
Host smart-fcb494c2-0b5b-42fc-86e2-1f7f75b3ffd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982406549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3982406549
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2060747420
Short name T1205
Test name
Test status
Simulation time 12686022 ps
CPU time 0.56 seconds
Started Jul 14 04:53:38 PM PDT 24
Finished Jul 14 04:53:39 PM PDT 24
Peak memory 195020 kb
Host smart-4ed9083b-45f2-45c2-b69e-b219920bc203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060747420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2060747420
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2990976579
Short name T1246
Test name
Test status
Simulation time 17597097 ps
CPU time 0.6 seconds
Started Jul 14 04:53:40 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 195056 kb
Host smart-05139dea-2481-4ba5-803e-357c4a2b6d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990976579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2990976579
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2194474361
Short name T1189
Test name
Test status
Simulation time 12581815 ps
CPU time 0.6 seconds
Started Jul 14 04:53:40 PM PDT 24
Finished Jul 14 04:53:41 PM PDT 24
Peak memory 195040 kb
Host smart-2c09244f-81db-4c37-8be6-8531a827de99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194474361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2194474361
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1275744221
Short name T1233
Test name
Test status
Simulation time 43168684 ps
CPU time 0.54 seconds
Started Jul 14 04:53:40 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 194420 kb
Host smart-f31cacd5-c7e0-4e80-8f25-f41204c3bc64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275744221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1275744221
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2395438631
Short name T1220
Test name
Test status
Simulation time 19142406 ps
CPU time 0.55 seconds
Started Jul 14 04:53:40 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 194604 kb
Host smart-8e767ff5-0b9e-4c61-ba3f-ed58c37b1d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395438631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2395438631
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2268019004
Short name T1269
Test name
Test status
Simulation time 43051905 ps
CPU time 0.59 seconds
Started Jul 14 04:53:40 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 195112 kb
Host smart-29412522-b5af-43fa-ae1c-07874984aa2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268019004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2268019004
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.307808338
Short name T1253
Test name
Test status
Simulation time 33182017 ps
CPU time 0.59 seconds
Started Jul 14 04:53:38 PM PDT 24
Finished Jul 14 04:53:39 PM PDT 24
Peak memory 195032 kb
Host smart-11ece1bc-4ef6-45ee-9b62-086c7292288c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307808338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.307808338
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.546056577
Short name T1271
Test name
Test status
Simulation time 13828525 ps
CPU time 0.59 seconds
Started Jul 14 04:53:40 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 195056 kb
Host smart-2ce2907f-b51e-47d7-9be4-8e93a2473872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546056577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.546056577
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3223859654
Short name T57
Test name
Test status
Simulation time 113346199 ps
CPU time 0.75 seconds
Started Jul 14 04:53:09 PM PDT 24
Finished Jul 14 04:53:10 PM PDT 24
Peak memory 196884 kb
Host smart-b7bef5d9-a0b3-4b51-869e-395c2b1eb694
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223859654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3223859654
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3090730209
Short name T1279
Test name
Test status
Simulation time 60598855 ps
CPU time 1.37 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:01 PM PDT 24
Peak memory 198736 kb
Host smart-823f0ccc-5ff5-445e-9511-e8fb0f5fbfae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090730209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3090730209
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3604628475
Short name T1308
Test name
Test status
Simulation time 36645253 ps
CPU time 0.56 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:52:59 PM PDT 24
Peak memory 196020 kb
Host smart-c50afb32-9a2c-42b0-a006-003bd31cbaed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604628475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3604628475
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.177055263
Short name T1316
Test name
Test status
Simulation time 67142754 ps
CPU time 1.05 seconds
Started Jul 14 04:53:07 PM PDT 24
Finished Jul 14 04:53:09 PM PDT 24
Peak memory 200456 kb
Host smart-b8807239-61df-4861-a071-9718d9b270ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177055263 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.177055263
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3393320637
Short name T1283
Test name
Test status
Simulation time 11107126 ps
CPU time 0.62 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:00 PM PDT 24
Peak memory 196068 kb
Host smart-9cacca1d-456d-4a0f-96ca-55a299671193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393320637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3393320637
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.4034822761
Short name T1314
Test name
Test status
Simulation time 77180576 ps
CPU time 0.59 seconds
Started Jul 14 04:52:58 PM PDT 24
Finished Jul 14 04:53:00 PM PDT 24
Peak memory 195136 kb
Host smart-2f1815c1-e562-4a14-9b7c-f273b82dd330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034822761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4034822761
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1487381898
Short name T1239
Test name
Test status
Simulation time 32720970 ps
CPU time 0.82 seconds
Started Jul 14 04:53:05 PM PDT 24
Finished Jul 14 04:53:06 PM PDT 24
Peak memory 197836 kb
Host smart-fffe6d74-27b4-4a30-8db0-1557b8871769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487381898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1487381898
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.7365887
Short name T1272
Test name
Test status
Simulation time 378943906 ps
CPU time 1.17 seconds
Started Jul 14 04:52:59 PM PDT 24
Finished Jul 14 04:53:01 PM PDT 24
Peak memory 200684 kb
Host smart-a6625744-e382-49fc-a517-3fb7a7559cae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7365887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.7365887
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2652115697
Short name T1288
Test name
Test status
Simulation time 364383037 ps
CPU time 1.33 seconds
Started Jul 14 04:52:57 PM PDT 24
Finished Jul 14 04:52:59 PM PDT 24
Peak memory 199900 kb
Host smart-49508511-0040-4857-be30-3d823d49b7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652115697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2652115697
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2392135870
Short name T1280
Test name
Test status
Simulation time 15333036 ps
CPU time 0.58 seconds
Started Jul 14 04:53:41 PM PDT 24
Finished Jul 14 04:53:43 PM PDT 24
Peak memory 195084 kb
Host smart-27fc8322-7b4f-4342-8283-0463c29abb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392135870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2392135870
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.366055691
Short name T1236
Test name
Test status
Simulation time 15163567 ps
CPU time 0.58 seconds
Started Jul 14 04:53:40 PM PDT 24
Finished Jul 14 04:53:41 PM PDT 24
Peak memory 195060 kb
Host smart-8cba0c28-9d35-4df6-b614-2427234b024c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366055691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.366055691
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1861879175
Short name T1291
Test name
Test status
Simulation time 11147254 ps
CPU time 0.6 seconds
Started Jul 14 04:53:42 PM PDT 24
Finished Jul 14 04:53:43 PM PDT 24
Peak memory 195112 kb
Host smart-93d7b44c-cede-4bad-bfd4-54b4c0872509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861879175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1861879175
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.182135348
Short name T1208
Test name
Test status
Simulation time 13139660 ps
CPU time 0.59 seconds
Started Jul 14 04:53:42 PM PDT 24
Finished Jul 14 04:53:43 PM PDT 24
Peak memory 195032 kb
Host smart-d41fdf85-6db3-4cb5-8849-6cf67151111b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182135348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.182135348
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.230014457
Short name T1265
Test name
Test status
Simulation time 68813024 ps
CPU time 0.57 seconds
Started Jul 14 04:53:41 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 194988 kb
Host smart-54a17dfc-3b16-4340-9cf0-5380afb4fc49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230014457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.230014457
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4241800245
Short name T1262
Test name
Test status
Simulation time 16441369 ps
CPU time 0.62 seconds
Started Jul 14 04:53:39 PM PDT 24
Finished Jul 14 04:53:40 PM PDT 24
Peak memory 195076 kb
Host smart-8674a66a-fba6-4411-8d54-e7fce349dfe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241800245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4241800245
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2958688399
Short name T1258
Test name
Test status
Simulation time 35020980 ps
CPU time 0.57 seconds
Started Jul 14 04:53:39 PM PDT 24
Finished Jul 14 04:53:41 PM PDT 24
Peak memory 194968 kb
Host smart-cebe4c13-1330-49a0-b021-456d31dba244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958688399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2958688399
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1472392986
Short name T1211
Test name
Test status
Simulation time 11602742 ps
CPU time 0.57 seconds
Started Jul 14 04:53:38 PM PDT 24
Finished Jul 14 04:53:39 PM PDT 24
Peak memory 195076 kb
Host smart-65d1acfe-8525-43db-a92d-5173f0f17f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472392986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1472392986
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3288816689
Short name T1234
Test name
Test status
Simulation time 14154610 ps
CPU time 0.65 seconds
Started Jul 14 04:53:41 PM PDT 24
Finished Jul 14 04:53:43 PM PDT 24
Peak memory 195048 kb
Host smart-a6b731ac-68d1-4b68-9ab1-1c7ef406bd78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288816689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3288816689
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3936806673
Short name T1191
Test name
Test status
Simulation time 30421737 ps
CPU time 0.59 seconds
Started Jul 14 04:53:41 PM PDT 24
Finished Jul 14 04:53:43 PM PDT 24
Peak memory 195052 kb
Host smart-8526363e-7c58-4e44-bc0a-a01bd61233cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936806673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3936806673
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2076813230
Short name T68
Test name
Test status
Simulation time 26556173 ps
CPU time 0.82 seconds
Started Jul 14 04:53:06 PM PDT 24
Finished Jul 14 04:53:08 PM PDT 24
Peak memory 196996 kb
Host smart-694a8421-1b2f-4e41-9b70-7fc11984a562
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076813230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2076813230
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1185372418
Short name T70
Test name
Test status
Simulation time 408526002 ps
CPU time 2.76 seconds
Started Jul 14 04:53:05 PM PDT 24
Finished Jul 14 04:53:08 PM PDT 24
Peak memory 198748 kb
Host smart-f252263a-7768-4d0e-8170-8d6b9821b392
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185372418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1185372418
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1899877618
Short name T1284
Test name
Test status
Simulation time 16505068 ps
CPU time 0.6 seconds
Started Jul 14 04:53:06 PM PDT 24
Finished Jul 14 04:53:07 PM PDT 24
Peak memory 196040 kb
Host smart-8ea00904-2cc0-4bb4-8390-6d6b5cb23e40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899877618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1899877618
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3105958111
Short name T1304
Test name
Test status
Simulation time 43980475 ps
CPU time 1.1 seconds
Started Jul 14 04:53:04 PM PDT 24
Finished Jul 14 04:53:06 PM PDT 24
Peak memory 200796 kb
Host smart-35520e65-63ed-4e4f-aad4-054033997523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105958111 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3105958111
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3060157885
Short name T82
Test name
Test status
Simulation time 116320460 ps
CPU time 0.58 seconds
Started Jul 14 04:53:09 PM PDT 24
Finished Jul 14 04:53:10 PM PDT 24
Peak memory 196064 kb
Host smart-70d605b7-85b8-4cf5-abee-be3678de7cbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060157885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3060157885
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2018639712
Short name T1188
Test name
Test status
Simulation time 64583340 ps
CPU time 0.57 seconds
Started Jul 14 04:53:06 PM PDT 24
Finished Jul 14 04:53:08 PM PDT 24
Peak memory 195112 kb
Host smart-2a899432-aca8-46db-9bd3-9f66a43dcbaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018639712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2018639712
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1638411512
Short name T1244
Test name
Test status
Simulation time 89741000 ps
CPU time 0.75 seconds
Started Jul 14 04:53:05 PM PDT 24
Finished Jul 14 04:53:06 PM PDT 24
Peak memory 198244 kb
Host smart-f2e845c3-b243-465c-97b5-c6246c2e6584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638411512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1638411512
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1337353979
Short name T1261
Test name
Test status
Simulation time 218048738 ps
CPU time 2.44 seconds
Started Jul 14 04:53:05 PM PDT 24
Finished Jul 14 04:53:09 PM PDT 24
Peak memory 200684 kb
Host smart-57da2a84-87e4-4de3-ac5d-109db7dc3324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337353979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1337353979
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2814403687
Short name T97
Test name
Test status
Simulation time 94428062 ps
CPU time 1.32 seconds
Started Jul 14 04:53:06 PM PDT 24
Finished Jul 14 04:53:09 PM PDT 24
Peak memory 199992 kb
Host smart-a79a26d4-a3f1-4ae3-8bf6-88b8da2e0391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814403687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2814403687
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1506586492
Short name T1207
Test name
Test status
Simulation time 11962661 ps
CPU time 0.59 seconds
Started Jul 14 04:53:41 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 195028 kb
Host smart-29d40ac8-d954-4bd6-9b4b-ec69c355d059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506586492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1506586492
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.4272340130
Short name T1204
Test name
Test status
Simulation time 11514231 ps
CPU time 0.56 seconds
Started Jul 14 04:53:41 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 195036 kb
Host smart-aff2ae57-d2c7-44a2-9d20-08689fd00389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272340130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4272340130
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.535717026
Short name T1215
Test name
Test status
Simulation time 62947268 ps
CPU time 0.56 seconds
Started Jul 14 04:53:39 PM PDT 24
Finished Jul 14 04:53:40 PM PDT 24
Peak memory 195136 kb
Host smart-2c85d338-4f67-4557-bfbc-db681a077102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535717026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.535717026
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1420186814
Short name T1238
Test name
Test status
Simulation time 11610927 ps
CPU time 0.57 seconds
Started Jul 14 04:53:38 PM PDT 24
Finished Jul 14 04:53:39 PM PDT 24
Peak memory 195020 kb
Host smart-96fdeef0-8c22-48c9-82e2-e959ae468872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420186814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1420186814
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.337271070
Short name T1303
Test name
Test status
Simulation time 13997092 ps
CPU time 0.58 seconds
Started Jul 14 04:53:40 PM PDT 24
Finished Jul 14 04:53:42 PM PDT 24
Peak memory 194972 kb
Host smart-357a9584-65dc-4480-925c-fe75592bd317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337271070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.337271070
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1759776627
Short name T1252
Test name
Test status
Simulation time 40597216 ps
CPU time 0.57 seconds
Started Jul 14 04:53:39 PM PDT 24
Finished Jul 14 04:53:41 PM PDT 24
Peak memory 195024 kb
Host smart-4326c436-923a-402d-bc6d-e8f10b03af3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759776627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1759776627
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2610133387
Short name T1184
Test name
Test status
Simulation time 21457032 ps
CPU time 0.62 seconds
Started Jul 14 04:53:42 PM PDT 24
Finished Jul 14 04:53:43 PM PDT 24
Peak memory 194960 kb
Host smart-c7bacb1e-a94f-46c8-a84c-5d71ee562fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610133387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2610133387
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1181900141
Short name T1313
Test name
Test status
Simulation time 12416861 ps
CPU time 0.58 seconds
Started Jul 14 04:53:45 PM PDT 24
Finished Jul 14 04:53:46 PM PDT 24
Peak memory 195136 kb
Host smart-9d8ad9f1-1d50-4b0d-bda6-54401683a48b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181900141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1181900141
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1281167475
Short name T1240
Test name
Test status
Simulation time 39459201 ps
CPU time 0.55 seconds
Started Jul 14 04:53:46 PM PDT 24
Finished Jul 14 04:53:48 PM PDT 24
Peak memory 195060 kb
Host smart-3c20eacd-193c-4b8f-96da-8738e11d070e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281167475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1281167475
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2637212310
Short name T1224
Test name
Test status
Simulation time 52428597 ps
CPU time 0.6 seconds
Started Jul 14 04:53:46 PM PDT 24
Finished Jul 14 04:53:47 PM PDT 24
Peak memory 194940 kb
Host smart-e9051b6a-0d9b-4f51-9c08-5c26bf1b09f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637212310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2637212310
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.543799689
Short name T1195
Test name
Test status
Simulation time 419827743 ps
CPU time 0.81 seconds
Started Jul 14 04:53:11 PM PDT 24
Finished Jul 14 04:53:13 PM PDT 24
Peak memory 199448 kb
Host smart-af60458d-fbb0-4b95-8128-4751091a4d98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543799689 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.543799689
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1393208257
Short name T1219
Test name
Test status
Simulation time 43163523 ps
CPU time 0.62 seconds
Started Jul 14 04:53:06 PM PDT 24
Finished Jul 14 04:53:07 PM PDT 24
Peak memory 196136 kb
Host smart-45510ebf-7479-40ad-8b1f-5109780fa24c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393208257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1393208257
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3311574254
Short name T1296
Test name
Test status
Simulation time 16068964 ps
CPU time 0.58 seconds
Started Jul 14 04:53:06 PM PDT 24
Finished Jul 14 04:53:07 PM PDT 24
Peak memory 194988 kb
Host smart-3157a9d6-e281-4cc7-be40-982dae72139d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311574254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3311574254
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3671729853
Short name T1245
Test name
Test status
Simulation time 17810954 ps
CPU time 0.61 seconds
Started Jul 14 04:53:09 PM PDT 24
Finished Jul 14 04:53:10 PM PDT 24
Peak memory 196064 kb
Host smart-9ad2c2e2-993f-41d8-a5fb-2efb4b494bb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671729853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3671729853
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1492054557
Short name T1289
Test name
Test status
Simulation time 32386794 ps
CPU time 1.42 seconds
Started Jul 14 04:53:06 PM PDT 24
Finished Jul 14 04:53:09 PM PDT 24
Peak memory 200772 kb
Host smart-fd096a24-4b72-4a0f-9dd3-dace3967d4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492054557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1492054557
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3438967210
Short name T98
Test name
Test status
Simulation time 103729163 ps
CPU time 1.36 seconds
Started Jul 14 04:53:06 PM PDT 24
Finished Jul 14 04:53:09 PM PDT 24
Peak memory 200064 kb
Host smart-1207f200-8601-4589-a554-2f5e0f2cfa3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438967210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3438967210
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2762245879
Short name T1292
Test name
Test status
Simulation time 24797837 ps
CPU time 0.95 seconds
Started Jul 14 04:53:12 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 200508 kb
Host smart-83c7cdeb-161c-4c40-a694-db1875787b8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762245879 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2762245879
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3840442160
Short name T88
Test name
Test status
Simulation time 11629787 ps
CPU time 0.61 seconds
Started Jul 14 04:53:12 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 196060 kb
Host smart-7386fa65-ea0b-4ffb-99da-4bf0d494687f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840442160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3840442160
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1492293057
Short name T1194
Test name
Test status
Simulation time 38970665 ps
CPU time 0.57 seconds
Started Jul 14 04:53:13 PM PDT 24
Finished Jul 14 04:53:15 PM PDT 24
Peak memory 195096 kb
Host smart-afb057b5-8f17-41e5-ac1c-8e7809819fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492293057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1492293057
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2342181702
Short name T1268
Test name
Test status
Simulation time 259793696 ps
CPU time 0.76 seconds
Started Jul 14 04:53:12 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 197788 kb
Host smart-b7b6cd9b-e660-4640-80c8-107db7ce03d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342181702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2342181702
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1205093967
Short name T1217
Test name
Test status
Simulation time 120656827 ps
CPU time 1.89 seconds
Started Jul 14 04:53:13 PM PDT 24
Finished Jul 14 04:53:16 PM PDT 24
Peak memory 200724 kb
Host smart-01bc1462-3101-4bf4-9a42-f3ad6877b5b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205093967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1205093967
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.342478024
Short name T1301
Test name
Test status
Simulation time 75371611 ps
CPU time 1.36 seconds
Started Jul 14 04:53:12 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 199964 kb
Host smart-5be1afc5-9205-4752-8d47-e818cb5395ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342478024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.342478024
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3774707934
Short name T1221
Test name
Test status
Simulation time 30625074 ps
CPU time 0.79 seconds
Started Jul 14 04:53:15 PM PDT 24
Finished Jul 14 04:53:16 PM PDT 24
Peak memory 200404 kb
Host smart-9efbe08e-a17c-46a8-87ba-ba54ae9a5fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774707934 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3774707934
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.712820107
Short name T1273
Test name
Test status
Simulation time 31011811 ps
CPU time 0.63 seconds
Started Jul 14 04:53:13 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 196064 kb
Host smart-f55f8c9e-445c-428e-a31f-3e5730c88e04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712820107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.712820107
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1895771598
Short name T1218
Test name
Test status
Simulation time 22699515 ps
CPU time 0.58 seconds
Started Jul 14 04:53:13 PM PDT 24
Finished Jul 14 04:53:15 PM PDT 24
Peak memory 195020 kb
Host smart-c1acbee5-3b6a-48b2-9be6-e503164b0c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895771598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1895771598
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3145993745
Short name T85
Test name
Test status
Simulation time 31084869 ps
CPU time 0.76 seconds
Started Jul 14 04:53:12 PM PDT 24
Finished Jul 14 04:53:13 PM PDT 24
Peak memory 197528 kb
Host smart-ac0c0da6-6ca5-414f-8aa5-be32601b8ccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145993745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3145993745
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.755524471
Short name T1310
Test name
Test status
Simulation time 1637529390 ps
CPU time 1.82 seconds
Started Jul 14 04:53:15 PM PDT 24
Finished Jul 14 04:53:17 PM PDT 24
Peak memory 200748 kb
Host smart-4ba24ebe-f68c-40dd-bb52-bd5417b29b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755524471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.755524471
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.392723453
Short name T1230
Test name
Test status
Simulation time 75589081 ps
CPU time 1.28 seconds
Started Jul 14 04:53:12 PM PDT 24
Finished Jul 14 04:53:15 PM PDT 24
Peak memory 199836 kb
Host smart-39a2a6ee-6cd3-4688-abb9-1266b3d7a21e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392723453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.392723453
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1134193732
Short name T1299
Test name
Test status
Simulation time 33357393 ps
CPU time 0.78 seconds
Started Jul 14 04:53:13 PM PDT 24
Finished Jul 14 04:53:15 PM PDT 24
Peak memory 198968 kb
Host smart-072f0e69-51fe-4b4b-9462-a141f1f490ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134193732 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1134193732
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.893832280
Short name T1312
Test name
Test status
Simulation time 18388652 ps
CPU time 0.66 seconds
Started Jul 14 04:53:11 PM PDT 24
Finished Jul 14 04:53:12 PM PDT 24
Peak memory 196148 kb
Host smart-4425ee84-7970-4d45-90f9-0015df445204
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893832280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.893832280
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3741235649
Short name T1197
Test name
Test status
Simulation time 26353671 ps
CPU time 0.58 seconds
Started Jul 14 04:53:12 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 195092 kb
Host smart-a272b998-bdfb-4576-a64b-a2a72b5d9d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741235649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3741235649
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3331575018
Short name T1298
Test name
Test status
Simulation time 23987912 ps
CPU time 0.62 seconds
Started Jul 14 04:53:13 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 196216 kb
Host smart-031538c4-c734-4e37-adb8-7c7cb232a441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331575018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3331575018
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3429179664
Short name T1198
Test name
Test status
Simulation time 121496653 ps
CPU time 2.05 seconds
Started Jul 14 04:53:12 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 200684 kb
Host smart-a503908d-ddcb-47a8-9f23-ea70cf730516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429179664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3429179664
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.239986859
Short name T1232
Test name
Test status
Simulation time 255254993 ps
CPU time 1.29 seconds
Started Jul 14 04:53:16 PM PDT 24
Finished Jul 14 04:53:18 PM PDT 24
Peak memory 200092 kb
Host smart-1a7eb898-bca7-4594-8664-3d46a1f21225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239986859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.239986859
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.16366221
Short name T1254
Test name
Test status
Simulation time 63283827 ps
CPU time 0.85 seconds
Started Jul 14 04:53:18 PM PDT 24
Finished Jul 14 04:53:19 PM PDT 24
Peak memory 200540 kb
Host smart-59e155e9-e760-4d6c-b492-00b3151204a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16366221 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.16366221
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3782541852
Short name T1241
Test name
Test status
Simulation time 23449086 ps
CPU time 0.62 seconds
Started Jul 14 04:53:18 PM PDT 24
Finished Jul 14 04:53:19 PM PDT 24
Peak memory 196136 kb
Host smart-0f06252e-45ea-4860-9732-83f326eefb8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782541852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3782541852
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2971685093
Short name T1216
Test name
Test status
Simulation time 39871211 ps
CPU time 0.59 seconds
Started Jul 14 04:53:15 PM PDT 24
Finished Jul 14 04:53:16 PM PDT 24
Peak memory 195116 kb
Host smart-a5f98aea-3649-4eb3-bea5-a6959229b145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971685093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2971685093
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1492160217
Short name T89
Test name
Test status
Simulation time 17008751 ps
CPU time 0.72 seconds
Started Jul 14 04:53:20 PM PDT 24
Finished Jul 14 04:53:22 PM PDT 24
Peak memory 197572 kb
Host smart-dc169370-07ca-4d39-a7ce-987d73af11a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492160217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1492160217
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.218280275
Short name T1192
Test name
Test status
Simulation time 150949669 ps
CPU time 1.03 seconds
Started Jul 14 04:53:16 PM PDT 24
Finished Jul 14 04:53:18 PM PDT 24
Peak memory 200456 kb
Host smart-f3aa622b-f35b-4f6b-b65a-1d069c1871e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218280275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.218280275
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3747589930
Short name T1257
Test name
Test status
Simulation time 48506876 ps
CPU time 0.94 seconds
Started Jul 14 04:53:16 PM PDT 24
Finished Jul 14 04:53:17 PM PDT 24
Peak memory 199320 kb
Host smart-b70103d8-9a80-482e-8a46-f5c3d7eafb7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747589930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3747589930
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.14687630
Short name T631
Test name
Test status
Simulation time 92022503 ps
CPU time 0.55 seconds
Started Jul 14 04:23:21 PM PDT 24
Finished Jul 14 04:23:23 PM PDT 24
Peak memory 195100 kb
Host smart-bcb77a11-1e5f-4e5e-a4d5-f8dea4156cfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14687630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.14687630
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3973983760
Short name T894
Test name
Test status
Simulation time 33104153041 ps
CPU time 15.61 seconds
Started Jul 14 04:22:55 PM PDT 24
Finished Jul 14 04:23:11 PM PDT 24
Peak memory 199076 kb
Host smart-e1b14764-ec3e-4452-a02f-2c9fd9a92c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973983760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3973983760
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.840638809
Short name T843
Test name
Test status
Simulation time 96397445673 ps
CPU time 30.54 seconds
Started Jul 14 04:22:55 PM PDT 24
Finished Jul 14 04:23:26 PM PDT 24
Peak memory 199296 kb
Host smart-be74b0d9-c480-4d7d-9fc1-6812abd59a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840638809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.840638809
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3369557903
Short name T301
Test name
Test status
Simulation time 28509909635 ps
CPU time 8.03 seconds
Started Jul 14 04:18:02 PM PDT 24
Finished Jul 14 04:18:11 PM PDT 24
Peak memory 199452 kb
Host smart-243214c4-329e-456d-baf0-423415edf9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369557903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3369557903
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1034947663
Short name T616
Test name
Test status
Simulation time 92762472605 ps
CPU time 36.52 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:23:37 PM PDT 24
Peak memory 196740 kb
Host smart-a0d0cad0-aee9-402f-bc7d-81a933a0e616
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034947663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1034947663
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.313096586
Short name T1037
Test name
Test status
Simulation time 65280318455 ps
CPU time 241.66 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:27:33 PM PDT 24
Peak memory 199732 kb
Host smart-bf0edec5-532b-4f95-b666-6c33bd8e9eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313096586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.313096586
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.4163898394
Short name T505
Test name
Test status
Simulation time 6415410798 ps
CPU time 3.71 seconds
Started Jul 14 04:23:24 PM PDT 24
Finished Jul 14 04:23:28 PM PDT 24
Peak memory 197256 kb
Host smart-6d13bec8-a24e-4205-8df5-00d2fa28c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163898394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.4163898394
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3559678248
Short name T320
Test name
Test status
Simulation time 34576688017 ps
CPU time 14.72 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:22:11 PM PDT 24
Peak memory 198600 kb
Host smart-76e2b1a0-0157-4c69-bb64-73b96697b63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559678248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3559678248
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2993059941
Short name T752
Test name
Test status
Simulation time 26896882671 ps
CPU time 248.06 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:27:39 PM PDT 24
Peak memory 199804 kb
Host smart-acc24ec5-fe82-40fd-88b0-91d7964906a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993059941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2993059941
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3098361300
Short name T1152
Test name
Test status
Simulation time 4123490081 ps
CPU time 5.16 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:22:01 PM PDT 24
Peak memory 197696 kb
Host smart-95f95185-fbfc-4e07-93de-e6990b0aac13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098361300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3098361300
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.262924119
Short name T728
Test name
Test status
Simulation time 47306049825 ps
CPU time 40.42 seconds
Started Jul 14 04:19:25 PM PDT 24
Finished Jul 14 04:20:06 PM PDT 24
Peak memory 195700 kb
Host smart-2e41976c-7a5f-44ba-b345-4deb7fd823c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262924119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.262924119
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1732176357
Short name T611
Test name
Test status
Simulation time 486447596 ps
CPU time 1.19 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:23:02 PM PDT 24
Peak memory 199332 kb
Host smart-7e95aa1d-ae44-4413-97e8-829e1f63791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732176357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1732176357
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3312398775
Short name T200
Test name
Test status
Simulation time 196519857264 ps
CPU time 186.64 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:26:37 PM PDT 24
Peak memory 199772 kb
Host smart-0d5fd13b-c485-4035-b7b4-fd0bcae9847b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312398775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3312398775
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.387172520
Short name T1038
Test name
Test status
Simulation time 59789602757 ps
CPU time 347.88 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:29:19 PM PDT 24
Peak memory 216228 kb
Host smart-567539f8-ee8c-4566-936d-b95840596483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387172520 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.387172520
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3539114486
Short name T796
Test name
Test status
Simulation time 560631566 ps
CPU time 1.15 seconds
Started Jul 14 04:23:25 PM PDT 24
Finished Jul 14 04:23:27 PM PDT 24
Peak memory 196764 kb
Host smart-57d062a9-c781-48cb-b0c6-6574011c2992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539114486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3539114486
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2387993717
Short name T868
Test name
Test status
Simulation time 39957234468 ps
CPU time 43.99 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 04:23:51 PM PDT 24
Peak memory 199564 kb
Host smart-1951ffad-3e36-4b8a-ab80-0d9a239ce7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387993717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2387993717
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1182174759
Short name T823
Test name
Test status
Simulation time 53910300 ps
CPU time 0.53 seconds
Started Jul 14 04:23:27 PM PDT 24
Finished Jul 14 04:23:28 PM PDT 24
Peak memory 195384 kb
Host smart-9a12b25b-7f6e-4cdc-ad69-dfd660b310da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182174759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1182174759
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4204134494
Short name T508
Test name
Test status
Simulation time 84124015895 ps
CPU time 145.13 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:25:56 PM PDT 24
Peak memory 199552 kb
Host smart-65cece54-e4e4-49c9-930a-9032221ca19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204134494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4204134494
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2267413690
Short name T1062
Test name
Test status
Simulation time 48021515914 ps
CPU time 19.94 seconds
Started Jul 14 04:23:28 PM PDT 24
Finished Jul 14 04:23:49 PM PDT 24
Peak memory 199744 kb
Host smart-a28b5c42-1deb-4766-a418-5cb888b1ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267413690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2267413690
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1585666035
Short name T469
Test name
Test status
Simulation time 9469178561 ps
CPU time 16.99 seconds
Started Jul 14 04:23:27 PM PDT 24
Finished Jul 14 04:23:44 PM PDT 24
Peak memory 199708 kb
Host smart-b93089ea-1540-4d95-8388-84beb2caa177
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585666035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1585666035
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_loopback.3783777170
Short name T778
Test name
Test status
Simulation time 2334646864 ps
CPU time 2.72 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:23:34 PM PDT 24
Peak memory 195764 kb
Host smart-49b3c70b-8a86-4e34-8272-338c45a3ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783777170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3783777170
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2745446113
Short name T419
Test name
Test status
Simulation time 91478521087 ps
CPU time 36.6 seconds
Started Jul 14 04:23:20 PM PDT 24
Finished Jul 14 04:23:58 PM PDT 24
Peak memory 209476 kb
Host smart-c1f15c8d-ece9-4271-b40f-1326304c07f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745446113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2745446113
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3202922557
Short name T840
Test name
Test status
Simulation time 18871065345 ps
CPU time 292.55 seconds
Started Jul 14 04:23:20 PM PDT 24
Finished Jul 14 04:28:14 PM PDT 24
Peak memory 199800 kb
Host smart-8e145d7d-b35e-4a60-bfa2-b2a4c604849a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202922557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3202922557
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1253754793
Short name T889
Test name
Test status
Simulation time 1901963407 ps
CPU time 9.93 seconds
Started Jul 14 04:23:26 PM PDT 24
Finished Jul 14 04:23:37 PM PDT 24
Peak memory 199292 kb
Host smart-7f904523-0acb-433b-b051-7cd2d83d2bac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253754793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1253754793
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3214713403
Short name T900
Test name
Test status
Simulation time 83109822650 ps
CPU time 134.35 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:25:45 PM PDT 24
Peak memory 199304 kb
Host smart-1eb1bdf6-c4fc-4354-bba2-6ed8258fd23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214713403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3214713403
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2519132814
Short name T555
Test name
Test status
Simulation time 3611445624 ps
CPU time 3.6 seconds
Started Jul 14 04:23:28 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 196024 kb
Host smart-941dec0c-13e3-4453-bec2-81166bd09691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519132814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2519132814
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2221171602
Short name T102
Test name
Test status
Simulation time 67596296 ps
CPU time 0.76 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 217940 kb
Host smart-f961295f-c071-4d3a-8dfe-bb96b99908a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221171602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2221171602
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.898950217
Short name T490
Test name
Test status
Simulation time 828407731 ps
CPU time 1.6 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 198392 kb
Host smart-3fd27485-fdcb-4555-bc73-aebf5f940a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898950217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.898950217
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3713162408
Short name T633
Test name
Test status
Simulation time 168209356561 ps
CPU time 253.44 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:27:47 PM PDT 24
Peak memory 199728 kb
Host smart-e9e4cb31-2da1-4583-998b-79ac3e12c3ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713162408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3713162408
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2489908014
Short name T656
Test name
Test status
Simulation time 215944993742 ps
CPU time 745.34 seconds
Started Jul 14 04:23:22 PM PDT 24
Finished Jul 14 04:35:48 PM PDT 24
Peak memory 224656 kb
Host smart-d0ace670-d913-44de-88c6-90c7fa0738df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489908014 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2489908014
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.50670864
Short name T694
Test name
Test status
Simulation time 1754345872 ps
CPU time 1.61 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:35 PM PDT 24
Peak memory 198084 kb
Host smart-a9b1092a-f544-42e1-a9ae-cf25b5ad61df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50670864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.50670864
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3129486846
Short name T446
Test name
Test status
Simulation time 69194536232 ps
CPU time 29.15 seconds
Started Jul 14 04:23:25 PM PDT 24
Finished Jul 14 04:23:55 PM PDT 24
Peak memory 199748 kb
Host smart-91ac06de-45dc-4fb6-b575-a7b60b370409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129486846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3129486846
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.592787553
Short name T718
Test name
Test status
Simulation time 11847916 ps
CPU time 0.54 seconds
Started Jul 14 04:23:59 PM PDT 24
Finished Jul 14 04:24:00 PM PDT 24
Peak memory 194772 kb
Host smart-fb418633-4911-4abc-b49e-b0ec2ff00ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592787553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.592787553
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1928468276
Short name T380
Test name
Test status
Simulation time 10784608504 ps
CPU time 14.94 seconds
Started Jul 14 04:23:50 PM PDT 24
Finished Jul 14 04:24:06 PM PDT 24
Peak memory 199796 kb
Host smart-2812dfc9-c621-4e77-99af-bf7cf8cfddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928468276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1928468276
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1566779004
Short name T675
Test name
Test status
Simulation time 25970614670 ps
CPU time 40.92 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:24:44 PM PDT 24
Peak memory 199704 kb
Host smart-e6a924b0-1420-4560-bff9-aa5343a02d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566779004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1566779004
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.2070164818
Short name T471
Test name
Test status
Simulation time 11028958890 ps
CPU time 22.19 seconds
Started Jul 14 04:23:48 PM PDT 24
Finished Jul 14 04:24:11 PM PDT 24
Peak memory 199788 kb
Host smart-a448ce38-3dfe-41cf-a573-fbd603224cb7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070164818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2070164818
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2117985635
Short name T1145
Test name
Test status
Simulation time 203353515556 ps
CPU time 532.04 seconds
Started Jul 14 04:23:45 PM PDT 24
Finished Jul 14 04:32:38 PM PDT 24
Peak memory 199664 kb
Host smart-efccca25-8f9d-442a-923b-6be166a3c988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117985635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2117985635
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3258879105
Short name T1135
Test name
Test status
Simulation time 8123042682 ps
CPU time 14.96 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:24:10 PM PDT 24
Peak memory 199652 kb
Host smart-5a5164fa-89c0-4c76-8f20-8311358d1b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258879105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3258879105
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.4184024389
Short name T369
Test name
Test status
Simulation time 279667489082 ps
CPU time 46.12 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:24:35 PM PDT 24
Peak memory 208216 kb
Host smart-1fae194f-0a41-4866-90cd-8467be46d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184024389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.4184024389
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.458213437
Short name T727
Test name
Test status
Simulation time 17932064777 ps
CPU time 52.74 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:24:37 PM PDT 24
Peak memory 199624 kb
Host smart-ba5c22dc-5c63-4c77-ba44-ee7576f7715c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458213437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.458213437
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.18834300
Short name T763
Test name
Test status
Simulation time 2557490402 ps
CPU time 17.3 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:24:13 PM PDT 24
Peak memory 197684 kb
Host smart-c6607e0d-8861-4e64-bce7-887ac0653d28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18834300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.18834300
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2756491957
Short name T376
Test name
Test status
Simulation time 18029170170 ps
CPU time 29.13 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 199820 kb
Host smart-007b5b69-d951-4afc-b4c7-79bb96498e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756491957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2756491957
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2513239699
Short name T772
Test name
Test status
Simulation time 33690512827 ps
CPU time 8.09 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:23:55 PM PDT 24
Peak memory 196196 kb
Host smart-9325e43b-6916-40e9-8950-9c0beb1176c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513239699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2513239699
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.961420700
Short name T666
Test name
Test status
Simulation time 512096693 ps
CPU time 1.96 seconds
Started Jul 14 04:24:04 PM PDT 24
Finished Jul 14 04:24:07 PM PDT 24
Peak memory 199400 kb
Host smart-74e15cfe-ee2c-4ba0-b965-b83008754aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961420700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.961420700
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1078912768
Short name T996
Test name
Test status
Simulation time 193130518527 ps
CPU time 959.91 seconds
Started Jul 14 04:23:56 PM PDT 24
Finished Jul 14 04:39:57 PM PDT 24
Peak memory 224660 kb
Host smart-aa396ffb-f267-4892-b7a6-e53d319c6867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078912768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1078912768
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1381867891
Short name T367
Test name
Test status
Simulation time 895657514 ps
CPU time 2.89 seconds
Started Jul 14 04:24:00 PM PDT 24
Finished Jul 14 04:24:04 PM PDT 24
Peak memory 198128 kb
Host smart-063bfb97-060d-490a-9856-7a6bbac72e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381867891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1381867891
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.930970732
Short name T414
Test name
Test status
Simulation time 124491069497 ps
CPU time 10.34 seconds
Started Jul 14 04:23:53 PM PDT 24
Finished Jul 14 04:24:04 PM PDT 24
Peak memory 199492 kb
Host smart-f3fee0a7-8d34-4e44-a2dc-89a97419327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930970732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.930970732
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2674401249
Short name T803
Test name
Test status
Simulation time 139638222213 ps
CPU time 255.94 seconds
Started Jul 14 04:26:34 PM PDT 24
Finished Jul 14 04:30:50 PM PDT 24
Peak memory 199804 kb
Host smart-e24d6d4b-ee86-41da-b94e-677683f3219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674401249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2674401249
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.340134614
Short name T543
Test name
Test status
Simulation time 54404176524 ps
CPU time 36.11 seconds
Started Jul 14 04:26:37 PM PDT 24
Finished Jul 14 04:27:15 PM PDT 24
Peak memory 199764 kb
Host smart-9c4ec97f-c976-4c8a-a95b-8f704f506fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340134614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.340134614
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2426325414
Short name T75
Test name
Test status
Simulation time 73958578693 ps
CPU time 42.98 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:27:21 PM PDT 24
Peak memory 199492 kb
Host smart-c77d729a-0aa9-444d-a925-f84d12882b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426325414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2426325414
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2508010702
Short name T858
Test name
Test status
Simulation time 105021697939 ps
CPU time 36.22 seconds
Started Jul 14 04:26:34 PM PDT 24
Finished Jul 14 04:27:11 PM PDT 24
Peak memory 199684 kb
Host smart-a33b8ed7-a704-46b7-ba3f-8a0f17b71ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508010702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2508010702
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3283301545
Short name T216
Test name
Test status
Simulation time 43769050777 ps
CPU time 44.85 seconds
Started Jul 14 04:26:35 PM PDT 24
Finished Jul 14 04:27:21 PM PDT 24
Peak memory 199804 kb
Host smart-5e50544e-a224-4075-817e-cf022dfe2a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283301545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3283301545
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.4197317673
Short name T137
Test name
Test status
Simulation time 8606526377 ps
CPU time 14.32 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:26:51 PM PDT 24
Peak memory 199736 kb
Host smart-26315ccb-b4c0-4555-8f59-e0b82b1430a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197317673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4197317673
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2892636685
Short name T1176
Test name
Test status
Simulation time 101279131155 ps
CPU time 39.84 seconds
Started Jul 14 04:26:34 PM PDT 24
Finished Jul 14 04:27:15 PM PDT 24
Peak memory 199824 kb
Host smart-0fee8072-912e-4b2c-8250-defd9d68fb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892636685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2892636685
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.322353033
Short name T433
Test name
Test status
Simulation time 115133256740 ps
CPU time 192.31 seconds
Started Jul 14 04:26:37 PM PDT 24
Finished Jul 14 04:29:51 PM PDT 24
Peak memory 199708 kb
Host smart-97340857-6e1b-407e-81e0-673a79cf2cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322353033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.322353033
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.943908760
Short name T1099
Test name
Test status
Simulation time 37987478766 ps
CPU time 25.74 seconds
Started Jul 14 04:26:38 PM PDT 24
Finished Jul 14 04:27:05 PM PDT 24
Peak memory 199848 kb
Host smart-baef34e2-a2e5-4895-bc30-17a0d6433ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943908760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.943908760
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3383535417
Short name T973
Test name
Test status
Simulation time 175642126347 ps
CPU time 242.98 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:27:58 PM PDT 24
Peak memory 199760 kb
Host smart-608c9a74-b5b2-42ec-98ca-9fcbf938874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383535417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3383535417
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2582677189
Short name T983
Test name
Test status
Simulation time 105418367526 ps
CPU time 45.96 seconds
Started Jul 14 04:24:09 PM PDT 24
Finished Jul 14 04:24:56 PM PDT 24
Peak memory 199656 kb
Host smart-c325242c-92b5-4baf-968b-a2d4efe271d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582677189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2582677189
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3487116691
Short name T698
Test name
Test status
Simulation time 69820178390 ps
CPU time 112.34 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:26:00 PM PDT 24
Peak memory 199732 kb
Host smart-ac50d50b-a8b2-4075-9e8c-a068244f2468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487116691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3487116691
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.140992263
Short name T440
Test name
Test status
Simulation time 51684957790 ps
CPU time 41.87 seconds
Started Jul 14 04:23:55 PM PDT 24
Finished Jul 14 04:24:38 PM PDT 24
Peak memory 199516 kb
Host smart-958f5555-6e1b-41e0-ba8c-6eabea9fcf51
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140992263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.140992263
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3403167018
Short name T477
Test name
Test status
Simulation time 66317803899 ps
CPU time 552.32 seconds
Started Jul 14 04:24:01 PM PDT 24
Finished Jul 14 04:33:14 PM PDT 24
Peak memory 199680 kb
Host smart-dc24813f-67a9-49c2-a3dc-7f5728bec632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403167018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3403167018
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.635802361
Short name T971
Test name
Test status
Simulation time 10175758681 ps
CPU time 10.99 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:24:14 PM PDT 24
Peak memory 199684 kb
Host smart-59083b49-4279-47b8-a46b-2886eb57e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635802361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.635802361
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3182453609
Short name T272
Test name
Test status
Simulation time 550409503446 ps
CPU time 99.21 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:25:46 PM PDT 24
Peak memory 199360 kb
Host smart-26dc3384-0784-46fd-a21c-f1c7dee704da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182453609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3182453609
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.707803685
Short name T119
Test name
Test status
Simulation time 28899970254 ps
CPU time 390.71 seconds
Started Jul 14 04:23:59 PM PDT 24
Finished Jul 14 04:30:31 PM PDT 24
Peak memory 199744 kb
Host smart-5948889a-bf58-4add-8c4d-a781fc9cca22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707803685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.707803685
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.117823871
Short name T709
Test name
Test status
Simulation time 7105272251 ps
CPU time 5.94 seconds
Started Jul 14 04:24:12 PM PDT 24
Finished Jul 14 04:24:19 PM PDT 24
Peak memory 198992 kb
Host smart-5e104068-3cbb-42e3-a52a-55e64d386f77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117823871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.117823871
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2243775914
Short name T600
Test name
Test status
Simulation time 54529120747 ps
CPU time 16.1 seconds
Started Jul 14 04:24:08 PM PDT 24
Finished Jul 14 04:24:25 PM PDT 24
Peak memory 199680 kb
Host smart-f5f59c70-bcbf-447f-8e14-42e4c665197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243775914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2243775914
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3045607094
Short name T820
Test name
Test status
Simulation time 4141165762 ps
CPU time 2.39 seconds
Started Jul 14 04:23:51 PM PDT 24
Finished Jul 14 04:23:55 PM PDT 24
Peak memory 195960 kb
Host smart-a104f611-083a-4864-9f4d-a08cdad61c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045607094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3045607094
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1953249522
Short name T572
Test name
Test status
Simulation time 928848466 ps
CPU time 4.07 seconds
Started Jul 14 04:24:01 PM PDT 24
Finished Jul 14 04:24:06 PM PDT 24
Peak memory 199648 kb
Host smart-5d553fe6-4b5a-425a-967e-1925528a1b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953249522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1953249522
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2493906814
Short name T159
Test name
Test status
Simulation time 301309999962 ps
CPU time 231.83 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:27:56 PM PDT 24
Peak memory 199676 kb
Host smart-5adcef54-0d07-4a0a-b399-2cf693241b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493906814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2493906814
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2656053068
Short name T873
Test name
Test status
Simulation time 2391228006 ps
CPU time 2.25 seconds
Started Jul 14 04:24:07 PM PDT 24
Finished Jul 14 04:24:10 PM PDT 24
Peak memory 199688 kb
Host smart-417842e4-da67-44c2-8571-54ecc02eb9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656053068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2656053068
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3724631524
Short name T536
Test name
Test status
Simulation time 24799689709 ps
CPU time 34.84 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:24:47 PM PDT 24
Peak memory 199612 kb
Host smart-69ceb4df-9a49-4c10-b43a-78cb1f18c801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724631524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3724631524
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1534112219
Short name T220
Test name
Test status
Simulation time 24551946300 ps
CPU time 41.01 seconds
Started Jul 14 04:26:34 PM PDT 24
Finished Jul 14 04:27:16 PM PDT 24
Peak memory 199652 kb
Host smart-535cf476-2daf-48f8-9b0f-d57677bde3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534112219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1534112219
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.880540188
Short name T681
Test name
Test status
Simulation time 135574391722 ps
CPU time 147.92 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:29:06 PM PDT 24
Peak memory 199776 kb
Host smart-e6ac9a6c-992b-499f-bb67-c53a8c2fb660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880540188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.880540188
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.685332664
Short name T342
Test name
Test status
Simulation time 72780261344 ps
CPU time 31.79 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:27:09 PM PDT 24
Peak memory 199764 kb
Host smart-224e3d67-ad80-4e17-9c4b-dcc8a0cdc937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685332664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.685332664
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.872435487
Short name T434
Test name
Test status
Simulation time 119015931810 ps
CPU time 52.23 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:27:30 PM PDT 24
Peak memory 199472 kb
Host smart-f3566a89-14d8-40ec-b76d-b85292079062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872435487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.872435487
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1688400840
Short name T374
Test name
Test status
Simulation time 150088930870 ps
CPU time 152.14 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:29:10 PM PDT 24
Peak memory 199744 kb
Host smart-6cac3bf3-3039-4e60-a22e-be5279f263da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688400840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1688400840
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1641027181
Short name T411
Test name
Test status
Simulation time 69865992426 ps
CPU time 55.35 seconds
Started Jul 14 04:26:34 PM PDT 24
Finished Jul 14 04:27:30 PM PDT 24
Peak memory 199748 kb
Host smart-44c37087-8174-4bd6-a99c-f0914a16caff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641027181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1641027181
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2515287521
Short name T47
Test name
Test status
Simulation time 47440721902 ps
CPU time 42.66 seconds
Started Jul 14 04:26:37 PM PDT 24
Finished Jul 14 04:27:22 PM PDT 24
Peak memory 199268 kb
Host smart-6010a68c-cf7b-4d72-a183-4a060c17f7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515287521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2515287521
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.690173766
Short name T213
Test name
Test status
Simulation time 82865774069 ps
CPU time 148.34 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:29:05 PM PDT 24
Peak memory 199688 kb
Host smart-6f9ff361-c46d-41c6-99ee-df4a95a6920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690173766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.690173766
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3247338973
Short name T442
Test name
Test status
Simulation time 13357855 ps
CPU time 0.55 seconds
Started Jul 14 04:23:55 PM PDT 24
Finished Jul 14 04:23:56 PM PDT 24
Peak memory 194792 kb
Host smart-061b8360-1de9-403a-993a-7a4667883fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247338973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3247338973
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3336768233
Short name T883
Test name
Test status
Simulation time 172084106475 ps
CPU time 22.62 seconds
Started Jul 14 04:24:04 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 199728 kb
Host smart-45ad23e3-6467-4dcd-bf8f-4a58c7e7ca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336768233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3336768233
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.836196308
Short name T173
Test name
Test status
Simulation time 85875377654 ps
CPU time 43.26 seconds
Started Jul 14 04:24:01 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 199220 kb
Host smart-5c051f67-2346-4ccf-8b48-5c10e998b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836196308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.836196308
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.534851678
Short name T1083
Test name
Test status
Simulation time 36045558160 ps
CPU time 59.35 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:24:55 PM PDT 24
Peak memory 199776 kb
Host smart-5d4d0970-dee4-4819-bb92-47bca5f453b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534851678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.534851678
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2154370711
Short name T1106
Test name
Test status
Simulation time 207442499298 ps
CPU time 192.65 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:27:16 PM PDT 24
Peak memory 199696 kb
Host smart-674af722-5f42-42ae-b510-ec653872792c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154370711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2154370711
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.929282780
Short name T1125
Test name
Test status
Simulation time 4849867467 ps
CPU time 9.77 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:24:22 PM PDT 24
Peak memory 198484 kb
Host smart-e3ea91b1-8861-4d00-aced-ce3d40485cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929282780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.929282780
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.4145284994
Short name T1056
Test name
Test status
Simulation time 148290001600 ps
CPU time 158.91 seconds
Started Jul 14 04:23:59 PM PDT 24
Finished Jul 14 04:26:38 PM PDT 24
Peak memory 200032 kb
Host smart-fd3c5e54-7835-4d93-a77a-526cfb108f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145284994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.4145284994
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1231651202
Short name T1146
Test name
Test status
Simulation time 16253471627 ps
CPU time 897.76 seconds
Started Jul 14 04:24:02 PM PDT 24
Finished Jul 14 04:39:00 PM PDT 24
Peak memory 199740 kb
Host smart-7afbd134-e377-4cb3-8a0d-13fa40bee1ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231651202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1231651202
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4031714267
Short name T664
Test name
Test status
Simulation time 6978872622 ps
CPU time 18.14 seconds
Started Jul 14 04:24:04 PM PDT 24
Finished Jul 14 04:24:24 PM PDT 24
Peak memory 197884 kb
Host smart-4ff3c16d-7d3d-4c45-90e7-cfcf6817b8dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031714267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4031714267
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.681191703
Short name T497
Test name
Test status
Simulation time 39612572357 ps
CPU time 30.2 seconds
Started Jul 14 04:24:12 PM PDT 24
Finished Jul 14 04:24:43 PM PDT 24
Peak memory 199632 kb
Host smart-3c9674d6-acff-4829-85db-dd724a8e4789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681191703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.681191703
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3884436675
Short name T295
Test name
Test status
Simulation time 46337641983 ps
CPU time 26.9 seconds
Started Jul 14 04:24:04 PM PDT 24
Finished Jul 14 04:24:32 PM PDT 24
Peak memory 196152 kb
Host smart-5d9425c6-d71c-4dc5-90de-35988431c52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884436675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3884436675
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3734367080
Short name T707
Test name
Test status
Simulation time 531803268 ps
CPU time 2.02 seconds
Started Jul 14 04:24:08 PM PDT 24
Finished Jul 14 04:24:11 PM PDT 24
Peak memory 198608 kb
Host smart-f964337e-0e01-45cd-a38c-078f575b328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734367080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3734367080
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.146298439
Short name T464
Test name
Test status
Simulation time 206578978047 ps
CPU time 1273.57 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:45:18 PM PDT 24
Peak memory 199768 kb
Host smart-7fd53e88-ff76-4930-be6d-c6a2e110f350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146298439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.146298439
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3810210768
Short name T457
Test name
Test status
Simulation time 108003916409 ps
CPU time 329.4 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:29:36 PM PDT 24
Peak memory 216188 kb
Host smart-49da9f0d-6d50-40c2-877c-3387b468aea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810210768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3810210768
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1161173827
Short name T520
Test name
Test status
Simulation time 667969924 ps
CPU time 1.49 seconds
Started Jul 14 04:24:07 PM PDT 24
Finished Jul 14 04:24:10 PM PDT 24
Peak memory 198836 kb
Host smart-47eccd4e-8c6d-495f-9b87-81654ffba67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161173827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1161173827
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.894261892
Short name T587
Test name
Test status
Simulation time 22692669078 ps
CPU time 14.97 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:24:19 PM PDT 24
Peak memory 199764 kb
Host smart-f7d36b9a-7e9b-47b3-9091-bca10939b61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894261892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.894261892
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4047987541
Short name T204
Test name
Test status
Simulation time 32928140379 ps
CPU time 26.62 seconds
Started Jul 14 04:26:37 PM PDT 24
Finished Jul 14 04:27:05 PM PDT 24
Peak memory 199732 kb
Host smart-47f81467-0062-4b5d-ac42-b2ce14686a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047987541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4047987541
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1448241143
Short name T293
Test name
Test status
Simulation time 111637520868 ps
CPU time 160.76 seconds
Started Jul 14 04:26:34 PM PDT 24
Finished Jul 14 04:29:15 PM PDT 24
Peak memory 199724 kb
Host smart-a8058db4-3fbe-4de9-b6e5-1c3bb8a49a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448241143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1448241143
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1105339982
Short name T700
Test name
Test status
Simulation time 303941450792 ps
CPU time 58.39 seconds
Started Jul 14 04:26:37 PM PDT 24
Finished Jul 14 04:27:37 PM PDT 24
Peak memory 199788 kb
Host smart-b19be11e-3ef3-4f29-8b9f-33d2daad60b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105339982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1105339982
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3701880933
Short name T169
Test name
Test status
Simulation time 60603645256 ps
CPU time 79.12 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:27:57 PM PDT 24
Peak memory 199812 kb
Host smart-b193a078-fa60-42b6-903f-92fa532b03e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701880933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3701880933
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.67426758
Short name T251
Test name
Test status
Simulation time 94754944814 ps
CPU time 74.65 seconds
Started Jul 14 04:26:34 PM PDT 24
Finished Jul 14 04:27:49 PM PDT 24
Peak memory 199812 kb
Host smart-78b1e72c-b15b-41f4-a96b-92650480fc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67426758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.67426758
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1614183387
Short name T1053
Test name
Test status
Simulation time 21822386159 ps
CPU time 40.52 seconds
Started Jul 14 04:26:35 PM PDT 24
Finished Jul 14 04:27:16 PM PDT 24
Peak memory 199800 kb
Host smart-6906ed19-2b07-4224-959b-15493bd4f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614183387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1614183387
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2601953891
Short name T606
Test name
Test status
Simulation time 17639373824 ps
CPU time 31 seconds
Started Jul 14 04:26:37 PM PDT 24
Finished Jul 14 04:27:10 PM PDT 24
Peak memory 199760 kb
Host smart-5ba4eef8-0853-4965-9ca7-c54c6a462a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601953891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2601953891
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1182963110
Short name T552
Test name
Test status
Simulation time 102718994066 ps
CPU time 42.44 seconds
Started Jul 14 04:26:35 PM PDT 24
Finished Jul 14 04:27:19 PM PDT 24
Peak memory 199756 kb
Host smart-d46728b4-d1f0-4b33-a008-b6340ee80312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182963110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1182963110
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1334726234
Short name T753
Test name
Test status
Simulation time 106859223095 ps
CPU time 28.58 seconds
Started Jul 14 04:26:39 PM PDT 24
Finished Jul 14 04:27:09 PM PDT 24
Peak memory 199676 kb
Host smart-675922e5-0fe7-44e0-8a77-0343d0914904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334726234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1334726234
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.922795866
Short name T845
Test name
Test status
Simulation time 13162335 ps
CPU time 0.53 seconds
Started Jul 14 04:24:13 PM PDT 24
Finished Jul 14 04:24:15 PM PDT 24
Peak memory 194044 kb
Host smart-dcc58706-604c-458b-946c-cf549a77d51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922795866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.922795866
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1221359017
Short name T939
Test name
Test status
Simulation time 91739688245 ps
CPU time 95.2 seconds
Started Jul 14 04:23:59 PM PDT 24
Finished Jul 14 04:25:35 PM PDT 24
Peak memory 199800 kb
Host smart-77e74975-6fbf-44d0-9b00-ad4171f165cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221359017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1221359017
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.412052997
Short name T123
Test name
Test status
Simulation time 107816584974 ps
CPU time 38.66 seconds
Started Jul 14 04:23:56 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 199788 kb
Host smart-e9846bf9-192b-41ca-b908-4808101f99af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412052997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.412052997
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1359647417
Short name T933
Test name
Test status
Simulation time 52258917457 ps
CPU time 26.9 seconds
Started Jul 14 04:24:05 PM PDT 24
Finished Jul 14 04:24:34 PM PDT 24
Peak memory 199740 kb
Host smart-20fe7acc-f000-424a-8085-e6db3588dd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359647417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1359647417
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3164670575
Short name T329
Test name
Test status
Simulation time 234910314579 ps
CPU time 381.44 seconds
Started Jul 14 04:23:52 PM PDT 24
Finished Jul 14 04:30:14 PM PDT 24
Peak memory 196668 kb
Host smart-1e6c1284-a424-4168-a0f6-6fb754cc79bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164670575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3164670575
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.906220263
Short name T325
Test name
Test status
Simulation time 128133586144 ps
CPU time 478.95 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:32:11 PM PDT 24
Peak memory 199644 kb
Host smart-7b42d3d8-e815-4cda-ab62-e3c0a7c073da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906220263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.906220263
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3099317632
Short name T1095
Test name
Test status
Simulation time 4885817235 ps
CPU time 4.45 seconds
Started Jul 14 04:24:07 PM PDT 24
Finished Jul 14 04:24:12 PM PDT 24
Peak memory 199460 kb
Host smart-6eccf13b-95e4-4d9b-a77a-515930a9dd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099317632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3099317632
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1296479264
Short name T685
Test name
Test status
Simulation time 56932595106 ps
CPU time 26.79 seconds
Started Jul 14 04:23:59 PM PDT 24
Finished Jul 14 04:24:26 PM PDT 24
Peak memory 199748 kb
Host smart-b8e7e4af-197e-4691-b24b-a1cadf2cb702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296479264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1296479264
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.69722239
Short name T1064
Test name
Test status
Simulation time 19360126636 ps
CPU time 235.32 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:27:59 PM PDT 24
Peak memory 199548 kb
Host smart-be250b22-114a-47f5-b7d6-662bd09ff538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69722239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.69722239
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.641722505
Short name T361
Test name
Test status
Simulation time 5608042355 ps
CPU time 9.48 seconds
Started Jul 14 04:24:07 PM PDT 24
Finished Jul 14 04:24:18 PM PDT 24
Peak memory 197916 kb
Host smart-677acafc-7bd6-4eea-a95b-5d54ecc59c11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641722505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.641722505
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3176475552
Short name T63
Test name
Test status
Simulation time 15157456545 ps
CPU time 14.67 seconds
Started Jul 14 04:24:05 PM PDT 24
Finished Jul 14 04:24:21 PM PDT 24
Peak memory 199536 kb
Host smart-faa42651-4657-4037-9a5c-fc3212a3809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176475552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3176475552
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1172593588
Short name T1129
Test name
Test status
Simulation time 6328777850 ps
CPU time 8.91 seconds
Started Jul 14 04:23:51 PM PDT 24
Finished Jul 14 04:24:00 PM PDT 24
Peak memory 195952 kb
Host smart-71711289-81dc-4bbf-9677-cf2ad0f7a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172593588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1172593588
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2735742548
Short name T428
Test name
Test status
Simulation time 650648436 ps
CPU time 3.45 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:24:11 PM PDT 24
Peak memory 199020 kb
Host smart-b0f506be-2942-4ce9-9fad-dcfb00b3bbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735742548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2735742548
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2296151482
Short name T696
Test name
Test status
Simulation time 177638303832 ps
CPU time 531.72 seconds
Started Jul 14 04:24:05 PM PDT 24
Finished Jul 14 04:32:57 PM PDT 24
Peak memory 199716 kb
Host smart-2e4848c2-f0c1-4209-ad88-1443d91eb3fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296151482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2296151482
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1819984155
Short name T720
Test name
Test status
Simulation time 164420356937 ps
CPU time 480.37 seconds
Started Jul 14 04:24:04 PM PDT 24
Finished Jul 14 04:32:05 PM PDT 24
Peak memory 216524 kb
Host smart-2cb65bff-1246-4372-ae9d-1b6402df4119
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819984155 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1819984155
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3134195424
Short name T1073
Test name
Test status
Simulation time 871681561 ps
CPU time 1.33 seconds
Started Jul 14 04:24:12 PM PDT 24
Finished Jul 14 04:24:15 PM PDT 24
Peak memory 197980 kb
Host smart-d372a497-d788-47b7-91a7-dcfa155cdb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134195424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3134195424
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3336342154
Short name T954
Test name
Test status
Simulation time 60559087988 ps
CPU time 119.64 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:26:12 PM PDT 24
Peak memory 199752 kb
Host smart-19800d55-060e-47c9-9501-06420f5babd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336342154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3336342154
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2689335270
Short name T18
Test name
Test status
Simulation time 64931650768 ps
CPU time 14.14 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:26:52 PM PDT 24
Peak memory 199544 kb
Host smart-116fb577-48db-4fdc-85a8-f0860e582bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689335270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2689335270
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2179093661
Short name T908
Test name
Test status
Simulation time 35055755049 ps
CPU time 50.8 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:27:29 PM PDT 24
Peak memory 199604 kb
Host smart-61e976a0-03f9-41fa-b832-008ff6d01077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179093661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2179093661
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3958315455
Short name T661
Test name
Test status
Simulation time 108032486834 ps
CPU time 18.24 seconds
Started Jul 14 04:26:38 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 199788 kb
Host smart-06d6a9db-d6eb-4633-ad60-883ca490e89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958315455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3958315455
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.951366833
Short name T323
Test name
Test status
Simulation time 206107707357 ps
CPU time 339.91 seconds
Started Jul 14 04:26:39 PM PDT 24
Finished Jul 14 04:32:20 PM PDT 24
Peak memory 199768 kb
Host smart-1f40e0ba-ee62-4943-8485-fe01cabfe54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951366833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.951366833
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3597657479
Short name T42
Test name
Test status
Simulation time 44065687186 ps
CPU time 71.78 seconds
Started Jul 14 04:26:37 PM PDT 24
Finished Jul 14 04:27:51 PM PDT 24
Peak memory 199240 kb
Host smart-65b2d1b2-bc3a-432f-8b40-b822a5d1550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597657479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3597657479
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3494031164
Short name T468
Test name
Test status
Simulation time 52662797746 ps
CPU time 37.67 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:27:16 PM PDT 24
Peak memory 199656 kb
Host smart-86ca7afe-c170-48a3-bdee-49376089aa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494031164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3494031164
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2667863864
Short name T194
Test name
Test status
Simulation time 147078246230 ps
CPU time 14.76 seconds
Started Jul 14 04:26:45 PM PDT 24
Finished Jul 14 04:27:01 PM PDT 24
Peak memory 199608 kb
Host smart-3c5bd184-e138-4549-84b1-a9a27df139e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667863864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2667863864
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3295336892
Short name T218
Test name
Test status
Simulation time 102022337488 ps
CPU time 70.06 seconds
Started Jul 14 04:26:45 PM PDT 24
Finished Jul 14 04:27:56 PM PDT 24
Peak memory 199628 kb
Host smart-670091fb-4250-41b7-92a2-41123bda834d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295336892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3295336892
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3432325583
Short name T711
Test name
Test status
Simulation time 56819871888 ps
CPU time 143.65 seconds
Started Jul 14 04:26:45 PM PDT 24
Finished Jul 14 04:29:09 PM PDT 24
Peak memory 199788 kb
Host smart-bf44b64a-a0cd-4357-808a-5f18a2b476a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432325583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3432325583
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2632962899
Short name T615
Test name
Test status
Simulation time 41427308 ps
CPU time 0.65 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:24:08 PM PDT 24
Peak memory 195060 kb
Host smart-29f93b33-53bd-4dcc-ba8a-c9f2769ce88c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632962899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2632962899
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.580128601
Short name T1034
Test name
Test status
Simulation time 24267332460 ps
CPU time 10.39 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:24:22 PM PDT 24
Peak memory 199672 kb
Host smart-cae09de3-8c43-4eb3-8e75-0edfd72853ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580128601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.580128601
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2498107664
Short name T1113
Test name
Test status
Simulation time 89919723445 ps
CPU time 131.06 seconds
Started Jul 14 04:24:09 PM PDT 24
Finished Jul 14 04:26:20 PM PDT 24
Peak memory 199728 kb
Host smart-4043d8d2-66f7-4836-8477-fb7081097c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498107664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2498107664
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.2191345438
Short name T491
Test name
Test status
Simulation time 227036857105 ps
CPU time 89.42 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:25:42 PM PDT 24
Peak memory 199184 kb
Host smart-e4229179-4d35-4b87-855c-113df285de5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191345438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2191345438
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2306858091
Short name T927
Test name
Test status
Simulation time 212503732980 ps
CPU time 201.65 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:27:29 PM PDT 24
Peak memory 199868 kb
Host smart-19036f59-d507-4e67-81d5-65bc75a9fce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306858091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2306858091
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.847659761
Short name T570
Test name
Test status
Simulation time 2369115368 ps
CPU time 7.88 seconds
Started Jul 14 04:24:14 PM PDT 24
Finished Jul 14 04:24:23 PM PDT 24
Peak memory 198260 kb
Host smart-d03ffe87-6527-4d8a-a9a8-11aebf470a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847659761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.847659761
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2201035216
Short name T493
Test name
Test status
Simulation time 397765847544 ps
CPU time 105.94 seconds
Started Jul 14 04:24:10 PM PDT 24
Finished Jul 14 04:25:56 PM PDT 24
Peak memory 208148 kb
Host smart-db580a2d-224d-46ae-8786-fecdfdb6b683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201035216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2201035216
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3189900506
Short name T793
Test name
Test status
Simulation time 9224952021 ps
CPU time 530.94 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:33:03 PM PDT 24
Peak memory 199740 kb
Host smart-75a3e8c4-1ca7-4a02-833d-d9c1f18b6bd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189900506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3189900506
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3995437176
Short name T563
Test name
Test status
Simulation time 5339982558 ps
CPU time 46.03 seconds
Started Jul 14 04:24:10 PM PDT 24
Finished Jul 14 04:24:57 PM PDT 24
Peak memory 197940 kb
Host smart-3ea2c21b-6d87-4bb3-8941-dfd2a802f60b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995437176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3995437176
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2452402050
Short name T294
Test name
Test status
Simulation time 147575648003 ps
CPU time 207.71 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 199720 kb
Host smart-22f0b742-64b2-4825-9c70-a7bce05b595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452402050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2452402050
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.853425355
Short name T509
Test name
Test status
Simulation time 1851107015 ps
CPU time 1.29 seconds
Started Jul 14 04:24:13 PM PDT 24
Finished Jul 14 04:24:16 PM PDT 24
Peak memory 195188 kb
Host smart-738da993-14ea-4a2e-a140-d5042bad977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853425355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.853425355
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4188679291
Short name T918
Test name
Test status
Simulation time 5906274807 ps
CPU time 16.66 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:24:21 PM PDT 24
Peak memory 199020 kb
Host smart-258aa286-64e3-41d3-b1d9-d0f1b886a1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188679291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4188679291
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.352528590
Short name T660
Test name
Test status
Simulation time 247251658801 ps
CPU time 843.26 seconds
Started Jul 14 04:23:58 PM PDT 24
Finished Jul 14 04:38:02 PM PDT 24
Peak memory 199648 kb
Host smart-0815a24e-966b-4ee6-9883-18004b4215cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352528590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.352528590
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3540673699
Short name T379
Test name
Test status
Simulation time 746809654 ps
CPU time 1.98 seconds
Started Jul 14 04:24:12 PM PDT 24
Finished Jul 14 04:24:15 PM PDT 24
Peak memory 198032 kb
Host smart-d980ede9-3446-4d46-8961-988c9ad6cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540673699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3540673699
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1257172207
Short name T561
Test name
Test status
Simulation time 83023133208 ps
CPU time 28.71 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 199672 kb
Host smart-712031cd-9486-43b4-9baf-41167864d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257172207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1257172207
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.205866970
Short name T956
Test name
Test status
Simulation time 21639286266 ps
CPU time 35.85 seconds
Started Jul 14 04:26:47 PM PDT 24
Finished Jul 14 04:27:24 PM PDT 24
Peak memory 199768 kb
Host smart-bc7ca2f1-25be-4823-b55c-cbe72fa10cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205866970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.205866970
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3818868849
Short name T695
Test name
Test status
Simulation time 37809470981 ps
CPU time 27.15 seconds
Started Jul 14 04:26:46 PM PDT 24
Finished Jul 14 04:27:14 PM PDT 24
Peak memory 199716 kb
Host smart-d819dcfa-2117-403a-a139-8422a7309f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818868849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3818868849
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3204855034
Short name T758
Test name
Test status
Simulation time 50730462320 ps
CPU time 78.61 seconds
Started Jul 14 04:26:47 PM PDT 24
Finished Jul 14 04:28:07 PM PDT 24
Peak memory 199700 kb
Host smart-5fa7bb52-a6fb-484e-b7d9-ab3eec46e8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204855034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3204855034
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.767988236
Short name T779
Test name
Test status
Simulation time 90225854367 ps
CPU time 74.25 seconds
Started Jul 14 04:26:44 PM PDT 24
Finished Jul 14 04:27:58 PM PDT 24
Peak memory 199356 kb
Host smart-f48c8ea3-85d3-4edf-85ad-026f306b2ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767988236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.767988236
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.751925237
Short name T62
Test name
Test status
Simulation time 83079666399 ps
CPU time 144.25 seconds
Started Jul 14 04:26:44 PM PDT 24
Finished Jul 14 04:29:09 PM PDT 24
Peak memory 199704 kb
Host smart-c73dd9ae-8991-4bc9-8813-1eb4fef2d423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751925237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.751925237
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.677728218
Short name T33
Test name
Test status
Simulation time 8301261211 ps
CPU time 11.28 seconds
Started Jul 14 04:26:45 PM PDT 24
Finished Jul 14 04:26:57 PM PDT 24
Peak memory 198924 kb
Host smart-5b646177-a6a2-4aab-9cdd-b47e986ff7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677728218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.677728218
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.135802452
Short name T185
Test name
Test status
Simulation time 57391673129 ps
CPU time 47.7 seconds
Started Jul 14 04:26:44 PM PDT 24
Finished Jul 14 04:27:33 PM PDT 24
Peak memory 199904 kb
Host smart-ae5d752d-31e0-4da1-b4e3-10d6ddb208f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135802452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.135802452
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.59123131
Short name T381
Test name
Test status
Simulation time 144752255918 ps
CPU time 17.82 seconds
Started Jul 14 04:26:46 PM PDT 24
Finished Jul 14 04:27:05 PM PDT 24
Peak memory 199752 kb
Host smart-840567d9-0a02-46d1-928c-fd728f2d9edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59123131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.59123131
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3513247339
Short name T584
Test name
Test status
Simulation time 12758583 ps
CPU time 0.53 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:23 PM PDT 24
Peak memory 195072 kb
Host smart-745a6209-be0b-4461-a824-2227bf1e1c62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513247339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3513247339
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1356688536
Short name T444
Test name
Test status
Simulation time 199553938706 ps
CPU time 28.75 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:51 PM PDT 24
Peak memory 199736 kb
Host smart-b0407b89-e628-4fd8-8911-bd5450dff22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356688536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1356688536
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3798376790
Short name T626
Test name
Test status
Simulation time 52359739200 ps
CPU time 23.16 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 199684 kb
Host smart-7ac6176c-0ec2-4db2-9f56-fa54d8a8f237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798376790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3798376790
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3076827924
Short name T1028
Test name
Test status
Simulation time 67802997677 ps
CPU time 27.96 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:47 PM PDT 24
Peak memory 199816 kb
Host smart-a2bfbe9c-ca00-4cb2-b5b1-f6edf0dfa456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076827924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3076827924
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.785867675
Short name T997
Test name
Test status
Simulation time 9232272302 ps
CPU time 7.95 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:29 PM PDT 24
Peak memory 197320 kb
Host smart-1cad6975-95b0-4b3e-afd1-cf8da20aa363
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785867675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.785867675
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2450500580
Short name T916
Test name
Test status
Simulation time 99458620359 ps
CPU time 1080.73 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:42:23 PM PDT 24
Peak memory 199744 kb
Host smart-34acd0b7-b9c5-4a43-9ab5-0cfaf45f3905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2450500580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2450500580
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2784580325
Short name T577
Test name
Test status
Simulation time 4567867602 ps
CPU time 10.97 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:32 PM PDT 24
Peak memory 198732 kb
Host smart-7de5fe6c-9538-45cf-85f3-15c45052b890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784580325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2784580325
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1208471837
Short name T815
Test name
Test status
Simulation time 7004118471 ps
CPU time 11.4 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:24:35 PM PDT 24
Peak memory 195532 kb
Host smart-5d1a5cfa-c530-4cb9-8995-cec2d85e0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208471837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1208471837
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.675248299
Short name T958
Test name
Test status
Simulation time 29958363572 ps
CPU time 1610.87 seconds
Started Jul 14 04:24:12 PM PDT 24
Finished Jul 14 04:51:05 PM PDT 24
Peak memory 199684 kb
Host smart-21267995-1ed3-45a5-9c2e-76e206a9d61a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675248299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.675248299
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3228456930
Short name T592
Test name
Test status
Simulation time 4409098478 ps
CPU time 15.65 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:24:40 PM PDT 24
Peak memory 197912 kb
Host smart-dc2af0b7-8b82-4b84-b398-ef85c6adc952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228456930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3228456930
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.752245277
Short name T809
Test name
Test status
Simulation time 26757988085 ps
CPU time 37.04 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:55 PM PDT 24
Peak memory 199820 kb
Host smart-3568d3d9-f691-4d87-b85e-7acca6041010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752245277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.752245277
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2265388752
Short name T406
Test name
Test status
Simulation time 5653109116 ps
CPU time 2.78 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:19 PM PDT 24
Peak memory 195800 kb
Host smart-ce2caaf6-ab12-46b8-807f-38b224bcd4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265388752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2265388752
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1427380383
Short name T672
Test name
Test status
Simulation time 308715032 ps
CPU time 0.93 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:24:13 PM PDT 24
Peak memory 199340 kb
Host smart-fbe8bb17-27fe-45c0-9572-4c3373370f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427380383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1427380383
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3662995087
Short name T1078
Test name
Test status
Simulation time 7213057996 ps
CPU time 8.5 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:24:32 PM PDT 24
Peak memory 199340 kb
Host smart-3100c3a7-617c-4f0c-a646-22a4f541bb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662995087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3662995087
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2287640883
Short name T415
Test name
Test status
Simulation time 36888149930 ps
CPU time 32.85 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 199752 kb
Host smart-3f62fc83-6ea7-4660-ad04-b882467dd0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287640883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2287640883
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.103062408
Short name T203
Test name
Test status
Simulation time 99303927554 ps
CPU time 24.78 seconds
Started Jul 14 04:26:47 PM PDT 24
Finished Jul 14 04:27:12 PM PDT 24
Peak memory 199652 kb
Host smart-4de7bb8a-512b-41d7-b451-82bcb69b650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103062408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.103062408
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.279888769
Short name T890
Test name
Test status
Simulation time 20895696223 ps
CPU time 32.45 seconds
Started Jul 14 04:26:46 PM PDT 24
Finished Jul 14 04:27:19 PM PDT 24
Peak memory 199604 kb
Host smart-2923171f-a9e7-4a39-9aab-2e0c17600cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279888769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.279888769
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.848669649
Short name T163
Test name
Test status
Simulation time 57828952242 ps
CPU time 28.56 seconds
Started Jul 14 04:26:45 PM PDT 24
Finished Jul 14 04:27:14 PM PDT 24
Peak memory 199704 kb
Host smart-9f459fff-3252-4b29-ae19-f65d94f910b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848669649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.848669649
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.174312145
Short name T180
Test name
Test status
Simulation time 8948032051 ps
CPU time 5.8 seconds
Started Jul 14 04:26:48 PM PDT 24
Finished Jul 14 04:26:54 PM PDT 24
Peak memory 199680 kb
Host smart-5d1411b0-11d4-4e3c-98aa-52c1474c6c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174312145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.174312145
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.829460200
Short name T880
Test name
Test status
Simulation time 76679213772 ps
CPU time 33.01 seconds
Started Jul 14 04:26:42 PM PDT 24
Finished Jul 14 04:27:16 PM PDT 24
Peak memory 199716 kb
Host smart-2b8d7502-be6b-4046-8c9f-06bf46e5fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829460200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.829460200
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1719641081
Short name T212
Test name
Test status
Simulation time 75229934321 ps
CPU time 22.26 seconds
Started Jul 14 04:26:48 PM PDT 24
Finished Jul 14 04:27:10 PM PDT 24
Peak memory 199668 kb
Host smart-14cacc13-3775-48c2-955c-33c12612f158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719641081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1719641081
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.400114437
Short name T535
Test name
Test status
Simulation time 112022415907 ps
CPU time 170.79 seconds
Started Jul 14 04:26:47 PM PDT 24
Finished Jul 14 04:29:38 PM PDT 24
Peak memory 199652 kb
Host smart-aa17427d-12b2-4fdc-b5de-0739a627bc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400114437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.400114437
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2026017195
Short name T1175
Test name
Test status
Simulation time 8323763199 ps
CPU time 13.81 seconds
Started Jul 14 04:26:44 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 199924 kb
Host smart-d94704a6-f07d-4d87-8bfa-934a78b94ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026017195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2026017195
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3680068544
Short name T100
Test name
Test status
Simulation time 35240914 ps
CPU time 0.53 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:18 PM PDT 24
Peak memory 195068 kb
Host smart-422ee682-7eb1-449a-8d9c-bc9197d4e50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680068544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3680068544
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1350971142
Short name T930
Test name
Test status
Simulation time 17673952421 ps
CPU time 27.76 seconds
Started Jul 14 04:24:11 PM PDT 24
Finished Jul 14 04:24:40 PM PDT 24
Peak memory 199808 kb
Host smart-8b881cdb-b30b-4225-b056-d1258e777037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350971142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1350971142
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.439322142
Short name T1131
Test name
Test status
Simulation time 83859576052 ps
CPU time 67.64 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:25:25 PM PDT 24
Peak memory 199684 kb
Host smart-9869755d-c052-472b-90f6-32fe3c870ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439322142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.439322142
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2754982042
Short name T257
Test name
Test status
Simulation time 64319138082 ps
CPU time 23.08 seconds
Started Jul 14 04:24:13 PM PDT 24
Finished Jul 14 04:24:38 PM PDT 24
Peak memory 199448 kb
Host smart-c48fbbf8-bdad-4e0b-87d0-dc87252e8032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754982042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2754982042
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.908973911
Short name T825
Test name
Test status
Simulation time 16208462086 ps
CPU time 23.89 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:24:31 PM PDT 24
Peak memory 199768 kb
Host smart-b3221824-e8d6-4472-b6fe-5a4ead3c21a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908973911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.908973911
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.443223443
Short name T586
Test name
Test status
Simulation time 147365660188 ps
CPU time 903.29 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:39:20 PM PDT 24
Peak memory 199864 kb
Host smart-13b54309-cf38-4f47-bbfc-bd42c37c5500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443223443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.443223443
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.271287564
Short name T106
Test name
Test status
Simulation time 4453790396 ps
CPU time 13.53 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:32 PM PDT 24
Peak memory 199616 kb
Host smart-09662449-73ea-4731-aac2-cddb4f59dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271287564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.271287564
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2483642938
Short name T1031
Test name
Test status
Simulation time 113295131017 ps
CPU time 155.44 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:26:43 PM PDT 24
Peak memory 199920 kb
Host smart-314f596a-6a3d-497e-ae8a-d598ec519889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483642938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2483642938
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2798715985
Short name T7
Test name
Test status
Simulation time 16401017992 ps
CPU time 190.64 seconds
Started Jul 14 04:24:08 PM PDT 24
Finished Jul 14 04:27:19 PM PDT 24
Peak memory 199696 kb
Host smart-80fbb90c-011a-4a55-889c-c3293d81376f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798715985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2798715985
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2505724136
Short name T1140
Test name
Test status
Simulation time 3665973740 ps
CPU time 4.81 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:27 PM PDT 24
Peak memory 198368 kb
Host smart-23da384e-397a-4f45-bc46-e1f7baefcc0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505724136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2505724136
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.901002744
Short name T133
Test name
Test status
Simulation time 12318696221 ps
CPU time 20.12 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:39 PM PDT 24
Peak memory 199880 kb
Host smart-14c87ec8-a978-4bb5-ae00-f06301081fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901002744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.901002744
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1435710127
Short name T1171
Test name
Test status
Simulation time 32297806918 ps
CPU time 11.9 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 195728 kb
Host smart-f719fce4-3dc7-4ae4-b554-2d3b252881ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435710127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1435710127
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1039699084
Short name T578
Test name
Test status
Simulation time 489429915 ps
CPU time 1.25 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:24:25 PM PDT 24
Peak memory 198424 kb
Host smart-d471388f-7031-497b-9e3c-b30b480a3cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039699084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1039699084
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2921033361
Short name T783
Test name
Test status
Simulation time 11680461458 ps
CPU time 64.62 seconds
Started Jul 14 04:24:12 PM PDT 24
Finished Jul 14 04:25:17 PM PDT 24
Peak memory 199636 kb
Host smart-b76caca1-16e5-4a11-a3f6-5646202572c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921033361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2921033361
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1334863599
Short name T884
Test name
Test status
Simulation time 417466582473 ps
CPU time 1115.57 seconds
Started Jul 14 04:24:13 PM PDT 24
Finished Jul 14 04:42:50 PM PDT 24
Peak memory 227020 kb
Host smart-82f5ea00-e79f-4c43-a3dc-13453a89b004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334863599 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1334863599
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1953842581
Short name T856
Test name
Test status
Simulation time 1430452822 ps
CPU time 3.03 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:21 PM PDT 24
Peak memory 199092 kb
Host smart-635dc545-2eb7-43e7-9cc3-9d91ea1e5850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953842581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1953842581
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.783747287
Short name T74
Test name
Test status
Simulation time 54667730904 ps
CPU time 60.64 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:25:23 PM PDT 24
Peak memory 199732 kb
Host smart-d38d7ebc-c750-46db-a3ec-880c1603984f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783747287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.783747287
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3559827862
Short name T191
Test name
Test status
Simulation time 147260201726 ps
CPU time 97.74 seconds
Started Jul 14 04:26:50 PM PDT 24
Finished Jul 14 04:28:28 PM PDT 24
Peak memory 199716 kb
Host smart-f428d254-cc34-42da-aabb-9737e0319d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559827862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3559827862
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3342477029
Short name T441
Test name
Test status
Simulation time 147131769373 ps
CPU time 28.95 seconds
Started Jul 14 04:26:45 PM PDT 24
Finished Jul 14 04:27:15 PM PDT 24
Peak memory 199640 kb
Host smart-990a1635-4371-43a5-b984-1326e280a816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342477029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3342477029
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3609545378
Short name T459
Test name
Test status
Simulation time 90946435329 ps
CPU time 81.26 seconds
Started Jul 14 04:26:43 PM PDT 24
Finished Jul 14 04:28:05 PM PDT 24
Peak memory 199708 kb
Host smart-df02518f-b669-46bc-86f5-922953475cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609545378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3609545378
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2807363788
Short name T714
Test name
Test status
Simulation time 30205885423 ps
CPU time 22.97 seconds
Started Jul 14 04:26:47 PM PDT 24
Finished Jul 14 04:27:11 PM PDT 24
Peak memory 199756 kb
Host smart-0c56f08c-b6d0-44c1-996b-3010ba2ed2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807363788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2807363788
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2999544682
Short name T359
Test name
Test status
Simulation time 18488086168 ps
CPU time 25.1 seconds
Started Jul 14 04:27:51 PM PDT 24
Finished Jul 14 04:28:17 PM PDT 24
Peak memory 198804 kb
Host smart-c8fb848e-8825-44ea-a9f9-f2d33da269fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999544682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2999544682
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1052550140
Short name T967
Test name
Test status
Simulation time 70723287493 ps
CPU time 31.53 seconds
Started Jul 14 04:26:47 PM PDT 24
Finished Jul 14 04:27:19 PM PDT 24
Peak memory 199628 kb
Host smart-9964b1a1-d8b2-4117-b65d-cf242d904c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052550140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1052550140
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1606157324
Short name T742
Test name
Test status
Simulation time 14783666684 ps
CPU time 29.32 seconds
Started Jul 14 04:26:55 PM PDT 24
Finished Jul 14 04:27:25 PM PDT 24
Peak memory 198956 kb
Host smart-84566a21-b803-4d52-8c3c-87a8b2858362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606157324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1606157324
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1483986066
Short name T571
Test name
Test status
Simulation time 38330149808 ps
CPU time 56.68 seconds
Started Jul 14 04:26:54 PM PDT 24
Finished Jul 14 04:27:52 PM PDT 24
Peak memory 199612 kb
Host smart-6eeafeba-f656-4dce-9490-bf7c71c37d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483986066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1483986066
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1047302085
Short name T708
Test name
Test status
Simulation time 11153878 ps
CPU time 0.56 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:22 PM PDT 24
Peak memory 195052 kb
Host smart-2eb359e5-09a8-46de-97d1-ae419dc262e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047302085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1047302085
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1688855569
Short name T943
Test name
Test status
Simulation time 211389330397 ps
CPU time 24.55 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:42 PM PDT 24
Peak memory 199692 kb
Host smart-f975fde1-4d61-4b7d-a68f-f84f464a6fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688855569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1688855569
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3254469424
Short name T470
Test name
Test status
Simulation time 60292359903 ps
CPU time 14.46 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:24:38 PM PDT 24
Peak memory 197084 kb
Host smart-bae78860-9e65-40e8-b9f4-cd895e1d9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254469424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3254469424
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.842186951
Short name T1111
Test name
Test status
Simulation time 14891806498 ps
CPU time 16.06 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 199760 kb
Host smart-fe59e8a8-c988-4ca8-b22b-3ba96ac9a4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842186951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.842186951
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1054422728
Short name T328
Test name
Test status
Simulation time 24247425705 ps
CPU time 31.18 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:48 PM PDT 24
Peak memory 197496 kb
Host smart-8e29c49e-e0f3-40ca-addd-d6091d88a950
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054422728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1054422728
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2815612577
Short name T775
Test name
Test status
Simulation time 88996283763 ps
CPU time 205.15 seconds
Started Jul 14 04:24:06 PM PDT 24
Finished Jul 14 04:27:33 PM PDT 24
Peak memory 199664 kb
Host smart-a75aa7e7-e000-48f0-b395-d5facd0f6d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815612577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2815612577
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.502065370
Short name T365
Test name
Test status
Simulation time 7956168939 ps
CPU time 4.66 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:25 PM PDT 24
Peak memory 199420 kb
Host smart-d742aa3a-3cf8-40b6-a8a3-2767bc3e740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502065370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.502065370
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1521025209
Short name T999
Test name
Test status
Simulation time 182717507908 ps
CPU time 182.21 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:27:25 PM PDT 24
Peak memory 199932 kb
Host smart-8fe76b32-9bdc-445b-a534-de77e1f24f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521025209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1521025209
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2813251022
Short name T972
Test name
Test status
Simulation time 22964300575 ps
CPU time 149.8 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:26:52 PM PDT 24
Peak memory 199712 kb
Host smart-1150c6c4-a23f-4fda-8fd8-3d95ba37f7d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813251022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2813251022
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.996764757
Short name T902
Test name
Test status
Simulation time 2223780786 ps
CPU time 11.32 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:24:35 PM PDT 24
Peak memory 198520 kb
Host smart-92104c03-bdcb-4a34-b185-4eb09dea1916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996764757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.996764757
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1616241823
Short name T594
Test name
Test status
Simulation time 140228866052 ps
CPU time 79.3 seconds
Started Jul 14 04:24:10 PM PDT 24
Finished Jul 14 04:25:31 PM PDT 24
Peak memory 199684 kb
Host smart-7c03c6e6-6752-4ded-b54a-76c92be0987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616241823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1616241823
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2503109059
Short name T881
Test name
Test status
Simulation time 3488351657 ps
CPU time 6.33 seconds
Started Jul 14 04:24:08 PM PDT 24
Finished Jul 14 04:24:15 PM PDT 24
Peak memory 195984 kb
Host smart-b4e5bbc4-a737-4e87-b55f-470155805471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503109059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2503109059
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1942400816
Short name T322
Test name
Test status
Simulation time 6256946294 ps
CPU time 8.52 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:24:32 PM PDT 24
Peak memory 198456 kb
Host smart-106ffc51-55db-4bb2-8074-cbe00ddaf3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942400816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1942400816
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1653732328
Short name T313
Test name
Test status
Simulation time 1884059783 ps
CPU time 4.2 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:24:21 PM PDT 24
Peak memory 198112 kb
Host smart-6be9f9f5-fd91-4c2f-b6b7-da788377d847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653732328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1653732328
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3147502379
Short name T575
Test name
Test status
Simulation time 107527703774 ps
CPU time 26.69 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:24:51 PM PDT 24
Peak memory 199620 kb
Host smart-8a2a62ed-d07c-43d8-b19f-e22298f58efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147502379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3147502379
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1956307512
Short name T142
Test name
Test status
Simulation time 26185069970 ps
CPU time 39.34 seconds
Started Jul 14 04:26:53 PM PDT 24
Finished Jul 14 04:27:33 PM PDT 24
Peak memory 199648 kb
Host smart-c1f5a15e-122d-44bd-be9e-5b447c434d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956307512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1956307512
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2134039907
Short name T895
Test name
Test status
Simulation time 56025291359 ps
CPU time 139.21 seconds
Started Jul 14 04:26:53 PM PDT 24
Finished Jul 14 04:29:13 PM PDT 24
Peak memory 199700 kb
Host smart-feac3059-25d2-4ef6-b198-8bc52fba21d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134039907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2134039907
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2884134481
Short name T746
Test name
Test status
Simulation time 210288526664 ps
CPU time 43.42 seconds
Started Jul 14 04:26:54 PM PDT 24
Finished Jul 14 04:27:38 PM PDT 24
Peak memory 199556 kb
Host smart-3ae80b35-f0e3-4cfc-804d-fa7185893e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884134481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2884134481
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.338020369
Short name T480
Test name
Test status
Simulation time 16700190841 ps
CPU time 24.37 seconds
Started Jul 14 04:26:55 PM PDT 24
Finished Jul 14 04:27:20 PM PDT 24
Peak memory 199048 kb
Host smart-49d3edc6-abcb-4ebd-b699-72621a990724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338020369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.338020369
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.75456542
Short name T341
Test name
Test status
Simulation time 176902852836 ps
CPU time 22.87 seconds
Started Jul 14 04:26:53 PM PDT 24
Finished Jul 14 04:27:16 PM PDT 24
Peak memory 199676 kb
Host smart-f44c9966-48bd-4ee4-8175-ef54cf2e7d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75456542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.75456542
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1031915446
Short name T73
Test name
Test status
Simulation time 44782358400 ps
CPU time 42.19 seconds
Started Jul 14 04:26:55 PM PDT 24
Finished Jul 14 04:27:38 PM PDT 24
Peak memory 199732 kb
Host smart-83e7c62f-7251-4f96-9fe6-b9684f2e5d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031915446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1031915446
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.898191364
Short name T769
Test name
Test status
Simulation time 33581413831 ps
CPU time 65.07 seconds
Started Jul 14 04:26:51 PM PDT 24
Finished Jul 14 04:27:56 PM PDT 24
Peak memory 199600 kb
Host smart-bedcdbff-e03f-474c-897a-3b5d2d58d126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898191364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.898191364
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4037289272
Short name T201
Test name
Test status
Simulation time 162902730202 ps
CPU time 144.49 seconds
Started Jul 14 04:26:51 PM PDT 24
Finished Jul 14 04:29:16 PM PDT 24
Peak memory 199672 kb
Host smart-f556a52e-8eee-45e4-95a1-878cdb1e95fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037289272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4037289272
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2361075966
Short name T206
Test name
Test status
Simulation time 125460827955 ps
CPU time 203.73 seconds
Started Jul 14 04:27:58 PM PDT 24
Finished Jul 14 04:31:22 PM PDT 24
Peak memory 199444 kb
Host smart-7ef10aab-7345-437c-8dae-f08e5e86944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361075966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2361075966
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3982079133
Short name T704
Test name
Test status
Simulation time 12355984 ps
CPU time 0.52 seconds
Started Jul 14 04:24:22 PM PDT 24
Finished Jul 14 04:24:26 PM PDT 24
Peak memory 194024 kb
Host smart-6284378f-8c98-4f6f-9ec7-debcd5892eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982079133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3982079133
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2827434619
Short name T1087
Test name
Test status
Simulation time 152264606012 ps
CPU time 110.6 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:26:12 PM PDT 24
Peak memory 199664 kb
Host smart-f608dc26-33d8-40b7-88b8-d7f3e6aaacca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827434619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2827434619
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1793656819
Short name T168
Test name
Test status
Simulation time 74605523850 ps
CPU time 28.12 seconds
Started Jul 14 04:24:10 PM PDT 24
Finished Jul 14 04:24:40 PM PDT 24
Peak memory 199064 kb
Host smart-90200c4a-09e4-463d-8e3e-e3435522d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793656819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1793656819
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1989275959
Short name T609
Test name
Test status
Simulation time 53551202053 ps
CPU time 24.43 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 199788 kb
Host smart-6aa102a2-cfbc-4488-b29d-2d429fd3ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989275959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1989275959
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1309444597
Short name T1010
Test name
Test status
Simulation time 70569380505 ps
CPU time 32.87 seconds
Started Jul 14 04:24:14 PM PDT 24
Finished Jul 14 04:24:48 PM PDT 24
Peak memory 199648 kb
Host smart-cc844c85-d439-4bb2-8c81-8dd385d3e5c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309444597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1309444597
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1773330340
Short name T516
Test name
Test status
Simulation time 115865660745 ps
CPU time 231.82 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:28:09 PM PDT 24
Peak memory 199724 kb
Host smart-689498e6-2b08-47fe-b69b-244ebc174760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773330340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1773330340
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.412799752
Short name T831
Test name
Test status
Simulation time 12042265378 ps
CPU time 7.33 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 199684 kb
Host smart-d806cadc-86eb-40c4-b0b3-3bca902d5da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412799752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.412799752
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.121880656
Short name T368
Test name
Test status
Simulation time 2715294454 ps
CPU time 4.59 seconds
Started Jul 14 04:24:14 PM PDT 24
Finished Jul 14 04:24:21 PM PDT 24
Peak memory 194648 kb
Host smart-9c30238b-57f8-4a21-99b6-69e283bb4518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121880656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.121880656
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3721349216
Short name T81
Test name
Test status
Simulation time 27105526844 ps
CPU time 1449.91 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:48:27 PM PDT 24
Peak memory 199772 kb
Host smart-c2fc05f3-04fe-42d4-93e1-3b85d6905a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721349216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3721349216
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2948695571
Short name T438
Test name
Test status
Simulation time 2963483175 ps
CPU time 21.34 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:41 PM PDT 24
Peak memory 198152 kb
Host smart-7d4004de-d2c4-48b0-b7b5-0ff86e6e563c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948695571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2948695571
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3641210151
Short name T278
Test name
Test status
Simulation time 140660318792 ps
CPU time 128.36 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:26:29 PM PDT 24
Peak memory 199728 kb
Host smart-4940ad34-fb54-4679-a237-20a26911edd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641210151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3641210151
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3855057313
Short name T1009
Test name
Test status
Simulation time 3065884909 ps
CPU time 2.73 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:24:27 PM PDT 24
Peak memory 195108 kb
Host smart-429d02ae-2096-4973-a0d3-465201aad019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855057313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3855057313
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.332597067
Short name T358
Test name
Test status
Simulation time 108121515 ps
CPU time 0.9 seconds
Started Jul 14 04:24:10 PM PDT 24
Finished Jul 14 04:24:12 PM PDT 24
Peak memory 198212 kb
Host smart-705e2e33-802f-4561-8ea0-71c136243246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332597067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.332597067
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3762257130
Short name T814
Test name
Test status
Simulation time 102088847440 ps
CPU time 213.64 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:27:56 PM PDT 24
Peak memory 199716 kb
Host smart-c7069c49-f58d-43fa-8785-2fea62c72055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762257130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3762257130
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.379528122
Short name T16
Test name
Test status
Simulation time 41846782251 ps
CPU time 214.17 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:27:57 PM PDT 24
Peak memory 215216 kb
Host smart-3c52e507-1108-4319-8910-fc48578ec103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379528122 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.379528122
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4222388150
Short name T1149
Test name
Test status
Simulation time 8117232744 ps
CPU time 13.14 seconds
Started Jul 14 04:24:20 PM PDT 24
Finished Jul 14 04:24:38 PM PDT 24
Peak memory 199724 kb
Host smart-e1a3ab93-3fd3-4485-a475-a9cf62cd0d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222388150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4222388150
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1468843184
Short name T104
Test name
Test status
Simulation time 6335556474 ps
CPU time 11.03 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:32 PM PDT 24
Peak memory 199732 kb
Host smart-221a2ef8-7047-4a50-91c8-0babb33ec230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468843184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1468843184
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2005395814
Short name T260
Test name
Test status
Simulation time 44273339963 ps
CPU time 123.3 seconds
Started Jul 14 04:26:53 PM PDT 24
Finished Jul 14 04:28:57 PM PDT 24
Peak memory 199732 kb
Host smart-21797f39-f6ad-4413-b336-76dd160fba5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005395814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2005395814
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3699375377
Short name T1086
Test name
Test status
Simulation time 45222216240 ps
CPU time 14.8 seconds
Started Jul 14 04:26:54 PM PDT 24
Finished Jul 14 04:27:10 PM PDT 24
Peak memory 199476 kb
Host smart-b9b0eed5-a996-4d64-bcb4-7ef227167e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699375377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3699375377
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.439257594
Short name T658
Test name
Test status
Simulation time 49923258677 ps
CPU time 141.53 seconds
Started Jul 14 04:26:55 PM PDT 24
Finished Jul 14 04:29:17 PM PDT 24
Peak memory 199692 kb
Host smart-ca8beb2b-0c14-4339-93f2-3ed5bef778e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439257594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.439257594
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3272999970
Short name T492
Test name
Test status
Simulation time 139957952797 ps
CPU time 162.18 seconds
Started Jul 14 04:26:55 PM PDT 24
Finished Jul 14 04:29:38 PM PDT 24
Peak memory 199708 kb
Host smart-e3e0dea4-7e3f-48df-833a-8b4273c1e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272999970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3272999970
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1793364437
Short name T337
Test name
Test status
Simulation time 24285427695 ps
CPU time 10.67 seconds
Started Jul 14 04:26:55 PM PDT 24
Finished Jul 14 04:27:06 PM PDT 24
Peak memory 199160 kb
Host smart-6f7c0ba9-ca8b-47df-8360-ff67dbaa16ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793364437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1793364437
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.905122226
Short name T242
Test name
Test status
Simulation time 65998556075 ps
CPU time 17 seconds
Started Jul 14 04:27:58 PM PDT 24
Finished Jul 14 04:28:16 PM PDT 24
Peak memory 199376 kb
Host smart-1e07ca2b-b4e1-4cdc-bff4-b32f518836c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905122226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.905122226
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3517191568
Short name T495
Test name
Test status
Simulation time 256546495357 ps
CPU time 100.28 seconds
Started Jul 14 04:27:01 PM PDT 24
Finished Jul 14 04:28:42 PM PDT 24
Peak memory 199828 kb
Host smart-a776e5aa-c32b-442d-b906-716e18105fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517191568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3517191568
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2340563893
Short name T715
Test name
Test status
Simulation time 16487574 ps
CPU time 0.55 seconds
Started Jul 14 04:24:25 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 195344 kb
Host smart-2a793873-865e-475e-85de-06bd972319c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340563893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2340563893
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4027682847
Short name T893
Test name
Test status
Simulation time 99103295717 ps
CPU time 50.91 seconds
Started Jul 14 04:24:13 PM PDT 24
Finished Jul 14 04:25:05 PM PDT 24
Peak memory 199776 kb
Host smart-938dc10b-ec1d-41ca-acb1-1af3414072e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027682847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4027682847
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1931353340
Short name T304
Test name
Test status
Simulation time 154279090068 ps
CPU time 211.93 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:27:58 PM PDT 24
Peak memory 199776 kb
Host smart-a9081ab9-b62b-4c74-9a5d-5ea2006939a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931353340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1931353340
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.3934336038
Short name T1105
Test name
Test status
Simulation time 37053738620 ps
CPU time 16.86 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:24:43 PM PDT 24
Peak memory 199700 kb
Host smart-1e542af2-e577-456f-81f5-8bc33d6261ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934336038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3934336038
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.568175510
Short name T8
Test name
Test status
Simulation time 129164653211 ps
CPU time 136.54 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:26:37 PM PDT 24
Peak memory 199780 kb
Host smart-f4907fac-3947-4746-908b-f1ca4442cf31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568175510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.568175510
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.617970659
Short name T771
Test name
Test status
Simulation time 8060223702 ps
CPU time 13.6 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:35 PM PDT 24
Peak memory 198952 kb
Host smart-d6db5e62-9bfb-4b4b-9d81-4531cc6aada3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617970659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.617970659
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1658998161
Short name T393
Test name
Test status
Simulation time 81489267808 ps
CPU time 113.06 seconds
Started Jul 14 04:24:22 PM PDT 24
Finished Jul 14 04:26:19 PM PDT 24
Peak memory 198724 kb
Host smart-ed5e8df0-964b-4c3d-baf0-c69ab64d4a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658998161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1658998161
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3481798312
Short name T1108
Test name
Test status
Simulation time 8159235201 ps
CPU time 448.11 seconds
Started Jul 14 04:24:15 PM PDT 24
Finished Jul 14 04:31:45 PM PDT 24
Peak memory 199772 kb
Host smart-0b2c797a-1117-470e-99b8-66abb782234e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481798312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3481798312
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1016886458
Short name T554
Test name
Test status
Simulation time 1272999825 ps
CPU time 2.47 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:24:29 PM PDT 24
Peak memory 197872 kb
Host smart-3f0e7e36-dce9-4d66-bb33-2f21c2f3fb70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016886458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1016886458
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2564758617
Short name T175
Test name
Test status
Simulation time 30917550627 ps
CPU time 54.09 seconds
Started Jul 14 04:24:14 PM PDT 24
Finished Jul 14 04:25:10 PM PDT 24
Peak memory 199680 kb
Host smart-94d95cca-d9c7-457a-9b37-0077408e94a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564758617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2564758617
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2929052654
Short name T865
Test name
Test status
Simulation time 4334188434 ps
CPU time 1.85 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:24 PM PDT 24
Peak memory 196228 kb
Host smart-7d9eba64-d7d9-4550-9d0c-37ce127efe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929052654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2929052654
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2002236222
Short name T424
Test name
Test status
Simulation time 508924581 ps
CPU time 2.83 seconds
Started Jul 14 04:24:22 PM PDT 24
Finished Jul 14 04:24:29 PM PDT 24
Peak memory 198600 kb
Host smart-33c6b7e8-94ad-4ca1-b51b-1746d80de483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002236222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2002236222
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3581564016
Short name T849
Test name
Test status
Simulation time 365816412112 ps
CPU time 459.6 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:32:06 PM PDT 24
Peak memory 199708 kb
Host smart-375d0f74-9e1a-4741-9570-2a06af011d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581564016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3581564016
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1155540921
Short name T115
Test name
Test status
Simulation time 166733885589 ps
CPU time 530.31 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:33:16 PM PDT 24
Peak memory 224604 kb
Host smart-87bb8ca8-ad5e-4338-b6d7-09440f5839e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155540921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1155540921
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3997882628
Short name T608
Test name
Test status
Simulation time 2156508461 ps
CPU time 2.71 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:24:29 PM PDT 24
Peak memory 197912 kb
Host smart-6928a2d5-adfc-41ed-adef-535869c8fccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997882628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3997882628
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.395840143
Short name T485
Test name
Test status
Simulation time 167388370361 ps
CPU time 68.91 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:25:35 PM PDT 24
Peak memory 199688 kb
Host smart-526cb505-3081-4d18-a3d3-17c081b0c151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395840143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.395840143
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3888765253
Short name T1070
Test name
Test status
Simulation time 9710062484 ps
CPU time 14.22 seconds
Started Jul 14 04:27:00 PM PDT 24
Finished Jul 14 04:27:15 PM PDT 24
Peak memory 199368 kb
Host smart-fa21c08b-dc7c-43a1-b503-a073e9c3f0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888765253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3888765253
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3511129346
Short name T926
Test name
Test status
Simulation time 53812950518 ps
CPU time 19.75 seconds
Started Jul 14 04:26:59 PM PDT 24
Finished Jul 14 04:27:19 PM PDT 24
Peak memory 199696 kb
Host smart-a1bdf8ed-455e-4fc6-81c4-b92a5a218d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511129346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3511129346
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1308552300
Short name T265
Test name
Test status
Simulation time 123133758418 ps
CPU time 172.34 seconds
Started Jul 14 04:27:03 PM PDT 24
Finished Jul 14 04:29:56 PM PDT 24
Peak memory 199804 kb
Host smart-f353545b-539f-492b-9623-1f98d936882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308552300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1308552300
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2868507215
Short name T925
Test name
Test status
Simulation time 12408900556 ps
CPU time 19.47 seconds
Started Jul 14 04:27:04 PM PDT 24
Finished Jul 14 04:27:24 PM PDT 24
Peak memory 199532 kb
Host smart-71fcd292-efc3-484f-8314-20175f7b1bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868507215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2868507215
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2482754178
Short name T297
Test name
Test status
Simulation time 68794155188 ps
CPU time 59.21 seconds
Started Jul 14 04:27:00 PM PDT 24
Finished Jul 14 04:27:59 PM PDT 24
Peak memory 199656 kb
Host smart-9db80fd4-d950-4fe1-bb16-abfcedd7c5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482754178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2482754178
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3349044989
Short name T948
Test name
Test status
Simulation time 63852993120 ps
CPU time 25.99 seconds
Started Jul 14 04:27:04 PM PDT 24
Finished Jul 14 04:27:31 PM PDT 24
Peak memory 199644 kb
Host smart-ca053c0d-0a55-4ec0-8be2-6428041e543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349044989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3349044989
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2117774020
Short name T684
Test name
Test status
Simulation time 14407838105 ps
CPU time 25.38 seconds
Started Jul 14 04:27:03 PM PDT 24
Finished Jul 14 04:27:29 PM PDT 24
Peak memory 199804 kb
Host smart-d1cf84ba-9928-4a4b-a710-ae7937432823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117774020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2117774020
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2091483390
Short name T630
Test name
Test status
Simulation time 14877087 ps
CPU time 0.55 seconds
Started Jul 14 04:23:36 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 195112 kb
Host smart-bbba1a46-de81-40f4-b808-fd1a1813b3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091483390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2091483390
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1836204296
Short name T886
Test name
Test status
Simulation time 47173476169 ps
CPU time 21.62 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:54 PM PDT 24
Peak memory 199680 kb
Host smart-3982851c-5010-4481-8f65-962a8db80b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836204296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1836204296
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1843421497
Short name T629
Test name
Test status
Simulation time 28204720682 ps
CPU time 46.23 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:24:18 PM PDT 24
Peak memory 199596 kb
Host smart-b2e39111-ad3e-41f1-86cf-edb49e28ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843421497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1843421497
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3538220038
Short name T829
Test name
Test status
Simulation time 78267978483 ps
CPU time 74.52 seconds
Started Jul 14 04:23:29 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 199692 kb
Host smart-a0680c7c-b12c-4b30-8894-666b0c6460c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538220038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3538220038
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.419918943
Short name T632
Test name
Test status
Simulation time 7713097461 ps
CPU time 9.72 seconds
Started Jul 14 04:23:22 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 199716 kb
Host smart-f8a2e740-f29c-45bd-8c8e-5529a8b8228c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419918943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.419918943
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3886969930
Short name T377
Test name
Test status
Simulation time 111157240894 ps
CPU time 568.71 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:33:07 PM PDT 24
Peak memory 199716 kb
Host smart-398ba38e-c31a-455b-9f8f-d966e8313c77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886969930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3886969930
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1078914319
Short name T357
Test name
Test status
Simulation time 10922199200 ps
CPU time 7.32 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:23:43 PM PDT 24
Peak memory 199656 kb
Host smart-c741e4b9-12cc-4fd9-af44-f0745e34dcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078914319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1078914319
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2961219246
Short name T702
Test name
Test status
Simulation time 132863094231 ps
CPU time 68.61 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:24:43 PM PDT 24
Peak memory 199972 kb
Host smart-e8246c58-7463-4eb2-9d66-d336a6f98b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961219246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2961219246
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3769551266
Short name T1107
Test name
Test status
Simulation time 6717881458 ps
CPU time 339.29 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:29:12 PM PDT 24
Peak memory 199688 kb
Host smart-e987e0f0-7e6d-4c23-a0c6-3962fe01be08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769551266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3769551266
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.838921389
Short name T847
Test name
Test status
Simulation time 7209140922 ps
CPU time 38.32 seconds
Started Jul 14 04:23:20 PM PDT 24
Finished Jul 14 04:24:00 PM PDT 24
Peak memory 199524 kb
Host smart-19a02411-c4c6-47b5-ab44-b9b10455079f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838921389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.838921389
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2602935904
Short name T454
Test name
Test status
Simulation time 61887211479 ps
CPU time 23.59 seconds
Started Jul 14 04:23:38 PM PDT 24
Finished Jul 14 04:24:03 PM PDT 24
Peak memory 199236 kb
Host smart-01a981ba-97c0-4a1b-a20a-dc02c3a35501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602935904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2602935904
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2488187375
Short name T447
Test name
Test status
Simulation time 5905749948 ps
CPU time 1.35 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:23:36 PM PDT 24
Peak memory 196152 kb
Host smart-a31a0dbd-bb81-49b5-b814-27dd25d82b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488187375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2488187375
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.655339676
Short name T27
Test name
Test status
Simulation time 310744569 ps
CPU time 0.82 seconds
Started Jul 14 04:23:36 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 218108 kb
Host smart-d61ade94-3a77-4ce3-85d4-4524777be921
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655339676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.655339676
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2857705307
Short name T1011
Test name
Test status
Simulation time 667235000 ps
CPU time 1.4 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 198544 kb
Host smart-d6e7497b-b810-49b0-a3ba-1707976275ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857705307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2857705307
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.308835923
Short name T1067
Test name
Test status
Simulation time 299493625219 ps
CPU time 595.87 seconds
Started Jul 14 04:23:40 PM PDT 24
Finished Jul 14 04:33:37 PM PDT 24
Peak memory 199632 kb
Host smart-66f0ac3c-a817-4299-b0ea-200607ac9b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308835923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.308835923
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.764224929
Short name T29
Test name
Test status
Simulation time 13991875060 ps
CPU time 173.1 seconds
Started Jul 14 04:23:39 PM PDT 24
Finished Jul 14 04:26:33 PM PDT 24
Peak memory 209820 kb
Host smart-05e62ca3-41b5-4d43-9bb0-8b1a754695ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764224929 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.764224929
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2063492210
Short name T45
Test name
Test status
Simulation time 1435848983 ps
CPU time 3.11 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:36 PM PDT 24
Peak memory 198908 kb
Host smart-068940db-3306-49a9-9b39-6eaaf94d745e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063492210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2063492210
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2827526256
Short name T850
Test name
Test status
Simulation time 192099295407 ps
CPU time 31.43 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:24:04 PM PDT 24
Peak memory 199680 kb
Host smart-0c0a3004-0a9d-4db2-8e98-3328ddff50ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827526256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2827526256
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1715032410
Short name T774
Test name
Test status
Simulation time 11458232 ps
CPU time 0.55 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:24:24 PM PDT 24
Peak memory 195076 kb
Host smart-30e88dc2-2421-4483-9f98-b1308424a265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715032410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1715032410
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2567931690
Short name T500
Test name
Test status
Simulation time 35703028548 ps
CPU time 27.08 seconds
Started Jul 14 04:24:25 PM PDT 24
Finished Jul 14 04:24:54 PM PDT 24
Peak memory 199652 kb
Host smart-fb75d253-8776-4b70-9bb7-064996552f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567931690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2567931690
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.577172255
Short name T439
Test name
Test status
Simulation time 109862157069 ps
CPU time 38.89 seconds
Started Jul 14 04:24:20 PM PDT 24
Finished Jul 14 04:25:04 PM PDT 24
Peak memory 199608 kb
Host smart-efc08b00-da1d-450a-a7f8-d7e2c38ede41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577172255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.577172255
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.4199530820
Short name T219
Test name
Test status
Simulation time 111236501611 ps
CPU time 194.28 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:27:37 PM PDT 24
Peak memory 199776 kb
Host smart-8ddc071a-36c8-4597-9c72-91e4e6ce1548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199530820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.4199530820
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1424888335
Short name T128
Test name
Test status
Simulation time 66835423810 ps
CPU time 81.94 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:25:41 PM PDT 24
Peak memory 199632 kb
Host smart-d434afcc-1c3c-4fb1-9770-8b0bd2d5e00a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424888335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1424888335
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1056862170
Short name T307
Test name
Test status
Simulation time 159767346490 ps
CPU time 224.99 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:28:09 PM PDT 24
Peak memory 199864 kb
Host smart-a7ea6dbb-71b0-40f1-a26e-ab79d2759630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056862170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1056862170
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.441222295
Short name T1161
Test name
Test status
Simulation time 8927871696 ps
CPU time 20.2 seconds
Started Jul 14 04:24:14 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 199568 kb
Host smart-9464a95e-2181-42da-8afa-03b16a32d43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441222295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.441222295
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2674201630
Short name T1173
Test name
Test status
Simulation time 76249011592 ps
CPU time 62.49 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:25:23 PM PDT 24
Peak memory 208152 kb
Host smart-56268955-eb87-4df0-9fa3-42283143ff71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674201630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2674201630
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3702051549
Short name T403
Test name
Test status
Simulation time 2443294300 ps
CPU time 100.21 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:26:06 PM PDT 24
Peak memory 199780 kb
Host smart-dc8ea29f-ae65-4137-8ca2-0c6c6bc81652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3702051549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3702051549
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2369061664
Short name T668
Test name
Test status
Simulation time 2091686915 ps
CPU time 10.92 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:32 PM PDT 24
Peak memory 198508 kb
Host smart-919a64ac-e92e-4150-abae-562972b2a962
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369061664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2369061664
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2821660616
Short name T1041
Test name
Test status
Simulation time 99648496506 ps
CPU time 78.09 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:25:42 PM PDT 24
Peak memory 199780 kb
Host smart-e6f2e89b-d3f1-4656-ba13-98c2b3adb766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821660616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2821660616
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4225080074
Short name T513
Test name
Test status
Simulation time 36756449025 ps
CPU time 50.13 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:25:14 PM PDT 24
Peak memory 195972 kb
Host smart-fab134fc-1a93-4cef-88b8-9f3dd5e9d853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225080074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4225080074
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2718194258
Short name T959
Test name
Test status
Simulation time 930297615 ps
CPU time 2.92 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:22 PM PDT 24
Peak memory 198560 kb
Host smart-bb950ca7-7614-450d-ac67-e3902fa761ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718194258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2718194258
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2253018527
Short name T1039
Test name
Test status
Simulation time 177225503034 ps
CPU time 80.86 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:25:45 PM PDT 24
Peak memory 199824 kb
Host smart-bf4f9223-aba7-4326-9303-0d71574c6729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253018527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2253018527
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1075418444
Short name T805
Test name
Test status
Simulation time 1128510102 ps
CPU time 2.85 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:24:29 PM PDT 24
Peak memory 199712 kb
Host smart-7674dfbe-c8fd-4b3f-a325-92a7a7a63028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075418444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1075418444
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2871654570
Short name T345
Test name
Test status
Simulation time 35086452730 ps
CPU time 11.48 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:24:35 PM PDT 24
Peak memory 196768 kb
Host smart-6f4badaa-751a-47fa-89f4-0e6924d81068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871654570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2871654570
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4213195531
Short name T187
Test name
Test status
Simulation time 25776577316 ps
CPU time 53.1 seconds
Started Jul 14 04:26:58 PM PDT 24
Finished Jul 14 04:27:52 PM PDT 24
Peak memory 199728 kb
Host smart-397aede6-7c25-4e6b-9abe-9b3fb9dbf513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213195531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4213195531
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2178342239
Short name T78
Test name
Test status
Simulation time 97769848553 ps
CPU time 157.03 seconds
Started Jul 14 04:26:58 PM PDT 24
Finished Jul 14 04:29:36 PM PDT 24
Peak memory 199684 kb
Host smart-5e552b84-7cb8-4da7-ad99-8b242813bffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178342239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2178342239
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1872759825
Short name T1085
Test name
Test status
Simulation time 26331403977 ps
CPU time 62.85 seconds
Started Jul 14 04:27:02 PM PDT 24
Finished Jul 14 04:28:05 PM PDT 24
Peak memory 199752 kb
Host smart-f522018f-cb56-4e73-b439-6649bfcaf335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872759825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1872759825
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3770906736
Short name T598
Test name
Test status
Simulation time 17035476653 ps
CPU time 15.54 seconds
Started Jul 14 04:27:02 PM PDT 24
Finished Jul 14 04:27:18 PM PDT 24
Peak memory 199828 kb
Host smart-02906200-8924-4513-af03-34bf56459539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770906736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3770906736
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1680856177
Short name T241
Test name
Test status
Simulation time 96893406365 ps
CPU time 53.9 seconds
Started Jul 14 04:27:04 PM PDT 24
Finished Jul 14 04:27:58 PM PDT 24
Peak memory 199680 kb
Host smart-92d0e1bd-3295-48d3-932c-14a8da9c7e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680856177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1680856177
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1755075691
Short name T877
Test name
Test status
Simulation time 57972912439 ps
CPU time 72.36 seconds
Started Jul 14 04:27:03 PM PDT 24
Finished Jul 14 04:28:16 PM PDT 24
Peak memory 199620 kb
Host smart-8c52dfdd-8540-45f9-964c-530fb3ff6ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755075691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1755075691
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3806285243
Short name T1023
Test name
Test status
Simulation time 36336579641 ps
CPU time 14.62 seconds
Started Jul 14 04:27:01 PM PDT 24
Finished Jul 14 04:27:16 PM PDT 24
Peak memory 199740 kb
Host smart-dfdcd2c5-4828-452f-917e-eb69e74239d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806285243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3806285243
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.870305567
Short name T224
Test name
Test status
Simulation time 35964808537 ps
CPU time 20.76 seconds
Started Jul 14 04:27:04 PM PDT 24
Finished Jul 14 04:27:26 PM PDT 24
Peak memory 199744 kb
Host smart-007753df-423e-40b3-b5a8-440ab1a29af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870305567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.870305567
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.718191610
Short name T697
Test name
Test status
Simulation time 35466520 ps
CPU time 0.54 seconds
Started Jul 14 04:24:24 PM PDT 24
Finished Jul 14 04:24:27 PM PDT 24
Peak memory 194304 kb
Host smart-d0b841d8-2cce-43bd-832f-f38a4777723a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718191610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.718191610
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2598591030
Short name T1033
Test name
Test status
Simulation time 115346322293 ps
CPU time 189.78 seconds
Started Jul 14 04:24:24 PM PDT 24
Finished Jul 14 04:27:37 PM PDT 24
Peak memory 199540 kb
Host smart-c4e7c7d8-3128-4a74-8c59-66aa40afc654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598591030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2598591030
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.399787973
Short name T504
Test name
Test status
Simulation time 127932727075 ps
CPU time 34.63 seconds
Started Jul 14 04:24:24 PM PDT 24
Finished Jul 14 04:25:01 PM PDT 24
Peak memory 199652 kb
Host smart-010b309f-a0b4-437c-9cb7-6a47d3a25e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399787973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.399787973
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.163627959
Short name T691
Test name
Test status
Simulation time 11247251457 ps
CPU time 18.18 seconds
Started Jul 14 04:24:20 PM PDT 24
Finished Jul 14 04:24:43 PM PDT 24
Peak memory 199856 kb
Host smart-5c6956e9-052f-4971-8f35-1a9cef2a78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163627959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.163627959
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2260390018
Short name T396
Test name
Test status
Simulation time 125525750196 ps
CPU time 65.25 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:25:29 PM PDT 24
Peak memory 199768 kb
Host smart-bc6c1915-8f95-4b18-97f4-23d720c64d5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260390018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2260390018
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2662700362
Short name T279
Test name
Test status
Simulation time 173977035616 ps
CPU time 724.7 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:36:30 PM PDT 24
Peak memory 199864 kb
Host smart-0039a513-9c12-414e-9d42-ea3e6dfad754
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662700362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2662700362
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3164432000
Short name T789
Test name
Test status
Simulation time 6986036349 ps
CPU time 2.68 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:23 PM PDT 24
Peak memory 197888 kb
Host smart-0d5fe2a5-e2cb-4799-84e0-3ed6d8e51543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164432000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3164432000
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.613712351
Short name T332
Test name
Test status
Simulation time 21437128459 ps
CPU time 22.39 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 195756 kb
Host smart-0546ff1f-47a9-4cb4-ae6e-defe6c9cbe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613712351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.613712351
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2464232357
Short name T938
Test name
Test status
Simulation time 13780019618 ps
CPU time 581.07 seconds
Started Jul 14 04:24:14 PM PDT 24
Finished Jul 14 04:33:57 PM PDT 24
Peak memory 199684 kb
Host smart-7d1e1fd0-d0da-42e4-8551-fd9ef5b35f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464232357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2464232357
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1932321053
Short name T422
Test name
Test status
Simulation time 1783383255 ps
CPU time 1.4 seconds
Started Jul 14 04:24:20 PM PDT 24
Finished Jul 14 04:24:26 PM PDT 24
Peak memory 197960 kb
Host smart-bb097878-0a78-49b2-a682-e7807995c330
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932321053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1932321053
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3071370489
Short name T1013
Test name
Test status
Simulation time 173373392950 ps
CPU time 32.86 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:24:57 PM PDT 24
Peak memory 199736 kb
Host smart-aa533d8a-2861-4d51-a2ef-3eaf962fd578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071370489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3071370489
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2103575379
Short name T963
Test name
Test status
Simulation time 3678146455 ps
CPU time 1.79 seconds
Started Jul 14 04:24:16 PM PDT 24
Finished Jul 14 04:24:22 PM PDT 24
Peak memory 196608 kb
Host smart-2b515b50-2880-45a7-a6c4-0b866bcca037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103575379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2103575379
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2408052439
Short name T375
Test name
Test status
Simulation time 532921551 ps
CPU time 1.56 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 198544 kb
Host smart-1fad7c6f-e1b0-43c7-9632-424934a48c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408052439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2408052439
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.135946703
Short name T748
Test name
Test status
Simulation time 70153076643 ps
CPU time 30.85 seconds
Started Jul 14 04:24:25 PM PDT 24
Finished Jul 14 04:24:58 PM PDT 24
Peak memory 199428 kb
Host smart-9a1a0a07-4e87-4de7-9d6a-3ba3f25c717b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135946703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.135946703
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1379238463
Short name T530
Test name
Test status
Simulation time 21943525963 ps
CPU time 253.69 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:28:36 PM PDT 24
Peak memory 216284 kb
Host smart-b4e748c7-9f28-4b53-96cf-80056517a25d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379238463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1379238463
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1068754213
Short name T588
Test name
Test status
Simulation time 1021130234 ps
CPU time 2.62 seconds
Started Jul 14 04:24:13 PM PDT 24
Finished Jul 14 04:24:17 PM PDT 24
Peak memory 198472 kb
Host smart-8fbe2d0e-9a1b-42c2-8053-df2cbae82b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068754213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1068754213
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.407163567
Short name T921
Test name
Test status
Simulation time 49243633121 ps
CPU time 20.08 seconds
Started Jul 14 04:24:17 PM PDT 24
Finished Jul 14 04:24:41 PM PDT 24
Peak memory 199660 kb
Host smart-00ed5743-cca7-4026-87c1-02f2134d713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407163567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.407163567
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3775091783
Short name T209
Test name
Test status
Simulation time 28600522930 ps
CPU time 11.95 seconds
Started Jul 14 04:27:03 PM PDT 24
Finished Jul 14 04:27:16 PM PDT 24
Peak memory 199704 kb
Host smart-06027ba8-3463-4151-bbe7-270ccba7176a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775091783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3775091783
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3769766161
Short name T674
Test name
Test status
Simulation time 202194956746 ps
CPU time 378.4 seconds
Started Jul 14 04:27:00 PM PDT 24
Finished Jul 14 04:33:19 PM PDT 24
Peak memory 199636 kb
Host smart-92ae2541-56c6-4024-953f-31797383c9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769766161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3769766161
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4116665787
Short name T1080
Test name
Test status
Simulation time 189681599621 ps
CPU time 65.47 seconds
Started Jul 14 04:27:03 PM PDT 24
Finished Jul 14 04:28:09 PM PDT 24
Peak memory 199696 kb
Host smart-a020a2e9-dd09-47b1-953e-99b8889ca692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116665787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4116665787
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3664417849
Short name T833
Test name
Test status
Simulation time 271852052131 ps
CPU time 50.15 seconds
Started Jul 14 04:27:01 PM PDT 24
Finished Jul 14 04:27:52 PM PDT 24
Peak memory 199832 kb
Host smart-0f985a4c-31e2-49d4-8c8c-8125cb8cb363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664417849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3664417849
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1933383474
Short name T262
Test name
Test status
Simulation time 161240162732 ps
CPU time 92.62 seconds
Started Jul 14 04:26:59 PM PDT 24
Finished Jul 14 04:28:32 PM PDT 24
Peak memory 199896 kb
Host smart-0577b77d-eeff-4662-afbb-22c6eb35cb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933383474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1933383474
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1106662030
Short name T929
Test name
Test status
Simulation time 122291696813 ps
CPU time 23.83 seconds
Started Jul 14 04:27:11 PM PDT 24
Finished Jul 14 04:27:35 PM PDT 24
Peak memory 199704 kb
Host smart-da272fe9-9af9-45aa-bab7-1f458445d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106662030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1106662030
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1602829564
Short name T184
Test name
Test status
Simulation time 59780041256 ps
CPU time 40.89 seconds
Started Jul 14 04:27:07 PM PDT 24
Finished Jul 14 04:27:49 PM PDT 24
Peak memory 199648 kb
Host smart-367a142e-2926-4f2f-929e-c8ab524e5b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602829564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1602829564
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1850008983
Short name T189
Test name
Test status
Simulation time 14900332235 ps
CPU time 26.16 seconds
Started Jul 14 04:27:11 PM PDT 24
Finished Jul 14 04:27:38 PM PDT 24
Peak memory 199584 kb
Host smart-99fd82da-8f17-4282-99bf-dc585a11f143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850008983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1850008983
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3312183890
Short name T431
Test name
Test status
Simulation time 30942042590 ps
CPU time 45.86 seconds
Started Jul 14 04:27:08 PM PDT 24
Finished Jul 14 04:27:54 PM PDT 24
Peak memory 199668 kb
Host smart-396337ae-c2af-4826-80e2-2d8b2045442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312183890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3312183890
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2154368985
Short name T1049
Test name
Test status
Simulation time 13689594 ps
CPU time 0.6 seconds
Started Jul 14 04:25:34 PM PDT 24
Finished Jul 14 04:25:36 PM PDT 24
Peak memory 192196 kb
Host smart-b6872564-748a-4552-a540-fda0749ab076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154368985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2154368985
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1671297483
Short name T729
Test name
Test status
Simulation time 274782862248 ps
CPU time 57.77 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:25:22 PM PDT 24
Peak memory 199728 kb
Host smart-c4668b9e-e160-4124-b91e-92536cc5e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671297483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1671297483
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2958076417
Short name T121
Test name
Test status
Simulation time 17212846219 ps
CPU time 19.18 seconds
Started Jul 14 04:24:33 PM PDT 24
Finished Jul 14 04:24:55 PM PDT 24
Peak memory 198964 kb
Host smart-b93fe79e-b2f0-4903-9c3d-61dde829f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958076417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2958076417
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2904993326
Short name T111
Test name
Test status
Simulation time 22520096530 ps
CPU time 9.09 seconds
Started Jul 14 04:24:20 PM PDT 24
Finished Jul 14 04:24:34 PM PDT 24
Peak memory 200104 kb
Host smart-30489c95-5e3b-4e36-bf6f-046f7d8fee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904993326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2904993326
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3492104279
Short name T511
Test name
Test status
Simulation time 63343678933 ps
CPU time 46.99 seconds
Started Jul 14 04:24:27 PM PDT 24
Finished Jul 14 04:25:15 PM PDT 24
Peak memory 199860 kb
Host smart-221b97ba-d2f4-4ba2-91d7-9d024d91d134
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492104279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3492104279
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2461716735
Short name T757
Test name
Test status
Simulation time 229114569285 ps
CPU time 383.28 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:30:50 PM PDT 24
Peak memory 199600 kb
Host smart-ce005471-d24f-491e-aec2-6d15fb4696c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461716735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2461716735
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1079377766
Short name T826
Test name
Test status
Simulation time 6627446705 ps
CPU time 12.27 seconds
Started Jul 14 04:24:25 PM PDT 24
Finished Jul 14 04:24:39 PM PDT 24
Peak memory 199896 kb
Host smart-6d1379b6-9cd2-405b-a896-b8c19b298e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079377766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1079377766
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.550627849
Short name T1112
Test name
Test status
Simulation time 71600522369 ps
CPU time 122.67 seconds
Started Jul 14 04:24:19 PM PDT 24
Finished Jul 14 04:26:27 PM PDT 24
Peak memory 208032 kb
Host smart-7e56e6dc-a67f-4d58-b600-1748f71cf2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550627849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.550627849
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3026070343
Short name T876
Test name
Test status
Simulation time 17493772378 ps
CPU time 222.42 seconds
Started Jul 14 04:24:20 PM PDT 24
Finished Jul 14 04:28:07 PM PDT 24
Peak memory 199832 kb
Host smart-4f35ab98-aff5-46bd-9195-581e23c975e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026070343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3026070343
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.939013613
Short name T1164
Test name
Test status
Simulation time 7186403775 ps
CPU time 60.42 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:25:26 PM PDT 24
Peak memory 198668 kb
Host smart-d39a2ba7-bca7-48a9-8659-573ab1b2eaed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939013613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.939013613
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2134927646
Short name T2
Test name
Test status
Simulation time 697809418 ps
CPU time 1.68 seconds
Started Jul 14 04:24:27 PM PDT 24
Finished Jul 14 04:24:30 PM PDT 24
Peak memory 195180 kb
Host smart-3526535b-2f4b-4030-b59f-ba7ab75a1fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134927646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2134927646
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3794789953
Short name T1130
Test name
Test status
Simulation time 509710711 ps
CPU time 1.83 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 198168 kb
Host smart-e3343c97-a233-4fb5-9ab8-9cc7f84769f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794789953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3794789953
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.516037742
Short name T725
Test name
Test status
Simulation time 146248156825 ps
CPU time 225.35 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:28:11 PM PDT 24
Peak memory 199692 kb
Host smart-4dda9989-a8ee-4771-b16e-e3a43ca239c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516037742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.516037742
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3071174898
Short name T221
Test name
Test status
Simulation time 289003491688 ps
CPU time 1092.44 seconds
Started Jul 14 04:24:33 PM PDT 24
Finished Jul 14 04:42:47 PM PDT 24
Peak memory 224740 kb
Host smart-6e1925a1-16e3-449d-ab9a-99f3a9976786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071174898 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3071174898
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.250127582
Short name T298
Test name
Test status
Simulation time 3334832936 ps
CPU time 1.76 seconds
Started Jul 14 04:24:20 PM PDT 24
Finished Jul 14 04:24:27 PM PDT 24
Peak memory 198852 kb
Host smart-6efa7aa0-990f-4d67-8b55-d3d3aa951c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250127582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.250127582
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.105434937
Short name T998
Test name
Test status
Simulation time 39932055181 ps
CPU time 64.08 seconds
Started Jul 14 04:24:18 PM PDT 24
Finished Jul 14 04:25:27 PM PDT 24
Peak memory 199704 kb
Host smart-1bde9808-aec0-4f9a-bc79-ada0302e9a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105434937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.105434937
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3452293881
Short name T1066
Test name
Test status
Simulation time 33716921864 ps
CPU time 49.44 seconds
Started Jul 14 04:27:12 PM PDT 24
Finished Jul 14 04:28:02 PM PDT 24
Peak memory 199644 kb
Host smart-a9ffae64-798f-450b-bf1e-3add56c8e4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452293881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3452293881
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2233939456
Short name T333
Test name
Test status
Simulation time 156267660436 ps
CPU time 20.59 seconds
Started Jul 14 04:27:10 PM PDT 24
Finished Jul 14 04:27:32 PM PDT 24
Peak memory 199724 kb
Host smart-a3ef8ea6-bfb8-42a3-89e1-7589fd95eeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233939456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2233939456
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2027259511
Short name T1047
Test name
Test status
Simulation time 21386430585 ps
CPU time 33.95 seconds
Started Jul 14 04:27:11 PM PDT 24
Finished Jul 14 04:27:46 PM PDT 24
Peak memory 199732 kb
Host smart-7e47e1b3-3113-4ca0-9b85-d4d8a86e0a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027259511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2027259511
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.234700195
Short name T284
Test name
Test status
Simulation time 57273726898 ps
CPU time 35.15 seconds
Started Jul 14 04:27:09 PM PDT 24
Finished Jul 14 04:27:45 PM PDT 24
Peak memory 199720 kb
Host smart-ce6400be-bd08-4f63-9243-d54bcd06002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234700195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.234700195
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1818203976
Short name T1029
Test name
Test status
Simulation time 97968054556 ps
CPU time 108.97 seconds
Started Jul 14 04:27:11 PM PDT 24
Finished Jul 14 04:29:01 PM PDT 24
Peak memory 199732 kb
Host smart-ce7284da-f659-46aa-98bd-eedda09d14f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818203976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1818203976
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3700676083
Short name T755
Test name
Test status
Simulation time 109357329780 ps
CPU time 52.1 seconds
Started Jul 14 04:27:10 PM PDT 24
Finished Jul 14 04:28:04 PM PDT 24
Peak memory 199736 kb
Host smart-33e25d9d-f295-4ffa-bf06-a4110f261142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700676083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3700676083
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.717189276
Short name T135
Test name
Test status
Simulation time 59919397284 ps
CPU time 42.08 seconds
Started Jul 14 04:27:08 PM PDT 24
Finished Jul 14 04:27:51 PM PDT 24
Peak memory 199836 kb
Host smart-07d4253b-5e71-4650-9f0c-a35174899327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717189276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.717189276
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3006976191
Short name T950
Test name
Test status
Simulation time 21156548871 ps
CPU time 13.06 seconds
Started Jul 14 04:27:09 PM PDT 24
Finished Jul 14 04:27:23 PM PDT 24
Peak memory 199560 kb
Host smart-65ad96a8-349f-4fa0-904d-48712e5afe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006976191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3006976191
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3672843349
Short name T245
Test name
Test status
Simulation time 40876469626 ps
CPU time 13.27 seconds
Started Jul 14 04:27:09 PM PDT 24
Finished Jul 14 04:27:23 PM PDT 24
Peak memory 199876 kb
Host smart-32aefaf8-2706-437f-ab38-9974052f213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672843349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3672843349
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.4203822082
Short name T1068
Test name
Test status
Simulation time 31791455 ps
CPU time 0.54 seconds
Started Jul 14 04:24:29 PM PDT 24
Finished Jul 14 04:24:30 PM PDT 24
Peak memory 195376 kb
Host smart-0ef37fb5-978f-4eb5-a5a4-90a3add596ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203822082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.4203822082
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1940507421
Short name T730
Test name
Test status
Simulation time 36814271465 ps
CPU time 52.8 seconds
Started Jul 14 04:24:27 PM PDT 24
Finished Jul 14 04:25:21 PM PDT 24
Peak memory 199680 kb
Host smart-8092e49a-efe0-4440-8dd5-10a01305a4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940507421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1940507421
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3264170302
Short name T1096
Test name
Test status
Simulation time 43124256650 ps
CPU time 25.21 seconds
Started Jul 14 04:25:47 PM PDT 24
Finished Jul 14 04:26:13 PM PDT 24
Peak memory 199364 kb
Host smart-31127569-897b-4d21-8e04-cfbddffc2375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264170302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3264170302
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.673017700
Short name T863
Test name
Test status
Simulation time 8293450329 ps
CPU time 9.78 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:24:35 PM PDT 24
Peak memory 199904 kb
Host smart-ea18c2c4-026b-4bc7-ac25-489ed83aa6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673017700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.673017700
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.928169937
Short name T130
Test name
Test status
Simulation time 47351748934 ps
CPU time 9.35 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 199308 kb
Host smart-5fb9a089-f1b8-445c-908b-4b1767be3423
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928169937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.928169937
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1762317908
Short name T807
Test name
Test status
Simulation time 149606986583 ps
CPU time 925.85 seconds
Started Jul 14 04:24:27 PM PDT 24
Finished Jul 14 04:39:54 PM PDT 24
Peak memory 199748 kb
Host smart-1dca0553-1fe0-4a21-b906-ec727443302e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762317908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1762317908
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.4230673903
Short name T548
Test name
Test status
Simulation time 8035714815 ps
CPU time 3.38 seconds
Started Jul 14 04:24:34 PM PDT 24
Finished Jul 14 04:24:39 PM PDT 24
Peak memory 199672 kb
Host smart-ee4d0b14-e736-4808-908b-d1e6489f64cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230673903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4230673903
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1687168502
Short name T285
Test name
Test status
Simulation time 63780546395 ps
CPU time 102.13 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:26:17 PM PDT 24
Peak memory 208100 kb
Host smart-7c7b13dd-4985-4074-bd89-bf2dfe9a060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687168502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1687168502
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.4265049957
Short name T787
Test name
Test status
Simulation time 20957125608 ps
CPU time 611.43 seconds
Started Jul 14 04:24:21 PM PDT 24
Finished Jul 14 04:34:37 PM PDT 24
Peak memory 199672 kb
Host smart-4a515c88-8cbd-4bd4-b8c4-fa782076d8f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265049957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4265049957
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.22617641
Short name T762
Test name
Test status
Simulation time 4941276742 ps
CPU time 8.36 seconds
Started Jul 14 04:24:22 PM PDT 24
Finished Jul 14 04:24:34 PM PDT 24
Peak memory 198096 kb
Host smart-e8b1357a-bbf3-4be3-8240-c15c61485fe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22617641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.22617641
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1919967135
Short name T178
Test name
Test status
Simulation time 42496223153 ps
CPU time 68.35 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:26:45 PM PDT 24
Peak memory 199428 kb
Host smart-fec9ec9e-b476-4e8f-a3fa-188c1bb1d2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919967135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1919967135
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2869247868
Short name T667
Test name
Test status
Simulation time 527248335 ps
CPU time 0.88 seconds
Started Jul 14 04:25:34 PM PDT 24
Finished Jul 14 04:25:36 PM PDT 24
Peak memory 193092 kb
Host smart-3b1b9fca-bd6b-472b-8b87-73368ca72918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869247868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2869247868
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1354971028
Short name T673
Test name
Test status
Simulation time 124041366 ps
CPU time 0.69 seconds
Started Jul 14 04:24:33 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 196644 kb
Host smart-6ae1d71d-1b37-44aa-b18c-e263b44e4591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354971028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1354971028
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.466243986
Short name T266
Test name
Test status
Simulation time 641872391260 ps
CPU time 725.1 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:37:42 PM PDT 24
Peak memory 199356 kb
Host smart-747ad669-5ce7-43ff-a734-581e9b19f7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466243986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.466243986
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2552445970
Short name T603
Test name
Test status
Simulation time 126777524210 ps
CPU time 2066.29 seconds
Started Jul 14 04:24:23 PM PDT 24
Finished Jul 14 04:58:53 PM PDT 24
Peak memory 225212 kb
Host smart-def635e7-c4a6-4e86-87eb-8e7a3955f7e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552445970 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2552445970
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1670198588
Short name T289
Test name
Test status
Simulation time 509018310 ps
CPU time 1.79 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 199644 kb
Host smart-f7a5fac1-7ea3-467e-b40e-b0d757b635b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670198588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1670198588
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3996658689
Short name T665
Test name
Test status
Simulation time 49350349969 ps
CPU time 17.38 seconds
Started Jul 14 04:24:34 PM PDT 24
Finished Jul 14 04:24:53 PM PDT 24
Peak memory 199788 kb
Host smart-b8715b75-88ec-48f6-a6d1-f6f46b7bd2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996658689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3996658689
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2777432307
Short name T614
Test name
Test status
Simulation time 44357920823 ps
CPU time 16.81 seconds
Started Jul 14 04:27:14 PM PDT 24
Finished Jul 14 04:27:31 PM PDT 24
Peak memory 199684 kb
Host smart-338b8f0a-f8be-470a-8cf0-7b37e288c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777432307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2777432307
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2571943235
Short name T79
Test name
Test status
Simulation time 32956758595 ps
CPU time 15.17 seconds
Started Jul 14 04:27:10 PM PDT 24
Finished Jul 14 04:27:26 PM PDT 24
Peak memory 199660 kb
Host smart-ca5ed6a5-9b75-4593-8f3b-5257fd08a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571943235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2571943235
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.982867961
Short name T174
Test name
Test status
Simulation time 133445794080 ps
CPU time 61.97 seconds
Started Jul 14 04:27:07 PM PDT 24
Finished Jul 14 04:28:10 PM PDT 24
Peak memory 199692 kb
Host smart-ab4eef14-0db8-4dc3-8ee6-cd6d6295bde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982867961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.982867961
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2475510648
Short name T1019
Test name
Test status
Simulation time 106919459784 ps
CPU time 89.43 seconds
Started Jul 14 04:27:11 PM PDT 24
Finished Jul 14 04:28:41 PM PDT 24
Peak memory 199696 kb
Host smart-efbabc4f-7355-4912-a59d-235d8e1de2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475510648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2475510648
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.986223759
Short name T351
Test name
Test status
Simulation time 9579619448 ps
CPU time 12.7 seconds
Started Jul 14 04:27:09 PM PDT 24
Finished Jul 14 04:27:23 PM PDT 24
Peak memory 199548 kb
Host smart-c83e7b3d-9742-40f4-a964-134ae4f7e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986223759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.986223759
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3386746480
Short name T936
Test name
Test status
Simulation time 31265234103 ps
CPU time 27.45 seconds
Started Jul 14 04:27:08 PM PDT 24
Finished Jul 14 04:27:36 PM PDT 24
Peak memory 199772 kb
Host smart-48a6984a-a221-4478-991a-5aaffc70396b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386746480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3386746480
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1762112714
Short name T912
Test name
Test status
Simulation time 87072837297 ps
CPU time 143.78 seconds
Started Jul 14 04:27:11 PM PDT 24
Finished Jul 14 04:29:36 PM PDT 24
Peak memory 199540 kb
Host smart-80ad713b-8e52-4395-9603-15d624f7add9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762112714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1762112714
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3454688671
Short name T754
Test name
Test status
Simulation time 113105658227 ps
CPU time 46.28 seconds
Started Jul 14 04:27:08 PM PDT 24
Finished Jul 14 04:27:55 PM PDT 24
Peak memory 199796 kb
Host smart-1743c958-7092-4523-878c-24f36eabb536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454688671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3454688671
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3333896601
Short name T871
Test name
Test status
Simulation time 65390752677 ps
CPU time 27.07 seconds
Started Jul 14 04:27:09 PM PDT 24
Finished Jul 14 04:27:37 PM PDT 24
Peak memory 199796 kb
Host smart-b8f1c7f7-848c-4936-9788-1838ec6049b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333896601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3333896601
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.920247865
Short name T1128
Test name
Test status
Simulation time 95312206550 ps
CPU time 68.56 seconds
Started Jul 14 04:27:08 PM PDT 24
Finished Jul 14 04:28:17 PM PDT 24
Peak memory 199820 kb
Host smart-92cdcdd8-8c04-4935-bf12-8f42c8d5dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920247865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.920247865
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1028597710
Short name T532
Test name
Test status
Simulation time 11623317 ps
CPU time 0.57 seconds
Started Jul 14 04:24:33 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 194508 kb
Host smart-c052b4b2-9b96-4e25-b45f-2982a5a1d80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028597710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1028597710
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.4209602080
Short name T463
Test name
Test status
Simulation time 82252001283 ps
CPU time 35.5 seconds
Started Jul 14 04:24:29 PM PDT 24
Finished Jul 14 04:25:05 PM PDT 24
Peak memory 199752 kb
Host smart-76aa8e4e-23ed-4097-9f2c-293f8e48b3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209602080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.4209602080
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1999519924
Short name T688
Test name
Test status
Simulation time 121971189130 ps
CPU time 86.86 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:25:59 PM PDT 24
Peak memory 199704 kb
Host smart-0950222c-aae0-4dc1-b12e-3abb51a49017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999519924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1999519924
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.2001542054
Short name T610
Test name
Test status
Simulation time 49544034334 ps
CPU time 19.79 seconds
Started Jul 14 04:24:34 PM PDT 24
Finished Jul 14 04:24:56 PM PDT 24
Peak memory 199736 kb
Host smart-c0763075-f5ab-440c-b6a4-20be1ae22ef8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001542054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2001542054
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4001819430
Short name T810
Test name
Test status
Simulation time 83448103702 ps
CPU time 418.76 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:31:30 PM PDT 24
Peak memory 199748 kb
Host smart-86208db1-f19f-4f9e-a3e0-90c0ba257496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4001819430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4001819430
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1422138725
Short name T653
Test name
Test status
Simulation time 5813353493 ps
CPU time 5.6 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 199348 kb
Host smart-e1a80781-c693-48fe-ae46-ba55b01a9c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422138725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1422138725
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4124220179
Short name T781
Test name
Test status
Simulation time 484568948326 ps
CPU time 75.28 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:25:47 PM PDT 24
Peak memory 208164 kb
Host smart-a95aee6f-10df-4223-8cb2-02786da4667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124220179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4124220179
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.889239426
Short name T1132
Test name
Test status
Simulation time 10373008832 ps
CPU time 180.57 seconds
Started Jul 14 04:24:31 PM PDT 24
Finished Jul 14 04:27:33 PM PDT 24
Peak memory 199716 kb
Host smart-ca90e1f4-bb11-4390-8aee-052789a1111e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889239426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.889239426
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3651258709
Short name T397
Test name
Test status
Simulation time 6852720206 ps
CPU time 66.22 seconds
Started Jul 14 04:24:28 PM PDT 24
Finished Jul 14 04:25:35 PM PDT 24
Peak memory 198988 kb
Host smart-7d57427f-d91a-43bd-b699-f6da3954f944
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651258709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3651258709
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2964575500
Short name T870
Test name
Test status
Simulation time 28814152761 ps
CPU time 46.19 seconds
Started Jul 14 04:24:33 PM PDT 24
Finished Jul 14 04:25:22 PM PDT 24
Peak memory 199760 kb
Host smart-37427283-2424-4444-8d1b-7ac3d656fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964575500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2964575500
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1291326976
Short name T988
Test name
Test status
Simulation time 2990311443 ps
CPU time 4.63 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 195716 kb
Host smart-e21d3c56-621f-4bc2-a294-e3f4281853e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291326976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1291326976
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2095122303
Short name T13
Test name
Test status
Simulation time 42266427586 ps
CPU time 143.2 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 216276 kb
Host smart-071a9734-43e2-4e89-bb0e-76fad207c1f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095122303 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2095122303
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3211146118
Short name T1059
Test name
Test status
Simulation time 1763480442 ps
CPU time 1.6 seconds
Started Jul 14 04:24:28 PM PDT 24
Finished Jul 14 04:24:31 PM PDT 24
Peak memory 198044 kb
Host smart-d9419c6c-4bb2-4e20-b439-740b1d1a3a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211146118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3211146118
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2790276284
Short name T1091
Test name
Test status
Simulation time 269695080757 ps
CPU time 67.1 seconds
Started Jul 14 04:25:34 PM PDT 24
Finished Jul 14 04:26:42 PM PDT 24
Peak memory 196856 kb
Host smart-67e8d060-8c90-49d7-8bd3-31b45fe0e27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790276284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2790276284
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.986408750
Short name T348
Test name
Test status
Simulation time 103312064300 ps
CPU time 22.77 seconds
Started Jul 14 04:27:08 PM PDT 24
Finished Jul 14 04:27:32 PM PDT 24
Peak memory 199556 kb
Host smart-b975b30c-a700-43d5-9f56-d7debb248424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986408750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.986408750
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3075589883
Short name T35
Test name
Test status
Simulation time 107522582153 ps
CPU time 202.54 seconds
Started Jul 14 04:27:09 PM PDT 24
Finished Jul 14 04:30:32 PM PDT 24
Peak memory 199828 kb
Host smart-ae5ebe61-bf8a-44a3-a91a-5d9eadd537ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075589883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3075589883
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2539741117
Short name T236
Test name
Test status
Simulation time 16128186235 ps
CPU time 23.06 seconds
Started Jul 14 04:27:10 PM PDT 24
Finished Jul 14 04:27:34 PM PDT 24
Peak memory 199668 kb
Host smart-8d9f433c-2b39-4769-91fe-184ac7dd7204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539741117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2539741117
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3979662533
Short name T34
Test name
Test status
Simulation time 18638993691 ps
CPU time 26.52 seconds
Started Jul 14 04:27:10 PM PDT 24
Finished Jul 14 04:27:38 PM PDT 24
Peak memory 199700 kb
Host smart-d812f6ca-ad0b-4fd1-b276-d5fe13199d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979662533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3979662533
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3766762480
Short name T703
Test name
Test status
Simulation time 72780412571 ps
CPU time 59.57 seconds
Started Jul 14 04:27:14 PM PDT 24
Finished Jul 14 04:28:14 PM PDT 24
Peak memory 199684 kb
Host smart-8b81258e-9f11-471f-aeaa-1c104766c215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766762480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3766762480
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1911374943
Short name T1088
Test name
Test status
Simulation time 60904598419 ps
CPU time 46.93 seconds
Started Jul 14 04:27:09 PM PDT 24
Finished Jul 14 04:27:57 PM PDT 24
Peak memory 199656 kb
Host smart-8cbd03dd-91e2-461f-a41f-80062f960eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911374943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1911374943
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.78845499
Short name T862
Test name
Test status
Simulation time 194097135496 ps
CPU time 142.79 seconds
Started Jul 14 04:27:21 PM PDT 24
Finished Jul 14 04:29:44 PM PDT 24
Peak memory 199756 kb
Host smart-67d8447d-0eeb-4cf8-8fcc-586cde2bd08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78845499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.78845499
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.315070883
Short name T990
Test name
Test status
Simulation time 60400568874 ps
CPU time 108.36 seconds
Started Jul 14 04:27:20 PM PDT 24
Finished Jul 14 04:29:09 PM PDT 24
Peak memory 199792 kb
Host smart-ae585e43-7580-404c-89b6-70d153e54ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315070883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.315070883
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1623136328
Short name T231
Test name
Test status
Simulation time 25233110382 ps
CPU time 38.15 seconds
Started Jul 14 04:27:18 PM PDT 24
Finished Jul 14 04:27:56 PM PDT 24
Peak memory 199816 kb
Host smart-e4f4cb48-2d33-49ec-b37f-bc35fb044a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623136328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1623136328
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3095487275
Short name T1116
Test name
Test status
Simulation time 115727642842 ps
CPU time 250.81 seconds
Started Jul 14 04:27:18 PM PDT 24
Finished Jul 14 04:31:29 PM PDT 24
Peak memory 199708 kb
Host smart-464e9ef7-a518-4fb4-a9d0-92088cf33a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095487275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3095487275
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4248874821
Short name T910
Test name
Test status
Simulation time 34059559 ps
CPU time 0.54 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:24:31 PM PDT 24
Peak memory 195144 kb
Host smart-52b55d31-9143-4dd5-be22-4287a2556ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248874821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4248874821
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1019884729
Short name T995
Test name
Test status
Simulation time 21068702727 ps
CPU time 31.61 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:25:06 PM PDT 24
Peak memory 199720 kb
Host smart-80370b4b-b57a-4a2d-8001-5533f7fcbf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019884729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1019884729
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2628314918
Short name T901
Test name
Test status
Simulation time 39955548986 ps
CPU time 17.29 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:24:51 PM PDT 24
Peak memory 199760 kb
Host smart-e6abaa89-0740-431c-a993-15f7fbd97a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628314918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2628314918
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3020259676
Short name T797
Test name
Test status
Simulation time 13097396163 ps
CPU time 19.88 seconds
Started Jul 14 04:24:31 PM PDT 24
Finished Jul 14 04:24:52 PM PDT 24
Peak memory 199656 kb
Host smart-3d39bee4-9aa8-4c05-95ba-f727d1ea24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020259676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3020259676
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3474877772
Short name T1000
Test name
Test status
Simulation time 74344547243 ps
CPU time 40.06 seconds
Started Jul 14 04:24:34 PM PDT 24
Finished Jul 14 04:25:16 PM PDT 24
Peak memory 199700 kb
Host smart-e13b617f-deb7-4613-abfa-f2972bb84a4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474877772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3474877772
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.4068706647
Short name T427
Test name
Test status
Simulation time 139203258157 ps
CPU time 1145.25 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:43:36 PM PDT 24
Peak memory 199688 kb
Host smart-d775580b-5d11-4fae-87fc-d31f83385f1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068706647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.4068706647
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1373425685
Short name T356
Test name
Test status
Simulation time 9823285857 ps
CPU time 17.16 seconds
Started Jul 14 04:24:34 PM PDT 24
Finished Jul 14 04:24:53 PM PDT 24
Peak memory 199620 kb
Host smart-f610a0e6-c15e-478d-ba11-e8957114c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373425685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1373425685
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3786979187
Short name T271
Test name
Test status
Simulation time 139383841653 ps
CPU time 58.96 seconds
Started Jul 14 04:24:33 PM PDT 24
Finished Jul 14 04:25:34 PM PDT 24
Peak memory 199808 kb
Host smart-1aa4e3c6-04ca-4977-a1f4-356889280b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786979187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3786979187
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2379549788
Short name T891
Test name
Test status
Simulation time 3573558776 ps
CPU time 176.38 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:27:30 PM PDT 24
Peak memory 199716 kb
Host smart-85c2f93c-91e7-4d46-81b7-bc899640736e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379549788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2379549788
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2775781773
Short name T363
Test name
Test status
Simulation time 1787593907 ps
CPU time 6.18 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:24:38 PM PDT 24
Peak memory 198116 kb
Host smart-b5d9c7e5-d02f-412c-abc6-cb92188dbd16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2775781773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2775781773
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1290391294
Short name T951
Test name
Test status
Simulation time 29389979445 ps
CPU time 20.36 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:24:54 PM PDT 24
Peak memory 194872 kb
Host smart-d4db7d0f-e534-4330-b54d-f995676d4c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290391294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1290391294
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3759698384
Short name T5
Test name
Test status
Simulation time 332314521 ps
CPU time 1.04 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 198388 kb
Host smart-95d37d92-cac9-4e71-95cb-65b54e7bce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759698384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3759698384
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1039558235
Short name T740
Test name
Test status
Simulation time 62769985732 ps
CPU time 28.35 seconds
Started Jul 14 04:24:29 PM PDT 24
Finished Jul 14 04:24:58 PM PDT 24
Peak memory 208140 kb
Host smart-d143b7cf-110c-4939-a264-f51ea05d3270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039558235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1039558235
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.321830430
Short name T1157
Test name
Test status
Simulation time 63656038264 ps
CPU time 1119.99 seconds
Started Jul 14 04:24:31 PM PDT 24
Finished Jul 14 04:43:13 PM PDT 24
Peak memory 224732 kb
Host smart-d695fe64-f125-4740-b2b1-15e83dc0f749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321830430 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.321830430
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1635478891
Short name T426
Test name
Test status
Simulation time 3830915253 ps
CPU time 1.46 seconds
Started Jul 14 04:24:35 PM PDT 24
Finished Jul 14 04:24:38 PM PDT 24
Peak memory 198816 kb
Host smart-364f589b-6363-4e04-ad9e-8f8b17159df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635478891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1635478891
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3608350700
Short name T274
Test name
Test status
Simulation time 212905811592 ps
CPU time 52.88 seconds
Started Jul 14 04:24:31 PM PDT 24
Finished Jul 14 04:25:25 PM PDT 24
Peak memory 199776 kb
Host smart-f441884e-62a8-4505-b05a-2ce20383e17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608350700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3608350700
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2112101011
Short name T852
Test name
Test status
Simulation time 83014304960 ps
CPU time 15.04 seconds
Started Jul 14 04:27:18 PM PDT 24
Finished Jul 14 04:27:35 PM PDT 24
Peak memory 199664 kb
Host smart-51c064a9-1bc3-4103-912b-680f9c163f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112101011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2112101011
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.934668212
Short name T732
Test name
Test status
Simulation time 7990915385 ps
CPU time 11.65 seconds
Started Jul 14 04:27:20 PM PDT 24
Finished Jul 14 04:27:32 PM PDT 24
Peak memory 199720 kb
Host smart-13b58442-35bb-437c-bda4-590f5c216d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934668212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.934668212
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.423758607
Short name T1018
Test name
Test status
Simulation time 40725033319 ps
CPU time 19.62 seconds
Started Jul 14 04:27:19 PM PDT 24
Finished Jul 14 04:27:39 PM PDT 24
Peak memory 199676 kb
Host smart-2909a2f7-3fa6-42d3-afb0-536051169f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423758607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.423758607
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2760240083
Short name T80
Test name
Test status
Simulation time 70453169853 ps
CPU time 26.87 seconds
Started Jul 14 04:28:14 PM PDT 24
Finished Jul 14 04:28:42 PM PDT 24
Peak memory 198428 kb
Host smart-4707bceb-542b-4374-955b-ffaf72281239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760240083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2760240083
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.632382725
Short name T197
Test name
Test status
Simulation time 33419642218 ps
CPU time 55.93 seconds
Started Jul 14 04:27:20 PM PDT 24
Finished Jul 14 04:28:16 PM PDT 24
Peak memory 199632 kb
Host smart-e4a29ec6-779f-4353-89a7-4422d7758ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632382725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.632382725
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2422940219
Short name T110
Test name
Test status
Simulation time 19607000475 ps
CPU time 7.74 seconds
Started Jul 14 04:27:20 PM PDT 24
Finished Jul 14 04:27:28 PM PDT 24
Peak memory 199520 kb
Host smart-136674a9-05aa-4773-805e-ea030356c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422940219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2422940219
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2539948876
Short name T759
Test name
Test status
Simulation time 16743115639 ps
CPU time 9.79 seconds
Started Jul 14 04:27:18 PM PDT 24
Finished Jul 14 04:27:29 PM PDT 24
Peak memory 199772 kb
Host smart-0b26a876-f8ce-4491-bda9-039e018bc067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539948876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2539948876
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4072668534
Short name T1015
Test name
Test status
Simulation time 18693507824 ps
CPU time 25.81 seconds
Started Jul 14 04:27:16 PM PDT 24
Finished Jul 14 04:27:43 PM PDT 24
Peak memory 200004 kb
Host smart-97dbaaa8-5113-49be-bb4c-30d617fb4ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072668534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4072668534
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4153628713
Short name T861
Test name
Test status
Simulation time 43978785 ps
CPU time 0.53 seconds
Started Jul 14 04:24:40 PM PDT 24
Finished Jul 14 04:24:42 PM PDT 24
Peak memory 195112 kb
Host smart-9fa7e222-6d71-4cd6-98c2-7bafa0c6a0e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153628713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4153628713
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.592364154
Short name T625
Test name
Test status
Simulation time 27443193723 ps
CPU time 42.52 seconds
Started Jul 14 04:24:31 PM PDT 24
Finished Jul 14 04:25:15 PM PDT 24
Peak memory 199744 kb
Host smart-0714eaa3-a065-44b9-baa0-1577b56fbbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592364154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.592364154
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1197964642
Short name T1055
Test name
Test status
Simulation time 114671036352 ps
CPU time 55.61 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:25:29 PM PDT 24
Peak memory 198852 kb
Host smart-fdf1b5d5-631d-4125-90b2-c0b7048d7e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197964642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1197964642
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.493685966
Short name T198
Test name
Test status
Simulation time 67008245370 ps
CPU time 89.5 seconds
Started Jul 14 04:24:29 PM PDT 24
Finished Jul 14 04:26:00 PM PDT 24
Peak memory 199704 kb
Host smart-2c943ea1-800a-4733-8b87-88546f703ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493685966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.493685966
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3004820551
Short name T853
Test name
Test status
Simulation time 34151806320 ps
CPU time 54.63 seconds
Started Jul 14 04:24:34 PM PDT 24
Finished Jul 14 04:25:31 PM PDT 24
Peak memory 198756 kb
Host smart-fb2d3ba3-6855-4a71-96c7-f3cacaf13741
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004820551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3004820551
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.548016959
Short name T581
Test name
Test status
Simulation time 84900648202 ps
CPU time 124.48 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:26:44 PM PDT 24
Peak memory 199820 kb
Host smart-9275e8cc-d1df-4cde-97dd-8d65b03ffe45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=548016959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.548016959
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1080185400
Short name T741
Test name
Test status
Simulation time 6046585675 ps
CPU time 3.6 seconds
Started Jul 14 04:24:40 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 199600 kb
Host smart-156cd0b1-dce7-4ef4-ab12-3a0b22a0a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080185400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1080185400
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.843098832
Short name T502
Test name
Test status
Simulation time 15535958404 ps
CPU time 12.61 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 195684 kb
Host smart-524c1102-d05e-4a48-80f9-c9836aa93cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843098832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.843098832
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.676461748
Short name T1133
Test name
Test status
Simulation time 5994737043 ps
CPU time 181 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:27:40 PM PDT 24
Peak memory 199800 kb
Host smart-087d976f-4a60-4cc0-a4b4-be78f577c680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676461748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.676461748
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2325930572
Short name T1021
Test name
Test status
Simulation time 6716209826 ps
CPU time 55.03 seconds
Started Jul 14 04:24:30 PM PDT 24
Finished Jul 14 04:25:27 PM PDT 24
Peak memory 199700 kb
Host smart-58cfce00-cb45-4a73-84d3-eaff19179b6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325930572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2325930572
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3655048800
Short name T922
Test name
Test status
Simulation time 162041984371 ps
CPU time 72.52 seconds
Started Jul 14 04:24:39 PM PDT 24
Finished Jul 14 04:25:53 PM PDT 24
Peak memory 199648 kb
Host smart-bef37f3c-2b82-4d3a-9417-a638e132dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655048800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3655048800
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.865636521
Short name T915
Test name
Test status
Simulation time 5571819063 ps
CPU time 2.92 seconds
Started Jul 14 04:24:37 PM PDT 24
Finished Jul 14 04:24:41 PM PDT 24
Peak memory 195856 kb
Host smart-a9fd6e4b-500a-4405-ab77-8c55d28e5bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865636521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.865636521
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1476791344
Short name T531
Test name
Test status
Simulation time 669463647 ps
CPU time 2.6 seconds
Started Jul 14 04:24:32 PM PDT 24
Finished Jul 14 04:24:37 PM PDT 24
Peak memory 199252 kb
Host smart-4aaa6a04-5af8-4b78-b6a4-09cecf322e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476791344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1476791344
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.663315050
Short name T157
Test name
Test status
Simulation time 217409504887 ps
CPU time 171.84 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:27:31 PM PDT 24
Peak memory 208108 kb
Host smart-3136b4da-793d-4ae1-a4d8-9ca6b14f64ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663315050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.663315050
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1564202670
Short name T521
Test name
Test status
Simulation time 59776088087 ps
CPU time 1160.82 seconds
Started Jul 14 04:24:37 PM PDT 24
Finished Jul 14 04:43:59 PM PDT 24
Peak memory 216272 kb
Host smart-51111787-4ec6-4207-b01e-297dd6da192d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564202670 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1564202670
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4232000980
Short name T499
Test name
Test status
Simulation time 7843508059 ps
CPU time 11.26 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:24:51 PM PDT 24
Peak memory 200144 kb
Host smart-e34f2cf8-cce5-4b78-acc9-f3b6f5cb9222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232000980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4232000980
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2867460263
Short name T540
Test name
Test status
Simulation time 60091729320 ps
CPU time 101.64 seconds
Started Jul 14 04:24:33 PM PDT 24
Finished Jul 14 04:26:17 PM PDT 24
Peak memory 199584 kb
Host smart-8221837d-ebe5-44db-b13d-758dff8f138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867460263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2867460263
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2499195691
Short name T312
Test name
Test status
Simulation time 80868906893 ps
CPU time 75.72 seconds
Started Jul 14 04:27:18 PM PDT 24
Finished Jul 14 04:28:35 PM PDT 24
Peak memory 199828 kb
Host smart-745aee48-dfa1-45b9-9764-b813f7bc921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499195691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2499195691
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1955316778
Short name T569
Test name
Test status
Simulation time 18804194061 ps
CPU time 14.07 seconds
Started Jul 14 04:28:13 PM PDT 24
Finished Jul 14 04:28:28 PM PDT 24
Peak memory 199484 kb
Host smart-c5472636-89f5-45ec-8753-7f57fde41186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955316778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1955316778
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2996074773
Short name T450
Test name
Test status
Simulation time 44346607018 ps
CPU time 17.58 seconds
Started Jul 14 04:27:17 PM PDT 24
Finished Jul 14 04:27:35 PM PDT 24
Peak memory 199688 kb
Host smart-28fc6349-e8e7-4f71-a499-a40f542f3b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996074773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2996074773
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3818466927
Short name T671
Test name
Test status
Simulation time 9789787295 ps
CPU time 10.04 seconds
Started Jul 14 04:28:13 PM PDT 24
Finished Jul 14 04:28:24 PM PDT 24
Peak memory 199476 kb
Host smart-42eefa20-ed01-4c2c-b4f0-bc95d0868cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818466927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3818466927
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1932847538
Short name T977
Test name
Test status
Simulation time 21380915900 ps
CPU time 17.05 seconds
Started Jul 14 04:27:17 PM PDT 24
Finished Jul 14 04:27:34 PM PDT 24
Peak memory 199588 kb
Host smart-fdf8ae6c-9349-4ea4-8ed3-b73dc71303ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932847538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1932847538
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3116256526
Short name T226
Test name
Test status
Simulation time 12904636292 ps
CPU time 10.33 seconds
Started Jul 14 04:27:18 PM PDT 24
Finished Jul 14 04:27:30 PM PDT 24
Peak memory 199636 kb
Host smart-a8cb23ef-01fa-41c5-803b-8b1f743a83d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116256526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3116256526
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.203962279
Short name T343
Test name
Test status
Simulation time 61106507527 ps
CPU time 132.98 seconds
Started Jul 14 04:27:16 PM PDT 24
Finished Jul 14 04:29:30 PM PDT 24
Peak memory 199880 kb
Host smart-415cfa60-4fdf-405c-b032-dc648ad9e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203962279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.203962279
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1089004381
Short name T196
Test name
Test status
Simulation time 48225233705 ps
CPU time 17.55 seconds
Started Jul 14 04:27:17 PM PDT 24
Finished Jul 14 04:27:35 PM PDT 24
Peak memory 199716 kb
Host smart-6f92d999-a57d-4e43-9aa4-d3a48ef1cd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089004381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1089004381
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2246064549
Short name T1166
Test name
Test status
Simulation time 31616206 ps
CPU time 0.51 seconds
Started Jul 14 04:24:40 PM PDT 24
Finished Jul 14 04:24:41 PM PDT 24
Peak memory 195052 kb
Host smart-3c9298fa-0025-441f-b6c2-e6bbfaaae34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246064549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2246064549
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3182429682
Short name T418
Test name
Test status
Simulation time 56862183472 ps
CPU time 122.51 seconds
Started Jul 14 04:24:39 PM PDT 24
Finished Jul 14 04:26:43 PM PDT 24
Peak memory 199668 kb
Host smart-e69fd2d3-34ea-42b4-9491-b47a05ae7f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182429682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3182429682
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.954627805
Short name T352
Test name
Test status
Simulation time 110657240765 ps
CPU time 38.99 seconds
Started Jul 14 04:24:39 PM PDT 24
Finished Jul 14 04:25:19 PM PDT 24
Peak memory 199628 kb
Host smart-35394b77-7056-4074-b670-fe170f77a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954627805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.954627805
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.973144648
Short name T172
Test name
Test status
Simulation time 58008155132 ps
CPU time 147.38 seconds
Started Jul 14 04:24:39 PM PDT 24
Finished Jul 14 04:27:08 PM PDT 24
Peak memory 199732 kb
Host smart-101465b5-570b-4e3b-84cb-a5138d69a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973144648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.973144648
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.812420998
Short name T719
Test name
Test status
Simulation time 40067419547 ps
CPU time 18.09 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:24:57 PM PDT 24
Peak memory 199652 kb
Host smart-10eea99a-06b0-4072-bab0-8c5926739b95
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812420998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.812420998
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.201651268
Short name T372
Test name
Test status
Simulation time 117271302936 ps
CPU time 664.98 seconds
Started Jul 14 04:24:40 PM PDT 24
Finished Jul 14 04:35:46 PM PDT 24
Peak memory 199688 kb
Host smart-1a5d19cc-bc42-4cfa-bf3d-1d0b34c9f475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201651268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.201651268
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.520691794
Short name T370
Test name
Test status
Simulation time 2228304535 ps
CPU time 1.14 seconds
Started Jul 14 04:24:41 PM PDT 24
Finished Jul 14 04:24:43 PM PDT 24
Peak memory 196984 kb
Host smart-daaffeb6-7533-4da6-b961-824107820ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520691794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.520691794
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3485880794
Short name T545
Test name
Test status
Simulation time 40845638733 ps
CPU time 14.65 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:24:54 PM PDT 24
Peak memory 198928 kb
Host smart-1372c821-ca32-4799-859d-d45d73dac5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485880794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3485880794
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.285471016
Short name T10
Test name
Test status
Simulation time 6742726915 ps
CPU time 85.25 seconds
Started Jul 14 04:24:42 PM PDT 24
Finished Jul 14 04:26:08 PM PDT 24
Peak memory 199700 kb
Host smart-f76f385c-47dd-4d2a-96c8-ba466651d430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285471016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.285471016
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4147367700
Short name T991
Test name
Test status
Simulation time 4316904111 ps
CPU time 7.58 seconds
Started Jul 14 04:24:39 PM PDT 24
Finished Jul 14 04:24:48 PM PDT 24
Peak memory 197892 kb
Host smart-97bb0a3c-5e9d-4b54-9c70-13670685f69a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147367700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4147367700
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3550921273
Short name T1104
Test name
Test status
Simulation time 100003766820 ps
CPU time 36.78 seconds
Started Jul 14 04:24:40 PM PDT 24
Finished Jul 14 04:25:18 PM PDT 24
Peak memory 199816 kb
Host smart-16950f25-4c32-46b7-89ad-2bb57e43233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550921273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3550921273
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3595833598
Short name T527
Test name
Test status
Simulation time 3106196936 ps
CPU time 1.16 seconds
Started Jul 14 04:24:42 PM PDT 24
Finished Jul 14 04:24:44 PM PDT 24
Peak memory 196232 kb
Host smart-70459924-635a-4691-b058-b68f27aed79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595833598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3595833598
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1787539039
Short name T692
Test name
Test status
Simulation time 507853395 ps
CPU time 1.27 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:24:40 PM PDT 24
Peak memory 199032 kb
Host smart-ebdaab5f-8186-4629-ab82-74ea00750bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787539039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1787539039
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3701791561
Short name T760
Test name
Test status
Simulation time 143433151262 ps
CPU time 197.13 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:27:57 PM PDT 24
Peak memory 208200 kb
Host smart-2c01ef8f-7aed-454b-9804-a5e318021829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701791561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3701791561
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.791808181
Short name T1071
Test name
Test status
Simulation time 81272469794 ps
CPU time 350.14 seconds
Started Jul 14 04:24:36 PM PDT 24
Finished Jul 14 04:30:27 PM PDT 24
Peak memory 213220 kb
Host smart-d375c587-59d3-43c6-9849-cb62caaaca25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791808181 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.791808181
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3338332347
Short name T585
Test name
Test status
Simulation time 1441000365 ps
CPU time 4.27 seconds
Started Jul 14 04:24:42 PM PDT 24
Finished Jul 14 04:24:47 PM PDT 24
Peak memory 198776 kb
Host smart-67af5ab2-9010-48cb-842a-b3ddcf7c9c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338332347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3338332347
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.212649500
Short name T636
Test name
Test status
Simulation time 66009851009 ps
CPU time 20.06 seconds
Started Jul 14 04:24:39 PM PDT 24
Finished Jul 14 04:25:00 PM PDT 24
Peak memory 199872 kb
Host smart-73a0df0c-9d50-4043-b8e5-456a01b7b397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212649500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.212649500
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2652020745
Short name T1136
Test name
Test status
Simulation time 25433169707 ps
CPU time 36.94 seconds
Started Jul 14 04:27:27 PM PDT 24
Finished Jul 14 04:28:04 PM PDT 24
Peak memory 198724 kb
Host smart-8033835d-56c2-4f70-95e5-6ad5143390ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652020745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2652020745
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3303505736
Short name T65
Test name
Test status
Simulation time 24130266895 ps
CPU time 35.09 seconds
Started Jul 14 04:27:25 PM PDT 24
Finished Jul 14 04:28:01 PM PDT 24
Peak memory 199792 kb
Host smart-90b86f84-e41c-4ae8-8494-29f4127fcbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303505736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3303505736
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3592035159
Short name T299
Test name
Test status
Simulation time 72106653135 ps
CPU time 31.18 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:28:00 PM PDT 24
Peak memory 199680 kb
Host smart-b3984ac6-161c-498c-b4ff-f78c6ee170d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592035159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3592035159
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3589903319
Short name T777
Test name
Test status
Simulation time 23911548635 ps
CPU time 38.22 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:28:07 PM PDT 24
Peak memory 199896 kb
Host smart-4eb450db-5073-470d-a905-c8ac345e0b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589903319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3589903319
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1200417241
Short name T136
Test name
Test status
Simulation time 199392352429 ps
CPU time 546.85 seconds
Started Jul 14 04:27:27 PM PDT 24
Finished Jul 14 04:36:35 PM PDT 24
Peak memory 199716 kb
Host smart-fb78ce09-7210-4308-959a-f5ea892e3954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200417241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1200417241
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1863427963
Short name T657
Test name
Test status
Simulation time 78592432044 ps
CPU time 139.19 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:29:49 PM PDT 24
Peak memory 199740 kb
Host smart-df32ae87-ddd3-483e-a70b-a7e8452f6dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863427963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1863427963
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.149619627
Short name T239
Test name
Test status
Simulation time 25287352599 ps
CPU time 12.45 seconds
Started Jul 14 04:27:27 PM PDT 24
Finished Jul 14 04:27:40 PM PDT 24
Peak memory 199684 kb
Host smart-b60da5c0-9802-4324-acd0-ab4b6c8112c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149619627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.149619627
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2160642725
Short name T269
Test name
Test status
Simulation time 64970161722 ps
CPU time 85.6 seconds
Started Jul 14 04:27:29 PM PDT 24
Finished Jul 14 04:28:55 PM PDT 24
Peak memory 199764 kb
Host smart-a6fbef0d-e7dd-49b1-89ad-17740f2237ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160642725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2160642725
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2703540287
Short name T1141
Test name
Test status
Simulation time 43409272835 ps
CPU time 95.49 seconds
Started Jul 14 04:27:27 PM PDT 24
Finished Jul 14 04:29:04 PM PDT 24
Peak memory 199672 kb
Host smart-ba193e1b-b2ee-420a-91aa-a5a78605d27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703540287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2703540287
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.613396672
Short name T931
Test name
Test status
Simulation time 69118641428 ps
CPU time 25.92 seconds
Started Jul 14 04:27:26 PM PDT 24
Finished Jul 14 04:27:53 PM PDT 24
Peak memory 199756 kb
Host smart-bc0146fc-18e5-4518-8c98-66c3589aa2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613396672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.613396672
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1211595684
Short name T859
Test name
Test status
Simulation time 13944485 ps
CPU time 0.56 seconds
Started Jul 14 04:24:52 PM PDT 24
Finished Jul 14 04:24:55 PM PDT 24
Peak memory 195076 kb
Host smart-f07276ec-28cb-4844-a4a9-a0963d42972d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211595684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1211595684
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.748417340
Short name T177
Test name
Test status
Simulation time 42710353934 ps
CPU time 16.42 seconds
Started Jul 14 04:24:38 PM PDT 24
Finished Jul 14 04:24:55 PM PDT 24
Peak memory 199828 kb
Host smart-e475a203-3b57-4647-b005-fda613bf5d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748417340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.748417340
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.618901359
Short name T1014
Test name
Test status
Simulation time 10733502935 ps
CPU time 5.91 seconds
Started Jul 14 04:24:50 PM PDT 24
Finished Jul 14 04:24:57 PM PDT 24
Peak memory 199600 kb
Host smart-bbb41762-5a41-4c03-a025-5ba3e5ca0c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618901359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.618901359
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.369244500
Short name T1060
Test name
Test status
Simulation time 135145956262 ps
CPU time 17.84 seconds
Started Jul 14 04:24:50 PM PDT 24
Finished Jul 14 04:25:10 PM PDT 24
Peak memory 199080 kb
Host smart-42fa21e7-d971-4138-8456-ad1c001e96f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369244500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.369244500
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.433028992
Short name T911
Test name
Test status
Simulation time 21515387364 ps
CPU time 31.42 seconds
Started Jul 14 04:24:52 PM PDT 24
Finished Jul 14 04:25:25 PM PDT 24
Peak memory 199840 kb
Host smart-7edb7bb8-2226-4699-ba87-bd38701177f4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433028992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.433028992
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1265622400
Short name T766
Test name
Test status
Simulation time 57989771059 ps
CPU time 178.46 seconds
Started Jul 14 04:24:50 PM PDT 24
Finished Jul 14 04:27:49 PM PDT 24
Peak memory 199512 kb
Host smart-2f4d9505-3179-42a7-a237-ac0977726153
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265622400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1265622400
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3223738268
Short name T557
Test name
Test status
Simulation time 4788546931 ps
CPU time 4.04 seconds
Started Jul 14 04:24:54 PM PDT 24
Finished Jul 14 04:25:00 PM PDT 24
Peak memory 198956 kb
Host smart-d599f5cc-4026-47a5-b19a-16e681e34947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223738268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3223738268
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3714523261
Short name T984
Test name
Test status
Simulation time 232579479658 ps
CPU time 142.16 seconds
Started Jul 14 04:24:49 PM PDT 24
Finished Jul 14 04:27:12 PM PDT 24
Peak memory 199872 kb
Host smart-7479a12f-e090-4c5d-a23d-8ecf59bfbf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714523261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3714523261
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.743652635
Short name T595
Test name
Test status
Simulation time 21971639568 ps
CPU time 961.08 seconds
Started Jul 14 04:24:55 PM PDT 24
Finished Jul 14 04:40:58 PM PDT 24
Peak memory 199664 kb
Host smart-4c6570d9-593b-45b5-bafe-bc923f1f880e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743652635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.743652635
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2046517455
Short name T1169
Test name
Test status
Simulation time 3888975567 ps
CPU time 7.85 seconds
Started Jul 14 04:24:49 PM PDT 24
Finished Jul 14 04:24:58 PM PDT 24
Peak memory 199264 kb
Host smart-3f8e7e8c-7263-4428-8e1c-e5c050619439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046517455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2046517455
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1405512471
Short name T510
Test name
Test status
Simulation time 163902622979 ps
CPU time 271.19 seconds
Started Jul 14 04:24:47 PM PDT 24
Finished Jul 14 04:29:19 PM PDT 24
Peak memory 199820 kb
Host smart-c9954eed-b7ac-4d59-b6d1-8579dd70d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405512471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1405512471
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2527922310
Short name T839
Test name
Test status
Simulation time 2738025143 ps
CPU time 1.65 seconds
Started Jul 14 04:24:48 PM PDT 24
Finished Jul 14 04:24:51 PM PDT 24
Peak memory 195484 kb
Host smart-104da0a4-6c89-4748-a055-402bc806f805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527922310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2527922310
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.185474904
Short name T1089
Test name
Test status
Simulation time 289024939 ps
CPU time 1.42 seconds
Started Jul 14 04:24:44 PM PDT 24
Finished Jul 14 04:24:46 PM PDT 24
Peak memory 198528 kb
Host smart-a8c00a3d-b8ad-4ea5-acc5-6ba3b91715e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185474904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.185474904
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1527182443
Short name T834
Test name
Test status
Simulation time 141169263247 ps
CPU time 774.3 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:37:53 PM PDT 24
Peak memory 199656 kb
Host smart-d80cfccb-ea82-4626-94d2-03512326cab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527182443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1527182443
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1677494160
Short name T131
Test name
Test status
Simulation time 76136997802 ps
CPU time 353.29 seconds
Started Jul 14 04:24:51 PM PDT 24
Finished Jul 14 04:30:46 PM PDT 24
Peak memory 216184 kb
Host smart-2fcbd8cf-f854-478a-bade-0d8b9f726840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677494160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1677494160
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2041219079
Short name T407
Test name
Test status
Simulation time 5800834218 ps
CPU time 1.51 seconds
Started Jul 14 04:24:55 PM PDT 24
Finished Jul 14 04:24:58 PM PDT 24
Peak memory 198900 kb
Host smart-5e7e4885-b92e-4a7c-97a1-e221d62ae3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041219079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2041219079
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3629366796
Short name T496
Test name
Test status
Simulation time 14603142785 ps
CPU time 23.37 seconds
Started Jul 14 04:24:41 PM PDT 24
Finished Jul 14 04:25:06 PM PDT 24
Peak memory 199636 kb
Host smart-d33a025e-d192-47ef-a9e2-cc6c3f74c47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629366796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3629366796
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.487576343
Short name T287
Test name
Test status
Simulation time 106167954659 ps
CPU time 154.94 seconds
Started Jul 14 04:27:26 PM PDT 24
Finished Jul 14 04:30:01 PM PDT 24
Peak memory 199732 kb
Host smart-012fcb97-8689-460d-ae35-0d78547dadd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487576343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.487576343
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1219245867
Short name T1035
Test name
Test status
Simulation time 80047579577 ps
CPU time 15.6 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:27:45 PM PDT 24
Peak memory 199768 kb
Host smart-5720ede1-066e-4906-932a-ed11179da784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219245867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1219245867
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1957576361
Short name T330
Test name
Test status
Simulation time 15328239829 ps
CPU time 25.24 seconds
Started Jul 14 04:27:27 PM PDT 24
Finished Jul 14 04:27:52 PM PDT 24
Peak memory 199736 kb
Host smart-bfd0a6e2-66ce-419a-89e0-4d39f78add29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957576361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1957576361
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1895479555
Short name T249
Test name
Test status
Simulation time 129976603822 ps
CPU time 84.06 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:28:54 PM PDT 24
Peak memory 199804 kb
Host smart-e42eb251-d2f3-4f87-b1ab-3be5317ed6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895479555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1895479555
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1911144197
Short name T651
Test name
Test status
Simulation time 17687793438 ps
CPU time 30.13 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:28:00 PM PDT 24
Peak memory 199656 kb
Host smart-be91699c-7885-4cca-a0c1-9ddd3a7a30b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911144197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1911144197
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.743248391
Short name T562
Test name
Test status
Simulation time 98317119219 ps
CPU time 165.22 seconds
Started Jul 14 04:27:26 PM PDT 24
Finished Jul 14 04:30:12 PM PDT 24
Peak memory 199684 kb
Host smart-b2ef443c-e121-4fbb-a08e-32629ec1512a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743248391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.743248391
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1323048237
Short name T195
Test name
Test status
Simulation time 55773713641 ps
CPU time 89.4 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:28:58 PM PDT 24
Peak memory 199660 kb
Host smart-ff11ce17-0843-4b91-a88a-534ac2d95e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323048237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1323048237
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3244006184
Short name T235
Test name
Test status
Simulation time 41433006471 ps
CPU time 13.76 seconds
Started Jul 14 04:27:30 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 199736 kb
Host smart-c9a7aa94-f296-455f-96fb-4d120f17ad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244006184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3244006184
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2152793257
Short name T217
Test name
Test status
Simulation time 232597855876 ps
CPU time 42.6 seconds
Started Jul 14 04:27:27 PM PDT 24
Finished Jul 14 04:28:10 PM PDT 24
Peak memory 199792 kb
Host smart-c6a66eba-abb3-4e1d-a130-fc350178b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152793257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2152793257
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1963710738
Short name T1065
Test name
Test status
Simulation time 72982345921 ps
CPU time 59.85 seconds
Started Jul 14 04:27:27 PM PDT 24
Finished Jul 14 04:28:28 PM PDT 24
Peak memory 199776 kb
Host smart-cdab113a-1cc4-4938-a9fd-44ed4bf06ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963710738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1963710738
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3321830814
Short name T445
Test name
Test status
Simulation time 56091123 ps
CPU time 0.55 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:24:59 PM PDT 24
Peak memory 195168 kb
Host smart-52fdc85e-11da-4503-af06-bb3bbf9e1c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321830814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3321830814
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3869203212
Short name T167
Test name
Test status
Simulation time 25345001550 ps
CPU time 18.52 seconds
Started Jul 14 04:24:51 PM PDT 24
Finished Jul 14 04:25:12 PM PDT 24
Peak memory 199768 kb
Host smart-b4c9eb06-257d-4935-8351-3d84250a7c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869203212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3869203212
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3445451081
Short name T147
Test name
Test status
Simulation time 17631699004 ps
CPU time 17.26 seconds
Started Jul 14 04:24:48 PM PDT 24
Finished Jul 14 04:25:06 PM PDT 24
Peak memory 199744 kb
Host smart-18796b45-2e7a-4f51-8ce8-da066e9efd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445451081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3445451081
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1803544713
Short name T205
Test name
Test status
Simulation time 12000069674 ps
CPU time 21.08 seconds
Started Jul 14 04:24:45 PM PDT 24
Finished Jul 14 04:25:07 PM PDT 24
Peak memory 199680 kb
Host smart-27828591-1a4f-47ce-bcd6-de8d7005ae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803544713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1803544713
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2290009091
Short name T451
Test name
Test status
Simulation time 24712164291 ps
CPU time 16.39 seconds
Started Jul 14 04:24:48 PM PDT 24
Finished Jul 14 04:25:05 PM PDT 24
Peak memory 199440 kb
Host smart-8b6545e2-83fc-4d55-b465-762a3ea33127
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290009091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2290009091
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.303657047
Short name T523
Test name
Test status
Simulation time 83700441121 ps
CPU time 708.08 seconds
Started Jul 14 04:24:50 PM PDT 24
Finished Jul 14 04:36:40 PM PDT 24
Peak memory 199000 kb
Host smart-d9a5611d-ac4e-4861-9da9-4cdfb47bc5c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303657047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.303657047
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.45538337
Short name T597
Test name
Test status
Simulation time 6359830840 ps
CPU time 5.33 seconds
Started Jul 14 04:24:49 PM PDT 24
Finished Jul 14 04:24:55 PM PDT 24
Peak memory 199740 kb
Host smart-7050e0d8-3079-456d-9505-4b155c5e9c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45538337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.45538337
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2005259798
Short name T443
Test name
Test status
Simulation time 163754904394 ps
CPU time 125.2 seconds
Started Jul 14 04:24:51 PM PDT 24
Finished Jul 14 04:26:59 PM PDT 24
Peak memory 208248 kb
Host smart-1b83cc28-085a-4008-895b-c08403bb3261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005259798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2005259798
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3984555031
Short name T388
Test name
Test status
Simulation time 31550728031 ps
CPU time 77.72 seconds
Started Jul 14 04:24:48 PM PDT 24
Finished Jul 14 04:26:06 PM PDT 24
Peak memory 199744 kb
Host smart-3b31f1bd-06d4-4079-b75c-7bdb7a225897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984555031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3984555031
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.400292790
Short name T1093
Test name
Test status
Simulation time 1622522711 ps
CPU time 1.64 seconds
Started Jul 14 04:24:47 PM PDT 24
Finished Jul 14 04:24:49 PM PDT 24
Peak memory 197644 kb
Host smart-3af93018-428b-403f-abae-f35eabf4c65d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400292790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.400292790
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1796329399
Short name T162
Test name
Test status
Simulation time 174860809457 ps
CPU time 97.82 seconds
Started Jul 14 04:24:49 PM PDT 24
Finished Jul 14 04:26:28 PM PDT 24
Peak memory 199708 kb
Host smart-435a58e3-0870-49e6-ab1d-9c48f17e235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796329399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1796329399
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2344341447
Short name T321
Test name
Test status
Simulation time 2667417478 ps
CPU time 1.74 seconds
Started Jul 14 04:24:46 PM PDT 24
Finished Jul 14 04:24:49 PM PDT 24
Peak memory 195664 kb
Host smart-7bca0775-4506-4a10-acf5-39e89e466443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344341447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2344341447
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2268069649
Short name T1122
Test name
Test status
Simulation time 90043982 ps
CPU time 0.8 seconds
Started Jul 14 04:24:52 PM PDT 24
Finished Jul 14 04:24:55 PM PDT 24
Peak memory 196872 kb
Host smart-ab1400aa-f399-4618-9350-71c91f1a61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268069649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2268069649
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1359405540
Short name T994
Test name
Test status
Simulation time 108154234847 ps
CPU time 415.77 seconds
Started Jul 14 04:24:51 PM PDT 24
Finished Jul 14 04:31:49 PM PDT 24
Peak memory 199592 kb
Host smart-8ee088f1-5236-4f15-bd3a-530626920cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359405540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1359405540
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1514998664
Short name T118
Test name
Test status
Simulation time 81575316962 ps
CPU time 201.02 seconds
Started Jul 14 04:24:54 PM PDT 24
Finished Jul 14 04:28:17 PM PDT 24
Peak memory 216152 kb
Host smart-76f84cd3-ede8-400a-bf29-6536cc20c943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514998664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1514998664
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1098994121
Short name T15
Test name
Test status
Simulation time 7103909049 ps
CPU time 11.66 seconds
Started Jul 14 04:24:51 PM PDT 24
Finished Jul 14 04:25:04 PM PDT 24
Peak memory 199004 kb
Host smart-1632793d-bcc1-4b2c-bfbe-424604bc60d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098994121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1098994121
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3521822628
Short name T408
Test name
Test status
Simulation time 66020021823 ps
CPU time 121.14 seconds
Started Jul 14 04:24:47 PM PDT 24
Finished Jul 14 04:26:48 PM PDT 24
Peak memory 199704 kb
Host smart-473fb513-85a4-45b5-8e6c-441ee39972ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521822628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3521822628
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.999943182
Short name T211
Test name
Test status
Simulation time 134647937029 ps
CPU time 126.46 seconds
Started Jul 14 04:27:29 PM PDT 24
Finished Jul 14 04:29:36 PM PDT 24
Peak memory 199688 kb
Host smart-e25fd565-cab4-479a-94c6-0cb43c84d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999943182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.999943182
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.4200284650
Short name T851
Test name
Test status
Simulation time 30153340382 ps
CPU time 36 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:28:05 PM PDT 24
Peak memory 199636 kb
Host smart-30661391-a358-4c62-a2c4-81ea0b93c75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200284650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.4200284650
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4237285930
Short name T214
Test name
Test status
Simulation time 81213281246 ps
CPU time 293.68 seconds
Started Jul 14 04:27:26 PM PDT 24
Finished Jul 14 04:32:20 PM PDT 24
Peak memory 199736 kb
Host smart-112bc9c2-bf2b-4c64-9c71-0b515be7c93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237285930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4237285930
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1916104419
Short name T794
Test name
Test status
Simulation time 26802484472 ps
CPU time 38.45 seconds
Started Jul 14 04:27:28 PM PDT 24
Finished Jul 14 04:28:07 PM PDT 24
Peak memory 199684 kb
Host smart-07360020-c161-4000-8415-572dbca23cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916104419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1916104419
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3002834127
Short name T346
Test name
Test status
Simulation time 105876487564 ps
CPU time 17.53 seconds
Started Jul 14 04:27:30 PM PDT 24
Finished Jul 14 04:27:48 PM PDT 24
Peak memory 199504 kb
Host smart-74246627-60a5-40fd-ac2a-0010037922b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002834127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3002834127
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1428543768
Short name T1148
Test name
Test status
Simulation time 86898877972 ps
CPU time 234.28 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:31:32 PM PDT 24
Peak memory 199800 kb
Host smart-77dd863c-506d-4125-85b9-f88502134368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428543768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1428543768
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.470496944
Short name T170
Test name
Test status
Simulation time 16879456359 ps
CPU time 18.62 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:54 PM PDT 24
Peak memory 199816 kb
Host smart-3250cd97-96bf-486d-a13f-49f3f0fc4d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470496944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.470496944
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3630563081
Short name T1058
Test name
Test status
Simulation time 55066254117 ps
CPU time 47.67 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:28:25 PM PDT 24
Peak memory 199756 kb
Host smart-aee561ce-1364-4b50-806c-41e727f94e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630563081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3630563081
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3472743359
Short name T960
Test name
Test status
Simulation time 23965773543 ps
CPU time 25.47 seconds
Started Jul 14 04:27:39 PM PDT 24
Finished Jul 14 04:28:05 PM PDT 24
Peak memory 199704 kb
Host smart-0222f6e6-71bc-4b09-ae5c-5e185ef6c21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472743359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3472743359
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4068378852
Short name T58
Test name
Test status
Simulation time 107607268840 ps
CPU time 157.42 seconds
Started Jul 14 04:27:34 PM PDT 24
Finished Jul 14 04:30:12 PM PDT 24
Peak memory 199860 kb
Host smart-d6edadf2-66df-418a-b064-bb5e8da6c182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068378852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4068378852
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2269609917
Short name T941
Test name
Test status
Simulation time 72790063 ps
CPU time 0.54 seconds
Started Jul 14 04:23:38 PM PDT 24
Finished Jul 14 04:23:40 PM PDT 24
Peak memory 195056 kb
Host smart-2093f856-1042-4ac7-acd8-4614d8d7ee8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269609917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2269609917
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1544848146
Short name T888
Test name
Test status
Simulation time 41861514171 ps
CPU time 56.86 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 199696 kb
Host smart-d12e32df-d21d-4732-8183-fcbb19bee466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544848146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1544848146
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.715418277
Short name T1075
Test name
Test status
Simulation time 41429456204 ps
CPU time 71.53 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:24:46 PM PDT 24
Peak memory 199820 kb
Host smart-33df81bd-1572-4e5e-be8c-47e69bc0bc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715418277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.715418277
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2329216178
Short name T331
Test name
Test status
Simulation time 17230123336 ps
CPU time 13.27 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:23:52 PM PDT 24
Peak memory 199560 kb
Host smart-bfdef6e4-25f0-4484-b845-3d829237b856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329216178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2329216178
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.688308680
Short name T897
Test name
Test status
Simulation time 109080057277 ps
CPU time 170.09 seconds
Started Jul 14 04:23:35 PM PDT 24
Finished Jul 14 04:26:28 PM PDT 24
Peak memory 196492 kb
Host smart-e2d18173-5c92-475b-80a0-077f8a2961dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688308680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.688308680
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3426755980
Short name T436
Test name
Test status
Simulation time 97220423941 ps
CPU time 381.16 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:29:56 PM PDT 24
Peak memory 199720 kb
Host smart-f84129aa-1aa7-42fd-aa38-ea4ecbd5f89e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426755980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3426755980
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2015158404
Short name T399
Test name
Test status
Simulation time 132277075 ps
CPU time 0.69 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:23:36 PM PDT 24
Peak memory 195860 kb
Host smart-37b4c258-d6a8-41ad-8bb8-1c069b694614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015158404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2015158404
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2588791822
Short name T591
Test name
Test status
Simulation time 153001748695 ps
CPU time 80.85 seconds
Started Jul 14 04:23:39 PM PDT 24
Finished Jul 14 04:25:01 PM PDT 24
Peak memory 199868 kb
Host smart-f611120b-475e-4d9b-af43-17142bb8764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588791822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2588791822
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2116950392
Short name T449
Test name
Test status
Simulation time 13648199754 ps
CPU time 785.07 seconds
Started Jul 14 04:24:02 PM PDT 24
Finished Jul 14 04:37:08 PM PDT 24
Peak memory 199780 kb
Host smart-9ccbc054-0fb7-4be1-b870-9c1b8c36b152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2116950392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2116950392
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.4079961522
Short name T735
Test name
Test status
Simulation time 2723329391 ps
CPU time 16.73 seconds
Started Jul 14 04:23:45 PM PDT 24
Finished Jul 14 04:24:02 PM PDT 24
Peak memory 197928 kb
Host smart-d1be7f14-3f23-4fdd-ac0e-880526545308
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079961522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.4079961522
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3290450615
Short name T437
Test name
Test status
Simulation time 119323505480 ps
CPU time 252.6 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:27:51 PM PDT 24
Peak memory 199740 kb
Host smart-bced0951-196c-4ad2-a7dd-6835b692fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290450615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3290450615
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3061514077
Short name T792
Test name
Test status
Simulation time 3432792511 ps
CPU time 2.03 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:23:41 PM PDT 24
Peak memory 195816 kb
Host smart-7d57634c-3756-48f3-99dc-baed5977bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061514077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3061514077
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1662990657
Short name T101
Test name
Test status
Simulation time 56304764 ps
CPU time 0.83 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:34 PM PDT 24
Peak memory 218088 kb
Host smart-007c7fc1-ab72-478b-b882-8f36c05750f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662990657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1662990657
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2065403991
Short name T687
Test name
Test status
Simulation time 470791621 ps
CPU time 2.32 seconds
Started Jul 14 04:23:35 PM PDT 24
Finished Jul 14 04:23:40 PM PDT 24
Peak memory 199504 kb
Host smart-03a832bf-1d71-4263-b8d1-956671de82ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065403991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2065403991
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.724701452
Short name T986
Test name
Test status
Simulation time 89508392150 ps
CPU time 122.51 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:25:37 PM PDT 24
Peak memory 199656 kb
Host smart-f81b0d93-3a18-4e14-a141-81e7671fe331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724701452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.724701452
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2360474659
Short name T107
Test name
Test status
Simulation time 473528688287 ps
CPU time 493.98 seconds
Started Jul 14 04:23:34 PM PDT 24
Finished Jul 14 04:31:51 PM PDT 24
Peak memory 228032 kb
Host smart-1999ec0a-eadb-440d-ab68-dcf1bb51a0a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360474659 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2360474659
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2986624654
Short name T1134
Test name
Test status
Simulation time 1770220437 ps
CPU time 1.52 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 199628 kb
Host smart-b17c920b-2951-4922-9c4a-dba5f85713e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986624654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2986624654
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1907373616
Short name T1110
Test name
Test status
Simulation time 30349673347 ps
CPU time 13.36 seconds
Started Jul 14 04:23:34 PM PDT 24
Finished Jul 14 04:23:50 PM PDT 24
Peak memory 199800 kb
Host smart-b351c816-4dfd-4b22-9604-797db52086d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907373616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1907373616
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3691421307
Short name T25
Test name
Test status
Simulation time 40712802 ps
CPU time 0.57 seconds
Started Jul 14 04:25:05 PM PDT 24
Finished Jul 14 04:25:07 PM PDT 24
Peak memory 194032 kb
Host smart-3a6f0ab6-611b-4093-a093-fdfe710f6f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691421307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3691421307
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3595094766
Short name T622
Test name
Test status
Simulation time 77730831088 ps
CPU time 25.48 seconds
Started Jul 14 04:25:04 PM PDT 24
Finished Jul 14 04:25:30 PM PDT 24
Peak memory 199728 kb
Host smart-3bb1f427-ecc3-45dd-96bf-1835dfa8836d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595094766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3595094766
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1180840250
Short name T721
Test name
Test status
Simulation time 42642931903 ps
CPU time 32.36 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:25:32 PM PDT 24
Peak memory 199784 kb
Host smart-62d39edb-76b8-4021-afc4-462f6a224cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180840250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1180840250
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.569370553
Short name T553
Test name
Test status
Simulation time 124653954441 ps
CPU time 19.82 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:25:19 PM PDT 24
Peak memory 199680 kb
Host smart-04abd548-fc43-4fba-9030-50238ec63565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569370553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.569370553
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.167172535
Short name T398
Test name
Test status
Simulation time 63159775560 ps
CPU time 97.83 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:26:46 PM PDT 24
Peak memory 199668 kb
Host smart-c781f089-39bc-402a-805f-bcbb8d624968
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167172535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.167172535
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3825998879
Short name T812
Test name
Test status
Simulation time 57729093414 ps
CPU time 243.24 seconds
Started Jul 14 04:24:56 PM PDT 24
Finished Jul 14 04:29:01 PM PDT 24
Peak memory 199740 kb
Host smart-0e4f4951-6488-4e0f-affe-23a703cacdef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825998879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3825998879
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2309723438
Short name T1117
Test name
Test status
Simulation time 7411016541 ps
CPU time 4.64 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:25:03 PM PDT 24
Peak memory 197832 kb
Host smart-e9c084fb-5f76-4306-9116-f454aa8b9147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309723438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2309723438
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1969362739
Short name T1155
Test name
Test status
Simulation time 2345817921 ps
CPU time 2.18 seconds
Started Jul 14 04:25:01 PM PDT 24
Finished Jul 14 04:25:04 PM PDT 24
Peak memory 199672 kb
Host smart-9db1cc14-407c-4888-80eb-1af5947bcaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969362739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1969362739
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.752744080
Short name T913
Test name
Test status
Simulation time 3019705784 ps
CPU time 3.41 seconds
Started Jul 14 04:25:05 PM PDT 24
Finished Jul 14 04:25:09 PM PDT 24
Peak memory 198060 kb
Host smart-c32d5ad2-0f92-43f8-a9db-7998635bef4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=752744080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.752744080
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2887078299
Short name T987
Test name
Test status
Simulation time 5310445487 ps
CPU time 8.49 seconds
Started Jul 14 04:25:04 PM PDT 24
Finished Jul 14 04:25:13 PM PDT 24
Peak memory 195992 kb
Host smart-a3fb3e63-e9a3-4d39-a9f3-cc7d3c37fb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887078299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2887078299
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2202125357
Short name T957
Test name
Test status
Simulation time 691923373 ps
CPU time 4.33 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:25:03 PM PDT 24
Peak memory 198536 kb
Host smart-97497a31-8a2a-4062-b857-aa6ab9f4f3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202125357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2202125357
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.480069323
Short name T481
Test name
Test status
Simulation time 346987158896 ps
CPU time 240.12 seconds
Started Jul 14 04:24:58 PM PDT 24
Finished Jul 14 04:29:00 PM PDT 24
Peak memory 199732 kb
Host smart-208e3c62-6db4-4929-9c9a-0165cef9b62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480069323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.480069323
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.632635235
Short name T514
Test name
Test status
Simulation time 65234607388 ps
CPU time 281.72 seconds
Started Jul 14 04:25:03 PM PDT 24
Finished Jul 14 04:29:45 PM PDT 24
Peak memory 216480 kb
Host smart-0bc25eb1-ca2a-427a-a486-c6ae81c842fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632635235 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.632635235
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3629096450
Short name T373
Test name
Test status
Simulation time 855266384 ps
CPU time 2.13 seconds
Started Jul 14 04:24:56 PM PDT 24
Finished Jul 14 04:25:00 PM PDT 24
Peak memory 198084 kb
Host smart-5ed1208c-301b-48ba-b1b4-24fae3705576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629096450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3629096450
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.4261170137
Short name T806
Test name
Test status
Simulation time 58708073122 ps
CPU time 16.77 seconds
Started Jul 14 04:24:59 PM PDT 24
Finished Jul 14 04:25:17 PM PDT 24
Peak memory 199660 kb
Host smart-8be77b59-16b9-48e3-bd3e-20249f4cd041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261170137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4261170137
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.137718787
Short name T515
Test name
Test status
Simulation time 13438240 ps
CPU time 0.57 seconds
Started Jul 14 04:25:10 PM PDT 24
Finished Jul 14 04:25:12 PM PDT 24
Peak memory 195196 kb
Host smart-027dff0c-049b-4762-bec2-5fbc934ce051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137718787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.137718787
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3973842869
Short name T872
Test name
Test status
Simulation time 37035720956 ps
CPU time 17.78 seconds
Started Jul 14 04:25:04 PM PDT 24
Finished Jul 14 04:25:22 PM PDT 24
Peak memory 199688 kb
Host smart-82fb13a9-21c4-453f-b04c-8b6710af3b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973842869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3973842869
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3362689217
Short name T1160
Test name
Test status
Simulation time 54458316072 ps
CPU time 92.66 seconds
Started Jul 14 04:25:00 PM PDT 24
Finished Jul 14 04:26:33 PM PDT 24
Peak memory 199768 kb
Host smart-d63fd2f9-4247-4226-a740-75d879b992a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362689217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3362689217
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.777016721
Short name T208
Test name
Test status
Simulation time 91834196024 ps
CPU time 18.11 seconds
Started Jul 14 04:25:04 PM PDT 24
Finished Jul 14 04:25:23 PM PDT 24
Peak memory 199684 kb
Host smart-7136c347-ff93-4ffb-aaa4-51de16d241b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777016721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.777016721
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1582445470
Short name T1057
Test name
Test status
Simulation time 29649842049 ps
CPU time 16.95 seconds
Started Jul 14 04:24:58 PM PDT 24
Finished Jul 14 04:25:16 PM PDT 24
Peak memory 199712 kb
Host smart-0bb01370-0acf-49a4-a159-d8621aa2a61c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582445470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1582445470
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2055869433
Short name T801
Test name
Test status
Simulation time 121529678041 ps
CPU time 1073.58 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:42:53 PM PDT 24
Peak memory 199700 kb
Host smart-f5dc22e7-005c-4fa6-a79b-d832a8dbe787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055869433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2055869433
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2060820156
Short name T928
Test name
Test status
Simulation time 12246431448 ps
CPU time 9.71 seconds
Started Jul 14 04:24:58 PM PDT 24
Finished Jul 14 04:25:09 PM PDT 24
Peak memory 199104 kb
Host smart-e5f38d43-a786-4daf-8e57-615146bd00c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060820156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2060820156
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.953679277
Short name T879
Test name
Test status
Simulation time 191105428424 ps
CPU time 74.21 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:26:12 PM PDT 24
Peak memory 199960 kb
Host smart-fbc11955-7f35-40ac-b7b3-d26c40175ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953679277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.953679277
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1491047414
Short name T917
Test name
Test status
Simulation time 8058715320 ps
CPU time 406.52 seconds
Started Jul 14 04:24:59 PM PDT 24
Finished Jul 14 04:31:46 PM PDT 24
Peak memory 199668 kb
Host smart-c39c5089-ff73-4cd0-ba95-52ecd8275612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491047414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1491047414
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.814341934
Short name T416
Test name
Test status
Simulation time 3403504454 ps
CPU time 6.38 seconds
Started Jul 14 04:24:59 PM PDT 24
Finished Jul 14 04:25:06 PM PDT 24
Peak memory 198932 kb
Host smart-1ff4a39a-608e-4a34-b082-1526e7dad9c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814341934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.814341934
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3606275814
Short name T765
Test name
Test status
Simulation time 82695064534 ps
CPU time 68.87 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:26:07 PM PDT 24
Peak memory 199820 kb
Host smart-fa73f498-765b-4b00-8b86-6e4cae57e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606275814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3606275814
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.970325689
Short name T764
Test name
Test status
Simulation time 36801625157 ps
CPU time 15.21 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:25:14 PM PDT 24
Peak memory 195624 kb
Host smart-68ac7106-cd3f-467a-af3c-2aa41fcb8a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970325689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.970325689
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2537669112
Short name T558
Test name
Test status
Simulation time 122457420 ps
CPU time 1.01 seconds
Started Jul 14 04:24:57 PM PDT 24
Finished Jul 14 04:25:00 PM PDT 24
Peak memory 198588 kb
Host smart-ca1a1edd-7d4f-4274-ac9d-4c6008bc212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537669112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2537669112
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3991128894
Short name T780
Test name
Test status
Simulation time 434807065388 ps
CPU time 809.88 seconds
Started Jul 14 04:25:10 PM PDT 24
Finished Jul 14 04:38:41 PM PDT 24
Peak memory 208068 kb
Host smart-6795fba0-42ea-4ea3-9a16-aa086543d9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991128894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3991128894
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2996429364
Short name T602
Test name
Test status
Simulation time 63390860081 ps
CPU time 575.17 seconds
Started Jul 14 04:25:02 PM PDT 24
Finished Jul 14 04:34:37 PM PDT 24
Peak memory 215712 kb
Host smart-825cd9c6-a090-49be-ac9c-fcf6afa9ab67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996429364 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2996429364
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1742713790
Short name T1154
Test name
Test status
Simulation time 12422988457 ps
CPU time 21.21 seconds
Started Jul 14 04:24:55 PM PDT 24
Finished Jul 14 04:25:18 PM PDT 24
Peak memory 199668 kb
Host smart-1a84b806-3e4b-4ad2-af60-ce993ff5c11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742713790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1742713790
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1559152985
Short name T507
Test name
Test status
Simulation time 122021417271 ps
CPU time 239.93 seconds
Started Jul 14 04:24:58 PM PDT 24
Finished Jul 14 04:29:00 PM PDT 24
Peak memory 199692 kb
Host smart-5c418e32-7f92-48b3-8b8d-9e42e435911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559152985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1559152985
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3008967130
Short name T818
Test name
Test status
Simulation time 34898380 ps
CPU time 0.62 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:25:11 PM PDT 24
Peak memory 194696 kb
Host smart-f008499a-dc9a-4a7c-a2c5-1784cdf3c1d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008967130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3008967130
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2760203016
Short name T579
Test name
Test status
Simulation time 408117314821 ps
CPU time 87.34 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:26:35 PM PDT 24
Peak memory 199812 kb
Host smart-d8eb09e9-bda5-4de5-a86e-c0e3857c4943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760203016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2760203016
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1384045302
Short name T466
Test name
Test status
Simulation time 69336772571 ps
CPU time 92.98 seconds
Started Jul 14 04:25:11 PM PDT 24
Finished Jul 14 04:26:46 PM PDT 24
Peak memory 199728 kb
Host smart-f1b96022-c1d4-4789-8dcb-034f315f1ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384045302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1384045302
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3747163433
Short name T1162
Test name
Test status
Simulation time 19230139444 ps
CPU time 67.36 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:26:18 PM PDT 24
Peak memory 199680 kb
Host smart-cecc7764-8ddb-460a-8827-528bb0813421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747163433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3747163433
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2196943425
Short name T125
Test name
Test status
Simulation time 9539561399 ps
CPU time 2.71 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:25:11 PM PDT 24
Peak memory 197016 kb
Host smart-bf17d3aa-fdaa-4fd3-9632-15006aa9edff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196943425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2196943425
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2996031364
Short name T821
Test name
Test status
Simulation time 81515580198 ps
CPU time 232.77 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:29:04 PM PDT 24
Peak memory 199732 kb
Host smart-1b8cc250-91c6-4767-b5e2-08fb9c5dab83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996031364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2996031364
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1501401652
Short name T686
Test name
Test status
Simulation time 3098741759 ps
CPU time 2.1 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:25:13 PM PDT 24
Peak memory 196508 kb
Host smart-1decc881-8adc-496f-bcd6-4bd8861d5987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501401652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1501401652
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2825317475
Short name T288
Test name
Test status
Simulation time 86540267788 ps
CPU time 122.1 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:27:10 PM PDT 24
Peak memory 198792 kb
Host smart-82e9ae82-cfe1-4cbb-b5c4-5e01a3192cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825317475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2825317475
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1773390991
Short name T1120
Test name
Test status
Simulation time 5600631112 ps
CPU time 294.23 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:30:05 PM PDT 24
Peak memory 199672 kb
Host smart-45645945-1e4b-484e-93bd-0414386e47b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773390991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1773390991
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3542364029
Short name T529
Test name
Test status
Simulation time 4968491728 ps
CPU time 37.09 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:25:45 PM PDT 24
Peak memory 197656 kb
Host smart-e483c2c6-dcf6-49d2-946e-88a67978228b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542364029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3542364029
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.514365067
Short name T283
Test name
Test status
Simulation time 61584419043 ps
CPU time 45.85 seconds
Started Jul 14 04:25:11 PM PDT 24
Finished Jul 14 04:25:58 PM PDT 24
Peak memory 199720 kb
Host smart-406b52d2-659b-456b-a0eb-e976259dd841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514365067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.514365067
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.849129298
Short name T1048
Test name
Test status
Simulation time 2616123326 ps
CPU time 1.19 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:25:12 PM PDT 24
Peak memory 195720 kb
Host smart-d72e4fc7-35ae-402e-b7c7-fc89f1d00399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849129298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.849129298
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2039988680
Short name T869
Test name
Test status
Simulation time 681165969 ps
CPU time 2.87 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:25:12 PM PDT 24
Peak memory 198672 kb
Host smart-e50c0671-e510-465d-9e51-d3359f6c8f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039988680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2039988680
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.324621521
Short name T582
Test name
Test status
Simulation time 167396424023 ps
CPU time 68.52 seconds
Started Jul 14 04:25:10 PM PDT 24
Finished Jul 14 04:26:21 PM PDT 24
Peak memory 199792 kb
Host smart-b85f95dd-1960-4c99-b3d8-0c5cf13d95e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324621521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.324621521
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3131401789
Short name T679
Test name
Test status
Simulation time 2138571746 ps
CPU time 2.22 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:25:11 PM PDT 24
Peak memory 198684 kb
Host smart-cccbe037-faec-40a2-aa83-10c341da4c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131401789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3131401789
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.635200053
Short name T522
Test name
Test status
Simulation time 90960976289 ps
CPU time 40.17 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:25:50 PM PDT 24
Peak memory 199844 kb
Host smart-2355ea8e-4bf0-4e9b-b21f-3f896988b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635200053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.635200053
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.683855371
Short name T432
Test name
Test status
Simulation time 31315652 ps
CPU time 0.54 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:25:09 PM PDT 24
Peak memory 194576 kb
Host smart-d7f760b3-09cf-4e4d-af0a-ba46fb348b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683855371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.683855371
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.4007854382
Short name T736
Test name
Test status
Simulation time 20693559931 ps
CPU time 31.49 seconds
Started Jul 14 04:25:12 PM PDT 24
Finished Jul 14 04:25:44 PM PDT 24
Peak memory 199628 kb
Host smart-107815e4-3af0-4b31-96e5-b3a218635e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007854382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4007854382
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3549382221
Short name T875
Test name
Test status
Simulation time 13594668609 ps
CPU time 5.82 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:25:17 PM PDT 24
Peak memory 199788 kb
Host smart-dcbeae0d-a7ce-45fa-909b-c69c52bd4fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549382221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3549382221
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3031582229
Short name T230
Test name
Test status
Simulation time 16619725884 ps
CPU time 6.09 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:25:17 PM PDT 24
Peak memory 199676 kb
Host smart-fce3722b-f92b-444d-89f0-8e12a4b1897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031582229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3031582229
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2380829455
Short name T788
Test name
Test status
Simulation time 249741574982 ps
CPU time 378.2 seconds
Started Jul 14 04:25:10 PM PDT 24
Finished Jul 14 04:31:30 PM PDT 24
Peak memory 198724 kb
Host smart-e89e95c6-38bf-4673-bf2d-4fc0bf224170
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380829455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2380829455
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1026427551
Short name T887
Test name
Test status
Simulation time 25709700232 ps
CPU time 170.28 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:28:01 PM PDT 24
Peak memory 199884 kb
Host smart-22b39425-1329-4cad-8e72-871993e69761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026427551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1026427551
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3038221085
Short name T795
Test name
Test status
Simulation time 1414035571 ps
CPU time 4.38 seconds
Started Jul 14 04:25:10 PM PDT 24
Finished Jul 14 04:25:16 PM PDT 24
Peak memory 199564 kb
Host smart-b458c758-c690-4002-a2ed-3cdab1ddce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038221085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3038221085
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2980636795
Short name T1142
Test name
Test status
Simulation time 66534114918 ps
CPU time 120.73 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:27:09 PM PDT 24
Peak memory 207948 kb
Host smart-3f18111f-8676-4f5f-8002-32f20b726bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980636795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2980636795
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.972366899
Short name T907
Test name
Test status
Simulation time 4052317086 ps
CPU time 105.39 seconds
Started Jul 14 04:25:12 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 199668 kb
Host smart-9b208f68-80bb-4645-854e-35abe6d9e26e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972366899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.972366899
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1153379212
Short name T985
Test name
Test status
Simulation time 5457909322 ps
CPU time 10.46 seconds
Started Jul 14 04:25:12 PM PDT 24
Finished Jul 14 04:25:23 PM PDT 24
Peak memory 199616 kb
Host smart-57d8b397-ef33-4b0b-929f-5f0c1828c47b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153379212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1153379212
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3491791207
Short name T308
Test name
Test status
Simulation time 25698006811 ps
CPU time 29.74 seconds
Started Jul 14 04:25:06 PM PDT 24
Finished Jul 14 04:25:37 PM PDT 24
Peak memory 199732 kb
Host smart-769f5432-4e04-420d-9a72-33cd2de7adbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491791207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3491791207
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1278384939
Short name T317
Test name
Test status
Simulation time 3430023130 ps
CPU time 2.04 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:25:13 PM PDT 24
Peak memory 196196 kb
Host smart-5a780286-13eb-4a98-a17e-1f8a87d876c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278384939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1278384939
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1761068824
Short name T624
Test name
Test status
Simulation time 470273552 ps
CPU time 1.29 seconds
Started Jul 14 04:25:10 PM PDT 24
Finished Jul 14 04:25:13 PM PDT 24
Peak memory 199612 kb
Host smart-963edf38-c69d-4f57-9ec8-792e9370530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761068824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1761068824
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.244842949
Short name T969
Test name
Test status
Simulation time 90346011495 ps
CPU time 92.64 seconds
Started Jul 14 04:25:11 PM PDT 24
Finished Jul 14 04:26:45 PM PDT 24
Peak memory 199708 kb
Host smart-f9022cc1-4769-4f4c-a8f0-ca9e3243f3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244842949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.244842949
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.4015422583
Short name T117
Test name
Test status
Simulation time 336368254638 ps
CPU time 904.24 seconds
Started Jul 14 04:25:10 PM PDT 24
Finished Jul 14 04:40:16 PM PDT 24
Peak memory 224508 kb
Host smart-71fa4130-b3d9-47a8-ae1f-3d622af62ffb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015422583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.4015422583
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2114944698
Short name T390
Test name
Test status
Simulation time 2039524148 ps
CPU time 2.63 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:25:14 PM PDT 24
Peak memory 199168 kb
Host smart-c812c900-1cca-4258-ad37-4983355e9a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114944698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2114944698
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2578449215
Short name T277
Test name
Test status
Simulation time 78835872557 ps
CPU time 54.18 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:26:03 PM PDT 24
Peak memory 199620 kb
Host smart-b28dbcde-03e5-49f6-b46d-b7b070a7e439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578449215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2578449215
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2748612564
Short name T627
Test name
Test status
Simulation time 20669249 ps
CPU time 0.55 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:24 PM PDT 24
Peak memory 195124 kb
Host smart-4a6d7462-65d9-4cc1-ac65-41989b74ee82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748612564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2748612564
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3985037888
Short name T1102
Test name
Test status
Simulation time 84590498746 ps
CPU time 36.31 seconds
Started Jul 14 04:25:09 PM PDT 24
Finished Jul 14 04:25:47 PM PDT 24
Peak memory 199796 kb
Host smart-914b5ad0-7c01-4f7d-8a63-644ced98f837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985037888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3985037888
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.387078484
Short name T76
Test name
Test status
Simulation time 7727909075 ps
CPU time 12.29 seconds
Started Jul 14 04:25:10 PM PDT 24
Finished Jul 14 04:25:24 PM PDT 24
Peak memory 199680 kb
Host smart-8cb22e89-3276-440b-ae74-895977937d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387078484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.387078484
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2493327831
Short name T482
Test name
Test status
Simulation time 21059335326 ps
CPU time 54.19 seconds
Started Jul 14 04:25:12 PM PDT 24
Finished Jul 14 04:26:07 PM PDT 24
Peak memory 199624 kb
Host smart-2f12a6e8-cb74-40be-9277-a61d6e2dc1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493327831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2493327831
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3711930466
Short name T473
Test name
Test status
Simulation time 31482963026 ps
CPU time 21.06 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:25:29 PM PDT 24
Peak memory 199812 kb
Host smart-d63e7d09-7a33-4b58-98f5-ba37e9726838
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711930466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3711930466
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1923984156
Short name T475
Test name
Test status
Simulation time 168153514320 ps
CPU time 145.95 seconds
Started Jul 14 04:25:18 PM PDT 24
Finished Jul 14 04:27:46 PM PDT 24
Peak memory 199708 kb
Host smart-2e45d8f5-de60-459a-bb39-37adfee03971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1923984156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1923984156
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4124280501
Short name T22
Test name
Test status
Simulation time 9632422699 ps
CPU time 16.94 seconds
Started Jul 14 04:25:23 PM PDT 24
Finished Jul 14 04:25:44 PM PDT 24
Peak memory 199588 kb
Host smart-188960c9-914a-48a1-be30-6dd502868775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124280501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4124280501
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3579500800
Short name T677
Test name
Test status
Simulation time 59316250081 ps
CPU time 85.53 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:26:36 PM PDT 24
Peak memory 200004 kb
Host smart-c85820bf-675d-4b89-9881-e9d6ea7c9ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579500800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3579500800
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.791498787
Short name T506
Test name
Test status
Simulation time 18942619240 ps
CPU time 137.73 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:27:41 PM PDT 24
Peak memory 199716 kb
Host smart-a7573b9d-7d75-4b7d-990a-6a5e3bea3811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791498787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.791498787
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3224311458
Short name T362
Test name
Test status
Simulation time 2551772803 ps
CPU time 4.29 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:25:14 PM PDT 24
Peak memory 198800 kb
Host smart-f86be0e8-5ac4-4d51-b918-3cae723dc894
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224311458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3224311458
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.271870957
Short name T138
Test name
Test status
Simulation time 47664856146 ps
CPU time 19.44 seconds
Started Jul 14 04:25:11 PM PDT 24
Finished Jul 14 04:25:32 PM PDT 24
Peak memory 199668 kb
Host smart-bd5871b6-387d-4b0f-a2da-a5d47839ed26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271870957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.271870957
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1292148933
Short name T989
Test name
Test status
Simulation time 38919675622 ps
CPU time 6.73 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:25:16 PM PDT 24
Peak memory 196164 kb
Host smart-dedfff90-8384-43b1-9ba5-08d48205dfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292148933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1292148933
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.685334033
Short name T945
Test name
Test status
Simulation time 11131688724 ps
CPU time 6.94 seconds
Started Jul 14 04:25:08 PM PDT 24
Finished Jul 14 04:25:17 PM PDT 24
Peak memory 199716 kb
Host smart-4b17e600-cda4-43f6-a3bb-035931a9badc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685334033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.685334033
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1541767774
Short name T944
Test name
Test status
Simulation time 40697542990 ps
CPU time 54.9 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:26:21 PM PDT 24
Peak memory 199576 kb
Host smart-4e6a18a4-d537-4341-99b8-5336635eec28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541767774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1541767774
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.611031826
Short name T66
Test name
Test status
Simulation time 27753799781 ps
CPU time 301.1 seconds
Started Jul 14 04:25:21 PM PDT 24
Finished Jul 14 04:30:26 PM PDT 24
Peak memory 215348 kb
Host smart-c3c967eb-5853-4602-8503-34186be16182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611031826 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.611031826
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1693760078
Short name T750
Test name
Test status
Simulation time 715888095 ps
CPU time 2.34 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:25:24 PM PDT 24
Peak memory 198116 kb
Host smart-72d720ca-068e-494c-94a3-3a93ac31300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693760078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1693760078
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2084733411
Short name T327
Test name
Test status
Simulation time 22979852564 ps
CPU time 8.44 seconds
Started Jul 14 04:25:07 PM PDT 24
Finished Jul 14 04:25:17 PM PDT 24
Peak memory 199624 kb
Host smart-e1e75225-3c99-437c-978d-b3055541fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084733411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2084733411
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3479028040
Short name T23
Test name
Test status
Simulation time 14146743 ps
CPU time 0.57 seconds
Started Jul 14 04:25:21 PM PDT 24
Finished Jul 14 04:25:27 PM PDT 24
Peak memory 194072 kb
Host smart-253e6644-8284-4609-98ab-db6a38380e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479028040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3479028040
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2748667871
Short name T391
Test name
Test status
Simulation time 28913985884 ps
CPU time 23.16 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:47 PM PDT 24
Peak memory 199652 kb
Host smart-adfa9d7b-f7e9-4e6e-a6cc-c2f2c25ce1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748667871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2748667871
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1772370947
Short name T635
Test name
Test status
Simulation time 22649045771 ps
CPU time 35.51 seconds
Started Jul 14 04:25:21 PM PDT 24
Finished Jul 14 04:26:01 PM PDT 24
Peak memory 199660 kb
Host smart-9aa1b903-a0d1-4393-9ed9-f50c0751590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772370947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1772370947
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1211166477
Short name T670
Test name
Test status
Simulation time 48270176296 ps
CPU time 35.6 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:26:02 PM PDT 24
Peak memory 199784 kb
Host smart-94f2ac35-f997-4d2f-ae77-9c3ad1a4714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211166477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1211166477
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3109578787
Short name T339
Test name
Test status
Simulation time 16140915365 ps
CPU time 6.17 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:31 PM PDT 24
Peak memory 197688 kb
Host smart-b87e57b1-8401-4c77-9ac5-99539c9e9b05
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109578787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3109578787
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2546624769
Short name T538
Test name
Test status
Simulation time 104898030137 ps
CPU time 574.63 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:34:55 PM PDT 24
Peak memory 199776 kb
Host smart-9ec421b2-6f9c-47fe-8e11-8b9c129a2bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546624769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2546624769
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2999592011
Short name T568
Test name
Test status
Simulation time 6897761297 ps
CPU time 14.76 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:25:36 PM PDT 24
Peak memory 199092 kb
Host smart-0c60e7bb-bd6c-431b-a977-126a27a20de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999592011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2999592011
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3601713917
Short name T744
Test name
Test status
Simulation time 283777569075 ps
CPU time 132.85 seconds
Started Jul 14 04:25:24 PM PDT 24
Finished Jul 14 04:27:42 PM PDT 24
Peak memory 207756 kb
Host smart-5c8f48dd-071e-4958-b3c8-54233c565f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601713917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3601713917
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3085632157
Short name T654
Test name
Test status
Simulation time 18662178930 ps
CPU time 891.87 seconds
Started Jul 14 04:25:17 PM PDT 24
Finished Jul 14 04:40:10 PM PDT 24
Peak memory 199688 kb
Host smart-1f15383e-b6fb-4634-862e-f36ee8765291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085632157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3085632157
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2523758843
Short name T712
Test name
Test status
Simulation time 7024566689 ps
CPU time 63.15 seconds
Started Jul 14 04:25:23 PM PDT 24
Finished Jul 14 04:26:31 PM PDT 24
Peak memory 198672 kb
Host smart-8f02bf82-f49b-4556-958b-1605ba5f4558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523758843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2523758843
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.955550571
Short name T267
Test name
Test status
Simulation time 82412763118 ps
CPU time 184.23 seconds
Started Jul 14 04:25:24 PM PDT 24
Finished Jul 14 04:28:33 PM PDT 24
Peak memory 199832 kb
Host smart-b2c65dfb-db92-4fd2-ab60-a3b3da88b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955550571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.955550571
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1412725124
Short name T782
Test name
Test status
Simulation time 45963990049 ps
CPU time 77.56 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:26:44 PM PDT 24
Peak memory 195656 kb
Host smart-befe3a83-ee41-4a9d-b4ee-53e09df04434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412725124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1412725124
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1594490198
Short name T37
Test name
Test status
Simulation time 900165921 ps
CPU time 2.62 seconds
Started Jul 14 04:25:18 PM PDT 24
Finished Jul 14 04:25:23 PM PDT 24
Peak memory 198668 kb
Host smart-488e301c-5b02-4f8c-89e1-57d54baa20a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594490198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1594490198
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2264794721
Short name T919
Test name
Test status
Simulation time 42991866133 ps
CPU time 27.46 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:25:48 PM PDT 24
Peak memory 199792 kb
Host smart-343b44ce-0467-42f3-b133-0fb8918a30cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264794721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2264794721
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2300184562
Short name T165
Test name
Test status
Simulation time 303668005982 ps
CPU time 669.27 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:36:32 PM PDT 24
Peak memory 224696 kb
Host smart-771358d1-cf69-45c2-9542-cef971b65c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300184562 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2300184562
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2395959475
Short name T914
Test name
Test status
Simulation time 6496175948 ps
CPU time 18.98 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:43 PM PDT 24
Peak memory 199632 kb
Host smart-4dcee0b8-2f15-4f72-9591-bdbe5b61b7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395959475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2395959475
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3020562134
Short name T1027
Test name
Test status
Simulation time 60252005271 ps
CPU time 28.78 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:25:55 PM PDT 24
Peak memory 199604 kb
Host smart-efd84b29-c400-4ca4-846c-fabc0de8ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020562134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3020562134
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1840195704
Short name T1043
Test name
Test status
Simulation time 10937761 ps
CPU time 0.56 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:25 PM PDT 24
Peak memory 195208 kb
Host smart-9fd194ca-b433-4337-8f72-2e6460ef68ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840195704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1840195704
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3149036358
Short name T767
Test name
Test status
Simulation time 66509189792 ps
CPU time 99.63 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:27:01 PM PDT 24
Peak memory 199748 kb
Host smart-874066f5-d8bf-490f-9110-305126eea1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149036358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3149036358
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.683320003
Short name T494
Test name
Test status
Simulation time 209155623349 ps
CPU time 275.47 seconds
Started Jul 14 04:25:18 PM PDT 24
Finished Jul 14 04:29:55 PM PDT 24
Peak memory 199684 kb
Host smart-b464805f-65bd-4a00-99e8-d6c1452560a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683320003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.683320003
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1247536173
Short name T192
Test name
Test status
Simulation time 31106139012 ps
CPU time 60.25 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:26:27 PM PDT 24
Peak memory 199816 kb
Host smart-f73b6052-a600-44cf-b1b8-b4160bd8a2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247536173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1247536173
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3391336880
Short name T315
Test name
Test status
Simulation time 50264707817 ps
CPU time 49.32 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:26:17 PM PDT 24
Peak memory 199720 kb
Host smart-26dccd39-9e87-4196-b3cb-93e80728aa5b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391336880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3391336880
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2796795836
Short name T623
Test name
Test status
Simulation time 81123933186 ps
CPU time 396.29 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:32:01 PM PDT 24
Peak memory 199724 kb
Host smart-c03cae29-b4a5-40c0-b626-80f877f17b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796795836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2796795836
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3361049496
Short name T946
Test name
Test status
Simulation time 5853349621 ps
CPU time 8.43 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:32 PM PDT 24
Peak memory 199788 kb
Host smart-c9d8a242-4dd2-47ee-81b6-02a5e9b79a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361049496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3361049496
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2037434072
Short name T41
Test name
Test status
Simulation time 86328900321 ps
CPU time 68.21 seconds
Started Jul 14 04:25:21 PM PDT 24
Finished Jul 14 04:26:34 PM PDT 24
Peak memory 200052 kb
Host smart-29237407-103f-492a-8ca4-6786ea7894ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037434072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2037434072
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.660335280
Short name T456
Test name
Test status
Simulation time 23263539156 ps
CPU time 261.13 seconds
Started Jul 14 04:25:24 PM PDT 24
Finished Jul 14 04:29:50 PM PDT 24
Peak memory 199748 kb
Host smart-22b0dd65-73bc-4731-ac99-80d9122b6b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660335280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.660335280
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.26390910
Short name T593
Test name
Test status
Simulation time 4964279405 ps
CPU time 36.68 seconds
Started Jul 14 04:25:18 PM PDT 24
Finished Jul 14 04:25:56 PM PDT 24
Peak memory 198620 kb
Host smart-1530b738-65f7-4184-8041-0d9eed0d6b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26390910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.26390910
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3770665280
Short name T590
Test name
Test status
Simulation time 40819259909 ps
CPU time 16.86 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:25:43 PM PDT 24
Peak memory 199748 kb
Host smart-5420a9ac-046c-4acd-948d-5b9a618b01af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770665280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3770665280
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.231661247
Short name T770
Test name
Test status
Simulation time 33239589720 ps
CPU time 4.55 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:29 PM PDT 24
Peak memory 195708 kb
Host smart-b0c296e1-4599-467e-9efc-071e07d0b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231661247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.231661247
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2699749031
Short name T643
Test name
Test status
Simulation time 504762549 ps
CPU time 1.53 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:25:23 PM PDT 24
Peak memory 198444 kb
Host smart-3cbf3de5-77a2-45ca-b8ea-f7aeac02f63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699749031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2699749031
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1603315474
Short name T309
Test name
Test status
Simulation time 252502722358 ps
CPU time 558.8 seconds
Started Jul 14 04:25:23 PM PDT 24
Finished Jul 14 04:34:46 PM PDT 24
Peak memory 199724 kb
Host smart-b576bc8e-d8d8-4acf-8dc7-a1686e428ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603315474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1603315474
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2279621847
Short name T318
Test name
Test status
Simulation time 340974192685 ps
CPU time 895.88 seconds
Started Jul 14 04:25:21 PM PDT 24
Finished Jul 14 04:40:22 PM PDT 24
Peak memory 229412 kb
Host smart-62f4d1af-b9b7-4bf6-87bc-041947e1efef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279621847 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2279621847
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1160755857
Short name T556
Test name
Test status
Simulation time 1201689431 ps
CPU time 4.23 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:27 PM PDT 24
Peak memory 198780 kb
Host smart-406a9a23-7a4d-4228-9e04-67c4f0024c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160755857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1160755857
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1441640369
Short name T387
Test name
Test status
Simulation time 25124661630 ps
CPU time 36.73 seconds
Started Jul 14 04:25:23 PM PDT 24
Finished Jul 14 04:26:04 PM PDT 24
Peak memory 199280 kb
Host smart-80d3d056-bb57-4534-94cc-b0c42863a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441640369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1441640369
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3499648851
Short name T955
Test name
Test status
Simulation time 10671707 ps
CPU time 0.56 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:25:22 PM PDT 24
Peak memory 195140 kb
Host smart-ed54a767-f164-457e-aa73-14b465be014f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499648851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3499648851
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3940868211
Short name T474
Test name
Test status
Simulation time 158559500324 ps
CPU time 38.82 seconds
Started Jul 14 04:25:21 PM PDT 24
Finished Jul 14 04:26:05 PM PDT 24
Peak memory 199728 kb
Host smart-b8414040-0b57-4335-b687-51e23519c4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940868211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3940868211
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3292327077
Short name T819
Test name
Test status
Simulation time 40404897232 ps
CPU time 14.77 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:38 PM PDT 24
Peak memory 199172 kb
Host smart-080cf515-e34e-4730-b3e7-30d5eecd6e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292327077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3292327077
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1663410282
Short name T1024
Test name
Test status
Simulation time 31458463082 ps
CPU time 55.02 seconds
Started Jul 14 04:25:23 PM PDT 24
Finished Jul 14 04:26:23 PM PDT 24
Peak memory 199740 kb
Host smart-c50897ae-1d87-4f55-a2f9-56c95ef28c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663410282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1663410282
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3204110386
Short name T129
Test name
Test status
Simulation time 20028746254 ps
CPU time 10.03 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:33 PM PDT 24
Peak memory 199652 kb
Host smart-1133d4fd-2404-43c2-9dc6-c0b3261f82eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204110386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3204110386
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2744824307
Short name T518
Test name
Test status
Simulation time 82532671574 ps
CPU time 451.89 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:32:52 PM PDT 24
Peak memory 199736 kb
Host smart-17884792-41a9-4a3a-ba2f-b95b61610e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744824307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2744824307
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1853736929
Short name T1137
Test name
Test status
Simulation time 7218227443 ps
CPU time 12.8 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:38 PM PDT 24
Peak memory 198808 kb
Host smart-c0bfc127-5f0c-4934-9c56-4c276ac23c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853736929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1853736929
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.724257763
Short name T1097
Test name
Test status
Simulation time 85251112363 ps
CPU time 134.08 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:27:36 PM PDT 24
Peak memory 208152 kb
Host smart-e26ea1fd-8a72-46b9-bebf-c48cf5ccf3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724257763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.724257763
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4216894542
Short name T634
Test name
Test status
Simulation time 6207307141 ps
CPU time 183.88 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:28:30 PM PDT 24
Peak memory 199764 kb
Host smart-11236e87-524b-40ab-96bc-d5915ae267da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216894542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4216894542
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.202796351
Short name T966
Test name
Test status
Simulation time 4792177447 ps
CPU time 21.63 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:25:46 PM PDT 24
Peak memory 199080 kb
Host smart-cc934660-a079-41dd-add2-d169fdb67dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202796351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.202796351
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1443710166
Short name T1158
Test name
Test status
Simulation time 134264015117 ps
CPU time 165.15 seconds
Started Jul 14 04:25:24 PM PDT 24
Finished Jul 14 04:28:14 PM PDT 24
Peak memory 199816 kb
Host smart-26fc9bbe-45ef-45fc-80c4-e423791a4139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443710166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1443710166
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1797180981
Short name T689
Test name
Test status
Simulation time 36111556800 ps
CPU time 47.02 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:26:09 PM PDT 24
Peak memory 196120 kb
Host smart-766649d5-bcc9-48a1-a644-d78e3e1cb990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797180981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1797180981
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1798428073
Short name T574
Test name
Test status
Simulation time 523043656 ps
CPU time 1.31 seconds
Started Jul 14 04:25:21 PM PDT 24
Finished Jul 14 04:25:27 PM PDT 24
Peak memory 197816 kb
Host smart-6b454012-8b05-4bf2-9bd2-c06b8a01018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798428073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1798428073
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.4237635602
Short name T215
Test name
Test status
Simulation time 52133495677 ps
CPU time 32.51 seconds
Started Jul 14 04:25:24 PM PDT 24
Finished Jul 14 04:26:01 PM PDT 24
Peak memory 199772 kb
Host smart-832630e7-477b-4788-b08b-f496bca0026e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237635602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.4237635602
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3063243407
Short name T1138
Test name
Test status
Simulation time 343919053921 ps
CPU time 1149.06 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:44:32 PM PDT 24
Peak memory 232908 kb
Host smart-288e4320-6128-4247-a9a9-2fbecc77e5d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063243407 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3063243407
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1719769958
Short name T601
Test name
Test status
Simulation time 911710472 ps
CPU time 2.2 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:25:24 PM PDT 24
Peak memory 197972 kb
Host smart-821036bb-4f03-4ed8-9a8b-af6415e10d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719769958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1719769958
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1545929793
Short name T693
Test name
Test status
Simulation time 47163986225 ps
CPU time 69.12 seconds
Started Jul 14 04:25:20 PM PDT 24
Finished Jul 14 04:26:33 PM PDT 24
Peak memory 199828 kb
Host smart-36ecbfaf-294c-4491-8376-a17f840657f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545929793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1545929793
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3619458654
Short name T827
Test name
Test status
Simulation time 18535399 ps
CPU time 0.54 seconds
Started Jul 14 04:25:30 PM PDT 24
Finished Jul 14 04:25:33 PM PDT 24
Peak memory 194564 kb
Host smart-9f6a53b4-dfcb-4810-8f66-19df1d02a3a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619458654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3619458654
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1518523789
Short name T857
Test name
Test status
Simulation time 40921195046 ps
CPU time 31.85 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:25:59 PM PDT 24
Peak memory 199632 kb
Host smart-79580e20-9870-4ca0-98cb-4ee757b3eae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518523789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1518523789
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.4033527872
Short name T1167
Test name
Test status
Simulation time 38638371874 ps
CPU time 58.53 seconds
Started Jul 14 04:25:23 PM PDT 24
Finished Jul 14 04:26:26 PM PDT 24
Peak memory 199676 kb
Host smart-8279388c-85e2-47be-a82c-f463ecbd06ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033527872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.4033527872
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3124776380
Short name T435
Test name
Test status
Simulation time 53035092112 ps
CPU time 37.44 seconds
Started Jul 14 04:25:22 PM PDT 24
Finished Jul 14 04:26:04 PM PDT 24
Peak memory 199740 kb
Host smart-d4dd2d56-dea9-4610-92aa-58a3865d671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124776380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3124776380
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2049548902
Short name T734
Test name
Test status
Simulation time 52439255370 ps
CPU time 12.86 seconds
Started Jul 14 04:25:23 PM PDT 24
Finished Jul 14 04:25:40 PM PDT 24
Peak memory 199464 kb
Host smart-d17eb905-13e7-4b9b-8293-be96384c2ce5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049548902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2049548902
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1476744407
Short name T647
Test name
Test status
Simulation time 35542629662 ps
CPU time 126.67 seconds
Started Jul 14 04:25:34 PM PDT 24
Finished Jul 14 04:27:42 PM PDT 24
Peak memory 199576 kb
Host smart-4b4bb12a-0526-4ecc-b7df-afbab27b69ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476744407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1476744407
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.659020344
Short name T405
Test name
Test status
Simulation time 2189651509 ps
CPU time 1.65 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:25:34 PM PDT 24
Peak memory 196804 kb
Host smart-3c6e3731-84ae-42c6-a3b5-e427480925e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659020344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.659020344
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3154442546
Short name T1092
Test name
Test status
Simulation time 58431700816 ps
CPU time 86.98 seconds
Started Jul 14 04:25:39 PM PDT 24
Finished Jul 14 04:27:07 PM PDT 24
Peak memory 198280 kb
Host smart-e17d0a25-ffaa-41de-891f-d96ee2a31b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154442546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3154442546
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3771563125
Short name T1172
Test name
Test status
Simulation time 17824646184 ps
CPU time 935.38 seconds
Started Jul 14 04:25:31 PM PDT 24
Finished Jul 14 04:41:08 PM PDT 24
Peak memory 200108 kb
Host smart-0b2429bf-85fc-40b5-8149-56b67f4b35a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771563125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3771563125
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2683879017
Short name T599
Test name
Test status
Simulation time 6405407125 ps
CPU time 58.54 seconds
Started Jul 14 04:25:23 PM PDT 24
Finished Jul 14 04:26:26 PM PDT 24
Peak memory 198940 kb
Host smart-4aa18621-7e93-4918-bcde-117cbdb47d67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683879017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2683879017
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.957183404
Short name T1030
Test name
Test status
Simulation time 91021232034 ps
CPU time 13.17 seconds
Started Jul 14 04:25:27 PM PDT 24
Finished Jul 14 04:25:43 PM PDT 24
Peak memory 199792 kb
Host smart-5183b13c-39fe-4bed-9df1-ef187c63a8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957183404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.957183404
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2799886333
Short name T560
Test name
Test status
Simulation time 5109674153 ps
CPU time 8.01 seconds
Started Jul 14 04:25:27 PM PDT 24
Finished Jul 14 04:25:38 PM PDT 24
Peak memory 195884 kb
Host smart-2e30a1a4-b6ce-46ae-b160-7059275fb037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799886333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2799886333
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.355108240
Short name T9
Test name
Test status
Simulation time 454097852 ps
CPU time 1.45 seconds
Started Jul 14 04:25:19 PM PDT 24
Finished Jul 14 04:25:24 PM PDT 24
Peak memory 198248 kb
Host smart-d9e512b8-c1e2-4a13-ac45-86e9b20a81be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355108240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.355108240
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.927822377
Short name T646
Test name
Test status
Simulation time 55874331906 ps
CPU time 157.07 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:28:08 PM PDT 24
Peak memory 216520 kb
Host smart-2941d982-fece-46f9-861d-03af0fb6b7d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927822377 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.927822377
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.4034421200
Short name T389
Test name
Test status
Simulation time 2226705494 ps
CPU time 2.16 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:25:41 PM PDT 24
Peak memory 198456 kb
Host smart-b89057ab-d08b-4d9a-938e-8684c7453758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034421200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.4034421200
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2421311993
Short name T659
Test name
Test status
Simulation time 13400551320 ps
CPU time 25.59 seconds
Started Jul 14 04:25:21 PM PDT 24
Finished Jul 14 04:25:52 PM PDT 24
Peak memory 199652 kb
Host smart-edce08f7-848d-4cf0-af91-a92d81a9b9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421311993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2421311993
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.663016625
Short name T462
Test name
Test status
Simulation time 47053144 ps
CPU time 0.56 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:25:37 PM PDT 24
Peak memory 195360 kb
Host smart-079e898a-ae01-4e64-ad36-5279db937933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663016625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.663016625
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1444291520
Short name T942
Test name
Test status
Simulation time 49567111962 ps
CPU time 37.83 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:26:09 PM PDT 24
Peak memory 199688 kb
Host smart-cde67d51-b50a-44ba-a202-0c04e1db9db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444291520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1444291520
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1315097975
Short name T394
Test name
Test status
Simulation time 84770716538 ps
CPU time 123.35 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:27:42 PM PDT 24
Peak memory 199820 kb
Host smart-90336884-b7d0-43bb-b189-f84da1dbbfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315097975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1315097975
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.1479347153
Short name T1144
Test name
Test status
Simulation time 159629304927 ps
CPU time 100.63 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:27:12 PM PDT 24
Peak memory 199696 kb
Host smart-741496fa-ca4f-40ef-b0c5-e38c0c7a1697
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479347153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1479347153
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.545446017
Short name T804
Test name
Test status
Simulation time 222699077573 ps
CPU time 265.96 seconds
Started Jul 14 04:25:34 PM PDT 24
Finished Jul 14 04:30:02 PM PDT 24
Peak memory 199612 kb
Host smart-3375b3d6-5405-4951-9c1c-ebe0d3a6a2b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=545446017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.545446017
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3889256252
Short name T360
Test name
Test status
Simulation time 4714079763 ps
CPU time 4.11 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:25:36 PM PDT 24
Peak memory 199440 kb
Host smart-89116b97-4a47-4876-b18e-44960f57e081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889256252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3889256252
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3419639731
Short name T776
Test name
Test status
Simulation time 19053320450 ps
CPU time 31.68 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:26:11 PM PDT 24
Peak memory 199932 kb
Host smart-e3f63243-0de7-443a-936d-0f846d51e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419639731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3419639731
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1999319398
Short name T641
Test name
Test status
Simulation time 7589128252 ps
CPU time 401.3 seconds
Started Jul 14 04:25:27 PM PDT 24
Finished Jul 14 04:32:12 PM PDT 24
Peak memory 199872 kb
Host smart-da4f72dc-4adc-487f-a2e7-47e0d577a277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1999319398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1999319398
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3001169759
Short name T799
Test name
Test status
Simulation time 4223780998 ps
CPU time 15.57 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:25:52 PM PDT 24
Peak memory 198372 kb
Host smart-5cb05851-d280-4031-991f-f70d00384f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001169759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3001169759
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3171474646
Short name T59
Test name
Test status
Simulation time 24851309027 ps
CPU time 42.32 seconds
Started Jul 14 04:25:26 PM PDT 24
Finished Jul 14 04:26:12 PM PDT 24
Peak memory 199680 kb
Host smart-49114db0-61f1-49c9-a637-ca1810d3dfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171474646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3171474646
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.304726146
Short name T1046
Test name
Test status
Simulation time 5985785528 ps
CPU time 5.26 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:25:37 PM PDT 24
Peak memory 195952 kb
Host smart-bf1e78d1-5d21-4030-92cb-3e12af61deed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304726146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.304726146
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3829274424
Short name T738
Test name
Test status
Simulation time 683790791 ps
CPU time 2.21 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:25:33 PM PDT 24
Peak memory 199492 kb
Host smart-712dd8ef-303f-4a7e-a8cd-cca9bba6e7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829274424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3829274424
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1922735415
Short name T739
Test name
Test status
Simulation time 8866047791 ps
CPU time 6.65 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:25:39 PM PDT 24
Peak memory 199736 kb
Host smart-cca7dbfb-2d45-4a5a-80ca-3ce91153b0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922735415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1922735415
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2487798273
Short name T64
Test name
Test status
Simulation time 194362283116 ps
CPU time 180.9 seconds
Started Jul 14 04:25:33 PM PDT 24
Finished Jul 14 04:28:35 PM PDT 24
Peak memory 199668 kb
Host smart-ed486414-2fba-46c4-9db1-f36f0d1a6a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487798273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2487798273
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3919463172
Short name T448
Test name
Test status
Simulation time 42401227 ps
CPU time 0.59 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:35 PM PDT 24
Peak memory 194648 kb
Host smart-d09d11f5-4f36-4954-8ca5-565939fadd8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919463172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3919463172
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2472992358
Short name T961
Test name
Test status
Simulation time 26477934041 ps
CPU time 19.36 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:54 PM PDT 24
Peak memory 199760 kb
Host smart-e71efa6f-ef51-4c49-9ecc-f64b8f2055ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472992358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2472992358
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4226559995
Short name T564
Test name
Test status
Simulation time 251601579110 ps
CPU time 100.06 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:25:25 PM PDT 24
Peak memory 199592 kb
Host smart-4d66b7ef-80df-4810-84e6-cccd363e64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226559995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4226559995
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3916749130
Short name T836
Test name
Test status
Simulation time 55951431025 ps
CPU time 26.84 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:24:09 PM PDT 24
Peak memory 199740 kb
Host smart-7edf712c-c509-49a4-835c-e78cc4a77ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916749130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3916749130
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.56545584
Short name T637
Test name
Test status
Simulation time 13557428349 ps
CPU time 24.85 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:24:01 PM PDT 24
Peak memory 199744 kb
Host smart-4846f6ab-303e-4d4f-9c7e-2953703c31ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56545584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.56545584
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.993869259
Short name T537
Test name
Test status
Simulation time 84506365597 ps
CPU time 383.05 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:30:07 PM PDT 24
Peak memory 199692 kb
Host smart-4eb6e90c-340f-4f35-a42d-477dd6678ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993869259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.993869259
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.415072978
Short name T964
Test name
Test status
Simulation time 1525632012 ps
CPU time 1.71 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:23:49 PM PDT 24
Peak memory 198276 kb
Host smart-5380fc1f-a79f-4fd9-9715-816884423ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415072978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.415072978
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.744148536
Short name T662
Test name
Test status
Simulation time 310353354852 ps
CPU time 72.62 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:24:49 PM PDT 24
Peak memory 199968 kb
Host smart-e9138347-d62c-47c2-b03f-36943aa4cd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744148536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.744148536
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1914720861
Short name T1174
Test name
Test status
Simulation time 34226635127 ps
CPU time 209 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:27:05 PM PDT 24
Peak memory 199764 kb
Host smart-6ec8f1b8-2649-44fe-8fec-f1039a25848e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914720861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1914720861
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1460333826
Short name T400
Test name
Test status
Simulation time 2767414068 ps
CPU time 18.56 seconds
Started Jul 14 04:23:34 PM PDT 24
Finished Jul 14 04:23:55 PM PDT 24
Peak memory 197840 kb
Host smart-c82b5129-8859-4c21-bb48-6b6bd91280b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1460333826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1460333826
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3732026807
Short name T3
Test name
Test status
Simulation time 32647127297 ps
CPU time 51.28 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:24:25 PM PDT 24
Peak memory 199744 kb
Host smart-7e1651b2-afc3-4e37-ac43-8e78a3d572bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732026807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3732026807
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2862107950
Short name T761
Test name
Test status
Simulation time 4939049361 ps
CPU time 1.39 seconds
Started Jul 14 04:23:44 PM PDT 24
Finished Jul 14 04:23:47 PM PDT 24
Peak memory 196280 kb
Host smart-f1f06380-0107-4a2e-b878-dd36d74c0283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862107950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2862107950
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.591350156
Short name T28
Test name
Test status
Simulation time 179683889 ps
CPU time 0.82 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 218132 kb
Host smart-9584b865-fbe1-4a0f-b936-a366c63da62f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591350156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.591350156
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4079363365
Short name T846
Test name
Test status
Simulation time 266670273 ps
CPU time 1.33 seconds
Started Jul 14 04:23:35 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 198016 kb
Host smart-963e2cd2-b9a4-4f8b-967d-2901bf6b2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079363365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4079363365
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.4197118055
Short name T547
Test name
Test status
Simulation time 545337016628 ps
CPU time 103.42 seconds
Started Jul 14 04:23:36 PM PDT 24
Finished Jul 14 04:25:21 PM PDT 24
Peak memory 199792 kb
Host smart-7b68f0ef-db0a-4b5f-a25a-b621e4cdb761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197118055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4197118055
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.375053526
Short name T349
Test name
Test status
Simulation time 232195060389 ps
CPU time 1340.24 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:45:59 PM PDT 24
Peak memory 216464 kb
Host smart-e19dc4ec-dc07-4709-ab61-1d08922e8ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375053526 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.375053526
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3785956071
Short name T1022
Test name
Test status
Simulation time 8755084030 ps
CPU time 8.55 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:23:44 PM PDT 24
Peak memory 198848 kb
Host smart-e8169b86-fb55-40eb-8211-088f58b6d0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785956071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3785956071
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.75667289
Short name T44
Test name
Test status
Simulation time 183929738616 ps
CPU time 15.48 seconds
Started Jul 14 04:23:40 PM PDT 24
Finished Jul 14 04:23:56 PM PDT 24
Peak memory 199756 kb
Host smart-da5977f5-9c4a-441b-96d1-27c26218c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75667289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.75667289
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2131191919
Short name T24
Test name
Test status
Simulation time 13896931 ps
CPU time 0.54 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:25:39 PM PDT 24
Peak memory 194964 kb
Host smart-a029e497-617d-46a1-8b8c-2fa440d87a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131191919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2131191919
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2265410069
Short name T705
Test name
Test status
Simulation time 76195955452 ps
CPU time 51.88 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:26:24 PM PDT 24
Peak memory 199848 kb
Host smart-00a64ff4-885b-4c68-87b9-c2ab5dabf89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265410069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2265410069
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2077831925
Short name T1012
Test name
Test status
Simulation time 65241052926 ps
CPU time 22.66 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:25:53 PM PDT 24
Peak memory 199704 kb
Host smart-5fea8179-e0f7-49d3-8520-85925e495b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077831925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2077831925
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2756842504
Short name T680
Test name
Test status
Simulation time 37797773502 ps
CPU time 30.48 seconds
Started Jul 14 04:25:26 PM PDT 24
Finished Jul 14 04:26:00 PM PDT 24
Peak memory 199768 kb
Host smart-c34eb464-9f4f-4271-bf0d-1de7d4843e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756842504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2756842504
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2530698891
Short name T423
Test name
Test status
Simulation time 8805414289 ps
CPU time 3.93 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:25:41 PM PDT 24
Peak memory 196516 kb
Host smart-96ac4084-b254-4049-ab1e-5a88b8542815
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530698891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2530698891
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_loopback.3500667192
Short name T382
Test name
Test status
Simulation time 3673341837 ps
CPU time 6.43 seconds
Started Jul 14 04:25:25 PM PDT 24
Finished Jul 14 04:25:35 PM PDT 24
Peak memory 198380 kb
Host smart-c85f768a-acb3-4cb9-b75f-7bda600a81f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500667192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3500667192
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.160524384
Short name T619
Test name
Test status
Simulation time 179356766559 ps
CPU time 16.55 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:25:47 PM PDT 24
Peak memory 199716 kb
Host smart-48c8155c-afe7-4f89-91ef-6583f078758a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160524384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.160524384
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.13652193
Short name T302
Test name
Test status
Simulation time 17557985488 ps
CPU time 976.78 seconds
Started Jul 14 04:25:39 PM PDT 24
Finished Jul 14 04:41:57 PM PDT 24
Peak memory 199744 kb
Host smart-9beb4be1-82f8-4bb3-a2e8-a4a74075c143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13652193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.13652193
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1978377692
Short name T716
Test name
Test status
Simulation time 7014954632 ps
CPU time 15.19 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:25:46 PM PDT 24
Peak memory 198740 kb
Host smart-0b354939-6164-4b15-bd19-aa540a063f42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978377692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1978377692
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3016134901
Short name T1163
Test name
Test status
Simulation time 137574484738 ps
CPU time 52.85 seconds
Started Jul 14 04:25:31 PM PDT 24
Finished Jul 14 04:26:26 PM PDT 24
Peak memory 199648 kb
Host smart-707c4a6c-b0d9-4f51-97bf-3d08910cd5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016134901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3016134901
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1889330720
Short name T479
Test name
Test status
Simulation time 1776521767 ps
CPU time 1.39 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:25:32 PM PDT 24
Peak memory 195332 kb
Host smart-4746f491-dc75-4c26-b0dc-2998769966f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889330720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1889330720
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1014937490
Short name T319
Test name
Test status
Simulation time 5756078131 ps
CPU time 12.7 seconds
Started Jul 14 04:25:26 PM PDT 24
Finished Jul 14 04:25:42 PM PDT 24
Peak memory 199696 kb
Host smart-9028843b-3919-4375-bc25-e0a6a8593383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014937490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1014937490
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2037811623
Short name T108
Test name
Test status
Simulation time 86914083919 ps
CPU time 140.82 seconds
Started Jul 14 04:25:31 PM PDT 24
Finished Jul 14 04:27:54 PM PDT 24
Peak memory 199668 kb
Host smart-89840a5e-b84a-440f-a60f-0fd6340322a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037811623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2037811623
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1232064594
Short name T604
Test name
Test status
Simulation time 799909640 ps
CPU time 3.17 seconds
Started Jul 14 04:25:31 PM PDT 24
Finished Jul 14 04:25:36 PM PDT 24
Peak memory 199432 kb
Host smart-724bb5ad-8261-44a8-ae9e-85aeb6fdd3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232064594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1232064594
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.301360379
Short name T340
Test name
Test status
Simulation time 73825309498 ps
CPU time 23.06 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:25:59 PM PDT 24
Peak memory 199452 kb
Host smart-0cb0d813-d770-44e1-9180-c69acd432e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301360379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.301360379
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1277578158
Short name T785
Test name
Test status
Simulation time 15376532 ps
CPU time 0.55 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:25:40 PM PDT 24
Peak memory 195060 kb
Host smart-7336acf6-1bfa-4a46-9b3f-e40c6bf2f955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277578158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1277578158
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2634214163
Short name T155
Test name
Test status
Simulation time 88791311192 ps
CPU time 34.28 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:26:06 PM PDT 24
Peak memory 199840 kb
Host smart-dd1f0dca-b772-46d2-b6e8-21d0aceea8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634214163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2634214163
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3432635599
Short name T488
Test name
Test status
Simulation time 292975887064 ps
CPU time 53.3 seconds
Started Jul 14 04:25:30 PM PDT 24
Finished Jul 14 04:26:26 PM PDT 24
Peak memory 199728 kb
Host smart-99b9e6f5-8bbf-4c0b-b118-dc576ab75e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432635599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3432635599
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3616706215
Short name T223
Test name
Test status
Simulation time 82718366625 ps
CPU time 251.22 seconds
Started Jul 14 04:25:31 PM PDT 24
Finished Jul 14 04:29:44 PM PDT 24
Peak memory 200164 kb
Host smart-e0f99064-d5fb-4197-9828-225baa3b97d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616706215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3616706215
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3129530611
Short name T1006
Test name
Test status
Simulation time 6512157243 ps
CPU time 13.06 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:25:51 PM PDT 24
Peak memory 199784 kb
Host smart-e4789965-e711-4173-8052-55475b18c306
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129530611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3129530611
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.483760770
Short name T43
Test name
Test status
Simulation time 119835235946 ps
CPU time 384.59 seconds
Started Jul 14 04:25:36 PM PDT 24
Finished Jul 14 04:32:03 PM PDT 24
Peak memory 199744 kb
Host smart-5c7b1191-d3a1-49b5-baf5-1ad4d9fa0800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483760770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.483760770
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1715299201
Short name T472
Test name
Test status
Simulation time 6133912719 ps
CPU time 10.4 seconds
Started Jul 14 04:25:39 PM PDT 24
Finished Jul 14 04:25:51 PM PDT 24
Peak memory 198372 kb
Host smart-bf231a2c-ee43-4277-b53a-9fc5b327dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715299201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1715299201
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.4208083938
Short name T976
Test name
Test status
Simulation time 141884983371 ps
CPU time 81.98 seconds
Started Jul 14 04:25:36 PM PDT 24
Finished Jul 14 04:27:00 PM PDT 24
Peak memory 199604 kb
Host smart-f80bb683-20bf-4a37-9a72-62d5d8bbf7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208083938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.4208083938
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2977954561
Short name T837
Test name
Test status
Simulation time 9997907175 ps
CPU time 107.07 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:27:27 PM PDT 24
Peak memory 199804 kb
Host smart-383442cd-8b86-4269-8310-cae4200430f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977954561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2977954561
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.64211036
Short name T429
Test name
Test status
Simulation time 2960940467 ps
CPU time 5.54 seconds
Started Jul 14 04:25:28 PM PDT 24
Finished Jul 14 04:25:36 PM PDT 24
Peak memory 197900 kb
Host smart-41af5c05-355c-4293-8419-d1e83a8f2553
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64211036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.64211036
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2186006175
Short name T483
Test name
Test status
Simulation time 109676140038 ps
CPU time 81.21 seconds
Started Jul 14 04:25:34 PM PDT 24
Finished Jul 14 04:26:57 PM PDT 24
Peak memory 199380 kb
Host smart-49e00808-770f-4bac-8829-e485fe7d4735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186006175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2186006175
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1506710462
Short name T366
Test name
Test status
Simulation time 2694269613 ps
CPU time 4.13 seconds
Started Jul 14 04:25:29 PM PDT 24
Finished Jul 14 04:25:36 PM PDT 24
Peak memory 196252 kb
Host smart-34e2e069-2f9e-495a-8e57-2bf8d41969ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506710462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1506710462
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.210431621
Short name T305
Test name
Test status
Simulation time 504305390 ps
CPU time 1.25 seconds
Started Jul 14 04:25:31 PM PDT 24
Finished Jul 14 04:25:34 PM PDT 24
Peak memory 198384 kb
Host smart-e09a7a66-a856-43ca-b685-830cac974e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210431621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.210431621
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.4290269597
Short name T1016
Test name
Test status
Simulation time 39993461193 ps
CPU time 453.67 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:33:14 PM PDT 24
Peak memory 215828 kb
Host smart-28800d1b-67d0-4fc6-9859-2c5b2fb8e4ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290269597 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.4290269597
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3184237666
Short name T935
Test name
Test status
Simulation time 882593425 ps
CPU time 3.26 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:25:42 PM PDT 24
Peak memory 198424 kb
Host smart-3fc2e95e-bd74-474b-95c8-c643366b43da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184237666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3184237666
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1353938658
Short name T652
Test name
Test status
Simulation time 171434345755 ps
CPU time 53.13 seconds
Started Jul 14 04:25:31 PM PDT 24
Finished Jul 14 04:26:26 PM PDT 24
Peak memory 199684 kb
Host smart-d74ef114-c23e-4c86-9f41-0e752f2b5cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353938658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1353938658
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3626861596
Short name T467
Test name
Test status
Simulation time 35760450 ps
CPU time 0.61 seconds
Started Jul 14 04:25:40 PM PDT 24
Finished Jul 14 04:25:42 PM PDT 24
Peak memory 195372 kb
Host smart-36f24e88-8260-4069-b4aa-9475c64998cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626861596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3626861596
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2611768896
Short name T280
Test name
Test status
Simulation time 162331873364 ps
CPU time 127.85 seconds
Started Jul 14 04:25:40 PM PDT 24
Finished Jul 14 04:27:49 PM PDT 24
Peak memory 199704 kb
Host smart-73a03533-a1e5-4d5f-a859-9c39d03049c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611768896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2611768896
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3310401197
Short name T678
Test name
Test status
Simulation time 65693180756 ps
CPU time 49.22 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:26:28 PM PDT 24
Peak memory 199340 kb
Host smart-be117f52-ff7e-483b-bc64-952002bf16ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310401197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3310401197
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1972429181
Short name T867
Test name
Test status
Simulation time 22124504786 ps
CPU time 52.65 seconds
Started Jul 14 04:25:39 PM PDT 24
Finished Jul 14 04:26:33 PM PDT 24
Peak memory 199740 kb
Host smart-bddb980e-9a86-4659-a74a-19efddba44fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972429181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1972429181
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.772091130
Short name T103
Test name
Test status
Simulation time 40597691786 ps
CPU time 57.16 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:26:37 PM PDT 24
Peak memory 198972 kb
Host smart-d68dbe16-d210-4ab3-ab61-6f88d3a98483
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772091130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.772091130
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1476082189
Short name T364
Test name
Test status
Simulation time 131914526540 ps
CPU time 336.35 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:31:17 PM PDT 24
Peak memory 199748 kb
Host smart-4777d4ba-ea16-4b7f-99ba-7f69631ce5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476082189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1476082189
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3574695723
Short name T844
Test name
Test status
Simulation time 3521480129 ps
CPU time 1.87 seconds
Started Jul 14 04:26:03 PM PDT 24
Finished Jul 14 04:26:06 PM PDT 24
Peak memory 197932 kb
Host smart-5545fc3c-d43b-4e90-88eb-4f323396a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574695723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3574695723
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.742806472
Short name T1101
Test name
Test status
Simulation time 166618486355 ps
CPU time 41.89 seconds
Started Jul 14 04:26:03 PM PDT 24
Finished Jul 14 04:26:45 PM PDT 24
Peak memory 198484 kb
Host smart-b0ce3231-1c3f-4d8d-9105-370765372840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742806472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.742806472
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3915033685
Short name T970
Test name
Test status
Simulation time 20129556515 ps
CPU time 248.92 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:29:48 PM PDT 24
Peak memory 199820 kb
Host smart-ad612554-8c8f-46a1-a03e-ec8d33a307fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915033685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3915033685
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1012365979
Short name T567
Test name
Test status
Simulation time 5755692804 ps
CPU time 24.42 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:26:03 PM PDT 24
Peak memory 198936 kb
Host smart-775b5330-b0b7-492c-b509-25999a4ec2d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012365979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1012365979
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2029470160
Short name T1025
Test name
Test status
Simulation time 81045181889 ps
CPU time 11.33 seconds
Started Jul 14 04:25:36 PM PDT 24
Finished Jul 14 04:25:49 PM PDT 24
Peak memory 199804 kb
Host smart-65c4c817-b0cc-4a26-bda5-b8994c719c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029470160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2029470160
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1779021020
Short name T550
Test name
Test status
Simulation time 2700266577 ps
CPU time 4.92 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:25:44 PM PDT 24
Peak memory 195748 kb
Host smart-70ad381e-9d29-49af-b62b-850874f245b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779021020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1779021020
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2242806687
Short name T1061
Test name
Test status
Simulation time 518382756 ps
CPU time 1.02 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:25:38 PM PDT 24
Peak memory 198208 kb
Host smart-90e295d2-937b-4149-b7fb-e6e6f817e9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242806687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2242806687
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.4284315644
Short name T183
Test name
Test status
Simulation time 222897746656 ps
CPU time 193.89 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:28:50 PM PDT 24
Peak memory 199740 kb
Host smart-1060e056-36e7-44f5-bd80-834d25930e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284315644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.4284315644
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3263552920
Short name T1139
Test name
Test status
Simulation time 606945572 ps
CPU time 2.75 seconds
Started Jul 14 04:25:39 PM PDT 24
Finished Jul 14 04:25:43 PM PDT 24
Peak memory 199940 kb
Host smart-9e98d8e6-459a-4ab4-9107-db1ff4132dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263552920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3263552920
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1233510375
Short name T648
Test name
Test status
Simulation time 26449747251 ps
CPU time 24.44 seconds
Started Jul 14 04:25:36 PM PDT 24
Finished Jul 14 04:26:02 PM PDT 24
Peak memory 199692 kb
Host smart-5bba94b4-8710-4d12-a775-042d39880519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233510375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1233510375
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.720943438
Short name T378
Test name
Test status
Simulation time 30907984 ps
CPU time 0.54 seconds
Started Jul 14 04:25:48 PM PDT 24
Finished Jul 14 04:25:49 PM PDT 24
Peak memory 195132 kb
Host smart-bd23ad83-fd6a-4406-9610-720e0c77775d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720943438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.720943438
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1693657892
Short name T417
Test name
Test status
Simulation time 26439636557 ps
CPU time 16.05 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:25:55 PM PDT 24
Peak memory 199788 kb
Host smart-b90a20b8-b0d5-4557-aa79-2e1e994c0a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693657892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1693657892
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1475722474
Short name T252
Test name
Test status
Simulation time 153162651422 ps
CPU time 16.09 seconds
Started Jul 14 04:25:41 PM PDT 24
Finished Jul 14 04:25:58 PM PDT 24
Peak memory 199664 kb
Host smart-898bedf3-7ce4-4038-b49e-34992170b6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475722474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1475722474
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.544800722
Short name T940
Test name
Test status
Simulation time 23279220819 ps
CPU time 22.69 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:26:00 PM PDT 24
Peak memory 199820 kb
Host smart-4ecb17cd-6e68-41af-96ca-3df4f987fc21
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544800722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.544800722
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2475275832
Short name T974
Test name
Test status
Simulation time 179234589792 ps
CPU time 996.97 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:42:17 PM PDT 24
Peak memory 199728 kb
Host smart-975aa7ea-af61-464a-9b33-9b9b3a7f9808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475275832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2475275832
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2668256064
Short name T682
Test name
Test status
Simulation time 1614127309 ps
CPU time 0.91 seconds
Started Jul 14 04:25:39 PM PDT 24
Finished Jul 14 04:25:41 PM PDT 24
Peak memory 195780 kb
Host smart-edaadbdb-f8f9-4d55-976c-821f9bf0811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668256064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2668256064
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2103159304
Short name T791
Test name
Test status
Simulation time 122591880963 ps
CPU time 86.49 seconds
Started Jul 14 04:25:40 PM PDT 24
Finished Jul 14 04:27:08 PM PDT 24
Peak memory 200012 kb
Host smart-d826b8a9-e07b-4af7-b32f-0ac1f7ffb549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103159304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2103159304
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1239903114
Short name T296
Test name
Test status
Simulation time 7708870426 ps
CPU time 24.67 seconds
Started Jul 14 04:25:40 PM PDT 24
Finished Jul 14 04:26:06 PM PDT 24
Peak memory 199740 kb
Host smart-1c93e165-69c5-459d-94b3-5a7731e85be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239903114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1239903114
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3492392722
Short name T723
Test name
Test status
Simulation time 5510730795 ps
CPU time 2.46 seconds
Started Jul 14 04:25:35 PM PDT 24
Finished Jul 14 04:25:39 PM PDT 24
Peak memory 197704 kb
Host smart-264b470a-3570-483d-9c5a-a859b2d6084b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492392722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3492392722
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.681575397
Short name T519
Test name
Test status
Simulation time 72325448630 ps
CPU time 28.51 seconds
Started Jul 14 04:26:03 PM PDT 24
Finished Jul 14 04:26:32 PM PDT 24
Peak memory 199676 kb
Host smart-5dc47e84-a633-44d1-9eaf-e72c6747f17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681575397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.681575397
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2077428790
Short name T663
Test name
Test status
Simulation time 4417025390 ps
CPU time 6.7 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:25:47 PM PDT 24
Peak memory 195860 kb
Host smart-cead46bc-c6f5-4bc3-8e64-51dada772d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077428790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2077428790
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1188788327
Short name T1150
Test name
Test status
Simulation time 5791204061 ps
CPU time 5.81 seconds
Started Jul 14 04:25:36 PM PDT 24
Finished Jul 14 04:25:44 PM PDT 24
Peak memory 199524 kb
Host smart-77345480-6e50-43aa-9db5-b3e25438c0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188788327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1188788327
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1460382823
Short name T4
Test name
Test status
Simulation time 295386983786 ps
CPU time 270.72 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:30:17 PM PDT 24
Peak memory 199712 kb
Host smart-70a7b3ca-c006-4d7a-82cc-b57feb714285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460382823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1460382823
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2133675661
Short name T909
Test name
Test status
Simulation time 101904609173 ps
CPU time 453.8 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:33:20 PM PDT 24
Peak memory 216600 kb
Host smart-b8157214-cbeb-4e14-abb8-da07d483d13d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133675661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2133675661
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.668940060
Short name T842
Test name
Test status
Simulation time 368208265 ps
CPU time 1.4 seconds
Started Jul 14 04:25:37 PM PDT 24
Finished Jul 14 04:25:40 PM PDT 24
Peak memory 198040 kb
Host smart-d0a1dbd7-961b-458b-bf66-c9080817c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668940060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.668940060
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2829623072
Short name T409
Test name
Test status
Simulation time 52402763505 ps
CPU time 140.73 seconds
Started Jul 14 04:25:38 PM PDT 24
Finished Jul 14 04:28:01 PM PDT 24
Peak memory 199704 kb
Host smart-8483f770-4098-4fe3-93ef-c3eb41fb1adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829623072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2829623072
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.962483608
Short name T371
Test name
Test status
Simulation time 39528699 ps
CPU time 0.55 seconds
Started Jul 14 04:25:44 PM PDT 24
Finished Jul 14 04:25:46 PM PDT 24
Peak memory 194400 kb
Host smart-9c7df1b1-49ea-40a3-b4d3-708ed2f49d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962483608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.962483608
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.469507223
Short name T303
Test name
Test status
Simulation time 211164611492 ps
CPU time 397.92 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:32:24 PM PDT 24
Peak memory 199812 kb
Host smart-bfc0abc9-ea7d-4511-bdf5-1aec45f30a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469507223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.469507223
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2153678315
Short name T478
Test name
Test status
Simulation time 151394219612 ps
CPU time 135.83 seconds
Started Jul 14 04:25:48 PM PDT 24
Finished Jul 14 04:28:04 PM PDT 24
Peak memory 199688 kb
Host smart-5f8f3da1-b61f-4022-a549-826e85f36205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153678315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2153678315
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.325902587
Short name T151
Test name
Test status
Simulation time 63464981948 ps
CPU time 27.06 seconds
Started Jul 14 04:25:49 PM PDT 24
Finished Jul 14 04:26:16 PM PDT 24
Peak memory 199720 kb
Host smart-5d37eb1c-7941-41b0-bf90-0e573dfa0174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325902587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.325902587
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3343982344
Short name T36
Test name
Test status
Simulation time 15467951090 ps
CPU time 3.72 seconds
Started Jul 14 04:25:47 PM PDT 24
Finished Jul 14 04:25:51 PM PDT 24
Peak memory 196716 kb
Host smart-0c8f5cb0-b242-4817-bcb1-630bff857360
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343982344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3343982344
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.268891758
Short name T1079
Test name
Test status
Simulation time 108972256884 ps
CPU time 736.96 seconds
Started Jul 14 04:25:46 PM PDT 24
Finished Jul 14 04:38:04 PM PDT 24
Peak memory 199656 kb
Host smart-112a4358-1776-41ec-ba32-f57aa4f6480b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268891758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.268891758
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.508828619
Short name T903
Test name
Test status
Simulation time 2245679546 ps
CPU time 3.66 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:25:50 PM PDT 24
Peak memory 197436 kb
Host smart-d59021ea-0ee6-43c6-a83b-327a84993157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508828619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.508828619
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.32443361
Short name T517
Test name
Test status
Simulation time 41522228140 ps
CPU time 72.64 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:26:59 PM PDT 24
Peak memory 208192 kb
Host smart-4a79be4f-5055-40f0-92e3-29d6d1baab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32443361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.32443361
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.4046616730
Short name T1115
Test name
Test status
Simulation time 13401534989 ps
CPU time 325.75 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:31:12 PM PDT 24
Peak memory 199820 kb
Host smart-2bb32f9d-2011-42fd-aced-5d1fb634c716
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046616730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.4046616730
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.566098104
Short name T699
Test name
Test status
Simulation time 4620514660 ps
CPU time 40.09 seconds
Started Jul 14 04:25:44 PM PDT 24
Finished Jul 14 04:26:24 PM PDT 24
Peak memory 197916 kb
Host smart-f39120a6-bb5a-4acf-9ffa-f42fbd131b1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=566098104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.566098104
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.966485088
Short name T1007
Test name
Test status
Simulation time 36096529912 ps
CPU time 57.87 seconds
Started Jul 14 04:25:47 PM PDT 24
Finished Jul 14 04:26:46 PM PDT 24
Peak memory 199772 kb
Host smart-f92128f3-6b32-4df9-82d3-4c56384b8350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966485088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.966485088
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3210822571
Short name T975
Test name
Test status
Simulation time 4776990433 ps
CPU time 7.61 seconds
Started Jul 14 04:25:44 PM PDT 24
Finished Jul 14 04:25:53 PM PDT 24
Peak memory 196072 kb
Host smart-67294ef6-09dd-4f95-a047-842110c600f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210822571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3210822571
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3453595014
Short name T1076
Test name
Test status
Simulation time 982649998 ps
CPU time 2.26 seconds
Started Jul 14 04:25:44 PM PDT 24
Finished Jul 14 04:25:47 PM PDT 24
Peak memory 198064 kb
Host smart-9ef019c5-d77a-42b2-a7b3-dc02cc5c2112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453595014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3453595014
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2336541794
Short name T906
Test name
Test status
Simulation time 63219211892 ps
CPU time 85.25 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:27:11 PM PDT 24
Peak memory 199792 kb
Host smart-b4c950ec-4dc7-449a-9584-e7cbdf2208e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336541794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2336541794
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.727950798
Short name T749
Test name
Test status
Simulation time 172322057148 ps
CPU time 229.24 seconds
Started Jul 14 04:25:44 PM PDT 24
Finished Jul 14 04:29:34 PM PDT 24
Peak memory 216288 kb
Host smart-8d08eb1f-8169-4579-84fd-ea61fccc0aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727950798 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.727950798
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.576732927
Short name T549
Test name
Test status
Simulation time 1799501097 ps
CPU time 2.23 seconds
Started Jul 14 04:25:50 PM PDT 24
Finished Jul 14 04:25:53 PM PDT 24
Peak memory 198660 kb
Host smart-e144b685-8062-4e6c-893f-fa71f4868731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576732927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.576732927
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1288905102
Short name T392
Test name
Test status
Simulation time 40744773868 ps
CPU time 65.67 seconds
Started Jul 14 04:25:44 PM PDT 24
Finished Jul 14 04:26:50 PM PDT 24
Peak memory 199792 kb
Host smart-ba36f816-967e-446c-9a16-1b10be0cae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288905102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1288905102
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3026262785
Short name T724
Test name
Test status
Simulation time 40478319 ps
CPU time 0.54 seconds
Started Jul 14 04:25:51 PM PDT 24
Finished Jul 14 04:25:52 PM PDT 24
Peak memory 195400 kb
Host smart-c1adcc78-10cc-4731-a4a3-de602fa1fabb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026262785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3026262785
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3593219692
Short name T1036
Test name
Test status
Simulation time 46769881767 ps
CPU time 69.89 seconds
Started Jul 14 04:25:48 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 199708 kb
Host smart-d3ae8b44-8e1e-4f0c-854d-510ad3d2c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593219692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3593219692
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3126678770
Short name T465
Test name
Test status
Simulation time 112441557786 ps
CPU time 161.05 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:28:27 PM PDT 24
Peak memory 199880 kb
Host smart-ed17a30d-f87f-44ba-9bde-821a2a07d39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126678770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3126678770
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.115348980
Short name T234
Test name
Test status
Simulation time 106625606871 ps
CPU time 160.54 seconds
Started Jul 14 04:25:44 PM PDT 24
Finished Jul 14 04:28:24 PM PDT 24
Peak memory 199756 kb
Host smart-43e81979-529c-429e-a80b-71efd217d94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115348980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.115348980
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.412027546
Short name T932
Test name
Test status
Simulation time 347951348791 ps
CPU time 510.99 seconds
Started Jul 14 04:25:46 PM PDT 24
Finished Jul 14 04:34:18 PM PDT 24
Peak memory 198692 kb
Host smart-ac50f88f-0393-4e06-ab3e-7fb4b99baa94
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412027546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.412027546
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1445778727
Short name T1050
Test name
Test status
Simulation time 133724129092 ps
CPU time 725.11 seconds
Started Jul 14 04:25:53 PM PDT 24
Finished Jul 14 04:37:58 PM PDT 24
Peak memory 199732 kb
Host smart-fc089d6d-42c3-4579-b269-1c055ec32e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445778727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1445778727
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1609114242
Short name T855
Test name
Test status
Simulation time 1183690600 ps
CPU time 0.9 seconds
Started Jul 14 04:25:54 PM PDT 24
Finished Jul 14 04:25:56 PM PDT 24
Peak memory 195712 kb
Host smart-914c4616-a5c3-475c-aa34-ea5cdbf2aa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609114242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1609114242
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1161767643
Short name T981
Test name
Test status
Simulation time 211290360153 ps
CPU time 131.38 seconds
Started Jul 14 04:25:46 PM PDT 24
Finished Jul 14 04:27:59 PM PDT 24
Peak memory 199168 kb
Host smart-bc2a1494-c3c8-4ead-87c1-b9472f93a244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161767643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1161767643
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3419224231
Short name T402
Test name
Test status
Simulation time 7822936120 ps
CPU time 420.33 seconds
Started Jul 14 04:25:56 PM PDT 24
Finished Jul 14 04:32:57 PM PDT 24
Peak memory 199772 kb
Host smart-b934544c-dd92-4f5b-9cc1-fd8e62406f82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419224231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3419224231
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2045087945
Short name T980
Test name
Test status
Simulation time 1787682825 ps
CPU time 8.03 seconds
Started Jul 14 04:25:47 PM PDT 24
Finished Jul 14 04:25:56 PM PDT 24
Peak memory 197628 kb
Host smart-09015ead-b96f-4bdd-9429-49f0acccbb48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045087945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2045087945
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2878591112
Short name T841
Test name
Test status
Simulation time 125327274409 ps
CPU time 162.81 seconds
Started Jul 14 04:25:44 PM PDT 24
Finished Jul 14 04:28:28 PM PDT 24
Peak memory 199720 kb
Host smart-d640ee6b-d81e-4820-9e43-6dae2ae06eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878591112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2878591112
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3296971087
Short name T487
Test name
Test status
Simulation time 496457462 ps
CPU time 1.43 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:25:48 PM PDT 24
Peak memory 195312 kb
Host smart-00d54a93-8f0a-4643-92ef-84d3fa6bad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296971087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3296971087
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3493172584
Short name T1123
Test name
Test status
Simulation time 502064603 ps
CPU time 1.7 seconds
Started Jul 14 04:25:45 PM PDT 24
Finished Jul 14 04:25:47 PM PDT 24
Peak memory 197988 kb
Host smart-6cb05c8a-e282-40b8-8e83-11e89b4d2028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493172584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3493172584
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2163677024
Short name T811
Test name
Test status
Simulation time 70624383961 ps
CPU time 444.41 seconds
Started Jul 14 04:25:56 PM PDT 24
Finished Jul 14 04:33:21 PM PDT 24
Peak memory 199628 kb
Host smart-01f72e0a-2e0e-4e69-89d5-dc5ca0ea4813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163677024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2163677024
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3192295818
Short name T613
Test name
Test status
Simulation time 1759224338 ps
CPU time 2.22 seconds
Started Jul 14 04:25:51 PM PDT 24
Finished Jul 14 04:25:53 PM PDT 24
Peak memory 199412 kb
Host smart-fef7f002-d81a-4e11-8df4-75d980d54aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192295818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3192295818
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.701486473
Short name T747
Test name
Test status
Simulation time 135523886849 ps
CPU time 44.3 seconds
Started Jul 14 04:25:46 PM PDT 24
Finished Jul 14 04:26:31 PM PDT 24
Peak memory 199696 kb
Host smart-faf4764f-e8af-47d2-a690-7fb6b2449871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701486473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.701486473
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3607948323
Short name T528
Test name
Test status
Simulation time 11344507 ps
CPU time 0.54 seconds
Started Jul 14 04:25:52 PM PDT 24
Finished Jul 14 04:25:52 PM PDT 24
Peak memory 195104 kb
Host smart-76b0fb66-ce0e-40b6-926c-be088bb8382a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607948323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3607948323
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2550228136
Short name T621
Test name
Test status
Simulation time 147889216048 ps
CPU time 275.88 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:30:32 PM PDT 24
Peak memory 199756 kb
Host smart-7ecd2c7e-b1d7-4940-8ee4-ea98e870fdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550228136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2550228136
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2318002702
Short name T273
Test name
Test status
Simulation time 28941815872 ps
CPU time 46.78 seconds
Started Jul 14 04:25:54 PM PDT 24
Finished Jul 14 04:26:42 PM PDT 24
Peak memory 199708 kb
Host smart-c27e76f7-96f4-4c84-8df7-fbdd0fda4224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318002702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2318002702
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2359843083
Short name T355
Test name
Test status
Simulation time 112399818493 ps
CPU time 43.88 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:26:40 PM PDT 24
Peak memory 199720 kb
Host smart-ad8683e2-8235-4aea-9bac-40e86c3cb6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359843083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2359843083
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2480348166
Short name T458
Test name
Test status
Simulation time 15878046726 ps
CPU time 6.54 seconds
Started Jul 14 04:25:53 PM PDT 24
Finished Jul 14 04:26:00 PM PDT 24
Peak memory 196644 kb
Host smart-1874e4be-bdbc-4c24-94c0-961582057f1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480348166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2480348166
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.613995567
Short name T813
Test name
Test status
Simulation time 150583891014 ps
CPU time 642.89 seconds
Started Jul 14 04:25:51 PM PDT 24
Finished Jul 14 04:36:34 PM PDT 24
Peak memory 199832 kb
Host smart-b7255e76-253d-41f5-ac1b-fd70c4028efd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613995567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.613995567
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.730892642
Short name T1094
Test name
Test status
Simulation time 10056397345 ps
CPU time 8.39 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:26:05 PM PDT 24
Peak memory 199632 kb
Host smart-c91bc871-7f47-4b58-b4c3-a86aa6516ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730892642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.730892642
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2477178533
Short name T1100
Test name
Test status
Simulation time 230586397980 ps
CPU time 28.35 seconds
Started Jul 14 04:25:52 PM PDT 24
Finished Jul 14 04:26:22 PM PDT 24
Peak memory 200076 kb
Host smart-af07d6ca-4cd1-41d0-b879-1b99e9a2e37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477178533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2477178533
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.530015920
Short name T640
Test name
Test status
Simulation time 21236501252 ps
CPU time 252.64 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:30:09 PM PDT 24
Peak memory 199676 kb
Host smart-c88be65c-dfcc-4ecd-bee5-709514715b97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530015920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.530015920
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1462221338
Short name T650
Test name
Test status
Simulation time 4429088001 ps
CPU time 34.26 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:26:31 PM PDT 24
Peak memory 197972 kb
Host smart-912b2490-426b-4917-987c-679dc0d7e9a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462221338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1462221338
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1981494795
Short name T848
Test name
Test status
Simulation time 73724596396 ps
CPU time 67.18 seconds
Started Jul 14 04:25:51 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 199784 kb
Host smart-3e852838-7b3f-4cbc-bb1a-88e754ea1dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981494795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1981494795
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.892321894
Short name T904
Test name
Test status
Simulation time 38958206435 ps
CPU time 29.55 seconds
Started Jul 14 04:25:53 PM PDT 24
Finished Jul 14 04:26:23 PM PDT 24
Peak memory 195796 kb
Host smart-80268f90-2b2f-4084-ba7c-0ab04bcdcdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892321894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.892321894
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3584648376
Short name T710
Test name
Test status
Simulation time 459455158 ps
CPU time 2.01 seconds
Started Jul 14 04:25:57 PM PDT 24
Finished Jul 14 04:26:00 PM PDT 24
Peak memory 199448 kb
Host smart-1a4bc847-781d-4db7-a55e-384caa9cabd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584648376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3584648376
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.3204419722
Short name T1001
Test name
Test status
Simulation time 317554229232 ps
CPU time 571.03 seconds
Started Jul 14 04:25:54 PM PDT 24
Finished Jul 14 04:35:26 PM PDT 24
Peak memory 199644 kb
Host smart-f6789760-4c4c-4018-bd2b-21797f6a2ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204419722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3204419722
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3097159655
Short name T1127
Test name
Test status
Simulation time 69592045133 ps
CPU time 777.67 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:38:55 PM PDT 24
Peak memory 230404 kb
Host smart-5359c06e-4bee-47e8-af94-81cce9ad082f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097159655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3097159655
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.4113777853
Short name T413
Test name
Test status
Simulation time 1189184189 ps
CPU time 2.48 seconds
Started Jul 14 04:25:53 PM PDT 24
Finished Jul 14 04:25:57 PM PDT 24
Peak memory 199456 kb
Host smart-dc1d1344-f0c1-42d3-a15f-89b8f1484453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113777853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.4113777853
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1518669761
Short name T982
Test name
Test status
Simulation time 66164000782 ps
CPU time 212.84 seconds
Started Jul 14 04:25:54 PM PDT 24
Finished Jul 14 04:29:27 PM PDT 24
Peak memory 199768 kb
Host smart-a1f319fe-9305-4b7c-9d2c-4b742b6b7495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518669761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1518669761
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4156899145
Short name T576
Test name
Test status
Simulation time 41370358 ps
CPU time 0.56 seconds
Started Jul 14 04:26:04 PM PDT 24
Finished Jul 14 04:26:05 PM PDT 24
Peak memory 194016 kb
Host smart-036b9e7e-6257-4df2-955b-323d4e2b1f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156899145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4156899145
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3776934851
Short name T605
Test name
Test status
Simulation time 13676397823 ps
CPU time 20.53 seconds
Started Jul 14 04:25:56 PM PDT 24
Finished Jul 14 04:26:17 PM PDT 24
Peak memory 199260 kb
Host smart-9d686c86-7203-487f-8821-2de927d44cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776934851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3776934851
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1940013392
Short name T544
Test name
Test status
Simulation time 73681520444 ps
CPU time 40.3 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:26:36 PM PDT 24
Peak memory 199684 kb
Host smart-fd3e2b63-cd83-4a4a-9e53-6e3af1064ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940013392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1940013392
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3786871533
Short name T425
Test name
Test status
Simulation time 56270531778 ps
CPU time 108.88 seconds
Started Jul 14 04:25:52 PM PDT 24
Finished Jul 14 04:27:42 PM PDT 24
Peak memory 199860 kb
Host smart-43278b51-9470-4cdb-8f2d-119a3d1cc61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786871533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3786871533
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2474311152
Short name T706
Test name
Test status
Simulation time 14204578936 ps
CPU time 6.32 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:26:02 PM PDT 24
Peak memory 196432 kb
Host smart-0651966b-2d9b-4665-b9df-e50c7474dde8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474311152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2474311152
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.265552717
Short name T1109
Test name
Test status
Simulation time 93521801563 ps
CPU time 424.37 seconds
Started Jul 14 04:26:00 PM PDT 24
Finished Jul 14 04:33:06 PM PDT 24
Peak memory 199792 kb
Host smart-c9465af2-b112-4c13-ab42-02ec7a9dcf4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265552717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.265552717
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3917616109
Short name T892
Test name
Test status
Simulation time 11748577348 ps
CPU time 21.57 seconds
Started Jul 14 04:26:02 PM PDT 24
Finished Jul 14 04:26:24 PM PDT 24
Peak memory 199776 kb
Host smart-8cd37119-834e-41c7-9cc4-f48cb2174069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917616109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3917616109
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3067234642
Short name T713
Test name
Test status
Simulation time 20338204849 ps
CPU time 34.84 seconds
Started Jul 14 04:25:55 PM PDT 24
Finished Jul 14 04:26:31 PM PDT 24
Peak memory 199904 kb
Host smart-1efbc4d0-0ac6-48ae-9577-659afc3683bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067234642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3067234642
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1937443097
Short name T874
Test name
Test status
Simulation time 2268540879 ps
CPU time 30.87 seconds
Started Jul 14 04:26:12 PM PDT 24
Finished Jul 14 04:26:44 PM PDT 24
Peak memory 199492 kb
Host smart-b6f1fb1c-ab7b-497e-b720-93da352eb107
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937443097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1937443097
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.134861396
Short name T1143
Test name
Test status
Simulation time 5799660455 ps
CPU time 11.33 seconds
Started Jul 14 04:25:54 PM PDT 24
Finished Jul 14 04:26:07 PM PDT 24
Peak memory 198436 kb
Host smart-cab26d09-49ae-41a4-bf0c-1ad0f991f92d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134861396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.134861396
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.11490399
Short name T386
Test name
Test status
Simulation time 1483965643 ps
CPU time 1.22 seconds
Started Jul 14 04:25:52 PM PDT 24
Finished Jul 14 04:25:54 PM PDT 24
Peak memory 195324 kb
Host smart-80e70b9b-6567-4945-93a7-4de9167528a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11490399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.11490399
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1776165475
Short name T452
Test name
Test status
Simulation time 550841558 ps
CPU time 0.95 seconds
Started Jul 14 04:25:57 PM PDT 24
Finished Jul 14 04:25:58 PM PDT 24
Peak memory 198460 kb
Host smart-e65aa822-1dbd-4d47-90ce-e2424aefbe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776165475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1776165475
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.189384842
Short name T1124
Test name
Test status
Simulation time 22667724306 ps
CPU time 239.98 seconds
Started Jul 14 04:25:59 PM PDT 24
Finished Jul 14 04:30:00 PM PDT 24
Peak memory 199660 kb
Host smart-f6d6393f-7b46-4fa6-815b-b4ae5485009c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189384842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.189384842
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1407686747
Short name T1081
Test name
Test status
Simulation time 67555335885 ps
CPU time 577.3 seconds
Started Jul 14 04:26:00 PM PDT 24
Finished Jul 14 04:35:39 PM PDT 24
Peak memory 216512 kb
Host smart-76dc9f85-3449-4c39-b5a4-9c46413125f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407686747 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1407686747
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3354294348
Short name T546
Test name
Test status
Simulation time 1562972129 ps
CPU time 1.59 seconds
Started Jul 14 04:26:00 PM PDT 24
Finished Jul 14 04:26:03 PM PDT 24
Peak memory 198216 kb
Host smart-88b93fac-836b-4421-bc04-a05ce8df6cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354294348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3354294348
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1962716388
Short name T620
Test name
Test status
Simulation time 54167378764 ps
CPU time 31.25 seconds
Started Jul 14 04:25:56 PM PDT 24
Finished Jul 14 04:26:28 PM PDT 24
Peak memory 199764 kb
Host smart-f8fc57d7-8712-41cd-9477-8429a5f9984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962716388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1962716388
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1349222204
Short name T541
Test name
Test status
Simulation time 14210776 ps
CPU time 0.58 seconds
Started Jul 14 04:26:01 PM PDT 24
Finished Jul 14 04:26:02 PM PDT 24
Peak memory 195316 kb
Host smart-ff56430a-9f66-4e8b-bbe8-8772f178a431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349222204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1349222204
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2383551656
Short name T1156
Test name
Test status
Simulation time 59286797324 ps
CPU time 21.51 seconds
Started Jul 14 04:26:00 PM PDT 24
Finished Jul 14 04:26:22 PM PDT 24
Peak memory 199784 kb
Host smart-ebc28641-7c17-43f6-839f-e8c0e44587a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383551656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2383551656
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1768569892
Short name T1121
Test name
Test status
Simulation time 36672607857 ps
CPU time 11.47 seconds
Started Jul 14 04:26:01 PM PDT 24
Finished Jul 14 04:26:13 PM PDT 24
Peak memory 199592 kb
Host smart-6d51c62a-98b7-4dc9-ba5c-cc53f7740df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768569892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1768569892
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3698216415
Short name T455
Test name
Test status
Simulation time 39772646297 ps
CPU time 73.22 seconds
Started Jul 14 04:26:00 PM PDT 24
Finished Jul 14 04:27:14 PM PDT 24
Peak memory 199740 kb
Host smart-e6f81c85-7e33-4f26-97d4-3ad691911ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698216415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3698216415
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.391117654
Short name T1168
Test name
Test status
Simulation time 22835852211 ps
CPU time 22.19 seconds
Started Jul 14 04:25:59 PM PDT 24
Finished Jul 14 04:26:22 PM PDT 24
Peak memory 199320 kb
Host smart-39d6fb08-59de-4758-ae18-020d25b7a301
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391117654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.391117654
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2502569722
Short name T1042
Test name
Test status
Simulation time 58587410626 ps
CPU time 490.69 seconds
Started Jul 14 04:26:02 PM PDT 24
Finished Jul 14 04:34:13 PM PDT 24
Peak memory 199680 kb
Host smart-515fd3f2-6fbd-4bb9-adf1-e6ef7a680e30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2502569722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2502569722
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1415760352
Short name T731
Test name
Test status
Simulation time 9601637414 ps
CPU time 8.36 seconds
Started Jul 14 04:26:04 PM PDT 24
Finished Jul 14 04:26:13 PM PDT 24
Peak memory 199520 kb
Host smart-3e210851-eeda-436d-99e9-6a37d962ba52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415760352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1415760352
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.203629207
Short name T559
Test name
Test status
Simulation time 118292105272 ps
CPU time 141.82 seconds
Started Jul 14 04:26:01 PM PDT 24
Finished Jul 14 04:28:23 PM PDT 24
Peak memory 200000 kb
Host smart-46773d63-7437-4e0b-8f51-1287c38d76ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203629207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.203629207
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.767199295
Short name T270
Test name
Test status
Simulation time 7798461021 ps
CPU time 93.64 seconds
Started Jul 14 04:26:01 PM PDT 24
Finished Jul 14 04:27:35 PM PDT 24
Peak memory 199744 kb
Host smart-2ecb2932-bffd-40bf-a86f-1cedf8aebd89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767199295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.767199295
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1059468319
Short name T965
Test name
Test status
Simulation time 3494123273 ps
CPU time 26.63 seconds
Started Jul 14 04:26:04 PM PDT 24
Finished Jul 14 04:26:31 PM PDT 24
Peak memory 198108 kb
Host smart-a77ae19c-a584-4614-bd59-44d9171d22d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059468319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1059468319
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3283075324
Short name T618
Test name
Test status
Simulation time 63035471500 ps
CPU time 20.87 seconds
Started Jul 14 04:26:02 PM PDT 24
Finished Jul 14 04:26:23 PM PDT 24
Peak memory 199748 kb
Host smart-d1f88e21-d5aa-4577-b07c-4f5e8d871993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283075324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3283075324
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1711600478
Short name T802
Test name
Test status
Simulation time 4633077091 ps
CPU time 2.36 seconds
Started Jul 14 04:26:04 PM PDT 24
Finished Jul 14 04:26:07 PM PDT 24
Peak memory 195992 kb
Host smart-fbad995d-0baa-4781-a175-b3f7f662e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711600478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1711600478
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.278055713
Short name T745
Test name
Test status
Simulation time 936079937 ps
CPU time 3.88 seconds
Started Jul 14 04:26:00 PM PDT 24
Finished Jul 14 04:26:05 PM PDT 24
Peak memory 198420 kb
Host smart-d2e92801-6bb0-4fe9-a20b-d1e6a5876854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278055713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.278055713
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.4281655341
Short name T127
Test name
Test status
Simulation time 145690752186 ps
CPU time 52.76 seconds
Started Jul 14 04:26:01 PM PDT 24
Finished Jul 14 04:26:55 PM PDT 24
Peak memory 199760 kb
Host smart-a5d1aaab-ea33-484d-b140-1e7f3211a9e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281655341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4281655341
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2715966212
Short name T817
Test name
Test status
Simulation time 169756508966 ps
CPU time 2125.71 seconds
Started Jul 14 04:26:00 PM PDT 24
Finished Jul 14 05:01:27 PM PDT 24
Peak memory 226240 kb
Host smart-648df943-f62a-4ead-9a22-1b0e574d0dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715966212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2715966212
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3568445339
Short name T934
Test name
Test status
Simulation time 1228618857 ps
CPU time 2.78 seconds
Started Jul 14 04:26:02 PM PDT 24
Finished Jul 14 04:26:05 PM PDT 24
Peak memory 198436 kb
Host smart-7dab923f-10e8-4389-b9a7-6741252d0ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568445339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3568445339
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1754959016
Short name T822
Test name
Test status
Simulation time 62419183249 ps
CPU time 104.04 seconds
Started Jul 14 04:25:59 PM PDT 24
Finished Jul 14 04:27:43 PM PDT 24
Peak memory 199832 kb
Host smart-313023e5-9b87-4f21-b96d-b7138f49f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754959016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1754959016
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2564410743
Short name T1090
Test name
Test status
Simulation time 14833214 ps
CPU time 0.56 seconds
Started Jul 14 04:26:13 PM PDT 24
Finished Jul 14 04:26:14 PM PDT 24
Peak memory 195052 kb
Host smart-03954b70-ba60-4342-a5cb-f0846309497d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564410743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2564410743
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.391712028
Short name T385
Test name
Test status
Simulation time 58158852715 ps
CPU time 83.48 seconds
Started Jul 14 04:26:02 PM PDT 24
Finished Jul 14 04:27:26 PM PDT 24
Peak memory 199716 kb
Host smart-3c57de10-a5eb-4476-be74-72282d1a086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391712028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.391712028
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.879523612
Short name T905
Test name
Test status
Simulation time 56109977992 ps
CPU time 85.66 seconds
Started Jul 14 04:26:12 PM PDT 24
Finished Jul 14 04:27:38 PM PDT 24
Peak memory 199744 kb
Host smart-f4738c0c-e296-474f-af0a-b9b85ea3d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879523612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.879523612
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.4035951700
Short name T306
Test name
Test status
Simulation time 150208226086 ps
CPU time 65.49 seconds
Started Jul 14 04:26:09 PM PDT 24
Finished Jul 14 04:27:15 PM PDT 24
Peak memory 199708 kb
Host smart-b6841a3a-4714-422b-9250-d9672b17c56f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035951700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4035951700
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3263760479
Short name T786
Test name
Test status
Simulation time 173334887951 ps
CPU time 384.52 seconds
Started Jul 14 04:26:10 PM PDT 24
Finished Jul 14 04:32:36 PM PDT 24
Peak memory 199668 kb
Host smart-a5dca720-12ea-43c2-968b-97da19c61066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263760479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3263760479
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3260322188
Short name T896
Test name
Test status
Simulation time 2118335526 ps
CPU time 2.31 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:26:23 PM PDT 24
Peak memory 198784 kb
Host smart-35b4c401-3d7b-4d92-bc49-08c0308eb9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260322188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3260322188
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3894983125
Short name T338
Test name
Test status
Simulation time 5366289892 ps
CPU time 2.38 seconds
Started Jul 14 04:26:18 PM PDT 24
Finished Jul 14 04:26:22 PM PDT 24
Peak memory 199708 kb
Host smart-8761d85e-0f1e-4d1d-8531-d6d0136676d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894983125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3894983125
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1180180539
Short name T639
Test name
Test status
Simulation time 12470790177 ps
CPU time 557.58 seconds
Started Jul 14 04:26:10 PM PDT 24
Finished Jul 14 04:35:28 PM PDT 24
Peak memory 199752 kb
Host smart-c9300371-4a6e-4823-98dd-66864828294b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180180539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1180180539
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3499774103
Short name T1008
Test name
Test status
Simulation time 7310277659 ps
CPU time 15.96 seconds
Started Jul 14 04:26:10 PM PDT 24
Finished Jul 14 04:26:27 PM PDT 24
Peak memory 199128 kb
Host smart-d0a27764-4ec8-4960-a2ff-afeeed651a85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499774103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3499774103
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3045290309
Short name T669
Test name
Test status
Simulation time 67697965578 ps
CPU time 25.95 seconds
Started Jul 14 04:26:13 PM PDT 24
Finished Jul 14 04:26:39 PM PDT 24
Peak memory 199672 kb
Host smart-e8fbfae2-8316-4d30-a7f1-88f03a12ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045290309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3045290309
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1461183876
Short name T617
Test name
Test status
Simulation time 46651612070 ps
CPU time 37.62 seconds
Started Jul 14 04:26:14 PM PDT 24
Finished Jul 14 04:26:52 PM PDT 24
Peak memory 196272 kb
Host smart-b6bb3df9-8d58-4687-86a0-ddd831a83f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461183876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1461183876
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3578635597
Short name T310
Test name
Test status
Simulation time 478062833 ps
CPU time 1.96 seconds
Started Jul 14 04:26:12 PM PDT 24
Finished Jul 14 04:26:15 PM PDT 24
Peak memory 198248 kb
Host smart-bd69ad8f-f4a1-41ff-a880-a8577e713dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578635597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3578635597
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.740455115
Short name T773
Test name
Test status
Simulation time 253912856152 ps
CPU time 351.23 seconds
Started Jul 14 04:26:11 PM PDT 24
Finished Jul 14 04:32:03 PM PDT 24
Peak memory 199708 kb
Host smart-c7ae19a3-e147-44e5-988f-506708c0239a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740455115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.740455115
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1898917094
Short name T854
Test name
Test status
Simulation time 75281482072 ps
CPU time 593.03 seconds
Started Jul 14 04:26:09 PM PDT 24
Finished Jul 14 04:36:03 PM PDT 24
Peak memory 216592 kb
Host smart-fa1d0117-86db-4fd8-8698-8baa0aab633f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898917094 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1898917094
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3045335160
Short name T612
Test name
Test status
Simulation time 6362447876 ps
CPU time 14.55 seconds
Started Jul 14 04:26:10 PM PDT 24
Finished Jul 14 04:26:25 PM PDT 24
Peak memory 199672 kb
Host smart-ba606c83-fb17-496a-9592-a0a69f526a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045335160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3045335160
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1138191014
Short name T808
Test name
Test status
Simulation time 6055203386 ps
CPU time 6.87 seconds
Started Jul 14 04:26:02 PM PDT 24
Finished Jul 14 04:26:10 PM PDT 24
Peak memory 199472 kb
Host smart-7d4ab86a-8854-49b9-8d22-b359a7ac8a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138191014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1138191014
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3605868860
Short name T937
Test name
Test status
Simulation time 12330472 ps
CPU time 0.53 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:23:45 PM PDT 24
Peak memory 195080 kb
Host smart-592b413c-94f6-4578-9633-d6ff88c9089d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605868860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3605868860
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.213883889
Short name T1054
Test name
Test status
Simulation time 20046864469 ps
CPU time 34.42 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:24:18 PM PDT 24
Peak memory 199676 kb
Host smart-7deea3dc-24ab-40e7-9a5c-f361164dcbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213883889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.213883889
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.796524388
Short name T979
Test name
Test status
Simulation time 143516312064 ps
CPU time 100.89 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:25:25 PM PDT 24
Peak memory 199604 kb
Host smart-90ae5a67-660b-4e36-a743-31fe30a2e276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796524388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.796524388
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1981568109
Short name T968
Test name
Test status
Simulation time 21108812219 ps
CPU time 9.45 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:23:48 PM PDT 24
Peak memory 199692 kb
Host smart-655078f3-294c-4602-8906-58a7861da608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981568109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1981568109
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2272684097
Short name T607
Test name
Test status
Simulation time 36227879256 ps
CPU time 59.72 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 199672 kb
Host smart-0f72bd04-7cfc-4205-846d-0b7b2b6dca90
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272684097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2272684097
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3403620796
Short name T404
Test name
Test status
Simulation time 121016826413 ps
CPU time 270.76 seconds
Started Jul 14 04:23:36 PM PDT 24
Finished Jul 14 04:28:09 PM PDT 24
Peak memory 199660 kb
Host smart-38c114b0-bf36-46bd-a0e9-b2578e35e487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403620796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3403620796
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3102280511
Short name T526
Test name
Test status
Simulation time 9374437958 ps
CPU time 11.28 seconds
Started Jul 14 04:23:34 PM PDT 24
Finished Jul 14 04:23:48 PM PDT 24
Peak memory 199812 kb
Host smart-89a09b71-b99d-4089-b0d0-b095536428c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102280511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3102280511
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.4027859381
Short name T824
Test name
Test status
Simulation time 45008368064 ps
CPU time 83.61 seconds
Started Jul 14 04:23:34 PM PDT 24
Finished Jul 14 04:25:01 PM PDT 24
Peak memory 199700 kb
Host smart-7017e853-42ab-40ef-8437-38029e7eb800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027859381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.4027859381
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1048557452
Short name T1063
Test name
Test status
Simulation time 11322036406 ps
CPU time 510.04 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:32:06 PM PDT 24
Peak memory 199760 kb
Host smart-d760ca9c-2651-4d06-a100-829f3595892f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048557452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1048557452
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.935819866
Short name T784
Test name
Test status
Simulation time 1934315996 ps
CPU time 3.28 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 198872 kb
Host smart-f0bc0778-c34e-4e8c-818c-1649535b967c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935819866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.935819866
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.10958814
Short name T171
Test name
Test status
Simulation time 87485972308 ps
CPU time 54.1 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 199668 kb
Host smart-606fc582-8dbc-4bc7-9a49-2f0df419c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10958814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.10958814
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3721571364
Short name T395
Test name
Test status
Simulation time 3445242494 ps
CPU time 1.84 seconds
Started Jul 14 04:23:35 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 195896 kb
Host smart-68eeac19-9567-4bab-b01b-5c4ed71b281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721571364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3721571364
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1209203453
Short name T866
Test name
Test status
Simulation time 5571696991 ps
CPU time 8.5 seconds
Started Jul 14 04:23:41 PM PDT 24
Finished Jul 14 04:23:50 PM PDT 24
Peak memory 199500 kb
Host smart-253c5cfb-4eec-4cb7-a27e-fbdc4b7833a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209203453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1209203453
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3927097901
Short name T105
Test name
Test status
Simulation time 106947787844 ps
CPU time 181.45 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:26:46 PM PDT 24
Peak memory 216468 kb
Host smart-2660c06e-efc9-4385-94bc-3b09dbc8a69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927097901 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3927097901
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.213118090
Short name T525
Test name
Test status
Simulation time 1101126560 ps
CPU time 2.14 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:23:37 PM PDT 24
Peak memory 198144 kb
Host smart-65324148-986f-454a-be20-03cc8e68d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213118090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.213118090
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2060222401
Short name T1002
Test name
Test status
Simulation time 58938309533 ps
CPU time 48.52 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:24:22 PM PDT 24
Peak memory 199688 kb
Host smart-7978b500-cfa5-41e0-9388-80a3cd0979c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060222401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2060222401
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3575335589
Short name T347
Test name
Test status
Simulation time 55051904796 ps
CPU time 20.51 seconds
Started Jul 14 04:26:11 PM PDT 24
Finished Jul 14 04:26:32 PM PDT 24
Peak memory 199644 kb
Host smart-796b6424-411d-45ab-a60e-ee891d7d4e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575335589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3575335589
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.455189842
Short name T233
Test name
Test status
Simulation time 67902258675 ps
CPU time 522.8 seconds
Started Jul 14 04:26:10 PM PDT 24
Finished Jul 14 04:34:53 PM PDT 24
Peak memory 216556 kb
Host smart-efe0b4e9-04aa-4618-8c47-b4f2f1b003c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455189842 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.455189842
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1677814117
Short name T534
Test name
Test status
Simulation time 92820137364 ps
CPU time 519.9 seconds
Started Jul 14 04:26:12 PM PDT 24
Finished Jul 14 04:34:53 PM PDT 24
Peak memory 199724 kb
Host smart-e3480bf8-6cfd-45ef-8cf1-c9717c7a245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677814117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1677814117
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2733261161
Short name T832
Test name
Test status
Simulation time 38520602483 ps
CPU time 980.84 seconds
Started Jul 14 04:26:14 PM PDT 24
Finished Jul 14 04:42:36 PM PDT 24
Peak memory 209576 kb
Host smart-5cff6736-e548-43ff-8dbc-a60e8cb5944c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733261161 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2733261161
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2702747386
Short name T1147
Test name
Test status
Simulation time 45996243887 ps
CPU time 105.41 seconds
Started Jul 14 04:26:11 PM PDT 24
Finished Jul 14 04:27:58 PM PDT 24
Peak memory 199820 kb
Host smart-d2ca03a1-b9c0-43af-a040-2a9cb17f9536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702747386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2702747386
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.264440381
Short name T1004
Test name
Test status
Simulation time 125942257350 ps
CPU time 362.84 seconds
Started Jul 14 04:26:09 PM PDT 24
Finished Jul 14 04:32:13 PM PDT 24
Peak memory 216820 kb
Host smart-e15aec1f-78ba-4181-a8b9-8888b0564e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264440381 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.264440381
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1544913511
Short name T153
Test name
Test status
Simulation time 64899650279 ps
CPU time 20 seconds
Started Jul 14 04:26:09 PM PDT 24
Finished Jul 14 04:26:30 PM PDT 24
Peak memory 199740 kb
Host smart-67824198-0b27-4813-b4e6-a0ee91df327b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544913511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1544913511
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1991446580
Short name T489
Test name
Test status
Simulation time 40020357532 ps
CPU time 233.38 seconds
Started Jul 14 04:26:11 PM PDT 24
Finished Jul 14 04:30:06 PM PDT 24
Peak memory 208404 kb
Host smart-326822a4-fbbe-4003-8173-8e3499c889ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991446580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1991446580
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3997143842
Short name T56
Test name
Test status
Simulation time 119767782849 ps
CPU time 350.86 seconds
Started Jul 14 04:26:11 PM PDT 24
Finished Jul 14 04:32:03 PM PDT 24
Peak memory 210136 kb
Host smart-bcd913e3-de61-4722-b05c-8e0ee5a3fcd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997143842 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3997143842
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2532151786
Short name T291
Test name
Test status
Simulation time 19661681920 ps
CPU time 24.37 seconds
Started Jul 14 04:26:14 PM PDT 24
Finished Jul 14 04:26:39 PM PDT 24
Peak memory 199400 kb
Host smart-3904b508-5ca9-41e7-bb87-6924a2a68a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532151786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2532151786
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2754872983
Short name T589
Test name
Test status
Simulation time 11597801450 ps
CPU time 100.91 seconds
Started Jul 14 04:26:08 PM PDT 24
Finished Jul 14 04:27:50 PM PDT 24
Peak memory 216024 kb
Host smart-6ca49f2e-8897-4c66-843c-0324ece58036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754872983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2754872983
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3262964804
Short name T154
Test name
Test status
Simulation time 29542849413 ps
CPU time 25.19 seconds
Started Jul 14 04:26:11 PM PDT 24
Finished Jul 14 04:26:37 PM PDT 24
Peak memory 199692 kb
Host smart-b2047d53-d30c-40d9-98b0-3f2a7071dc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262964804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3262964804
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3564226194
Short name T1084
Test name
Test status
Simulation time 14887487503 ps
CPU time 211.41 seconds
Started Jul 14 04:26:10 PM PDT 24
Finished Jul 14 04:29:42 PM PDT 24
Peak memory 215376 kb
Host smart-30a8a550-3249-487e-9038-ab660dfdae30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564226194 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3564226194
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3351768575
Short name T1103
Test name
Test status
Simulation time 179916797864 ps
CPU time 75.88 seconds
Started Jul 14 04:26:11 PM PDT 24
Finished Jul 14 04:27:28 PM PDT 24
Peak memory 199892 kb
Host smart-3029126c-5144-4942-9d7b-37a3507f312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351768575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3351768575
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1739449391
Short name T21
Test name
Test status
Simulation time 33318266488 ps
CPU time 197.38 seconds
Started Jul 14 04:26:11 PM PDT 24
Finished Jul 14 04:29:30 PM PDT 24
Peak memory 208068 kb
Host smart-b248072d-ed21-4a3e-b1ed-952863abf4d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739449391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1739449391
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3439164863
Short name T952
Test name
Test status
Simulation time 101797050055 ps
CPU time 215.8 seconds
Started Jul 14 04:26:09 PM PDT 24
Finished Jul 14 04:29:45 PM PDT 24
Peak memory 199740 kb
Host smart-6fe16d3a-2bd5-4b69-9006-3c942395e26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439164863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3439164863
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1937203794
Short name T768
Test name
Test status
Simulation time 170191760102 ps
CPU time 935.2 seconds
Started Jul 14 04:26:10 PM PDT 24
Finished Jul 14 04:41:46 PM PDT 24
Peak memory 232872 kb
Host smart-6ca225aa-f5a3-42ee-84c6-ce0dfeaa71ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937203794 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1937203794
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.506668672
Short name T19
Test name
Test status
Simulation time 96074024272 ps
CPU time 68.19 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:27:28 PM PDT 24
Peak memory 199680 kb
Host smart-5d32f8cd-83d3-4fb9-8ac7-d0be81a5a31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506668672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.506668672
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2464947104
Short name T726
Test name
Test status
Simulation time 20211832 ps
CPU time 0.54 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:23:45 PM PDT 24
Peak memory 194516 kb
Host smart-30222032-8bce-4493-8743-58ae28c5d6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464947104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2464947104
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3977280033
Short name T126
Test name
Test status
Simulation time 45595930279 ps
CPU time 68.58 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:24:53 PM PDT 24
Peak memory 199744 kb
Host smart-7fd1e273-cc38-432e-b26c-28da0d880400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977280033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3977280033
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2812356140
Short name T181
Test name
Test status
Simulation time 64589196888 ps
CPU time 21.78 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:24:06 PM PDT 24
Peak memory 199620 kb
Host smart-40670744-83b9-4e61-b2ba-be9baa9351cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812356140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2812356140
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.1553388134
Short name T282
Test name
Test status
Simulation time 39823462080 ps
CPU time 32.95 seconds
Started Jul 14 04:23:45 PM PDT 24
Finished Jul 14 04:24:19 PM PDT 24
Peak memory 199632 kb
Host smart-e6191bdb-1722-4ca8-8559-371285dcec25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553388134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1553388134
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.713214202
Short name T48
Test name
Test status
Simulation time 35275015877 ps
CPU time 79.59 seconds
Started Jul 14 04:23:36 PM PDT 24
Finished Jul 14 04:24:58 PM PDT 24
Peak memory 199676 kb
Host smart-5dc7bff8-29a2-46e5-a936-06d3a5707ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713214202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.713214202
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.533375162
Short name T501
Test name
Test status
Simulation time 2696654102 ps
CPU time 1.56 seconds
Started Jul 14 04:23:38 PM PDT 24
Finished Jul 14 04:23:41 PM PDT 24
Peak memory 195700 kb
Host smart-c573c8a6-5f55-4259-bbaf-683fa95096b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533375162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.533375162
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3101105156
Short name T583
Test name
Test status
Simulation time 20026001826 ps
CPU time 7.02 seconds
Started Jul 14 04:23:35 PM PDT 24
Finished Jul 14 04:23:45 PM PDT 24
Peak memory 194304 kb
Host smart-0fe008a2-4e28-4f14-a6ca-93f5513a7e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101105156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3101105156
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2130152742
Short name T733
Test name
Test status
Simulation time 23296145358 ps
CPU time 236.75 seconds
Started Jul 14 04:23:45 PM PDT 24
Finished Jul 14 04:27:42 PM PDT 24
Peak memory 199716 kb
Host smart-babdca67-b715-4d8a-a38e-f916bfbd0c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130152742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2130152742
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.483406572
Short name T551
Test name
Test status
Simulation time 6729018857 ps
CPU time 15.19 seconds
Started Jul 14 04:23:34 PM PDT 24
Finished Jul 14 04:23:52 PM PDT 24
Peak memory 197988 kb
Host smart-5e4ad33a-2d6f-4d45-b9c1-736543c93be1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483406572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.483406572
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.165837948
Short name T828
Test name
Test status
Simulation time 389271312340 ps
CPU time 75.37 seconds
Started Jul 14 04:23:35 PM PDT 24
Finished Jul 14 04:24:53 PM PDT 24
Peak memory 199704 kb
Host smart-d8cca0dc-f671-4ff3-9fee-1a32f7603c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165837948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.165837948
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3468779413
Short name T717
Test name
Test status
Simulation time 5780584814 ps
CPU time 3 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:23:50 PM PDT 24
Peak memory 195816 kb
Host smart-988daf02-90d4-4ace-95a9-6022d1da295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468779413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3468779413
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1872872032
Short name T524
Test name
Test status
Simulation time 5549963032 ps
CPU time 18.52 seconds
Started Jul 14 04:23:35 PM PDT 24
Finished Jul 14 04:23:56 PM PDT 24
Peak memory 199688 kb
Host smart-70b7b8b2-992d-4237-9c44-078f888431be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872872032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1872872032
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3628742714
Short name T401
Test name
Test status
Simulation time 235161278410 ps
CPU time 474.59 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:31:42 PM PDT 24
Peak memory 216300 kb
Host smart-59cacb91-0c20-455c-9a10-88151404ba3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628742714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3628742714
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2679615933
Short name T1040
Test name
Test status
Simulation time 35689844312 ps
CPU time 416.28 seconds
Started Jul 14 04:23:37 PM PDT 24
Finished Jul 14 04:30:39 PM PDT 24
Peak memory 216484 kb
Host smart-7acd60b8-fe4f-45c5-acc1-0bd67df9e9a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679615933 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2679615933
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.373001851
Short name T420
Test name
Test status
Simulation time 701993825 ps
CPU time 2.76 seconds
Started Jul 14 04:23:44 PM PDT 24
Finished Jul 14 04:23:48 PM PDT 24
Peak memory 198764 kb
Host smart-bace7c16-b927-4b53-aaec-b0b7fc335bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373001851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.373001851
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3271058863
Short name T993
Test name
Test status
Simulation time 50261835854 ps
CPU time 67.83 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:24:52 PM PDT 24
Peak memory 199744 kb
Host smart-e1d5242b-bd86-49bf-a965-60432cbc4752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271058863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3271058863
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4082302510
Short name T790
Test name
Test status
Simulation time 98355057505 ps
CPU time 69.6 seconds
Started Jul 14 04:26:20 PM PDT 24
Finished Jul 14 04:27:31 PM PDT 24
Peak memory 199812 kb
Host smart-ed0de56f-6257-40eb-962f-c7e7c049213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082302510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4082302510
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1177594077
Short name T722
Test name
Test status
Simulation time 34450082523 ps
CPU time 452.15 seconds
Started Jul 14 04:26:17 PM PDT 24
Finished Jul 14 04:33:49 PM PDT 24
Peak memory 208068 kb
Host smart-005ec03f-482b-4ce8-8855-f51d2c155d0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177594077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1177594077
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1873011857
Short name T860
Test name
Test status
Simulation time 30058136669 ps
CPU time 12.71 seconds
Started Jul 14 04:26:16 PM PDT 24
Finished Jul 14 04:26:30 PM PDT 24
Peak memory 199724 kb
Host smart-4411f7d7-7872-4c65-a8cf-623036e4f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873011857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1873011857
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1045609919
Short name T565
Test name
Test status
Simulation time 104657467680 ps
CPU time 1556.24 seconds
Started Jul 14 04:26:20 PM PDT 24
Finished Jul 14 04:52:18 PM PDT 24
Peak memory 219772 kb
Host smart-044276ba-d6e2-4f06-814d-752e974eb803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045609919 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1045609919
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.345202035
Short name T1051
Test name
Test status
Simulation time 43063902172 ps
CPU time 35.95 seconds
Started Jul 14 04:26:20 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 199640 kb
Host smart-3a374280-f86a-416e-8437-16b29f3e6886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345202035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.345202035
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2921215686
Short name T334
Test name
Test status
Simulation time 120597164242 ps
CPU time 1303.84 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:48:04 PM PDT 24
Peak memory 216228 kb
Host smart-027e0e94-e2c2-4dcf-8ae0-6abeab80606a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921215686 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2921215686
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1199875636
Short name T225
Test name
Test status
Simulation time 71068748582 ps
CPU time 30.19 seconds
Started Jul 14 04:26:20 PM PDT 24
Finished Jul 14 04:26:52 PM PDT 24
Peak memory 199688 kb
Host smart-70296311-f130-40b2-8fac-0608f8fab45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199875636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1199875636
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.182068169
Short name T52
Test name
Test status
Simulation time 200816834663 ps
CPU time 1278.75 seconds
Started Jul 14 04:26:21 PM PDT 24
Finished Jul 14 04:47:41 PM PDT 24
Peak memory 224484 kb
Host smart-1f74fcc6-2238-42b1-a135-0645add5b0fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182068169 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.182068169
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2166450966
Short name T160
Test name
Test status
Simulation time 114789543871 ps
CPU time 153.68 seconds
Started Jul 14 04:26:18 PM PDT 24
Finished Jul 14 04:28:53 PM PDT 24
Peak memory 199704 kb
Host smart-fecc52ba-712d-47d7-aa97-ede66728d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166450966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2166450966
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3056887171
Short name T51
Test name
Test status
Simulation time 556020115584 ps
CPU time 877.89 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:40:59 PM PDT 24
Peak memory 216200 kb
Host smart-4112be10-774d-4a52-a88f-a013f63d77e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056887171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3056887171
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2481953126
Short name T898
Test name
Test status
Simulation time 28327150294 ps
CPU time 9.7 seconds
Started Jul 14 04:26:20 PM PDT 24
Finished Jul 14 04:26:32 PM PDT 24
Peak memory 199784 kb
Host smart-fb1046ea-b8f3-4ef0-a4fb-b514c0e84903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481953126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2481953126
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2364760771
Short name T962
Test name
Test status
Simulation time 492355567181 ps
CPU time 1107.33 seconds
Started Jul 14 04:26:23 PM PDT 24
Finished Jul 14 04:44:51 PM PDT 24
Peak memory 216284 kb
Host smart-37c42366-5f8e-487f-b35c-8c35240bb4a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364760771 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2364760771
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3485326184
Short name T1118
Test name
Test status
Simulation time 126085078935 ps
CPU time 197.19 seconds
Started Jul 14 04:26:17 PM PDT 24
Finished Jul 14 04:29:35 PM PDT 24
Peak memory 199820 kb
Host smart-6b4ac9a0-af1a-4dd9-be10-5ba37d46f14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485326184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3485326184
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.4293393126
Short name T30
Test name
Test status
Simulation time 19349319551 ps
CPU time 286.79 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:31:08 PM PDT 24
Peak memory 215908 kb
Host smart-1eac0015-8a9d-4e6a-b441-f6f71b53d038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293393126 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.4293393126
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1234833148
Short name T109
Test name
Test status
Simulation time 54781376381 ps
CPU time 42.67 seconds
Started Jul 14 04:26:21 PM PDT 24
Finished Jul 14 04:27:05 PM PDT 24
Peak memory 199684 kb
Host smart-cf11283b-cb22-492b-bbd7-29bbc6ea5149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234833148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1234833148
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.96284915
Short name T77
Test name
Test status
Simulation time 39168252648 ps
CPU time 1226.98 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:46:48 PM PDT 24
Peak memory 216344 kb
Host smart-22f74232-75ed-4a50-9ef1-4e2ca73d1be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96284915 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.96284915
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.775463760
Short name T134
Test name
Test status
Simulation time 108545332103 ps
CPU time 32.06 seconds
Started Jul 14 04:26:25 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 199772 kb
Host smart-53cdd0cf-ddd8-4f14-822a-ada100bf4d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775463760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.775463760
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1786452253
Short name T476
Test name
Test status
Simulation time 45954165417 ps
CPU time 136.98 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:28:38 PM PDT 24
Peak memory 216544 kb
Host smart-9a757864-4a8a-41c7-9700-a00280f1b897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786452253 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1786452253
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1237523056
Short name T882
Test name
Test status
Simulation time 14514875 ps
CPU time 0.54 seconds
Started Jul 14 04:23:49 PM PDT 24
Finished Jul 14 04:23:50 PM PDT 24
Peak memory 194560 kb
Host smart-1e0fb91f-8f4e-4dae-ba49-569d48ec47e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237523056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1237523056
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.16610778
Short name T311
Test name
Test status
Simulation time 181972904437 ps
CPU time 223.59 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:27:30 PM PDT 24
Peak memory 199652 kb
Host smart-e84f326c-ff0c-423b-bdd5-9f9f8c3b47fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16610778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.16610778
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1203379567
Short name T150
Test name
Test status
Simulation time 25157828346 ps
CPU time 54.88 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:24:42 PM PDT 24
Peak memory 199648 kb
Host smart-5f8dcee8-909d-42ad-b9ac-4d99d5a4854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203379567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1203379567
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1568684795
Short name T254
Test name
Test status
Simulation time 51242768116 ps
CPU time 26.37 seconds
Started Jul 14 04:23:45 PM PDT 24
Finished Jul 14 04:24:13 PM PDT 24
Peak memory 199648 kb
Host smart-b31ef55c-f842-462c-be00-0a032359913a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568684795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1568684795
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3163014103
Short name T486
Test name
Test status
Simulation time 63041376576 ps
CPU time 28.49 seconds
Started Jul 14 04:23:47 PM PDT 24
Finished Jul 14 04:24:17 PM PDT 24
Peak memory 199588 kb
Host smart-c21a68cd-5f7d-4212-9284-aeaa3fbeaa69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163014103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3163014103
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.144083382
Short name T453
Test name
Test status
Simulation time 34736383072 ps
CPU time 143.6 seconds
Started Jul 14 04:23:57 PM PDT 24
Finished Jul 14 04:26:21 PM PDT 24
Peak memory 199784 kb
Host smart-9c2754aa-4a48-402f-8fbc-0c1b28ce3d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=144083382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.144083382
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2957408654
Short name T751
Test name
Test status
Simulation time 1087765164 ps
CPU time 1.6 seconds
Started Jul 14 04:23:53 PM PDT 24
Finished Jul 14 04:23:55 PM PDT 24
Peak memory 199496 kb
Host smart-09170af9-0a52-4b3d-9a62-1af96e348718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957408654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2957408654
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1275382105
Short name T1032
Test name
Test status
Simulation time 48269118741 ps
CPU time 111.56 seconds
Started Jul 14 04:23:48 PM PDT 24
Finished Jul 14 04:25:40 PM PDT 24
Peak memory 199796 kb
Host smart-dd188b0a-1993-4a74-b73a-5874ffef0eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275382105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1275382105
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2715793660
Short name T61
Test name
Test status
Simulation time 6822474668 ps
CPU time 59.59 seconds
Started Jul 14 04:23:45 PM PDT 24
Finished Jul 14 04:24:46 PM PDT 24
Peak memory 199092 kb
Host smart-d064ea75-5292-4095-a58f-2ea6dafd1eac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715793660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2715793660
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.684688759
Short name T542
Test name
Test status
Simulation time 22250176932 ps
CPU time 35.74 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:24:19 PM PDT 24
Peak memory 199696 kb
Host smart-782c8e95-68ff-4e26-b9aa-14e618a54fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684688759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.684688759
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.4155581030
Short name T756
Test name
Test status
Simulation time 31705878487 ps
CPU time 20.52 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:24:07 PM PDT 24
Peak memory 195788 kb
Host smart-e5de469b-9719-42e0-aa9b-171a6eb67e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155581030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4155581030
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2496012453
Short name T838
Test name
Test status
Simulation time 5717297085 ps
CPU time 12.12 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:23:48 PM PDT 24
Peak memory 199656 kb
Host smart-761a8c7a-5427-4de6-95dc-161af94443a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496012453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2496012453
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2654004104
Short name T642
Test name
Test status
Simulation time 107155125832 ps
CPU time 349.51 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:29:33 PM PDT 24
Peak memory 199648 kb
Host smart-6d97948e-3bf6-4a22-be8e-92a3e7c5905a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654004104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2654004104
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3650330989
Short name T32
Test name
Test status
Simulation time 35294035987 ps
CPU time 295.22 seconds
Started Jul 14 04:23:50 PM PDT 24
Finished Jul 14 04:28:46 PM PDT 24
Peak memory 216240 kb
Host smart-e2ae085f-ecde-48f9-8e60-9e563e135064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650330989 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3650330989
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.498716300
Short name T412
Test name
Test status
Simulation time 1703494595 ps
CPU time 2.01 seconds
Started Jul 14 04:23:47 PM PDT 24
Finished Jul 14 04:23:50 PM PDT 24
Peak memory 197944 kb
Host smart-e27a09f5-9461-40be-9f20-39d60e07f288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498716300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.498716300
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3107511220
Short name T1151
Test name
Test status
Simulation time 170292986156 ps
CPU time 66.47 seconds
Started Jul 14 04:23:51 PM PDT 24
Finished Jul 14 04:24:58 PM PDT 24
Peak memory 199688 kb
Host smart-7928ddbd-3aee-467a-8de6-652db8aa7b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107511220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3107511220
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1673732830
Short name T324
Test name
Test status
Simulation time 34191897879 ps
CPU time 60.58 seconds
Started Jul 14 04:26:21 PM PDT 24
Finished Jul 14 04:27:23 PM PDT 24
Peak memory 199764 kb
Host smart-7aaaac14-2ad0-4944-ad0e-da776a6c19d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673732830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1673732830
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.768004952
Short name T120
Test name
Test status
Simulation time 125334080792 ps
CPU time 122.23 seconds
Started Jul 14 04:26:22 PM PDT 24
Finished Jul 14 04:28:25 PM PDT 24
Peak memory 199664 kb
Host smart-b52ef4e1-f885-4b7d-b95e-cb6a7b296049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768004952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.768004952
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1683417487
Short name T54
Test name
Test status
Simulation time 263575163084 ps
CPU time 842.01 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:40:23 PM PDT 24
Peak memory 224796 kb
Host smart-10596c26-e08d-474c-a913-23963f36adc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683417487 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1683417487
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2920572858
Short name T186
Test name
Test status
Simulation time 17623178547 ps
CPU time 26.42 seconds
Started Jul 14 04:26:21 PM PDT 24
Finished Jul 14 04:26:49 PM PDT 24
Peak memory 199532 kb
Host smart-090909d8-7937-4be4-9c97-4aa97a2c51f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920572858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2920572858
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.755353432
Short name T835
Test name
Test status
Simulation time 177543026109 ps
CPU time 358.55 seconds
Started Jul 14 04:26:17 PM PDT 24
Finished Jul 14 04:32:16 PM PDT 24
Peak memory 216440 kb
Host smart-c5b43fa4-5f46-4e03-90f0-73fc6420f2f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755353432 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.755353432
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2337873985
Short name T580
Test name
Test status
Simulation time 24006013322 ps
CPU time 13.46 seconds
Started Jul 14 04:26:20 PM PDT 24
Finished Jul 14 04:26:35 PM PDT 24
Peak memory 199724 kb
Host smart-f6eb0ba9-9ad9-4505-a489-77fbdd55f98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337873985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2337873985
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3078880312
Short name T354
Test name
Test status
Simulation time 71289237142 ps
CPU time 51.18 seconds
Started Jul 14 04:26:22 PM PDT 24
Finished Jul 14 04:27:14 PM PDT 24
Peak memory 199712 kb
Host smart-f076364e-92fb-4782-ad4e-2cb2a9326916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078880312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3078880312
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.417778758
Short name T573
Test name
Test status
Simulation time 95918095399 ps
CPU time 1043.11 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:43:44 PM PDT 24
Peak memory 232788 kb
Host smart-affaa04b-97af-4786-bdc8-9bd79cfb5712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417778758 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.417778758
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2757160556
Short name T1074
Test name
Test status
Simulation time 62225400432 ps
CPU time 29.3 seconds
Started Jul 14 04:26:17 PM PDT 24
Finished Jul 14 04:26:47 PM PDT 24
Peak memory 199764 kb
Host smart-314065ad-711d-4459-b60d-a607f2767a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757160556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2757160556
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.816199791
Short name T676
Test name
Test status
Simulation time 30330001740 ps
CPU time 21.53 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:26:43 PM PDT 24
Peak memory 199788 kb
Host smart-29d657ca-ee23-4f00-acaa-6b76b15aa242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816199791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.816199791
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1691254837
Short name T152
Test name
Test status
Simulation time 88432000262 ps
CPU time 28.76 seconds
Started Jul 14 04:26:18 PM PDT 24
Finished Jul 14 04:26:48 PM PDT 24
Peak memory 199736 kb
Host smart-79875b2c-c0f5-4a1f-98ea-f5dff0ad997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691254837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1691254837
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1148240058
Short name T798
Test name
Test status
Simulation time 343109714001 ps
CPU time 1014.51 seconds
Started Jul 14 04:26:26 PM PDT 24
Finished Jul 14 04:43:21 PM PDT 24
Peak memory 228056 kb
Host smart-91568ab4-6b5f-485a-93cb-8ae945900e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148240058 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1148240058
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.647016312
Short name T228
Test name
Test status
Simulation time 34123450366 ps
CPU time 13.61 seconds
Started Jul 14 04:26:19 PM PDT 24
Finished Jul 14 04:26:34 PM PDT 24
Peak memory 199684 kb
Host smart-cfd37e31-17e1-4312-98eb-d8f2c530d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647016312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.647016312
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3120839918
Short name T992
Test name
Test status
Simulation time 14924904683 ps
CPU time 21.35 seconds
Started Jul 14 04:26:21 PM PDT 24
Finished Jul 14 04:26:43 PM PDT 24
Peak memory 199632 kb
Host smart-2a4d7fb0-c325-4488-bad0-7d40a4910caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120839918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3120839918
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1027521268
Short name T53
Test name
Test status
Simulation time 95773566626 ps
CPU time 1048.46 seconds
Started Jul 14 04:26:25 PM PDT 24
Finished Jul 14 04:43:55 PM PDT 24
Peak memory 225856 kb
Host smart-efa6ecf5-0afd-4f76-b69f-39452017ce4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027521268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1027521268
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1467639599
Short name T410
Test name
Test status
Simulation time 99127224 ps
CPU time 0.55 seconds
Started Jul 14 04:23:55 PM PDT 24
Finished Jul 14 04:23:56 PM PDT 24
Peak memory 195112 kb
Host smart-568a9c8d-e993-496a-9483-0011d3311c3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467639599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1467639599
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3289925245
Short name T141
Test name
Test status
Simulation time 83780909252 ps
CPU time 43.62 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:24:48 PM PDT 24
Peak memory 199740 kb
Host smart-e86c3883-3bfc-4734-a75a-0925fe05339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289925245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3289925245
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.865655124
Short name T566
Test name
Test status
Simulation time 37373742267 ps
CPU time 56.38 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:24:40 PM PDT 24
Peak memory 199700 kb
Host smart-ef097baa-f676-49be-9c33-516dd824746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865655124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.865655124
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1963237600
Short name T1153
Test name
Test status
Simulation time 27322480609 ps
CPU time 31.94 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:24:27 PM PDT 24
Peak memory 199704 kb
Host smart-028d770d-c024-4e87-9e47-b3bd53fe0434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963237600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1963237600
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3566710975
Short name T1045
Test name
Test status
Simulation time 25376788539 ps
CPU time 37.94 seconds
Started Jul 14 04:23:50 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 198768 kb
Host smart-8c3ec5b4-94a5-4955-9b0a-c11c60fe0bf6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566710975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3566710975
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1759616498
Short name T947
Test name
Test status
Simulation time 103709684096 ps
CPU time 139.81 seconds
Started Jul 14 04:23:41 PM PDT 24
Finished Jul 14 04:26:01 PM PDT 24
Peak memory 199764 kb
Host smart-9187ef28-a536-4373-bd54-a737ff443926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1759616498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1759616498
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1687573517
Short name T649
Test name
Test status
Simulation time 6024194314 ps
CPU time 3.67 seconds
Started Jul 14 04:23:45 PM PDT 24
Finished Jul 14 04:23:50 PM PDT 24
Peak memory 198020 kb
Host smart-0f36c6a9-bfa5-44f7-bcbc-07ac8746e05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687573517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1687573517
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.3046371943
Short name T484
Test name
Test status
Simulation time 50588945214 ps
CPU time 21.8 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:24:17 PM PDT 24
Peak memory 198476 kb
Host smart-1ba6e569-4d24-4586-b273-43a1fb784aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046371943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3046371943
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2263470737
Short name T743
Test name
Test status
Simulation time 3560720171 ps
CPU time 45.25 seconds
Started Jul 14 04:23:47 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 199588 kb
Host smart-aea39554-75b9-4026-8a28-0aeef2c62c6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263470737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2263470737
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.4058174919
Short name T498
Test name
Test status
Simulation time 7019605888 ps
CPU time 32.91 seconds
Started Jul 14 04:24:01 PM PDT 24
Finished Jul 14 04:24:34 PM PDT 24
Peak memory 198848 kb
Host smart-20e37012-c174-4096-b447-8e359fd61844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058174919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.4058174919
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1045202670
Short name T1114
Test name
Test status
Simulation time 39476667151 ps
CPU time 32.36 seconds
Started Jul 14 04:24:05 PM PDT 24
Finished Jul 14 04:24:38 PM PDT 24
Peak memory 199720 kb
Host smart-5e555863-5d18-40c6-a506-15a04ce57f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045202670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1045202670
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1581554844
Short name T1052
Test name
Test status
Simulation time 3207017755 ps
CPU time 1.79 seconds
Started Jul 14 04:23:59 PM PDT 24
Finished Jul 14 04:24:01 PM PDT 24
Peak memory 196040 kb
Host smart-2df010af-ab1d-4afa-985b-70e4e31c6043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581554844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1581554844
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1211032749
Short name T800
Test name
Test status
Simulation time 674341164 ps
CPU time 1.82 seconds
Started Jul 14 04:23:46 PM PDT 24
Finished Jul 14 04:23:49 PM PDT 24
Peak memory 198616 kb
Host smart-3de48fc3-1aa4-464a-9260-cb458a43c8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211032749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1211032749
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2080771719
Short name T923
Test name
Test status
Simulation time 261623581208 ps
CPU time 322.47 seconds
Started Jul 14 04:23:51 PM PDT 24
Finished Jul 14 04:29:14 PM PDT 24
Peak memory 199712 kb
Host smart-c0adca37-f30f-4be9-9199-2bcfe019a1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080771719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2080771719
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.199213736
Short name T1026
Test name
Test status
Simulation time 468139697991 ps
CPU time 664.25 seconds
Started Jul 14 04:23:50 PM PDT 24
Finished Jul 14 04:34:55 PM PDT 24
Peak memory 224720 kb
Host smart-03f9822c-0541-4457-8478-ef7f76cdf5f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199213736 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.199213736
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1295683348
Short name T383
Test name
Test status
Simulation time 2654408392 ps
CPU time 2.37 seconds
Started Jul 14 04:23:56 PM PDT 24
Finished Jul 14 04:23:59 PM PDT 24
Peak memory 198836 kb
Host smart-640c6356-0a19-47cf-a361-646638e2c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295683348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1295683348
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3939255351
Short name T953
Test name
Test status
Simulation time 67229605765 ps
CPU time 96.6 seconds
Started Jul 14 04:23:50 PM PDT 24
Finished Jul 14 04:25:27 PM PDT 24
Peak memory 199700 kb
Host smart-ae2dcc33-865e-4682-8a76-1f57082e8feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939255351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3939255351
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4037276368
Short name T1159
Test name
Test status
Simulation time 25595959341 ps
CPU time 46.76 seconds
Started Jul 14 04:26:18 PM PDT 24
Finished Jul 14 04:27:06 PM PDT 24
Peak memory 199880 kb
Host smart-fe4a1c77-7c9e-432e-a267-f2b5d4a8fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037276368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4037276368
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.4184624835
Short name T1119
Test name
Test status
Simulation time 35874547809 ps
CPU time 620.9 seconds
Started Jul 14 04:26:18 PM PDT 24
Finished Jul 14 04:36:40 PM PDT 24
Peak memory 225392 kb
Host smart-be953126-49f4-4c82-846c-321fa7599fb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184624835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.4184624835
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.741227552
Short name T353
Test name
Test status
Simulation time 124089008517 ps
CPU time 61.13 seconds
Started Jul 14 04:26:28 PM PDT 24
Finished Jul 14 04:27:31 PM PDT 24
Peak memory 199848 kb
Host smart-ca275198-5e42-41da-88e8-03241a0a8baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741227552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.741227552
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2925071651
Short name T336
Test name
Test status
Simulation time 49396289241 ps
CPU time 413.02 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:33:22 PM PDT 24
Peak memory 216488 kb
Host smart-861818bf-cff7-46df-a7d1-30c926151232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925071651 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2925071651
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.7808036
Short name T1098
Test name
Test status
Simulation time 119730052193 ps
CPU time 609.07 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:36:37 PM PDT 24
Peak memory 216292 kb
Host smart-e20b9959-fd86-4ddd-be68-664ff37c8810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7808036 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.7808036
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3586585566
Short name T503
Test name
Test status
Simulation time 155953357043 ps
CPU time 79.22 seconds
Started Jul 14 04:26:29 PM PDT 24
Finished Jul 14 04:27:49 PM PDT 24
Peak memory 199848 kb
Host smart-d30fa654-12e3-4dce-a048-c8544d003004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586585566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3586585566
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2046370162
Short name T1072
Test name
Test status
Simulation time 116186130450 ps
CPU time 619.18 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:36:47 PM PDT 24
Peak memory 216256 kb
Host smart-8d150842-ed34-4b8c-9d7c-74621842fe6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046370162 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2046370162
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.685836849
Short name T644
Test name
Test status
Simulation time 187634953416 ps
CPU time 21.58 seconds
Started Jul 14 04:26:28 PM PDT 24
Finished Jul 14 04:26:51 PM PDT 24
Peak memory 199728 kb
Host smart-eb99e1c1-808c-4e1b-9e08-a8d9194ca381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685836849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.685836849
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3554516572
Short name T816
Test name
Test status
Simulation time 285036013006 ps
CPU time 1123.86 seconds
Started Jul 14 04:27:58 PM PDT 24
Finished Jul 14 04:46:43 PM PDT 24
Peak memory 215992 kb
Host smart-12d06636-31ce-4388-ae25-0ead90c20d21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554516572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3554516572
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1646247134
Short name T384
Test name
Test status
Simulation time 40453653684 ps
CPU time 17.19 seconds
Started Jul 14 04:26:28 PM PDT 24
Finished Jul 14 04:26:47 PM PDT 24
Peak memory 199684 kb
Host smart-50f98255-64f5-4f31-bc1e-40c3b966d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646247134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1646247134
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2760705812
Short name T1077
Test name
Test status
Simulation time 39969214033 ps
CPU time 266.69 seconds
Started Jul 14 04:26:28 PM PDT 24
Finished Jul 14 04:30:56 PM PDT 24
Peak memory 216528 kb
Host smart-abdb9ba1-7af9-4ca8-be88-8c8567484135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760705812 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2760705812
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1505587093
Short name T949
Test name
Test status
Simulation time 109298671002 ps
CPU time 406.38 seconds
Started Jul 14 04:27:58 PM PDT 24
Finished Jul 14 04:34:45 PM PDT 24
Peak memory 199460 kb
Host smart-7a361a4b-139b-40c4-8a38-e1a617b4cad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505587093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1505587093
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3613626125
Short name T920
Test name
Test status
Simulation time 459255695549 ps
CPU time 1316.66 seconds
Started Jul 14 04:26:28 PM PDT 24
Finished Jul 14 04:48:26 PM PDT 24
Peak memory 224408 kb
Host smart-6aa9f43d-20ba-413e-8cb9-354bd5da960a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613626125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3613626125
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3235951098
Short name T1005
Test name
Test status
Simulation time 62566648096 ps
CPU time 52.6 seconds
Started Jul 14 04:26:26 PM PDT 24
Finished Jul 14 04:27:20 PM PDT 24
Peak memory 199680 kb
Host smart-eb1349c4-1ea9-49bf-b45b-780cf5c6fe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235951098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3235951098
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2767275857
Short name T864
Test name
Test status
Simulation time 26688423075 ps
CPU time 312.19 seconds
Started Jul 14 04:26:28 PM PDT 24
Finished Jul 14 04:31:42 PM PDT 24
Peak memory 216472 kb
Host smart-8b6dfa39-2611-4fdb-9e61-7aff756c1531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767275857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2767275857
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1869764952
Short name T38
Test name
Test status
Simulation time 89460848537 ps
CPU time 109.26 seconds
Started Jul 14 04:26:26 PM PDT 24
Finished Jul 14 04:28:16 PM PDT 24
Peak memory 199748 kb
Host smart-7ea2e37d-302c-42c2-a530-4dff61eb29ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869764952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1869764952
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2581238653
Short name T300
Test name
Test status
Simulation time 39566131882 ps
CPU time 512.02 seconds
Started Jul 14 04:26:30 PM PDT 24
Finished Jul 14 04:35:03 PM PDT 24
Peak memory 216516 kb
Host smart-e692e674-d80c-4397-883a-c11a360da35d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581238653 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2581238653
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3807653613
Short name T1082
Test name
Test status
Simulation time 16535059550 ps
CPU time 29.61 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 199704 kb
Host smart-4b1224ed-1765-40b7-8f92-50cd44b182e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807653613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3807653613
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.534794265
Short name T512
Test name
Test status
Simulation time 240869463331 ps
CPU time 608.4 seconds
Started Jul 14 04:26:29 PM PDT 24
Finished Jul 14 04:36:38 PM PDT 24
Peak memory 216240 kb
Host smart-57013964-c4ae-4553-868f-b1972eddaef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534794265 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.534794265
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.36161911
Short name T1170
Test name
Test status
Simulation time 28634412 ps
CPU time 0.51 seconds
Started Jul 14 04:24:01 PM PDT 24
Finished Jul 14 04:24:02 PM PDT 24
Peak memory 194564 kb
Host smart-ea2c95a2-5660-4469-9143-6a5810a0dfb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.36161911
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.818983995
Short name T737
Test name
Test status
Simulation time 143271020236 ps
CPU time 229.18 seconds
Started Jul 14 04:23:47 PM PDT 24
Finished Jul 14 04:27:37 PM PDT 24
Peak memory 199684 kb
Host smart-5847fcf1-b19c-494c-a5fe-611b48e6fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818983995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.818983995
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.79562955
Short name T885
Test name
Test status
Simulation time 191711663151 ps
CPU time 133.94 seconds
Started Jul 14 04:24:03 PM PDT 24
Finished Jul 14 04:26:18 PM PDT 24
Peak memory 199820 kb
Host smart-7b33f8e7-e2e3-4a03-a65d-bc2b090bf9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79562955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.79562955
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2073710827
Short name T701
Test name
Test status
Simulation time 43702544973 ps
CPU time 20.35 seconds
Started Jul 14 04:23:53 PM PDT 24
Finished Jul 14 04:24:15 PM PDT 24
Peak memory 199788 kb
Host smart-47e472ae-5475-4e55-b5df-68d053bd40c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073710827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2073710827
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.4274696995
Short name T1165
Test name
Test status
Simulation time 21943239978 ps
CPU time 9.55 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:24:05 PM PDT 24
Peak memory 199684 kb
Host smart-ada84063-650c-490c-b01a-2cadb845c6d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274696995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4274696995
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2903744256
Short name T460
Test name
Test status
Simulation time 64668996387 ps
CPU time 272.41 seconds
Started Jul 14 04:23:50 PM PDT 24
Finished Jul 14 04:28:23 PM PDT 24
Peak memory 199604 kb
Host smart-0f8a11dd-6357-45f5-80cf-d9c92cad86cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903744256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2903744256
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.985114900
Short name T1003
Test name
Test status
Simulation time 6304182523 ps
CPU time 11.04 seconds
Started Jul 14 04:23:57 PM PDT 24
Finished Jul 14 04:24:08 PM PDT 24
Peak memory 199500 kb
Host smart-e136a47b-3897-4211-913a-2a2605328cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985114900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.985114900
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1777648770
Short name T878
Test name
Test status
Simulation time 215688997923 ps
CPU time 345.94 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:29:29 PM PDT 24
Peak memory 199908 kb
Host smart-4426fc32-0bda-487e-a0e4-20eebec99688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777648770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1777648770
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2166620830
Short name T40
Test name
Test status
Simulation time 19042494130 ps
CPU time 989.88 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:40:25 PM PDT 24
Peak memory 199732 kb
Host smart-8a6af3b5-709d-4e49-a6af-da33246704e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166620830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2166620830
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1216730747
Short name T830
Test name
Test status
Simulation time 6418163248 ps
CPU time 42.33 seconds
Started Jul 14 04:23:52 PM PDT 24
Finished Jul 14 04:24:35 PM PDT 24
Peak memory 197976 kb
Host smart-2b69c375-d611-4848-a2fa-37facf9dfc8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216730747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1216730747
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.4224228183
Short name T596
Test name
Test status
Simulation time 39252859907 ps
CPU time 24.85 seconds
Started Jul 14 04:23:50 PM PDT 24
Finished Jul 14 04:24:16 PM PDT 24
Peak memory 198964 kb
Host smart-28d0dcae-ac36-4759-83c0-f981dc2b20e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224228183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4224228183
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3403552134
Short name T628
Test name
Test status
Simulation time 37059784049 ps
CPU time 13.74 seconds
Started Jul 14 04:23:54 PM PDT 24
Finished Jul 14 04:24:09 PM PDT 24
Peak memory 195572 kb
Host smart-f39a2b61-12a4-4ffb-b6cf-766966d636be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403552134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3403552134
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1973055177
Short name T1069
Test name
Test status
Simulation time 538242322 ps
CPU time 2.79 seconds
Started Jul 14 04:23:44 PM PDT 24
Finished Jul 14 04:23:48 PM PDT 24
Peak memory 199296 kb
Host smart-281bad02-b140-4cd7-970a-38bde77f3f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973055177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1973055177
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1077766295
Short name T533
Test name
Test status
Simulation time 1465029336881 ps
CPU time 994.88 seconds
Started Jul 14 04:23:51 PM PDT 24
Finished Jul 14 04:40:27 PM PDT 24
Peak memory 226924 kb
Host smart-702e99b2-4bab-461e-aa6f-b85b4ee1a058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077766295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1077766295
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2741596519
Short name T292
Test name
Test status
Simulation time 6521439463 ps
CPU time 18.78 seconds
Started Jul 14 04:23:52 PM PDT 24
Finished Jul 14 04:24:11 PM PDT 24
Peak memory 199764 kb
Host smart-1017e2f7-2b91-4b6a-8f9a-98b96969d085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741596519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2741596519
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3021112865
Short name T461
Test name
Test status
Simulation time 70661795931 ps
CPU time 47.76 seconds
Started Jul 14 04:23:52 PM PDT 24
Finished Jul 14 04:24:40 PM PDT 24
Peak memory 199792 kb
Host smart-d027fa55-7089-4126-9663-5acaa1450ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021112865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3021112865
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2821945983
Short name T1126
Test name
Test status
Simulation time 83548656987 ps
CPU time 313.71 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:31:42 PM PDT 24
Peak memory 199820 kb
Host smart-f4bb8ceb-5664-4ca1-95c5-2c27743ed3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821945983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2821945983
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.355607645
Short name T350
Test name
Test status
Simulation time 209614932168 ps
CPU time 766.11 seconds
Started Jul 14 04:26:30 PM PDT 24
Finished Jul 14 04:39:17 PM PDT 24
Peak memory 216252 kb
Host smart-33b41f88-18d2-4168-bd01-b126b1885050
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355607645 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.355607645
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2911264872
Short name T114
Test name
Test status
Simulation time 100531991207 ps
CPU time 300.65 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:31:29 PM PDT 24
Peak memory 215460 kb
Host smart-f44bd3c8-3dee-44a6-b859-a4aa60c4119b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911264872 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2911264872
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4062680616
Short name T899
Test name
Test status
Simulation time 38447828239 ps
CPU time 17.54 seconds
Started Jul 14 04:27:58 PM PDT 24
Finished Jul 14 04:28:16 PM PDT 24
Peak memory 199424 kb
Host smart-5365ad39-af6c-4ccd-ac3d-e0011c0006cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062680616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4062680616
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3691271288
Short name T113
Test name
Test status
Simulation time 284639214292 ps
CPU time 832.09 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:40:20 PM PDT 24
Peak memory 222060 kb
Host smart-7a1b91ea-11b1-4bd3-a293-d4bb1378174e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691271288 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3691271288
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1497443230
Short name T344
Test name
Test status
Simulation time 73426164153 ps
CPU time 68.26 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:27:37 PM PDT 24
Peak memory 199860 kb
Host smart-5ea8187f-0734-4900-ab67-3c8d4d8006d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497443230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1497443230
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2650733817
Short name T924
Test name
Test status
Simulation time 56474495720 ps
CPU time 557.21 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:35:45 PM PDT 24
Peak memory 216412 kb
Host smart-4eec7f67-0012-467f-9442-51327ed1452f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650733817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2650733817
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1521106977
Short name T122
Test name
Test status
Simulation time 31186792906 ps
CPU time 26.57 seconds
Started Jul 14 04:26:26 PM PDT 24
Finished Jul 14 04:26:53 PM PDT 24
Peak memory 199796 kb
Host smart-3d09893d-2bcb-4cb2-a9ba-1a614d5c4243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521106977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1521106977
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.854347831
Short name T690
Test name
Test status
Simulation time 159042757453 ps
CPU time 575.72 seconds
Started Jul 14 04:26:29 PM PDT 24
Finished Jul 14 04:36:06 PM PDT 24
Peak memory 224632 kb
Host smart-c000d602-ac07-4fe7-9a21-9de243ba1b99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854347831 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.854347831
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3182625606
Short name T645
Test name
Test status
Simulation time 101841882745 ps
CPU time 38.49 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:27:07 PM PDT 24
Peak memory 199732 kb
Host smart-7a296a08-4178-4c08-896e-c8292df8276a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182625606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3182625606
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.4291691463
Short name T55
Test name
Test status
Simulation time 94729849409 ps
CPU time 282.5 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:31:11 PM PDT 24
Peak memory 216496 kb
Host smart-c328fa2f-40c9-4f16-958b-5a7da5bd2023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291691463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.4291691463
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.452503434
Short name T978
Test name
Test status
Simulation time 25414402253 ps
CPU time 22.67 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:26:50 PM PDT 24
Peak memory 199768 kb
Host smart-1be5b84b-aa95-4c50-8eb9-b07b9a0dbe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452503434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.452503434
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3039802265
Short name T430
Test name
Test status
Simulation time 19152746187 ps
CPU time 237.66 seconds
Started Jul 14 04:26:26 PM PDT 24
Finished Jul 14 04:30:24 PM PDT 24
Peak memory 208092 kb
Host smart-d9537f26-47af-4f5a-a9b8-73e649831149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039802265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3039802265
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.861063993
Short name T539
Test name
Test status
Simulation time 80059504406 ps
CPU time 20.57 seconds
Started Jul 14 04:26:29 PM PDT 24
Finished Jul 14 04:26:51 PM PDT 24
Peak memory 199616 kb
Host smart-bbeb4a4a-50f6-488f-985c-0b1674bddee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861063993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.861063993
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1159679991
Short name T281
Test name
Test status
Simulation time 37851931575 ps
CPU time 11.92 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:26:39 PM PDT 24
Peak memory 199756 kb
Host smart-8ae3877f-9fa5-460c-b5a6-46e7dc285975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159679991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1159679991
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.4259644491
Short name T683
Test name
Test status
Simulation time 102591137307 ps
CPU time 316.01 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:31:45 PM PDT 24
Peak memory 216152 kb
Host smart-b57eae50-2d55-4cb0-80df-734a144d5fe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259644491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.4259644491
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2159298120
Short name T638
Test name
Test status
Simulation time 78815860047 ps
CPU time 45.96 seconds
Started Jul 14 04:26:27 PM PDT 24
Finished Jul 14 04:27:14 PM PDT 24
Peak memory 199708 kb
Host smart-095f9d92-efdc-47fa-bb98-4ad92c896eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159298120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2159298120
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2176406643
Short name T1020
Test name
Test status
Simulation time 46996195275 ps
CPU time 776.95 seconds
Started Jul 14 04:26:36 PM PDT 24
Finished Jul 14 04:39:35 PM PDT 24
Peak memory 216636 kb
Host smart-af9fd9a4-01fe-46c9-bf7f-57583f848168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176406643 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2176406643
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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